FUJITSU MB89PV620

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12508-3E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89601R Series
MB89601R/603/P601/PV620
■ DESCRIPTION
The MB89601R series is compact one-chip microcontrollers using the F2MC-8L* CPU core for which can operate
at low voltage but at high speed. The microcontrollers contain peripheral functions such as timers, a serial interface
and an external interrupt and are applicable to welfare products, especially portable devices required savings in
board space.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• High-speed processing at low voltage
Minimum execution time: 0.5 µs/3.5 V at 8 MHz
• F2MC-8L family CPU core
• Timer
8-bit PWM timer (also usable as a reload timer)
• Serial interface
Switchable transfer direction allows communication with various equipment.
• External interrupt
Capable of wake-up from low-power consumption modes (with an edge detection function)
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
■ PACKAGE
48-pin Plastic SQFP
(FPT-48P-M05)
64-pin Ceramic MDIP
64-pin Ceramic MQFP
(MDP-64C-P02)
(MQP-64C-P01)
MB89601R Series
■ PRODUCT LINEUP
Part number
Parameter
Classification
ROM size
(internal ROM)
MB89601R
Mass production products
(mask ROM products)
4 K × 8 bits
8 K × 8 bits
(internal mask ROM) (internal mask ROM)
8-bit PWM timer
8-bit pulse-width
count timer
16-bit timer/counter
8-bit serial I/O
MB89P601
One-time PROM
product
4 K × 8 bits
(external ROM, programming
with general-purpose
EPROM programmer)
80 × 8 bits
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
RAM size
CPU functions
Ports
MB89603
MB89PV620*1
Piggyback/evaluation
product (for evaluation
and development)
32 K × 8 bits
(external ROM)
1 K × 8 bits
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.5 µs/8 MHz
4.5 µs/8 MHz
5 (4 ports also serve as
peripherals.)
8
(8
ports also serve as
Output ports:
none
peripherals.)
8 (4 ports also serve as
I/O ports (N-ch open-drain):
8 (3 ports also serve as peripherals)
peripherals.)
8
(8
ports also serve as
Output ports (CMOS):
none
peripherals.)
24 (24 ports also serve
I/O ports (CMOS):
24 (1 port also serves as peripherals.)
as
peripherals.)
Total:
33
53
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.5 to 8 µs)
8-bit resolution PWM operation (conversion cycle: 128 to 2048 µs)
8-bit timer operation
8-bit reload timer
operation
none
8-bit pulse-width
measurement operation
16-bit timer operation
none
16-bit event conter
Input ports:
1 (also serve as peripherals.)
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
SI/O × 2 channels
(one external shift clock, three internal shift clocks: 1.0 µs, 4.0 µs, 16.0 µs)
none
8-bit resolution × 8
channels
A/D conversion mode
Sense mode
Reference voltage
input
Edge selection, interrupt vector, source flag
Rising edge/falling edge selectability
Used also for wake-up from stop/sleep modes.
(Edge detection is also permitted in stop mode.)
External interrupt × 4
channels
8-bit A/D converter
External interrupt
(Continued)
2
MB89601R Series
(Continued)
Part number
Parameter
Standby mode
Process
Operating voltage*1
EPROM for use
MB89603
MB89601R
MB89P601
MB89PV620*1
Sleep mode, stop mode
CMOS
2.7 V to 6.0 V
2.2 V to 6.0 V
—
MBM27C256A-20TV
MBM27C256A-20CZ
*1: The piggyback/evaluation product is applicable to the MB89620 series.
*2: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB89601R
MB89603
MB89P601
MB89PV620
×
DIP-48P-M05
MDP-64C-P02
×
MQP-64C-P01
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89601R, MB89603, MB89P601, upper than 0140H of each register bank cannot be used.
• The stack area, etc., is set at the upper limit of the RAM.
• External area is used.
2. Current Consumption
• In the case of the MB89PV620, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see sections
“■ Electrical Characteristics” and “■ Example Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check “■ Mask Options.”
Take particular care on the following point:
• Options are fixed on the MB89PV620 and MB89P601.
3
MB89601R Series
■ PIN ASSIGNMENT
48
47
46
45
44
43
42
41
40
39
38
37
N.C.
VSS
P17
P16
P15
P14
P13
P12
P11
P10
MOD0
N.C.
(Top view)
N.C.
X1
X0
P40
P41
P42
P43
P44
P45/SCK
P46/SO
P47/SI
N.C.
36
35
34
33
32
31
30
29
28
27
26
25
N.C.
MOD1
P07
P06
P05
P04
P03
P02
P01
P00
VCC
N.C.
N.C.
RST
P60/INT
P30
P31
P32
P33
P34
P35
P36
P37/PTO
N.C.
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
(FPT-48P-M05)
(Top view)
P36/WTO
P37/PTO
P40
P41
P42
P43
P44/BZ
P45/SCK2
P46/SO2
P47/SI2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT0
P61/INT1
P62/INT2
P63/INT3
P64
RST
MOD0
MOD1
X0
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
92
91
90
89
88
87
86
85
84
83
82
81
80
79
Each pin inside the
dashed line is for
MB89PV620 only.
(MDP-64C-P02)
4
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P35/PWC
P34/EC
P33/SI1
P32/SO1
P31/SCK1
P30/ADST
VSS
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
P21/HAK
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
P27/ALE
MB89601R Series
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
94
95
96
65
66
67
68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Each pin inside the dashed
line is for MB89PV620 only.
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P30/ADST
VSS
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
RST
MOD0
MOD1
X0
X1
VSS
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
20
21
22
23
24
25
26
27
28
29
30
31
32
P45/SCK2
P46/SO2
P47/SI2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT0
P61/INT1
P62/INT2
P63/INT3
P64
84
83
82
81
80
79
78
64
63
62
61
60
59
58
57
56
55
54
53
52
P44/BZ
P43
P42
P41
P40
P37/PTO
P36/WTO
VCC
P35/PWC
P34/EC
P33/SI1
P32/SO1
P31/SCK1
(Top view)
(MQP-64C-P01)
• Pin assignment on package top (MB89PV620 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
65
N.C.
73
A2
81
N.C.
89
OE
66
VPP
74
A1
82
O4
90
N.C.
67
A12
75
A0
83
O5
91
A11
68
A7
76
N.C.
84
O6
92
A9
69
A6
77
O1
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
71
A4
79
O3
87
CE
95
A14
72
A3
80
VSS
88
A10
96
VCC
N.C.: Internally connected. Do not use.
5
MB89601R Series
■ PIN DESCRIPTION
• MB89601R/603/P601
Pin no.
Pin name
SQFP*
3
X0
2
X1
38
MOD0
35
MOD1
14
Function
A
Cystal oscillator pins
B
Operating mode selection pins
Connect directly to VSS.
RST
C
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up resistor,
and a hysteresis input type. "L" is output from this pin by an
internal reset source. The internal circuit is initialized by the input
of “L”.
27 to 34
P00 to P07
D
General-purpose I/O ports
39 to 46
P10 to P17
16 to 22
P30 to P36
E
General-purpose I/O ports
This port is a hysteresis input type.
A software pull-up resistor is provided as an option.
23
4 to 8
P37/PTO
P40 to P44
General-purpose I/O port
This port is a hysteresis input type.
Also serves as the toggle output for the 8-bit PWM timer.
A software pull-up resistor is provided as an option.
G
N-ch open-drain I/O port
This port is a hysteresis input type.
9
P45/SCK
N-ch open-drain I/O port
This port is a hysteresis input type.
Also serves as the clock I/O for the serial I/O.
10,
11
P46/SO,
P47/SI
N-ch open-drain I/O port
This port is a hysteresis input type.
Also serves as the data output for the serial I/O.
15
P60/INT
26
VCC
—
Power supply pin
47
VSS
—
Power supply (GND) pin
1, 12, 13,
24, 25, 36,
37, 48
N.C.
—
Be sure to leave them open.
* : FPT-48P-M05
6
Circuit
type
I
General-purpose input-only port
Also serves as an external interrupt input.
This port is a hysteresis input type.
MB89601R Series
• MB89PV620
Pin no.
*1
Pin name
MDIP
MQFP*2
30
23
X0
31
24
X1
28
21
MOD0
29
22
MOD1
27
20
56 to 49
Circuit
type
Function
A
Crystal oscillator pins
B
Operating mode selection pins
Connect directly to VCC or VSS.
RST
C
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up
resistor, and a hysteresis input type. “L” is output from
this pin by an internal reset source. The internal circuit is
initialized by the input of “L”.
49 to 42
P00/AD0 to
P07/AD7
D
General-purpose I/O ports
When an external bus is used, this port function as
multiplex pins of lower address output and data I/O.
48 to 41
41 to 34
P10/A08 to
P17/A15
D
General-purpose I/O ports
When an external bus is used, this port function as a
upper address output.
40
33
P20/BUFC
F
General-purpose output-only port
When an external bus is used, this port can also be used
as a buffer control output by setting the BCTR.
39
32
P21/HAK
F
General-purpose output-only port
When an external bus is used, this port can also be used
as a hold-acknowledge by setting the BCTR.
38
31
P22/HRQ
D
General-purpose output-only port
When an external bus is used, this port can also be used
as a hold request input by setting the BCTR.
37
30
P23/RDY
D
General-purpose output-only port
When an external bus is used, this port functions as a
ready input.
36
29
P24/CLK
F
General-purpose output-only port
When an external bus is used, this port functions as a
clock output.
35
28
P25/WR
F
General-purpose output-only port
When an external bus is used, this port functions as a
write signal output.
34
27
P26/RD
F
General-purpose output-only port
When an external bus is used, this port functions as a
read signal output.
*1: MDP-64C-P02
*2: MQP-64C-P01
(Continued)
7
MB89601R Series
(Continued)
Pin no.
Circuit
type
Function
P27/ALE
F
General-purpose output-only port
When an external bus is used, this port functions as an
address latch signal output.
51
P30/ADST
E
General-purpose I/O port
Also serves as the external activation input for the A/D
converter.
This port is a hysteresis input type.
59
52
P31/SCK1
E
General-purpose I/O port
Also serves as the clock I/O for the serial I/O 1.
This port is a hysteresis input type.
60
53
P32/SO1
E
General-purpose I/O port
Also serves as the data output for the serial I/O 1.
This port is a hysteresis input type.
61
54
P33/SI1
E
General-purpose I/O port
Also serves as the data input for the serial I/O 1.
This port is a hystereisis input type.
62
55
P34/EC
E
General-purpose I/O port
Also serves as the external clock input for the 16-bit
timer/counter.
This port is a hysteresis input type.
63
56
P35/PWC
E
General-purpose I/O port
Also serves as the measured-pulse input for the 8-bit
pulse width-counter.
This port is a hysteresis input type.
1
58
P36/WTO
E
General-purpose I/O port
Also serves as the toggle output for the 8-bit pulse-width
counter.
This port is a hysteresis input type.
2
59
P37/PTO
E
General-purpose I/O port
Also serves as the toggle output for the 8-bit PWM timer.
This port is a hysteresis input type.
3 to 6
60 to 63
P40 to P43
G
N-ch open-drain I/O ports
This port is a hysteresis input type.
7
64
P44/BZ
G
N-ch open-drain I/O port
Also serves as a buzzer output.
This port is a hysteresis input type.
8
1
P45/SCK2
G
N-ch open-drain I/O port
Also serves as the clock I/O for the serial I/O 2.
This port is a hysteresis input type.
9
2
P46/SO2
G
N-ch open-drain I/O port
Also serves as the data output for the serial I/O 2.
This port is a hysteresis input type.
*1
MDIP
MQFP*2
33
26
58
*1: MDP-64C-P02
*2: MQP-64C-P01
8
Pin name
(Continued)
MB89601R Series
(Continued)
Pin no.
*1
MDIP
MQFP*2
10
3
11 to 18
Pin name
Circuit
type
Function
P47/SI2
G
N-ch open-drain I/O port
Also serves as the data I/O for the serial I/O 2.
This port is a hysteresis input type.
4 to 11
P50/AN0 to
P57/AN7
H
N-ch open-drain output-only ports
Also serves as the analog input for the A/D converter.
22 to 25
15 to 18
P60/INT0 to
P63/INT3
I
General-purpose input-only ports
Also serves as an external interrupt input.
This port is a hysteresis input type.
26
19
P64
64
57
VCC
—
Power supply pin
32,
57
25,
50
VSS
—
Power supply (GND) pins
19
12
AVCC
—
A/D converter power supply pin
20
13
AVR
—
A/D converter reference voltage input pin
21
14
AVSS
—
A/D converter power supply pin.
Use this port at the same voltage as VSS.
I
General-purpose input-only port
This port is a hysteresis input type.
*1: MDP-64C-P02
*2: MQP-64C-P01
9
MB89601R Series
• External EPROM pins (MB89PV620 only)
Pin no.
10
Pin name
I/O
66
VPP
O
“H” level output pin
66
67
68
69
70
71
72
73
74
67
68
69
70
71
72
73
74
75
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
75
76
77
77
78
79
O1
O2
O3
I
Data input pins
78
80
VSS
O
Power supply (GND) pin
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
I
Data input pins
84
87
CE
O
ROM chip enable pin
Outputs “H” during standby.
85
88
A10
O
Address output pin
86
89
OE
O
ROM output enable pin
Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8
O
Address output pins
90
94
A13
O
91
95
A14
O
92
96
VCC
O
EPROM power supply pin
—
65
76
81
90
N.C.
—
Internally connected pins
Be sure to leave them open.
MDIP
MQFP
65
Function
MB89601R Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
B
C
R
P-ch
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
• Hysteresis input
N-ch
D
• CMOS I/O
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(MB89601R/603 only)
E
• CMOS output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Software pull-up resistor optional
(Continued)
11
MB89601R Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
P-ch
N-ch
G
• N-ch open-drain output
• Hysteresis input
R
P-ch
N-ch
• Pull-up resistor optional
(MB89601R/603 only)
H
• N-ch open-drain output
• Analog input
P-ch
P-ch
N-ch
Analog input
I
• Pull-up resistor optional
• Hysteresis input
R
• Pull-up resistor optional
(MB89601R/603 only)
12
MB89601R Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than P40 to P47, P60 or if higher than the voltage which shows on section “■ Electrical Characteristics”
is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
5. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
13
MB89601R Series
■ PROGRAMMING TO THE EPROM ON THE MB89P601
The MB89P601 is an OTPROM version of the MB89601R series.
1. Features
• 4-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 4-Kbyte PROM is diagrammed below.
Address
Single chip
EPROM mode
(Corresponding addresses on the EPROM programmer)
0000H
I/O
0080H
RAM
0140H
Not available
8000H
0000H
Vacancy
(Read value FFH)
Not available
E000H
7000H
PROM
EPROM
4 KB
4 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P601 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
When the operating ROM area for a single chip is 32 Kbytes (8000H to FFFFH) the PROM can be programmed
as follows:
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 7000H to 7FFFH (note that addresses E000H to FFFFH
while operating as a single chip assign to 7000H to 7FFFH in EPROM mode).
(3) Program to 0000H to 7FFFH with the EPROM programmer.
14
MB89601R Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
FPT-48P-M05
Compatible socket adapter
ROM-48QF-28DP-8L
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
Note: Connect the adapter jumper pin to VSS when using.
15
MB89601R Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV, MBM27C256A-20CZ
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
LCC-32(Rectangle)
Adapter socket part number
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, is diagrammed below.
Address
Corresponding addresses on the EPROM programmer
Single chip
0000H
I/O
0080H
RAM
0480H
Not available
8000H
0000H
PROM
EPROM
32 KB
32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0006H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
16
MB89601R Series
■ BLOCK DIAGRAM
X0
X1
Oscillator
Time-base timer
CMOS I/O Port
P07
P06
P05
P04
P03
P02
P01
P00
CMOS I/O Port
P17
P16
P15
P14
P13
P12
P11
P10
Port 0
Clock controller
8
Reset circuit (WDT)
Port 1
Internal bus
RST
F2MC-8L
CPU
8-bit PWM timer
Port 3
RAM
8
8
ROM
8-bit serial I/O
Port 4
CMOS I/O Port
8
External interrupt
Port 6
N-ch open-drain I/O Port
P37/PTO
P36
P35
P34
P33
P32
P31
P30
P47/SI
P46/SO
P45/SCK
P44
P43
P42
P41
P40
P60/INT
Other pins
VCC, VSS, MOD0, MOD1
Input Port
17
MB89601R Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89601R series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89601R series is structured as illustrated below.
Memory Space
MB89P601
MB89601R
MB89PV620
0000H
0000H
I/O
I/O
0080H
MB89603
0000H
0080H
I/O
0080H
Not available
00F0H
00F0H
RAM
80 B
RAM
1 KB
0100H
Not available
0100H
Register
RAM
80 B
0100H
Register
0140H
Register
0140H
0200H
0480H
Not available
Not available
External area
8000H
E000H
External
ROM
32 KB
FFFFH
18
F000H
ROM
8 KB
ROM
4 KB
FFFFH
FFFFH
MB89601R Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
11
10
9
8
Vacancy Vacancy Vacancy
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
19
MB89601R Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
20
MB89601R Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to 32 banks can be used on the architecture, but only 8 banks can be used on the
MB89601R series due to the restricted internal RAM size. The bank currently in use is indicated by the register
bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
Note: For software development, take care that the usable register banks on the MB89601R/603 are different from
that on the MB89PV620. On the MB89PV620, up to 32 banks can be used.
21
MB89601R Series
■ I/O MAP
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
SPCR
Port 3 pull-up register
05H
Vacancy
06H
Vacancy
07H
Vacancy
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBTC
Clock interrupt control register
Vacancy
0BH
0CH
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
Vacancy
10H
Vacancy
11H
(R)
PDR6
Port 6 data register
12H
(R/W)
CNTR
PWM control register
13H
(W)
COMR
PWM compare register
14H
Vacancy
15H
Vacancy
16H
Vacancy
17H
Vacancy
18H
Vacancy
19H
Vacancy
1AH
Vacancy
1BH
Vacancy
1CH
Vacancy
1DH
Vacancy
1EH
(R/W)
SMR
Serial mode register
1FH
(R/W)
SDR
Serial data register
(Continued)
22
MB89601R Series
(Continued)
Address
Read/write
Register name
Register description
20H
Vacancy
21H
Vacancy
22H
Vacancy
23H
Vacancy
24H
(R/W)
EIC
25H to 7BH
External interrupt control register
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
Note: Do not use vacancies.
23
MB89601R Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 7.0
V
VI1
VSS – 0.3
VCC + 0.3
V
Except P40 to P47, P60
VI2
VSS – 0.3
VSS + 7.0
V
P40 to P47, P60
VO1
VSS – 0.3
VCC + 0.3
V
Except P40 to P47
VO2
VSS – 0.3
VSS + 7.0
V
P40 to P47
“L” level maximum output
current
IOL

20
mA
“L” level average output current
IOLAV

4
mA
Average value (operating
current × operating rate)
“L” level total average output
current
∑IOLAV

40
mA
Average value (operating
current × operating rate)
“L” level total maximum output
current
∑IOL

100
mA
“H” level maximum output
current
IOH

–20
mA
“H” level average output current
IOHAV

–4
mA
Average value (operating
current × operating rate)
“H” level total average output
current
∑IOHAV

–20
mA
Average value (operating
current × operating rate)
“H” level total maximum output
current
∑IOH

–50
mA
Power consumption
PD

300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
Power supply voltage
Input voltage
Output voltage
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
24
MB89601R Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Symbol
Parameter
Power supply voltage
VCC
Operating temperature
TA
Value
Unit
Remarks
Min.
Max.
2.2*
6.0
V
Normal operation assurance range*
MB89601R/603
2.7*
6.0
V
Normal operation assurance range*
MB89P601
1.5
6.0
V
Retains the RAM state in stop mode
–40
+85
°C
* : These values vary with the operating frequency. See Figure 1.
6
5
Operating voltage (V)
Operation assurance range
4
3
2
1
0
1
2
3
4
5
6
7
8
9
Clock operating frequency (MHz)
Note: The shaded area is assured only for the MB89601R/603.
Figure 1
Operating Voltage vs. Clock Operating Frequency
25
MB89601R Series
3. DC Characteristics
(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Pin
Symbol
Condition
Value
Min.
Typ.
Max.
Unit
VIH
P00 to P07,
P10 to P17

0.7 VCC

VCC + 0.3
V
VIHS1
P30 to P37,
MOD0, MOD1,
RST

0.8 VCC

VCC + 0.3
V
VIHS2
P40 to P47,
P60

0.8 VCC

VSS + 6.0
V
VIL
P00 to P07,
P10 to P17

VSS − 0.3

0.3 VCC
V
VILS
P30 to P37,
MOD0, MOD1,
RST,
P40 to P47,
P60
—
VSS − 0.3

0.2 VCC
V
Open-drain output
VD
pin application voltage
P40 to P47
—
VSS − 0.3

VSS + 6.0
V
“H” level output
voltage
VOH
P00 to P07,
P10 to P17,
P30 to P37
IOH = –2.0 mA
4.0


V
VOL
P00 to P07,
P10 to P17,
P30 to P37,
P40 to P47
IOL = +1.8 mA


0.4
V
VOL2
RST
IOL = +4.0 mA


0.4
V
Input leakage
current
ILI1
(Hi-z output leakage
current)
P00 to P07,
P10 to P17,
P30 to P37,
P40 to P47,
P60,
MOD0, MOD1
0.0 V < VI < VCC


±5
µA
Pull-up resistance
P00 to P07,
P10 to P17,
P30 to P37,
P40 to P47,
P60, RST
VI = 0.0 V
25
50
100
kΩ
“H” level input
voltage
“L” level input
voltage
“L” level output
voltage
RPULL
Remarks
Without pullup resistor
(Continued)
26
MB89601R Series
(Continued)
(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Pin
Symbol
Condition
Value
Unit
Remarks
Min.
Typ.
Max.
Normal
operating mode
—
9
15
mA
FC = 8 MHz
—
10
18
mA MB89P601
ICCS
FC = 8 MHz
Sleep mode
—
3
4
mA External clock
ICCH
TA = +25°C
Stop mode
—
—
10
µA
—
10
—
pF
FC = 8 MHz
ICC
Power supply
current*
VCC
Input capacitance CIN
Other than VCC and
f = 1 MHz
VSS
* : The power supply current is measured at the external clock.
Note: A pull-up resistor for P00 to P07, P10 to P17, P40 to P47 and P60 is selectable on MB89601R/603 only.
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
RST “L” pulse width
Symbol
Condition
tZLZH
—
Value
Min.
Max.
16 tXCYL
—
Unit
Remarks
ns
Note: tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
tZLZH
RST
0.2 VCC
0.2 VCC
27
MB89601R Series
(2) Power-on Reset
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Remarks
Min.
Max.
—
50
ms
Power-on reset function only
1
—
ms
Due to repeated operations
Note: Abrupt change in power supply voltage may cause a power-on reset.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
2.0 V
VCC
0.2 V
0.2 V
0.2 V
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
28
Symbol
Pin
Condition
Value
Min.
Max.
Unit
Remarks
Clock frequency
FC
X0, X1
—
1
8
MHz
Clock cycle time
tXYCL
X0, X1
—
125
—
ns
Input clock pulse width
PWH
PWL
X0
—
20
—
ns
External clock
Input clock rising/falling
time
tCR
tCF
X0
—
—
10
ns
External clock
MB89601R Series
X0 and X1 Timing and Conditions
tXCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Clock Conditions
When a crystal
or
ceramic resonator is used
X0
When an external clock is used
X1
X0
X1
Open
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
Symbol
tinst
Value (typical)
Unit
4/FC
µs
Remarks
tinst = 0.5 µs when
operating at FC = 8 MHz
(5) Serial I/O Timing
(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
SCK
Serial clock “L” pulse width
tSLSH
SCK
Condition
Internal shift
clock mode
External shift
clock mode
Value
Unit
Min.
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
1/2 tinst*
—
µs
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
1/2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
29
MB89601R Series
Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SI
External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SI
30
MB89601R Series
(6) Peripheral Input Timing
(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
Pin
Condition
INT
—
Value
Unit
Min.
Max.
2 tinst*
—
µs
2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
tILIH1
INT
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
31
MB89601R Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
(2) “H” Level Output Voltage
VCC – VOH vs. IOH
VOL vs. IOL
VCC – VOH(V)
VCC = 2.0 V VCC = 2.5 V VCC = 3.0 V
1.0
TA = +25°C
0.9
VOL(V)
VCC = 2.0 V VCC = 2.5 V VCC = 3.0 V
0.6
VCC = 4.0 V
TA = +25°C
0.5
VCC = 5.0 V
VCC = 6.0 V
0.4
0.8
VCC = 4.0 V
0.7
VCC = 5.0 V
VCC = 6.0 V
0.6
0.3
0.5
0.2
0.4
0.3
0.1
0.2
0.1
0
0
1
2
3
4
5
6
7
8
10 IOL(mA)
9
0
–1
0
–2
–3
–4
–5 IOH(mA)
(3) “H” Level Input Voltage/“L” Level Input Voltage
VIN vs. VCC
CMOS input
VIN(V)
5.0
TA = +25°C
4.5
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
1
2
3
4
5
6
TA = +25°C
4.5
4.0
0
VIN vs. VCC
CMOS hysteresis input
VIN(V)
5.0
7 VCC(V)
0
VIHS
VILS
1
2
3
4
5
6
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
32
7 VCC(V)
MB89601R Series
(4) Pull-up Resistance
RPULL vs. VCC
RPULL(kΩ)
1000
500
100
50
TA = +25°C
10
1
2
3
4
5
6
7
VCC(V)
33
MB89601R Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1
Symbol
dir
off
ext
#vct
#d8
#d16
dir: b
rel
@
A
AH
AL
T
TH
TL
IX
EP
PC
SP
PS
dr
CCR
RP
Ri
×
(×)
(( × ))
Instruction Symbols
Meaning
Direct address (8 bits)
Offset (8 bits)
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~:
The number of instructions
#:
The number of bytes
Operation: Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
34
MB89601R Series
Table 2
Mnemonic
Transfer Instructions (48 instructions)
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Note
During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
35
MB89601R Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
(Continued)
36
MB89601R Series
(Continued)
Mnemonic
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
~
#
Operation
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
37
L
38
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0
R0,#d8
R0,#d8
dir: 0 dir: 0,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1
R1,#d8
R1,#d8
dir: 1 dir: 1,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2
R2,#d8
R2,#d8
dir: 2 dir: 2,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3
R3,#d8
R3,#d8
dir: 3 dir: 3,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4
R4,#d8
R4,#d8
dir: 4 dir: 4,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5
R5,#d8
R5,#d8
dir: 5 dir: 5,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6
R6,#d8
R6,#d8
dir: 6 dir: 6,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7
R7,#d8
R7,#d8
dir: 7 dir: 7,rel
9
A
B
C
D
E
F
A
SUBC
A
XCH
A, T
XOR
A
AND
A
OR
A
MOV
MOV
CLRB
BBC
INCW
DECW
MOVW
MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
DAS
R7
R6
R5
R4
R3
R2
R1
R0
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
R7
R6
R5
R4
R3
R2
R1
R0
rel
rel
rel
rel
CALLV
BLT
#7
rel
CALLV
BGE
#6
rel
CALLV
BZ
#5
CALLV
BNZ
#4
rel
CALLV
BN
#3
CALLV
BP
#2
CALLV
BC
#1
CALLV
BNC
#0
rel
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
dir: 4 dir: 4,rel
A,ext
ext,A
A,#d16
A,PC
ADDCW SUBCW XCHW
XORW
ANDW
ORW
MOVW
MOVW
CLRB
BBC
INCW
DECW
MOVW
MOVW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
ADDC
CLRB
BBC
INCW
DECW
MOVW
MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
8
A
A
SETC
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@EP
A,@EP
A,@EP
A,@EP
@EP,A
A,@EP
A,@EP
A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel
A,@EP
@EP,A EP,#d16
A,EP
CMPW
CMP
JMP
CALL
PUSHW POPW
MOV
MOVW
CLRC
addr16
addr16
IX
IX
ext,A
PS,A
7
F
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
dir: 6
dir: 6,rel A,@IX +d @IX +d,A
IX,#d16
A,IX
E
6
D
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir
dir,#d8
dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
C
5
B
CLRB
BBC
INCW
DECW
JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
MOV
CMP
ADDC
SUBC
A,#d8
A,#d8
A,#d8
A,#d8
A
A
DIVU
SETI
9
4
8
RORC
7
3
6
ROLC
A
5
PUSHW POPW
MOV
MOVW
CLRI
A
A
A,ext
A,PS
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
MB89601R Series
■ INSTRUCTION MAP
MB89601R Series
■ MASK OPTIONS
Part number
MB89601R
MB89603
MB89P601
MB89PV620
Specifying procedure
Specify when
ordering
masking
Setting not
possible
Setting not
possible
No.
Pull-up resistors
P00 to P07, P10 to P17,
P40 to P47*2, P60*2
Selectable by pin
Fixed to without pullup resistor
P30 to P33*1
Selectable by pin
Can be set per pin
(Software pull-up resistor)
(Software pull-up resistor)
P33 to P37*1
Selectable by 4 pins
Can be set per 4 pins
(Software pull-up resistor)
(Software pull-up resistor)
2
Power-on reset selection
With power-on reset
Without power-on reset
Selectable
Fixed to with power-on Fixed to with power-on
reset
reset
3
Selection of the oscillation
stabilization time
Selectable
Crystal oscillator: (218/FC)
Ceramic oscillator: (212/FC)
Fixed to crystal
oscillator (218/FC)
Fixed to crystal
oscillator (218/FC)
4
Reset pin output
With reset output
Without reset output
Fixed to with reset
output
Fixed to with reset
output
1
Selectable
Fixed to without
pull-up resistor
*1: A pull-up resistor for P30 to P37 is not set when ordering masking. It is set by software.
*2: When a pull-up resistor for P40 to P47 and P60 is selected, the input signal exceeding VCC voltage is not possible.
■ ORDERING INFORMATION
Part number
Package
MB89601RPFV
MB89603PFV
MB89P601PFV
48-pin Plastic SQFP
(FPT-48P-M05)
MB89PV620C-SH
64-pin Ceramic MDIP
(MDP-64C-P02)
MB89PV620CF
64-pin Ceramic MQFP
(MQP-64C-P01)
Remarks
39
MB89601R Series
■ PACKAGE DIMENSIONS
48 pin, Plastic LQFP
(FPT-48P-M05)
+0.20
9.00±0.20(.354±.008)SQ
1.50 –0.10
+.008
.059 –.004
7.00±0.10(.276±.004)SQ
36
25
37
24
5.50
(.217)
REF
8.00
(.315)
NOM
INDEX
Details of "A" part
48
LEAD No.
13
1
12
"A"
+0.08
0.18 –0.03
+.003
.007 –.001
0.50±0.08
(.0197±.0031)
+0.05
0.10±0.10
(STAND OFF)
(.004±.004)
0.127 –0.02
+.002
.005 –.001
0.50±0.20
(.020±.008)
0
0.10(.004)
C
10°
1994 FUJITSU LIMITED F48013S-2C-4
Dimensions in mm (inches).
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
2.54±0.25
(.100±.010)
33.02(1.300)REF
INDEX AREA
0.25±0.05
(.010±.002)
1.27±0.25
(.050±.010)
10.16(.400)MAX
1.778±0.25
(.070±.010)
C
19.05±0.30
(.750±.012)
+0.13
0.46 –0.08
+.005
.018 –.003
55.12(2.170)REF
0.90±0.13
(.035±.005)
3.43±0.38
(.135±.015)
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches).
40
MB89601R Series
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
+0.40
1.20 –0.20
+.016
.047 –.008
1.00±0.25
(.039±.010)
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
0.40±0.10
(.016±.004)
18.00(.709)
TYP
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP
C
10.82(.426)
0.15±0.05 MAX
(.006±.002)
1994 FUJITSU LIMITED M64004SC-1-3
Dimensions in mm (inches).
41
MB89601R Series
MEMO
42
MB89601R Series
MEMO
43
MB89601R Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, USA
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
F9703
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
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standard applications (computers, office automation and other
office equipments, industrial, communications, and
measurement equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
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