FUJITSU SEMICONDUCTOR DATA SHEET DS07-13715-3E 16-bit Proprietary Microcontrollers CMOS F2MC-16LX MB90560/565 Series MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 ■ DESCRIPTION The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and process control applications that require high-speed real-time processing. The device features a multi-function timer able to output a programmable waveform. The microcontroller instruction set is based on the same AT architecture as the F2MC-8L and F2MC-16L families with additional instructions for high-level languages, extended addressing modes, enhanced signed multiplication and division instructions, and a complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word (32-bit) data. ■ FEATURES • Clock • Internal oscillator circuit and PLL clock multiplication circuit • Oscillation clock Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the oscillation clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation clock multiplied by one to four (4 MHz to 16 MHz for a 4 MHz base oscillation) . • Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V) • Maximum CPU memory space : 16 MB • 24-bit addressing • Bank addressing (Continued) ■ PACKAGES 64-pin plastic QFP 64-pin plastic LQFP 64-pin plastic SH-DIP (FPT-64P-M06) (FPT-64P-M09) (DIP-64P-M01) MB90560/565 Series (Continued) • Instruction set • Bit, byte, word, and long word data types • 23 different addressing modes • Enhanced calculation precision using a 32-bit accumulator • Enhanced signed multiplication and division instructions and RETI instruction • Instruction set designed for high level language (C) and multi-tasking • Uses a system stack pointer • Symmetric instruction set and barrel shift instructions • Program patch function (2 address pointers) . • 4-byte instruction queue • Interrupt function • Priority levels are programmable • 32 interrupts • Data transfer function • Extended intelligent I/O service function : Up to 16 channels • Low-power consumption modes • Sleep mode (CPU operating clock stops.) • Timebase timer mode (Only oscillation clock and timebase timer continue to operate.) • Stop mode (Oscillation clock stops.) • CPU intermittent operation mode (The CPU operates intermittently at the specified interval.) • Package • LQFP-64P (FTP-64P-M09 : 0.65 mm pin pitch) • QFP-64P (FTP-64P-M06 : 1.00 mm pin pitch) • SH-DIP (DIP-64P-M01 : 1.778 mm pin pitch) • Process : CMOS technology ■ PERIPHERAL FUNCTIONS (RESOURCES) • • • • • I/O ports : 51 ports (max.) Timebase timer : 1 channel Watchdog timer : 1 channel 16-bit reload timer : 2 channel 5 Multi-function timer • 16-bit free-run timer : 1 channel • Output compare : 6 channels Can output an interrupt request when a match occurs between the count in the 16-bit freerun timer and the value set in the compare register. • Input capture : 4 channels On detecting an active edge on the input signal from an external input pin, copies the count value of the 16bit freerun timer to the input capture data register and generates an interrupt request. • 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) The period and duty of the output pulse can be set by the program. • Waveform generator (8-bit timer : 3 channels) • UART : 2 channels • Full-duplex, double-buffered (8-bit) • Can be set to asynchronous or clock synchronous serial transfer (I/O expansion serial) operation • DTP/external interrupt circuit (8 channels) • External interrupts can activate the extended intelligent I/O service. • Generates interrupts in response to external interrupt inputs. 2 MB90560/565 Series • Delayed interrupt generation module • Generates an interrupt request for task switching. • 8/10-bit A/D converter : 8 channels • 8-bit or 10-bit resolution selectable 3 MB90560/565 Series ■ PRODUCT LINEUP 1. MB90560 Series Part Number Classification MB90F562/B MB90562/A Internal flash memory product MB90561/A Internal mask ROM product MB90V560 Evaluation product ROM size 64 Kbytes 32 Kbytes No ROM RAM size 2 Kbytes 1 Kbytes 4 Kbytes No Dedicated emulator power supply* CPU functions Number of instructions : 351 Minimum instruction execution time : 62.5 ns for a 4 MHz oscillation (with ×4 multiplier) Addressing modes : 23 modes Program patch function : 2 address pointers Maximum memory space : 16 Mbytes Ports I/O ports (CMOS) : 51 UART Full-duplex, double-buffered Clock synchronous or asynchronous operation selectable Can be used as I/O serial Internal dedicated baud rate generator 2 channels 16-bit reload timer 16-bit reload timer operation 2 channels Multi-function timer 16-bit free-run timer × 1 channel Output compare × 6 channels Input capture × 4 channels 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) Waveform generator (8-bit timer × 3 channels) 3-phase waveform output, deadtime output 8/10-bit A/D converter 8 channels (multiplexed input) 8-bit or 10-bit resolution selectable Conversion time : 6.13 µs (min.) (for maximum machine clock speed 16 MHz) DTP/external interrupts 8 channels (8 channels available, shared with A/D input) Interrupt triggers : “L” → “H” edge, “H” → “L” edge, “L” level, “H” level (selectable) Low power consumption modes Sleep mode, timebase timer mode, stop mode, and CPU intermittent operation mode Process CMOS Operating voltage 5 V ± 10% * : DIP switch setting (S2) when using the emulation pod (MB2145-507) . Refer to “2.7 Dedicated Emulator Power Supply” in the “MB2145-507 Hardware Manual” for details. 4 MB90560/565 Series 2. MB90565 Series Part Number Classification MB90F568 MB90568 Internal flash memory product MB90567 Internal mask ROM product ROM size 128 Kbytes 96 Kbytes RAM size 4 Kbytes 4 Kbytes Dedicated emulator power supply* CPU functions Number of instructions : 351 Minimum instruction execution time : 62.5 ns for a 4 MHz oscillation (with ×4 multiplier) Addressing modes : 23 modes Program patch function : 2 address pointers Maximum memory space : 16 Mbytes Ports I/O ports (CMOS) : 51 UART Full-duplex, double-buffered Clock synchronous or asynchronous operation selectable Can be used as I/O serial Internal dedicated baud rate generator 2 channels 16-bit reload timer 16-bit reload timer operation 2 channels Multi-function timer 16-bit free-run timer × 1 channel Output compare × 6 channels Input capture × 4 channels 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) Waveform generator (8-bit timer × 3 channels) 3-phase waveform output, deadtime output 8/10-bit A/D converter 8 channels (multiplexed input) 8-bit or 10-bit resolution selectable Conversion time : 6.13 µs (min.) (for maximum machine clock speed 16 MHz) DTP/external interrupts 8 channels (8 channels available, shared with A/D input) Interrupt triggers : “L” → “H” edge, “H” → “L” edge, “L” level, “H” level (selectable) Low power consumption modes Sleep mode, timebase timer mode, stop mode, and CPU intermittent operation mode Process CMOS Operating voltage 3.3 V ± 0.3 V * : DIP switch setting (S2) when using the emulation pod (MB2145-507) . Refer to “2.7 Dedicated Emulator Power Supply” in the “MB2145-507 Hardware Manual” for details. 5 MB90560/565 Series ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB90561/A MB90562/A MB90F562/B MB90567 MB90568 MB90F568 MB90V560 FPT-64P-M09 (LQFP-0.65 mm) × FPT-64P-M06 (QFP-1.00 mm) × DIP-64P-M01 (SH-DIP) PGA-256C-A01 (PGA) × : Available × : Not available × × × × × × × × Note : See the “Package Dimensions” section for details of each package. 6 × MB90560/565 Series ■ PIN ASSIGNMENTS 64 63 62 61 60 59 58 57 56 55 54 53 52 P43/PPG2 P42/PPG1 P41/PPG0 P40/SCK0 P37/SOT0 P36/SIN0 C* VCC P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2 P31/RTO1 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/RTO0 VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/TO1 P22/TIN1 P21/TO0 P20/TIN0 P17/FRCK P16/INT6 P15/INT5 P14/INT4 P13/INT3 P12/INT2 P11/INT1 P10/INT0 P07 RST MD1 MD2 X0 X1 VSS P00 P01 P02 P03 P04 P05 P06 20 21 22 23 24 25 26 27 28 29 30 31 32 P44/PPG3 P45/PPG4 P46/PPG5 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7/DTTI MD0 (FPT-64P-M06) * : N.C. on the MB90F568, MB90567, and MB90568. (Continued) 7 MB90560/565 Series 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P44/PPG3 P43/PPG2 P42/PPG1 P41/PPG0 P40/SCK0 P37/SOT0 P36/SIN0 C* VCC P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2 P31/RTO1 P30/RTO0 VSS (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/TO1 P22/TIN1 P21/TO0 P20/TIN0 P17/FRCK P16/INT6 P15/INT5 P14/INT4 P13/INT3 P12/INT2 P11/INT1 P10/INT0 P63/INT7/DTTI MD0 RST MD1 MD2 X0 X1 VSS P00 P01 P02 P03 P04 P05 P06 P07 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P45/PPG4 P46/PPG5 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 (FPT-64P-M09) * : N.C. on the MB90F568, MB90567, and MB90568. (Continued) 8 MB90560/565 Series (Continued) (TOP VIEW) C* P36/SIN0 P37/SOT0 P40/SCK0 P41/PPG0 P42/PPG1 P43/PPG2 P44/PPG3 P45/PPG4 P46/PPG5 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7/DTTI MD0 RST MD1 MD2 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2 P31/RTO1 P30/RTO0 VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/TO1 P22/TIN1 P21/TO0 P20/TIN0 P17/FRCK P16/INT6 P15/INT5 P14/INT4 P13/INT3 P12/INT2 P11/INT1 P10/INT0 P07 P06 P05 P04 P03 P02 P01 P00 (DIP-64P-M01) (Only support MB90F562/B, MB90561/A, and MB90562/A.) * : Not support on the MB90F568, MB90567, and MB90568. 9 MB90560/565 Series ■ PIN DESCRIOTIONS Pin No. QFPM06 LQFPM09 SDIP State/ Circuit Pin Function Name Type* at Reset 23, 24 22, 23 30, 31 X0, X1 A Oscillator 20 19 27 RST B Reset input 26 to 33 25 to 32 33 to 40 P00 to P07 C 34 to 40 33 to 39 41 to 47 40 48 41 49 I/O ports INT0 to INT6 Can be used as interrupt request inputs ch0 to ch6. In standby mode, these pins can operate as inputs by setting the bits corresponding to EN0 to EN6 to “1” and setting as input ports. When used as a port, set the corresponding bits in the analog input enable register (ADER) to “port”. C FRCK I/O port TIN0 External clock input pin for the freerun timer. This pin can be used as an input when set as the clock input for the freerun timer and set as an input port. When used as a port, set the corresponding bit in the analog input enable register (ADER) to “port”. C D Port inputs (Hi-Z outputs) P21 43 42 50 TO0 43 51 TIN1 D 44 52 TO1 D 45 to 48 53 to 56 IN0 to IN3 Event output pin for reload timer ch0. Output operates when event output is enabled. External clock input pin for reload timer ch1. This pin can be used as an input when set as the external clock input and set as an input port. I/O port D P24 to P27 46 to 49 External clock input pin for reload timer ch0. This pin can be used as an input when set as the external clock input and set as an input port. I/O port P23 45 I/O port I/O port P22 44 External reset input pin P10 to P16 P20 42 Connect oscillator to these pins. If using an external clock, leave X1 open. I/O ports P17 41 Description Event output pin for reload timer ch1. Output operates when event output is enabled. I/O ports D Trigger input pins for input capture ch0 to ch3. These pins can be used as an input when set as an input capture trigger input and set as an input port. * : See “■ I/O CIRCUITS” for details of the circuit types. (Continued) 10 MB90560/565 Series Pin No. QFPM06 LQFPM09 SDIP Pin Name Circuit Type* State/ Function at Reset P30 to P35 51 to 56 50 to 55 58 to 63 RTO0 to RTO5 I/O ports Event output pins for the output compare and waveform generator output pins. The pins output the specified waveform generated by the waveform generator. If not using waveform generation, these terminals enable output compare event output to use as output compare outputs. When used as a port, set the corresponding bits in the analog input enable register (ADER) to “port”. E P36 59 58 2 SIN0 I/O port D Port inputs (Hi-Z) P37 60 59 3 SOT0 62 to 64, 1 to 3 60 61 to 64, 1, 2 4 SCK0 Serial data output pin for UART ch0. Output operates when UART ch0 output is enabled. I/O port Serial clock I/O pin for UART ch0. Output operates when UART ch0 clock output is enabled. D P41 to P46 5 to 10 PPG0 to PPG5 I/O ports D P50 to P57 Output pins for PPG ch0 to ch5. The outputs operate when output is enabled for PPG ch0 to ch5. I/O ports F Analog inputs AVCC Power supply input 20 AVR G 21 AVSS 4 to 11 3 to 10 11 to 18 12 11 19 13 12 14 13 AN0 to AN7 Serial data input pin for UART ch0. This pin is used continuously when input operation is enabled for UART ch0. In this case, do not use as a general input pin. I/O port D P40 61 Description Analog input pins for the A/D converter. Input is available when the corresponding analog input enable register bits are set. (ADER : bit0 to bit7) VCC power supply input pin for A/D converter. ReferReference voltage input pin for A/D converter. ence voltEnsure that the voltage does not exceed VCC. age input Power supply input VSS power supply input pin for A/D converter. * : See “■ I/O CIRCUITS” for details of the circuit types. (Continued) 11 MB90560/565 Series (Continued) Pin No. QFPM06 LQFPM09 SDIP Pin Name State/ Circuit Function Type*1 at Reset P60 15 14 22 SIN1 I/O port Serial data input pin for UART ch1. This pin is used continuously when input operation is enabled for UART ch1. In this case, do not use as a general input pin. D P61 16 15 23 SOT1 I/O port 18 16 17 24 SCK1 Serial data output pin for UART ch1. Output operates when UART ch1 output is enabled. D P62 17 D I/O port Port input Serial clock I/O pin for UART ch1. (Hi-Z) Output operates when UART ch1 clock output is enabled. P63 I/O port INT7 This pin can be used as interrupt request input ch7. In standby mode, this pin can operate as an input by setting the bit corresponding to EN7 to “1” and setting as an input port. 25 D Fixed pin level input pin when RTO0 to RTO5 pins are used. Input is enabled when “input enabled” set in the waveform generator. DTTI Capacitor Capacitor pin for stabilizing the power supply. pin, powConnect an external ceramic capacitor of approxer supply imately 0.1 µF. input 58 57 1 C*2 19 18 26 MD0 B Input pin for setting the operation mode. Connect directly to VCC or VSS. 21 20 28 MD1 B Mode Input pin for setting the operation mode. input pins Connect directly to VCC or VSS. 22 21 29 MD2 B Input pin for setting the operation mode. Connect directly to VSS. 25, 50 24, 49 32, 57 VSS 57 56 64 VCC Power supply inputs *1 : See “■ I/O CIRCUITS” for details of the circuit types. *2 : N.C. on the MB90F568, MB90567, and MB90568 12 Description Power supply (GND) input pin MB90560 series is power supply (5 V) input pin MB90565 series is power supply (3.3 V) input pin MB90560/565 Series ■ I/O CIRCUITS Type Circuit Remarks X1 Xout Rf A X0 • Oscillation circuit Internal oscillation feedback resistor (Rf) Nch Pch Pch Nch Standby control signal • CMOS hysteresis reset input pin B Reset input Pull-up control Rp C Pch Pout Nch Nout Input signal • CMOS hysteresis I/O pin with pull-up control CMOS output CMOS hysteresis input (with input cutoff function in standby mode) Internal pull-up resistor (Rp) < Note > • The pull-up resistor is active when the port is set as an input. Standby control signal Pch Pout Nch Nout D Input signal Standby control signal • CMOS hysteresis I/O pin CMOS output CMOS hysteresis input (with input cutoff function in standby mode) < Notes > • The I/O port output and internal resource output share the same output buffer. • The I/O port input and internal resource input share the same input buffer. (Continued) 13 MB90560/565 Series (Continued) Type Circuit Remarks Pch Pout Nch Nout E • CMOS I/O pin CMOS output CMOS hysteresis input (with input cutoff function in standby mode) < IOL = 12 mA > Hysteresis input Standby control signal Pch Pout Nch Nout Input signal F Standby control signal A/D converter analog input • Analog/CMOS hysteresis I/O pin CMOS output CMOS hysteresis input (with input cutoff function in standby mode) Analog input (Analog input to A/D converter is enabled when “1” is set in the corresponding bit in the analog input enable register (ADER) .) • The I/O port output and internal resource output share the same output buffer. • The I/O port input and internal resource input share the same input buffer. • A/D converter (AVR) voltage input pin Pch Pch G 14 Nch Nch AVR input Analog input enable signal from A/D converter MB90560/565 Series ■ HANDLING DEVICES Take note of the following nine points when handling devices : • Do not exceed maximum rated voltage (to prevent latch-up) • Supply voltage stability • Power-on precautions • Treatment of unused pins • Treatment of A/D converter power supply pins • Notes on using an external clock • Power supply pins • Sequence for connecting and disconnecting the A/D converter power supply and analog input pins • Notes on using the DIV A, Ri and DIVW A, RWi instructions • Device Handling Precautions (1) Do not exceed maximum rated voltage (to prevent latch-up) Do not apply a voltage grater than VCC or less than VSS to the MB90560/565 series input or output pins. Also ensure that the voltage between VCC and VSS does not exceed the rating. Applying a voltage in excess of the ratings may result in latch-up causing thermal damage to circuit elements. Similarly, when connecting or disconnecting the power to the analog power supply (AVCC, AVR) and analog inputs (AN0 to AN7) , ensure that the analog power supply voltages do not exceed the digital voltage (VCC) . (2) Supply voltage stability Rapid changes in the VCC supply voltage may cause the device to misoperate. Accordingly, ensure that the VCC power supply is stable. The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at the supply frequency (50 to 60 Hz) of 10% or less of VCC and a transient fluctuation in the voltage of 0.1 V/ms or less when turning the power supply on or off. (3) Power-on precautions To prevent misoperation of the internal regulator circuit, ensure that the voltage rise time at power-on is at least 50 µs (between 0.2 V to 2.7 V) . (4) Treatment of unused pins Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to latchup. Always pull-up or pull-down unused pins using a 2 kΩ or larger resistor. If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same way as input pins. (5) Treatment of A/D converter power supply pins If not using the A/D converter, connect the analog power supply pins so that AVCC = AVR = VCC and AVSS = VSS. (6) Notes on using an external clock Even if using an external clock, an oscillation stabilization delay time occurs after a power-on reset and when recovering from stop mode in the same way as when an oscillator is connected. When using an external clock, drive the X0 pin only and leave the X1 pin open. 15 MB90560/565 Series X0 OPEN X1 MB90560/565 series Example of using an external clock (7) Power supply pins The multiple VCC and VSS pins are connected together in the internal device design so as to prevent misoperation such as latch-up. However, always connect all VCC and VSS pins to the same potential externally to minimize spurious radiation, prevent misoperation of strobe signals due to increases in the ground level, and maintain the overall output current rating. Also, ensure that the impedance of the VCC and VSS connections to the power supply is as low as possible. To minimize these problems, connect a bypass capacitor of approximately 0.1 µF between VCC and VSS. Connect the capacitor close to the VCC and VSS pins. (8) Sequence for connecting and disconnecting power supply Do not apply voltage to the A/D converter power supply pins (AVCC, AVR, AVSS) or analog inputs (AN0 to AN7) until the digital power supply (VCC) is turned on. When turning the device off, turn off the digital power supply after disconnecting the A/D converter power supply and analog inputs. When turning the power on or off, ensure that AVR does not exceed AVCC. When using the I/O ports that share pins with the analog inputs, ensure that the input voltage does not exceed AVCC (turning the analog and digital power supplies on and off simultaneously is OK) . (9) Conditions when output from ports 0 and 1 is undefined After turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabilization delay time controlled by the regulator circuit (during the power-on reset) if the RST pin level is “H”. When the RST pin level is “L”, ports 0 and 1 go to high impedance. Figures 1 and 2 show the timing (for the MB90F562/B and MB90V560) . Note that this undefined output period does not occur on products without an internal regulator circuit as these products do not have an oscillation stabilization delay time. (MB90561/A, MB90562/A, MB90F568, and MB90567/8) 16 MB90560/565 Series • Figure 1 Timing chart for undefined output from ports 0 and 1 (When RST pin level is “H”) Oscillation stabilization delay time*2 Regulator circuit stabilization delay time*1 VCC (Power supply pin) PONR (Power-on reset) signal RST (External asynchronous reset) signal RST (Internal reset) signal Oscillation clock signal KA (Internal operating clock A) signal KB (Internal operating clock B) signal PORT (port output) signal Undefined output time *1 : Regulator circuit oscillation stabilization delay time : 217/Oscillation clock frequency (approx. 8.19 ms for a 16 MHz oscillation clock frequency) *2 : Oscillation stabilization delay time : 218/Oscillation clock frequency (approx. 16.38 ms for a 16 MHz oscillation clock frequency) 17 MB90560/565 Series • Figure 2 Timing chart for ports 0 and 1 going to high impedance state (When RST pin level is “L”) Oscillation stabilization delay time*2 Regulator circuit stabilization delay time*1 VCC (Power supply pin) PONR (Power-on reset) signal RST (External asynchronous reset) signal RST (Internal reset) signal Oscillation clock signal KA (Internal operating clock A) signal KB (Internal operating clock B) signal PORT (port output) signal High impedance *1 : Regulator circuit oscillation stabilization delay time : 217/Oscillation clock frequency (approx. 8.19 ms for a 16 MHz oscillation clock frequency) *2 : Oscillation stabilization delay time : 218/Oscillation clock frequency (approx. 16.38 ms for a 16 MHz oscillation clock frequency) (10) Notes on using the DIV A, Ri and DIVW A, RWi instructions The location in which the remainder value produced by the signed division instructions “DIV A, Ri” and “DIVW A, RWi” is stored depends on the bank register. The remainder is stored in an address in the memory bank specified in the bank register. Set the bank register to “00H” when using the “DIV A, Ri” and “DIVW A, RWi” instructions. (11) Notes on using REALOS The extended intelligent I/O service (EI2OS) cannot be used when using REALOS. (12) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the freerunning frequency of the self oscillation circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed. 18 MB90560/565 Series ■ BLOCK DIAGRAM X0, X1 RST MD0 to MD2 F2MC-16LX CPU Clock control circuit Interrupt controller RAM SIN0 SOT0 SCK0 UART ch0 SIN1 SOT1 SCK1 UART ch1 AVCC AVR AVSS AN0 to AN7 TO0 TIN0 TO1 TIN1 INT0 to INT7 Internal data bus ROM 8/16-bit PPG timer ch0 to ch5* PPG0 to PPG5 Input capture ch0 to ch3 IN0 to IN3 16-bit freerun timer 8/10-bit A/D converter FRCK Output compare ch0 to ch5 16-bit reload timer ch0 Waveform generator circuit RTO0 RTO1 RTO2 RTO3 RTO4 RTO5 DTTI 16-bit reload timer ch1 DTP/ external interrupts I/O ports (Ports 0, 1, 2, 3, 4, 5, and 6) P00 P10 P20 P30 P40 P50 P60 P07 P17 P27 P37 P46 P57 P63 * : Channel numbers when used as 8-bit timers. Three channels (ch1, ch3, and ch5) are available when used as 16-bit timers. Note: The I/O ports share pins with the various peripheral functions (resources) . See the Pin Assignment and Pin Description sections for details. Note that, if a pin is used by a peripheral function (resource) , it may not be used as an I/O port. 19 MB90560/565 Series ■ MEMORY MAP Single chip mode (with ROM mirror function) FFFFFFH ROM area Address #1 FF0000H 010000H ROM area (image of FF bank) Address #2 004000H Address #3 RAM area Registers 000100H 0000C0H Peripherals Access prohibited 000000H Part No. Address#1 Address#2 Address#3 MB90561/A FF8000H 008000H 000500H MB90562/A FF0000H 004000H 000900H MB90F562/B FF0000H 004000H 000900H MB90567 FE8000H 004000H 001100H MB90568 FE0000H 004000H 001100H MB90F568 FE0000H 004000H 001100H MB90V560 H* H* 001100H FE0000 004000 * : “V” products do not contain internal ROM. Treat this address as the ROM decode area used by the tools. Memory map of MB90560/565 series Notes : • When specified in the ROM mirror function register, the upper part of 00 bank (“004000H to 00FFFFH”) contains a mirror of the data in the upper part of FF bank (“FF4000H to FFFFFFH”) . • See “10. ROM Mirror Function Selection Module” in the Peripheral Functions section for details of the ROM mirror function settings. Remarks : • The ROM mirror function is provided so the C compiler’s small memory model can be used. • The lower 16 bits of the FF bank and 00 bank addresses are the same. However, as the FF bank ROM area exceeds 48 KBytes, the entire ROM data area cannot be mirrored in 00 bank. • When using the C compiler’s small memory model, locating data tables in the area “FF4000H to FFFFFFH” makes the image of the data visible in the “004000H to 00FFFFH” area. This means that data tables located in ROM can be referenced without needing to declare far pointers. 20 MB90560/565 Series ■ I/O MAP AbbreviatAddress ed Register Name Register name Read/ Write Resource Name Initial Value 000000H PDR0 Port 0 data register R/W Port 0 XXXXXXXXB 000001H PDR1 Port 1 data register R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 data register R/W Port 2 XXXXXXXXB 000003H PDR3 Port 3 data register R/W Port 3 XXXXXXXXB 000004H PDR4 Port 4 data register R/W Port 4 XXXXXXXXB 000005H PDR5 Port 5 data register R/W Port 5 XXXXXXXXB 000006H PDR6 Port 6 data register R/W Port 6 XXXXXXXXB 000007H to 00000FH Access prohibited 000010H DDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0B 000011H DDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0B 000012H DDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0B 000013H DDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0B 000014H DDR4 Port 4 direction register R/W Port 4 X 0 0 0 0 0 0 0B 000015H DDR5 Port 5 direction register R/W Port 5 0 0 0 0 0 0 0 0B 000016H DDR6 Port 6 direction register R/W Port 6 XXXX 0 0 0 0B 000017H ADER Analog input enable register R/W Port 5, A/D converter 1 1 1 1 1 1 1 1B 000018H to 00001FH Access prohibited 000020H SMR0 Mode register ch0 000021H SCR0 Control register ch0 SIDR0 Input data register ch0 R SODR0 Output data register ch0 W 000022H R/W 0 0 0 0 0 X 0 0B W, R/W 0 0 0 0 0 1 0 0B UART0 XXXXXXXXB 000023H SSR0 Status register ch0 R, R/W 0 0 0 0 1 0 0 0B 000024H SMR1 Mode register ch1 R/W 0 0 0 0 0 X 0 0B 000025H SCR1 Control register ch1 W, R/W 0 0 0 0 0 1 0 0B SIDR1 Input data register ch1 R SODR1 Output data register ch1 W 000026H 000027H SSR1 Status register ch1 000028H 000029H UART1 R, R/W XXXXXXXXB 0 0 0 0 1 0 0 0B Access prohibited CDCR0 Communication prescaler control register ch0 R/W Communication prescaler 0 XXX 0 0 0 0B (Continued) 21 MB90560/565 Series AbbreviatAddress ed Register Name Register name 00002AH 00002BH Read/ Write Resource Name Initial Value Communication prescaler 0 XXX 0 0 0 0B Access prohibited CDCR1 Communication prescaler control register ch1 00002CH to 00002FH R/W Access prohibited 000030H ENIR DTP/external interrupt enable register R/W 000031H EIRR DTP/external interrupt request register R/W Request level setting register (lower) R/W Request level setting register (upper) R/W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 000032H 000033H ELVR 0 0 0 0 0 0 0 0B DTP/external interrupts XXXXXXXXB 0 0 0 0 0 0 0 0B 000034H ADCS0 A/D control status register (lower) R/W 000035H ADCS1 A/D control status register (upper) W, R/W 000036H ADCR0 A/D data register (lower) R 000037H ADCR1 A/D data register (upper) R, W 0 0 0 0 0 XXXB 000038H PRLL0 PPG reload register ch0 (lower) R/W XXXXXXXXB 000039H PRLH0 PPG reload register ch0 (upper) R/W XXXXXXXXB 00003AH PRLL1 PPG reload register ch1 (lower) R/W XXXXXXXXB 00003BH PRLH1 PPG reload register ch1 (upper) R/W 8/16-bit PPG timer XXXXXXXXB 00003CH PPGC0 PPG control register ch0 (lower) R/W 0 0 0 0 0 0 0 1B 00003DH PPGC1 PPG control register ch1 (upper) R/W 0 0 0 0 0 0 0 1B 00003EH PCS01 PPG clock control register ch0, ch1 R/W 0 0 0 0 0 0 XXB 00003FH 8/10-bit A/D converter 0 0 0 0 0 0 0 0B XXXXXXXXB Access prohibited 000040H PRLL2 PPG reload register ch2 (lower) R/W XXXXXXXXB 000041H PRLH2 PPG reload register ch2 (upper) R/W XXXXXXXXB 000042H PRLL3 PPG reload register ch3 (lower) R/W XXXXXXXXB 000043H PRLH3 PPG reload register ch3 (upper) R/W 8/16-bit PPG timer XXXXXXXXB 000044H PPGC2 PPG control register ch2 (lower) R/W 0 0 0 0 0 0 0 1B 000045H PPGC3 PPG control register ch3 (upper) R/W 0 0 0 0 0 0 0 1B 000046H PCS23 PPG clock control register ch2, ch3 R/W 0 0 0 0 0 0 XXB 000047H Access prohibited 000048H PRLL4 PPG reload register ch4 (lower) R/W XXXXXXXXB 000049H PRLH4 PPG reload register ch4 (upper) R/W XXXXXXXXB 00004AH PRLL5 PPG reload register ch5 (lower) R/W 8/16-bit PPG timer XXXXXXXXB 00004BH PRLH5 PPG reload register ch5 (upper) R/W XXXXXXXXB 00004CH PPGC4 PPG control register ch4 (lower) R/W 0 0 0 0 0 0 0 1B (Continued) 22 MB90560/565 Series AbbreviatAddress ed Register Name Register name Read/ Write 00004DH PPGC5 PPG control register ch5 (upper) R/W 00004EH PCS45 PPG clock control register ch4, ch5 R/W 00004FH Resource Name 8/16-bit PPG timer Initial Value 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 XXB Access prohibited 000050H TMRR0 8-bit reload register ch0 R/W XXXXXXXXB 000051H DTCR0 8-bit timer control register ch0 R/W 0 0 0 0 0 0 0 0B 000052H TMRR1 8-bit reload register ch1 R/W XXXXXXXXB Waveform generator 000053H DTCR1 8-bit timer control register ch1 R/W 000054H TMRR2 8-bit reload register ch2 R/W XXXXXXXXB 000055H DTCR2 8-bit timer control register ch2 R/W 0 0 0 0 0 0 0 0B 000056H SIGCR Waveform control register R/W 0 0 0 0 0 0 0 0B 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH Access prohibited CPCLR TCDT TCCS 00005EH 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H IPCP0 IPCP1 IPCP2 IPCP3 ICS01 000069H 00006AH 00006BH to 00006EH Compare clear register (lower) R/W XXXXXXXXB Compare clear register (upper) R/W XXXXXXXXB Timer data register (lower) R/W Timer data register (upper) R/W Timer control/status register (lower) R/W 0 0 0 0 0 0 0 0B Timer control/status register (upper) R/W 0 XX 0 0 0 0 0B 16-bit freerun timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Access prohibited 00005FH 000060H 0 0 0 0 0 0 0 0B Input capture data register ch0 (lower) R XXXXXXXXB Input capture data register ch0 (upper) R XXXXXXXXB Input capture data register ch1 (lower) R XXXXXXXXB Input capture data register ch1 (upper) R XXXXXXXXB Input capture data register ch2 (lower) R Input capture data register ch2 (upper) R XXXXXXXXB Input capture data register ch3 (lower) R XXXXXXXXB Input capture data register ch3 (upper) R XXXXXXXXB R/W 0 0 0 0 0 0 0 0B Input capture control register 01 Input capture XXXXXXXXB Access prohibited ICS23 Input capture control register 23 R/W Input capture 0 0 0 0 0 0 0 0B Access prohibited (Continued) 23 MB90560/565 Series AbbreviatAddress ed Register Name 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH ROMM OCCP0 OCCP1 OCCP2 OCCP3 OCCP4 OCCP5 Register name ROM mirror function selection register Read/ Write Resource Name Initial Value W ROM mirror function selection module XXXXXXX 1B Compare register ch0 (lower) R/W XXXXXXXXB Compare register ch0 (upper) R/W XXXXXXXXB Compare register ch1 (lower) R/W XXXXXXXXB Compare register ch1 (upper) R/W XXXXXXXXB Compare register ch2 (lower) R/W XXXXXXXXB Compare register ch2 (upper) R/W XXXXXXXXB Compare register ch3 (lower) R/W XXXXXXXXB Compare register ch3 (upper) R/W XXXXXXXXB Compare register ch4 (lower) R/W Compare register ch4 (upper) R/W Compare register ch5 (lower) R/W XXXXXXXXB Compare register ch5 (upper) R/W XXXXXXXXB Output compare XXXXXXXXB XXXXXXXXB 00007CH OCS0 Compare control register ch0 (lower) R/W 0 0 0 0 XX 0 0B 00007DH OCS1 Compare control register ch1 (upper) R/W XXX 0 0 0 0 0B 00007EH OCS2 Compare control register ch2 (lower) R/W 0 0 0 0 XX 0 0B 00007FH OCS3 Compare control register ch3 (upper) R/W XXX 0 0 0 0 0B 000080H OCS4 Compare control register ch4 (lower) R/W 0 0 0 0 XX 0 0B 000081H OCS5 Compare control register ch5 (upper) R/W XXX 0 0 0 0 0B 000082H TMCSR0 : L Timer control status register ch0 (lower) R/W 0 0 0 0 0 0 0 0B 000083H TMCSR0 : H Timer control status register ch0 (upper) R/W XXXX 0 0 0 0B 000084H 000085H TMR0 16-bit timer register ch0 (lower) R XXXXXXXXB TMRLR0 16-bit reload register ch0 (lower) W XXXXXXXXB TMR0 16-bit timer register ch0 (upper) R XXXXXXXXB TMRHR0 16-bit reload register ch0 (upper) W 16-bit reload timer XXXXXXXXB 000086H TMCSR1 : L Timer control status register ch1 (lower) R/W 000087H TMCSR1 : H Timer control status register ch1 (upper) R/W XXXX 0 0 0 0B 000088H 000089H 0 0 0 0 0 0 0 0B TMR1 16-bit timer register ch1 (lower) R XXXXXXXXB TMRLR1 16-bit reload register ch1 (lower) W XXXXXXXXB TMR1 16-bit timer register ch1 (upper) R XXXXXXXXB TMRHR1 16-bit reload register ch1 (upper) W XXXXXXXXB (Continued) 24 MB90560/565 Series AbbreviatAddress ed Register Name Register name 00008AH to 00008BH Read/ Write Resource Name Initial Value Access prohibited 00008CH RDR0 Port 0 pull-up resistor setting register R/W Port 0 0 0 0 0 0 0 0 0B 00008DH RDR1 Port 1 pull-up resistor setting register R/W Port 1 0 0 0 0 0 0 0 0B 00008EH to 00009DH Access prohibited Program address detection control status register R/W Address match detection 0 0 0 0 0 0 0 0B DIRR Delayed interrupt request/clear register R/W Delayed interrupt XXXXXXX 0B 0000A0H LPMCR Low power consumption mode register W, R/W Low power consumption control circuit 0 0 0 1 1 0 0 0B 0000A1H CKSCR Clock selection register R, R/W Clock 1 1 1 1 1 1 0 0B R/W Watchdog timer 1 XXXX 1 1 1B W, R/W Timebase timer 1 XX 0 0 1 0 0B Flash memory 0 0 0 0 0 0 0 0B 00009EH PACSR 00009FH 0000A2H to 0000A7H Access prohibited 0000A8H WDTC Watchdog control register 0000A9H TBTC Timebase timer control register 0000AAH to 0000ADH 0000AEH Access prohibited FMCS 0000AFH Flash memory control status register R, W, R/W Access prohibited 0000B0H ICR00 0000B1H ICR01 0000B2H ICR02 0000B3H ICR03 0000B4H ICR04 0000B5H ICR05 Interrupt control register 00 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 00 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 01 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 01 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 02 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 02 (for reading) R, R/W Interrupt control register 03 (for writing) W, R/W Interrupt control register 03 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 04 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 04 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 05 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 05 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupts XX 0 0 0 1 1 1B XXXX 0 1 1 1B (Continued) 25 MB90560/565 Series AbbreviatAddress ed Register Name 0000B6H ICR06 0000B7H ICR07 0000B8H ICR08 0000B9H ICR09 0000BAH ICR10 0000BBH ICR11 0000BCH ICR12 0000BDH ICR13 0000BEH ICR14 0000BFH ICR15 Register name Read/ Write Interrupt control register 06 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 06 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 07 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 07 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 08 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 08 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 09 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 09 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 10 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 10 (for reading) R, R/W Interrupt control register 11 (for writing) W, R/W Interrupt control register 11 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 12 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 12 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 13 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 13 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 14 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 14 (for reading) R, R/W XX 0 0 0 1 1 1B Interrupt control register 15 (for writing) W, R/W XXXX 0 1 1 1B Interrupt control register 15 (for reading) R, R/W XX 0 0 0 1 1 1B 0000C0H to 0000FFH Unused area 000100H to #H RAM area #H to 001FEFH Reserved area 001FF0H 001FF1H 001FF2H PADR0 Program address detection register ch0 (lower) R/W Program address detection register ch0 (middle) R/W Program address detection register ch0 (lower) R/W Resource Name Interrupts Initial Value XX 0 0 0 1 1 1B XXXX 0 1 1 1B XXXXXXXXB Address match detection XXXXXXXXB XXXXXXXXB (Continued) 26 MB90560/565 Series (Continued) AbbreviatAddress ed Register Name 001FF3H 001FF4H 001FF5H PADR1 Register name Read/ Write Program address detection register ch1 (lower) R/W Program address detection register ch1 (middle) R/W Program address detection register ch1 (lower) R/W 001FF6H to 001FFFH Resource Name Initial Value XXXXXXXXB Address match detection XXXXXXXXB XXXXXXXXB Unused area • Read/write notation R/W : Reading and writing permitted R : Read-only W : Write-only • Initial value notation 0 : Initial value is “0”. 1 : Initial value is “1”. X : Initial value is undefined. 27 MB90560/565 Series ■ INTERRUPTS, INTERRUT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt EI2OS Support No.* Interrupt Control Register Address ICR Address Reset × #08 08H FFFFDCH INT 9 instruction × #09 09H FFFFD8H Exception × #10 0AH FFFFD4H A/D converter conversion complete #11 0BH FFFFD0H ICR00 0000B0H Output compare channel 0 match #13 0DH FFFFC8H 8/16-bit PPG timer 0 counter borrow #14 0EH FFFFC4H ICR01 0000B1H Output compare channel 1 match #15 0FH FFFFC0H 8/16-bit PPG timer 1 counter borrow #16 10H FFFFBCH ICR02 0000B2H Output compare channel 2 match #17 11H FFFFB8H 8/16-bit PPG timer 2 counter borrow #18 12H FFFFB4H ICR03 0000B3H Output compare channel 3 match #19 13H FFFFB0H 8/16-bit PPG timer 3 counter borrow #20 14H FFFFACH ICR04 0000B4H Output compare channel 4 match #21 15H FFFFA8H 8/16-bit PPG timer 4 counter borrow #22 16H FFFFA4H ICR05 0000B5H Output compare channel 5 match #23 17H FFFFA0H 8/16-bit PPG timer 5 counter borrow #24 18H FFFF9CH ICR06 0000B6H DTP/external interrupt channel 0/1 detection #25 19H FFFF98H DTP/external interrupt channel 2/3 detection #26 1AH FFFF94H ICR07 0000B7H DTP/external interrupt channel 4/5 detection #27 1BH FFFF90H DTP/external interrupt channel 6/7 detection #28 1CH FFFF8CH ICR08 0000B8H #29 1DH FFFF88H #30 1EH FFFF84H ICR09 0000B9H #31 1FH FFFF80H 16-bit reload timer 1 underflow #32 20H FFFF7CH ICR10 0000BAH Input capture channel 0/1 #33 21H FFFF78H #34 22H FFFF74H ICR11 0000BBH #35 23H FFFF70H #36 24H FFFF6CH ICR12 0000BCH UART1 receive #37 25H FFFF68H UART1 send #38 26H FFFF64H ICR13 0000BDH UART0 receive #39 27H FFFF60H UART0 send #40 28H FFFF5CH ICR14 0000BEH ICR15 0000BFH 8-bit timer 0/1/2 counter borrow × 16-bit reload timer 0 underflow 16-bit freerun timer overflow 16-bit freerun timer clear × × Input capture channel 2/3 Timebase timer 28 Interrupt Vector × Flash memory status × #41 29H FFFF58H Delay interrupt output module × #42 2AH FFFF54H Priority High Low MB90560/565 Series : Supported × : Not supported : Supported, includes EI2OS stop function : Available if the interrupt that shares the same ICR is not used. * : If two or more interrupts with the same level occur simultaneously, the interrupt with the lower interrupt vector number has priority 29 MB90560/565 Series ■ PERIPHERAL FUNCTIONS 1. I/O Ports • The I/O ports can be used as general-purpose I/O ports (parallel I/O ports) . The MB90560/565 series have 7 ports (51 pins) . The ports share pins with the inputs and outputs of the peripheral functions. • The port data registers (PDR) are used to output data to the I/O pins and read the data input from the I/O ports. Similarly, the port direction registers (DDR) set the I/O direction (input or output) for each individual port bit. • The following table lists the I/O ports and the peripheral functions with which they share pins. Pin Name (Port) Pin Name (Peripheral) Peripheral Function that Shares Pin Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P00-P07 P10-P16 INT0-INT6 P17 FRCK P20-P23 TIN0, TO0, TIN1, TO1 P24-P27 IN0-IN3 P30-P35 RTO0-RTO5 Output compare P36, P37 SIN0, SOT0 UART0 P40 SCK0 UART0 P41-P46 PPG0-PPG5 P50-P57 AN0-AN7 P60-P62 SIN1, SOT1, SCK1 P63 Not shared External interrupts Freerun timer external input 16-bit reload timer 0 and 1 Input capture 0 to 3 8/16-bit PPG timer 8/10-bit A/D converter UART1 INT7 External interrupts DTTI Waveform generator Notes : • Pins P30 to P35 of port 3 can drive a maximum of IOL = 12 mA. • Port 5 shares pins with the analog inputs. When using port 5 pins as a general-purpose ports, ensure that the corresponding analog input enable register (ADER) bits are set to “0B”. ADER is initialized to “FFH” after a reset. • Block diagram for port 0 and 1 pins Pull-up resistor setting register (PDRx) Internal data bus Internal pull-up resistor PDRx read PDRx write Port data register (PDRx) Port direction register (DDRx) 30 Input/output selection circuit Input buffer Output buffer Port pin Standby control (LPMCR : SPL = "1") MB90560/565 Series • Block diagram for port 2, 3, 4, and 6 pins Internal data bus Resource input PDRx read Port data register (PDRx) Input/output selection circuit PDRx write Port direction register (DDRx) Input buffer Output buffer Port pin Standby control (LPMCR : SPL = "1") Resource output control signal Resource output • Block diagram for port 5 pins Internal data bus Analog input enable register (ADER) Analog converter analog input signal PDR5 read PDR5 write Port data register (PDR5) Port direction register (DDR5) Input/output selection circuit Input buffer Output buffer Port 5 pin Standby control (LPMCR : SPL = "1") Notes : • When using as an input port, set the corresponding bit in the port 5 direction register (DDR5) to “0” and set the corresponding bit in the analog input enable register (ADER) to “0”. • When using as an analog input pin, set the corresponding bit in the port 5 direction register (DDR5) to “0” and set the corresponding bit in the analog input enable register (ADER) to “1”. 31 MB90560/565 Series 2. Timebase Timer • The timebase timer is an 18-bit freerun timer (timebase timer/counter) that counts up synchronized with the main clock (oscillation clock : HCLK divided into 2) . • The timer can generate interrupt requests at a specified interval, with four different interval time settings available. • The timer supplies the operating clock for peripheral functions including the oscillation stabilization delay timer and watchdog timer. • Timebase timer interval settings Internal Count Clock Period Interval Time 12 2 /HCLK (approx. 1.024 ms) 2/HCLK (0.5 µs) 214/HCLK (approx. 4.096 ms) 216/HCLK (approx. 16.384 ms) 219/HCLK (approx. 131.072 ms) Notes : • HCLK : Oscillation clock frequency • The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz. • Period of clocks supplied from timebase timer Peripheral Function Clock Period 210/HCLK (approx. 0.256 ms) Oscillation stabilization delay for the main clock 213/HCLK (approx. 2.048 ms) 215/HCLK (approx. 8.192 ms) 217/HCLK (approx. 32.768 ms) 212/HCLK (approx. 1.024 ms) Watchdog timer 214/HCLK (approx. 4.096 ms) 216/HCLK (approx. 16.384 ms) 219/HCLK (approx. 131.072 ms) Notes : • HCLK : Oscillation clock frequency • The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz. 32 MB90560/565 Series • Block diagram To watchdog timer To PPG timer Timebase timer/counter HCLK divided into 2 × 21 × 22 × 23 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF OF OF To oscillation stabilization delay time selector in clock controller Reset*1 Clear stop mode, etc.*2 Switch clock mode*3 Counter clear circuit Interval timer selector TBOF clear Timebase timer control register (TBTC) TBOF set TBIE TBOF TBR TBC1 TBC0 Timebase timer interrupt signal OF HCLK *1 *2 *3 : Overflow : Oscillation clock frequency : Power-on reset, watchdog reset : Recovery from stop mode and timebase timer mode : Main → PLL clock The actual interrupt request number for the timebase timer is : Interrupt request number : #36 (24H) 33 MB90560/565 Series 3. Watchdog Timer • The watchdog timer is a timer/counter used to detect faults such as program runaway. • The watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or clock timer. • Once started, the watchdog timer must be cleared before the 2-bit counter overflows. If an overflow occurs, the CPU is reset. • Interval time for the watchdog timer HCLK : Oscillation Clock (4 MHz) Min. Max. Clock Period Approx. 3.58 ms Approx. 4.61 ms 214 ± 211 / HCLK Approx. 14.33 ms Approx. 18.30 ms 216 ± 213 / HCLK Approx. 57.23 ms Approx. 73.73 ms 218 ± 215 / HCLK Approx. 458.75 ms Approx. 589.82 ms 218 ± 215 / HCLK Notes : • The difference between the maximum and minimum watchdog timer interval times is due to the timing when the counter is cleared. • As the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or clock timer, clearing the timebase timer (when operating on HCLK) or the clock timer (when operating on SCLK) lengthens the time until the watchdog timer reset is generated. • Watchdog timer count clock WTC : WDCS HCLK : Oscillation clock PCLK : PLL clock “0” Prohibited setting “1” Count the timebase timer output. • Events that stop the watchdog timer 1 : Stop due to a power-on reset 2 : Watchdog reset • Events that clear the watchdog timer 1 : External reset input from the RST pin. 2 : Writing “0” to the software reset bit. 3 : Writing “0” to the watchdog control bit (second and subsequent times) . 4 : Changing to sleep mode (clears the watchdog timer and temporarily halts the count) . 5 : Changing to timebase timer mode (clears the watchdog timer and temporarily halts the count) . 6 : Changing to stop mode (clears the watchdog timer and temporarily halts the count) . 34 MB90560/565 Series • Block diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE Watchdog timer WT1 WT0 2 Start Reset Change to sleep mode Change to timebase timer mode Change to stop mode Counter clear control circuit Counter clock selector 2-bit counter Watchdog timer reset generation circuit To internal reset circuit Clear 4 (Timebase timer/counter) Main clock (HCLK divided into 2) × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 HCLK : Oscillation clock frequency 35 MB90560/565 Series 4. 16-Bit Reload Timers 0 and 1 (With Event Count Function) • The 16-bit reload timers have the following functions. • The count clock can be selected from three internal clocks or the external event clock. • An interrupt to the CPU can be generated when an underflow occurs on 16-bit reload timer 0 or 1. This interrupt allows the timers to be used as interval timers. • Two different operation modes can be selected when an underflow occurs on 16-bit reload timer 0 or 1: oneshot mode in which timer operation halts when an underflow occurs or reload mode in which the value in the reload register is loaded into the timer and counting continues. • Extended intelligent I/O service (EI2OS) is supported. • The MB90560/565 series contains two 16-bit reload timer channels. • 16-bit reload timer operation modes Count Clock Start Trigger Software trigger Internal clock External trigger Event count mode (external clock mode) Software trigger • Interval times for the 16-bit reload timers Count Clock Count Clock Period Event count mode One-shot mode Reload mode One-shot mode Reload mode One-shot mode Reload mode Example of Interval Times 2 /φ (0.125 µs) 0.125 µs to 8.192 ms 2 /φ (0.5 µs) 0.5 µs to 32.768 ms 25/φ (2.0 µs) 2.0 µs to 131.1 ms 23/φ or longer 0.5 µs or longer 1 Internal clock Operation When an Underflow Occurs 3 Note : The values enclosed in ( ) and the example of interval times is for a machine clock frequency of 16 MHz. φ is the machine clock frequency value for the calculation. Remarks : 16-bit reload timer 0 can be used to generate the baud rate for UART0. 16-bit reload timer 1 can be used to generate the baud rate for UART1 and activation trigger for the A/D converter. 36 MB90560/565 Series • Block diagram Internal data bus TMRLR0*1 TMRLR1*2 16-bit reload register Reload signal TMR0*1 TMR1*2 Reload control circuit *4 UF 16-bit timer register CLK Count clock generation circuit Machine clock φ Prescaler 3 Gate input Clock pulse detection circuit Wait signal To UART0*1 To UART1 and A/D converter trigger*2 Clear trigger Internal clock Pin TIN0*1 TIN1*2 Input control circuit Clock selector External clock 2 3 CLK Output control circuit Output signal generation circuit Select signal Function selection CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE Timer control status register (TMCSR) Pin EN TO0*1 TO1*2 Operation control circuit UF CNTE TRG Interrupt request output #30 (1EH) *1, *3 #32 (20H) *2, *3 *1 : Channel 0 *2 : Channel 1 *3 : Interrupt number *4 : Underflow 37 MB90560/565 Series 5. Multi-Function Timer • Based on the 16-bit freerun timer, the multi-function timer can be used to generate 12 independent waveform outputs and to measure input pulse widths and external clock periods. • Structure of multi-function timer 16-bit 16-bit freerun timer output compare 1 ch 6 ch 16-bit input capture 8/16-bit PPG timer Waveform generator 4 ch 8 bit × 6 ch 16 bit × 3 ch 8-bit timer × 3 ch • 16-bit freerun timer (1 channel) The 16-bit freerun timer consists of a 16-bit up-counter (timer data register (TCDT) ) , compare clear register (CPCLR) , timer control status register (TCCS) , and prescaler. The count output value from the 16-bit freerun timer provides the base time for the input capture and output compare functions. • The count clock can be selected from the following eight clocks : 1/φ, 2/φ, 4/φ, 8/φ, 16/φ, 32/φ, 64/φ, 128/φ φ : Machine clock frequency • An interrupt can be generated when the 16-bit freerun timer overflows or when the 16-bit freerun timer count is cleared to “0000H” due to a match occurring between the value in the compare clear register (CPCLR) and the count in the 16-bit freerun timer (TCCS : ICRE = “1”, MODE = “1”) . • The 16-bit freerun timer is cleared to “0000H” when a reset occurs, on setting the timer clear bit (SCLR) in the timer control status register (TCCS) , when a compare match occurs between the 16-bit freerun timer count and the value in the compare clear register (CPCLR) (TCCS : MODE = “1”) , or by writing “0000H” to the timer data register (TCDT) . • Output compare (6 channels) The output compare unit consists of compare registers (OCCP0 to OCCP5) , compare control registers (OCS0 to OCS5) , and compare output latches. When a match occurs between a compare register (OCCP0 to OCCP5) value and the count from the 16-bit freerun timer, the output compare can invert the level of the corresponding output compare pin and generate an interrupt. • The compare registers (OCCP0 to OCCP5) operate independently for each channel. Each of the compare registers (OCCP0 to OCCP5) has a corresponding output pin and an interrupt request flag in the channel’s compare control register (lower) (OCS0, OCS2, OCS4) . • Two channels of the compare registers (OCCP0 to OCCP5) can be used to invert the output pins. • An interrupt can be output when a match occurs between a compare register (OCCP0 to OCCP5) and the count from the 16-bit freerun timer (OCS0, OCS2, OCS4 : IOP0 = “1”, IOP1 = “1”) . (OCS0, OCS2, OCS4 : IOE0 = “1”, IOE1 = “1”) • The initial output levels for the output compare pins can be set. • Input capture (4 channels) The input capture consists of external input pins (IN0 to IN3) , corresponding input capture data registers (IPCP0 to IPCP3) , and input capture control status registers (ICS01, ICS23) . The input capture can transfer the count value from the 16-bit freerun timer to the input capture data register (IPCP0 to IPCP3) and output an interrupt on detecting an active edge on the signal input from the external input pin. • Each channel of the input capture operates independently. • The active edge (rising edge, falling edge, or either edge) on the external signal can be specified. 38 MB90560/565 Series • An interrupt can be generated when an active edge is detected on the external signal (ICS01, ICS23 : ICE0 = “1”, ICE1 = “1”, ICE2 = “1”, ICE3 = “1”) . • 8/16-bit PPG timer (8-bit : 6 channels, 16-bit : 3 channels) The 8/16-bit PPG timer consists of an 8-bit down counter (PCNT) , PPG control registers (PPGC0 to PPGC 5) , PPG clock control registers (PCS01, PCS23, PCS45) , and PPG reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5) . When used as an 8/16-bit reload timer, the PPG operates as an event timer. The PPG can also be used to output pulses with specified frequency and duty ratio. • 8-bit PPG mode Each channel operates as an independent 8-bit PPG. • 8-bit prescaler + 8-bit PPG mode ch0 (ch2, ch4) operates as an 8-bit prescaler and ch1 (ch3, ch5) operates as a variable frequency PPG by counting up on the borrow output from ch0 (ch2, ch4) . • 16-bit PPG mode ch0 (ch2, ch4) and ch1 (ch3, ch5) operate together as a 16-bit PPG. • PPG operation Outputs pulses with the specified frequency and duty ratio (ratio of “H” level period and “L” level period), and can also be used as a D/A converter when combined with an external circuit. • Waveform generator The waveform generator consists of an 8-bit timer, 8-bit timer control registers (DTCR0 to DTCR2) , 8-bit reload registers (TMRR0 to TMRR2) , and waveform control register (SIGCR) . The waveform generator can generate a DC chopper output or non-overlapping three-phase waveform output for inverter control using the realtime outputs (RT0 to RT5) and 8/16-bit PPG timer. • A non-overlapping waveform can be generated by using the 8-bit timer as a deadtime timer and adding a nonoverlap time delay to the PPG timer pulse output. (Deadtime timer function) • A non-overlapping waveform can be generated by using the 8-bit timer as a deadtime timer and adding a nonoverlap time delay to the realtime outputs (RT1, RT3, RT5) . (Deadtime timer function) • A GATE signal can be generated when a match occurs between the count from the 16-bit freerun timer and compare register in the output compare (OCCP0 to OCCP5) (rising edge on realtime output (RT) ) to control the PPG timer operation. (GATE function) • Can control the RTO0 to RTO5 pin outputs using the DTTI pin input. By making the DTTI pin input clockless, the pins can be controlled externally even when the oscillation clock is halted. (The level for each pin can be set by the program.) However, the I/O ports (P30 to P35) must have been set beforehand as outputs and the output values set in the port 3 data register (PDR3) . 39 MB90560/565 Series • Block diagram • 16-bit freerun timer, input capture, and output compare To interrupt #31 (1FH) * φ 3 8 IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Divider Clock 16-bit freerun timer 16 16-bit compare clear register To interrupt #34 (22H) * Compare circuit 16 Compare registers 0, 2, 4 MS13 to 0 ICLR ICRE To A/D trigger Compare circuit T Q T Q To RT0, 2, 4 waveform generator 16 Compare registers 1, 3, 5 CMOD Internal data bus Compare circuit To RT1, 3, 5 waveform generator 4 IOP1 IOP0 IOE1 IOE0 To interrupts #13 (0DH) *, #17 (11H) *, #21 (15H) * #15 (0FH) *, #19 (13H) *, #23 (17H) * Capture registers 0, 2 Edge detection IN0/2 4 EG11 Capture registers 1, 3 EG10 EG01 Edge detection EG00 IN1/3 4 ICP0 ICP1 ICE0 ICE1 To interrupts #33 (21H) *, #35 (23H) * #33 (21H) *, #35 (23H) * * : Interrupt number φ : Machine clock frequency 40 MB90560/565 Series • Block diagram of 8/16-bit PPG timer PC02 PC01 PC00 POS0 OEN0 SST0 POE0 PUF0 PIE0 To interrupt #14 (0EH) * φ Selector Operation control Divider GATE0/1 PCNT0 (Down counter) Selector Selector To PPG0, 2, 4 Reload ch1, 3, 5 borrow L/H selector Internal data bus PRLL0/2/4 PRLBH0/2/4 PRLH0/2/4 PC12 PC11 PC10 SST1 POE1 PUF1 PIE1 To interrupt #16 (10H) * φ ch0, 2, 4 borrow Selector POS1 OEN1 Operation control Divider GATE1 PCNT1 (Down counter) Selector Selector To PPG1, 3, 5 Reload L/H selector PRLL1/3/5 PRLBH1/3/5 PRLH1/3/5 * : Interrupt number φ : Machine clock frequency 41 MB90560/565 Series • Block diagram of waveform generator φ DCK2 DCK1 DCK0 TMD1 TMD0 NRSL DTIL DTIE DTTI control circuit Divider Clock DTTI To GATE0, 1 (To PPG timer) RT0 Waveform generator TO0 TO1 RT1 Selector 8-bit timer Compare circuit RTO0/U RTO1/X Selector Internal data bus U 8-bit timer register 0 Deadtime generation X To GATE2, 3 (To PPG timer) Waveform generator RT2 TO2 TO3 RT3 8-bit timer Compare circuit Selector RTO2/V RTO3/Y Selector V 8-bit timer register 1 Deadtime generation Y To GATE4, 5 (To PPG timer) Waveform generator RT4 TO4 TO5 RT5 Selector 8-bit timer Compare circuit Selector RTO5/Z W 8-bit timer register 2 φ : Machine clock frequency 42 Deadtime generation RTO4/W MB90560/565 Series 6. UART (1) Overview • The UART is a general-purpose serial communications interface for performing synchronous or asynchronous (start-stop synchronization) communications with external devices. • The interface provides both a bi-directional communication function (normal mode) and a master-slave communication function (multi-processor mode) . • The UART can generate interrupt requests at receive complete, receive error detected, and transmit complete timings. Also the UART supports EI2OS. • UART functions The UART is a general-purpose serial communications interface for sending serial data to and from other CPUs and peripheral devices. Function Data buffer Transmission modes Baud rate Number of data bits Signal format Receive error detection Interrupt requests Master/slave communication function (multi-processor mode) Full-duplex double-buffered • Clock synchronous (no start and stop bits) • Clock asynchronous (start-stop synchronization) • • • • • Max. 2 MHz (for a 16 MHz machine clock) Baud rate generated by dedicated baud rate generator Baud rate generated by external clock (clock input from SCK0 and SCK1 pins) Baud rate generated by internal clock (clock supplied from 16-bit reload timer) Eight different baud rate settings are available. • 7 bits (asynchronous normal mode only) • 8 bits Non return to zero (NRZ) format • Framing errors • Overrun errors • Parity errors (not available in multi-processor mode) • Receive interrupt (Receive complete or receive error detected) • Transmit interrupt (Transmission complete) • Both transmit and receive support the extended intelligent I/O service (EI2OS) . Used for 1 (master) to n (slave) communications. (Can only be used as master) Note : The UART does not add the start and stop bits in clock synchronous mode. In this case, only data is transmitted. 43 MB90560/565 Series • UART operation modes No. of Data Bits Operation Mode 0 No Parity Normal mode With Parity 7 or 8 bits 1 Multi-processor mode 2 Clock synchronous mode Synchronization Asynchronous 8+1 Asynchronous 8 Synchronous *1 No. of Stop Bits 1 or 2 bits*2 None : Not available *1 : The “+1” represents the address/data (A/D) bit used for communication control. *2 : Only 1 stop bit supported for receiving. • UART interrupts and EI2OS Interrupt Interrupt No. Interrupt Control Register Vector Table Address EI2OS Register Name Address Lower Upper Bank UART1 receive interrupt #37 (25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH UART1 send interrupt #38 (26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H UART0 receive interrupt #39 (27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H UART0 send interrupt #40 (28H) ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH : The UART has a function to halt EI2OS if a receive error is detected. : Available when the interrupt shared with ICR13 or ICR14 is not used. 44 MB90560/565 Series (2) UART structure The UART consists of the following 11 blocks: • Clock selector • Mode registers (SMR0, SMR1) • Receive control circuit • Control registers (SCR0, SCR1) • Transmission control circuit • Status registers (SSR0, SSR1) • Receive status evaluation circuit • Input data registers (SIDR0, SIDR1) • Receive shift register • Output data registers (SODR0, SODR1) • Transmission shift register • Block diagram Control bus Dedicated baud rate generator Receive interrupt signal #39 (27H)* <#37 (25H)*> Transmit clock Clock selector 16-bit reload timer Receive clock Pin P40/SCK0 <P62/SCK1> Transmission control circuit Receive control circuit Start bit detection circuit Transmission start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter Transmit interrupt signal #40 (28H)* <#38 (26H)*> Pin P37/SOT0 <P61/SOT1> Receive shift register Pin P36/SIN0 <P60/SIN1> SIDR0/SIDR1 Transmission shift register Receive complete Transmission start SODR0/SODR1 Receive status evaluation circuit Receive error detection signal for EI2OS (to CPU) Internal data bus SMR0/SMR1 MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0/SCR1 PEN P SBL CL A/D REC RXE TXE SSR0/SSR1 PE ORE FRE RDRF TDRE BDS RIE TIE * : Interrupt number 45 MB90560/565 Series • Clock selector Selects the send/receive clock from either the dedicated baud rate generator, external input clock (clock input to SCK0 or SCK1 pin) , or internal clock (clock supplied by 16-bit reload timer) . • Receive control circuit The receive control circuit consists of a receive bit counter, start bit detection circuit, and receive parity counter. The receive bit counter counts the received data bits and outputs a receive interrupt request when the required number of data bits have been received. The start bit detection circuit detects the start bit on the serial input signal. On detecting a start bit, the receive data is shifted to the input data register (SIDR0 or SIDR1) in accordance with the specified transfer speed. The receive parity counter calculates the parity of the received data if parity is selected. • Transmission control circuit The transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission parity counter. The transmission bit counter counts the transmitted data bits and outputs a transmit interrupt request when the required number of data bits have been sent. The transmission start circuit starts transmission when data is written to the output data register (SODR0 or SODR1) . The transmission parity counter generates the parity bit for the transmitted data when parity is selected. • Receive shift register The receive shift register captures the data input from the SIN0 or SIN1 pin by shifting one bit at a time then transfers the received data to the input data register (SIDR0 or SIDR1) when reception completes. • Transmission shift register The transmission data is transferred from the output data register (SODR0 or SODR1) to the transmission shift register and output from the SOT0 or SOT1 pin by shifting one bit at a time. • Mode register (SMR0, SMR1) Set the operation mode, baud rate clock and serial clock input/output control, and enables output for the serial data pin. • Control register (SCR0, SCR1) Specifies whether to use parity, the type of parity, number of stop bits and data bits and the frame data format for operation mode 1, to clear the receive error flag bit, and to enable or disable send and receive operation. • Status register (SSR0, SSR1) Stores the send/receive and error status information, set the serial data transfer direction, and enables or disables the send and receive interrupt requests. • Input data register (SIDR0, SIDR1) Stores the received data. • Output data register (SODR0, SODR1) Set the transmission data. The data set in the output data register is converted to serial format and output. 46 MB90560/565 Series 7. DTP/External Interrupt Circuit (1) Overview of the DTP/external interrupt circuit The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input to the external interrupt input pins (INT7 to INT0) and outputs interrupt requests. • DTP/external interrupt circuit functions The DTP/external interrupt function detects edge or level signals input to the external interrupt input pins (INT7 to INT0) and outputs interrupt requests. The interrupt request is received by the CPU and, if the extended intelligent I/O service (EI2OS) is enabled, EI2OS performs automatic data transfer (DTP function) then passes control to the interrupt handler routine on completion. If EI2OS is disabled, control passes directly to the interrupt handler routine without performing automatic data transfer (DTP function) . • Overview of the DTP/external interrupt circuit External Interrupt DTP Function Input pins 8 channels (P10/INT0 to P16/INT6, P63/INT7) Interrupt conditions The level or edge to detect can be set independently for each pin in the detection level setup register (ELVR) . “L” level, “H” level, rising edge, or falling edge input Interrupt number #25 (19H) to #28 (1CH) Interrupt control Interrupts can be enabled or disabled in the DTP/external interrupt enable register (ENIR) . Interrupt flag The DTP/external interrupt request register (ENRR) stores interrupt requests. Processing selection Set EI2OS to disabled (ICR : ISE = 0) Set EI2OS to enabled (ICR : ISE = 1) Operation Jumps to interrupt handler routine Jumps to interrupt handler routine after automatic data transfer by EI2OS completes. ICR : Interrupt control register • DTP/external interrupt circuit interrupts and EI2OS Interrupt Control Register Interrupt Channel No. Register Name Address INT0/INT1 #25 (19H) INT2/INT3 #26 (1AH) INT4/INT5 #27 (1BH) INT6/INT7 #28 (1CH) ICR07 0000B7H ICR08 0000B8H Vector Table Address Lower Upper Bank FFFF98H FFFF99H FFFF9AH FFFF94H FFFF95H FFFF96H FFFF90H FFFF91H FFFF92H FFFF8CH FFFF8DH FFFF8EH EI2OS : Available when the interrupt shared with ICR07 or ICR08 is not used. 47 MB90560/565 Series (2) Structure of the DTP/external interrupt circuit The DTP/external interrupt circuit consists of the following four blocks : • DTP/interrupt detection circuit • DTP/interrupt request register (EIRR) • DTP/interrupt enable register (ENIR) • Request level setting register (ELVR) • Block diagram Request level setting register (ELVR) LB7 LA7 2 LB6 LA6 2 LA5 2 LB4 LA4 2 LB3 LA3 2 LB2 LA2 2 LB1 LA1 2 DTP/external interrupt input detection circuit Selector Pin LB5 LB0 LA0 2 Selector P63/INT7 P10/INT0 Selector Pin Selector P16/INT6 Selector Pin Internal data bus Pin P11/INT1 Selector Pin P15/INT5 P12/INT2 Pin Selector Selector Pin P14/INT4 P13/INT3 DTP/interrupt request register (EIRR) ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request signal #25 (19H)* #26 (1AH)* #27 (1BH)* DTP/interrupt enable register (ENIR) EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 * : Interrupt number 48 Pin #28 (1CH)* MB90560/565 Series 8. Delayed Interrupt Generation Module • The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this hardware interrupt can be specified by software. • Delayed interrupt generation module functions Function and Control Interrupt trigger • Writing “1” to bit R0 of the delayed interrupt request generation/clear register (DIRR : R0 = 1) generates an interrupt request. • Writing “0” to bit R0 of the delayed interrupt request generation/clear register (DIRR : R0 = 1) clears the interrupt request. Interrupt control • No enable/disable register is provided for this interrupt. • Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0) . Interrupt flag EI2OS support • Not supported by the extended intelligent I/O service (EI2OS) . • Block diagram Internal data bus Delayed interrupt request generation/ clear register (DIRR) R0 S Interrupt request R latch Interrupt request signal : Undefined 49 MB90560/565 Series 9. 8/10-Bit A/D Converter • Overview of the 8/10-bit A/D converter • The 8/10-bit A/D converter uses RC successive approximation to convert analog input voltages to an 8-bit or 10-bit digital value. • The input signals can be selected from the eight analog input pin channels. • 8/10-bit A/D converter functions The minimum conversion time is 6.13 µs (for a 16 MHz machine clock, including sampling A/D conversion time time) . The minimum sampling time is 2.0 µs (for a 16 MHz machine clock) Conversion method RC successive approximation with sample & hold circuit Resolution 8-bit or 10-bit, selectable Analog input pins Eight analog input pin channels are available. The input pin can be selected by the program. Interrupts An interrupt request can be generated and EI2OS invoked when A/D conversion completes. The conversion data protection function operates when A/D conversion is performed with the interrupt enabled. A/D conversion start trigger The conversion start trigger can be set from the following options : software, output of 16bit reload timer 1 (rising edge) , or zero detection edge from 16-bit freerun timer. EI2OS support Supported by the extended intelligent I/O service (EI2OS) . • 8/10-bit A/D converter conversion modes Conversion Mode Single Conversion Mode Operation Scan Conversion Mode Operation Sequentially performs one conversion Single-shot conversion mode 1 Performs one conversion for the specfor multiple channels (up to 8 channels Single-shot conversion mode 2 ified channel (1 channel) then halts. can be set) , then halts. Continuous conversion mode Performs repeated conversions for the Performs repeated conversions for the specified channels (up to 8 channels specified channel (1 channel) . can be set) . Incremental conversion mode Sequentially performs one conversion Performs one conversion for the specfor multiple channels (up to 8 channels ified channel (1 channel) then halts can be set) , then halts and waits for and waits for the next activation. the next activation. • 8/10-bit A/D converter interrupts and EI2OS Interrupt Control Register Interrupt No. Register Name Address #11 (0BH) : Available 50 ICR00 0000B0H Vector Table Address Lower Upper Bank FFFFD0H FFFFD1H FFFFD2H EI2OS MB90560/565 Series • Block diagram Interrupt request signal #11 (0BH) * A/D control status register (ADCS0, ADCS1) MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 BUSY INT INTE PAUS STS1 STS0 STRT Reserved 6 2 16-bit reload timer 1 output Decoder Clock selector Internal data bus 16-bit freerun timer zero-detect φ Comparator P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 Sample & hold circuit ST1 ST0 CT1 2 AVR AVCC AVSS A/D data register (ADCR0, ADCS1) S10 Control circuit Analog channel selector CT0 D9 D8 D7 D6 D/A converter D5 D4 D3 2 D2 D1 D0 φ : Machine clock * : Interrupt number 51 MB90560/565 Series 10. ROM Mirror Function Selection Module • The ROM mirror function selection module enables ROM data in FF bank to be read by accessing 00 bank. • ROM mirror function selection module functions Function • Data in FFFFFFH to FF4000H in FF bank can be read from 00FFFFH to 004000H in 00 bank. Mirror setting address Interrupts • None 2 • Not supported by the extended intelligent I/O service (EI2OS) . EI OS support • Relationship between addresses in the ROM mirror function FE0000H ROM area in MB90568 and MB90F568 FE8000H FEFFFFH FF0000H ROM area in MB90567 FF4000H ROM area in MB90562/A and MB90F562/B FF bank FF8000H FFFFFFH Mirrored ROM data area ROM area in MB90561/A • Block diagram ROM mirror function selection register (ROMM) Address Internal data bus Address space FF bank 00 bank Data ROM 52 MI MB90560/565 Series 11. Low Power Consumption (Standby) Modes • The power consumption of F2MC-16LX devices can be reduced by various settings that control the operating clock selection. • Functions of each CPU operation mode CPU Operation Operation Clock Mode PLL clock Normal Run The CPU and peripheral functions operate using the oscillation clock (HCLK) multiplied by the PLL circuit. Sleep The peripheral functions only operate using the oscillation clock (HCLK) multiplied by the PLL circuit. Pseudo-clock Main clock CPU intermittent operation Function The timebase timer only operates using the oscillation clock (HCLK) multiplied by the PLL circuit. Stop The oscillation clock is stopped and the CPU and peripherals halt operation. Normal Run The CPU and peripheral functions operate using the oscillation clock (HCLK) divided into 2. Sleep The peripheral functions only operate using the oscillation clock (HCLK) divided into 2. Stop The oscillation clock is stopped and the CPU and peripherals halt operation. Normal Run The oscillation clock (HCLK) divided into 2 operates intermittently for fixed time intervals. 53 MB90560/565 Series 12. 512 Kbit Flash Memory • This section describes the flash memory on the MB90F562/B and does not apply to evaluation and mask ROM versions. • The flash memory is located in bank FF in the CPU memory map. • Flash memory functions Function Memory size Memory configuration Sector configuration • 512 Kbit (64 KBytes) • 64 KWords × 8 bits or 32 KWords × 16 bits • 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes Sector protect function • Selectable for each sector Programming algorithm • Automatic programming algorithm (Embedded Algorithm* : Equivalent to MBM29F400TA) Operation commands No. of write/erase cycles Memory write/erase method • • • • Compatible with JEDEC standard commands Includes an erase pause and restart function Write/erase completion detection by data polling or toggle bit Erasing by sector available (sectors can be combined in any combination) • Min. 10,000 guaranteed • Can be written and erased using a parallel writer (Ando Denki AF9704, AF9705, AF9706, AF9708, and AF9709) • Can be written and erased using a dedicated serial writer (Yokogawa Digital Computer Corporation AF200, AF210, AF120, and AF110) • Can be written and erased by the program Interrupts • Write and erase completion interrupts 2 • Not supported by the extended intelligent I/O service (EI2OS) . EI OS support * : Embedded Algorithm is a trademark of Advanced Micro Devices. • Sector configuration of flash memory Flash memory SA1 (32 Kbyte) SA2 (8 Kbyte) SA3 (8 Kbyte) SA4 (16 Kbyte) CPU address Writer address* FF0000H 70000H FF7FFFH 77FFFH FF8000H 78000H FF9FFFH 79FFFH FFA000H 7A000H FFBFFFH 7BFFFH FFC000H 7C000H FEFFFFH 7FFFFH * : The writer address is the address to be used instead of the CPU address when writing data from a parallel flash memory writer. Use the writer address when programming or erasing with a general-purpose parallel writer. 54 MB90560/565 Series 13. 1 Mbit Flash Memory • This section describes the flash memory on the MB90F568 and does not apply to evaluation and mask ROM versions. • The flash memory is located in banks FE to FF in the CPU memory map. • Flash memory functions Function Memory size Memory configuration Sector configuration • 1 Mbit (128 KBytes) • 128 KWords × 8 bits or 64 KWords × 16 bits • 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes + 64 KBytes Sector protect function • Selectable for each sector Programming algorithm • Automatic programming algorithm (Embedded Algorithm* : Equivalent to MBM29F400TA) Operation commands No. of write/erase cycles Memory write/erase method • • • • Compatible with JEDEC standard commands Includes an erase pause and restart function Write/erase completion detection by data polling or toggle bit Erasing by sector available (sectors can be combined in any combination) • Min. 10,000 guaranteed • Can be written and erased using a parallel writer (Ando Denki AF9704, AF9705, AF9706, AF9708, and AF9709) • Can be written and erased using a dedicated serial writer (Yokogawa Digital Computer Corporation AF200, AF210, AF120, and AF110) • Can be written and erased by the program Interrupts • Write and erase completion interrupts 2 • Not supported by the extended intelligent I/O service (EI2OS) . EI OS support * : Embedded Algorithm is a trademark of Advanced Micro Devices. • Sector configuration of flash memory Flash memory SA0 (64 Kbyte) SA1 (32 Kbyte) SA2 (8 Kbyte) SA3 (8 Kbyte) SA4 (16 Kbyte) CPU address Writer address* FE0000H 60000H FEFFFH 6FFFFH FF0000H 70000H FF7FFFH 77FFFH FF8000H 78000H FF9FFFH 79FFFH FFA000H 7A000H FFBFFFH 7BFFFH FFC000H 7C000H FEFFFFH 7FFFFH * : The writer address is the address to be used instead of the CPU address when writing data from a parallel flash memory writer. Use the writer address when programming or erasing with a general-purpose parallel writer. 55 MB90560/565 Series • Standard configuration for Fujitsu standard serial on-board programming Fujitsu standard serial on-board programming uses a flash microcontroller writer from Yokogawa Digital Computer Corporation (AF220, AF210, AF120, or AF210) . Host interface cable (AZ201) General-purpose cable (AZ221) RS232C Flash microcontroller writer + memory card Clock synchronous serial MB90F562/F562B/F568 user system Can operate standalone Note : Contact Yokogawa Digital Computer Corporation for details of the functions and operation of the flash microcontroller writer (AF220, AF210, AF120, or AF110) , standard connection cable (AZ221) , and connectors. • Pins used for Fujitsu standard serial on-board programming Symbol Pin name 56 Function MD2, Mode input pins MD1, MD0 Setting MD2 = 1, MD1 = 1, and MD0 = 0 selects serial programming mode. X0, X1 Oscillation input pin As flash memory serial programming mode uses the PLL clock with the multiplier set to 1 as the internal CPU operation clock, the internal operation clock frequency is the same as the oscillation clock frequency. Accordingly, the frequency that can be input to the high speed oscillation input pin when performing serial programming is between 1 MHz and 16 MHz. P00, P01 Write program activation pins Input P00 = “L” level and P01 = “H” level. RST Reset input pin SIN1 Serial data input pin SOT1 Serial data output pin SCK0 Serial clock input pin Uses UART0 and UART1 in clock synchronous mode. In programming mode, the pins used by UART0 in clock synchronous mode are SIN1, SOT1, and SCK0. C Capacitor/power supply input pin Capacitor pin for power supply stabilization. Connect an external ceramic capacitor of approx. 0.1 µF. VCC Power supply input pins If the user system provides the programming voltage (MB90F562 : 5 V ± 10%, MB90F568 : 3 V ± 10%) , these do not need to be connected to the flash microcontroller writer. VSS GND pin Connect to common GND with the flash microcontroller writer. MB90560/565 Series The control circuit shown in the figure is required when the P00, P01, SIN1, SOT1, and SCK0 pins are used on the user system. Use the /TICS signal from the flash microcontroller writer to disconnect the user circuit during serial on-board programming. AF220/AF210/AF120/AF110 write control pin MB90F562/F562B/F568 write control pin 10 kΩ AF220/AF210/AF120/AF110 /TICS pin User Control circuit Use the formula below to calculate the serial clock frequency able to be input to the MB90F562/F562B/F568. Set up the flash microcontroller writer to use a serial clock input frequency that is permitted for the oscillation clock frequency you are using. Permitted input serial clock frequency = 0.125 × oscillation clock frequency • Maximum serial clock frequency Oscillation Maximum Serial Clock Maximum Serial Clock Maximum Serial Clock Clock Frequency that can be Input Frequency that can be Set on Frequency that can be Set on Frequency to Microcontroller the AF220/AF210/AF120/AF110 the AF200 4 MHz 500 kHz 500 kHz 500 kHz 8 MHz 1 MHz 850 kHz 500 kHz 16 MHz 2 MHz 1.25 MHz 500 kHz • System configuration of flash microcontroller writer (AF220/AF210/AF120/AF110) (Supplier : Yokogawa Digital Computer Corporation) Model Function Unit AF200/AC4P Internal Ethernet interface model /100 V to 220 V power adapter AF210/AC4P Standard model /100 V to 220 V power adapter AF120/AC4P Single key, Internal Ethernet interface model /100 V to 220 V power adapter AF110/AC4P Single key model /100 V to 220 V power adapter AZ221 Special RS232C cable for connecting writer to PC/AT AZ210 Standard target probe (a) Length : 1 m FF201 Control module for Fujitsu F2MC-16LX flash microcontrollers AZ290 Remote controller AZ264 Power supply regulator (MB90F568 : Required to supply 3 V versions from the flash microcontroller writer.) /P2 2 MB PC card (option) Supports FLASH memory sizes up to 128 KB /P4 4 MB PC card (option) Supports FLASH memory sizes up to 512 KB Contact : Yokogawa Digital Computer Corporation Tel : 042-333-6224 Note : The AF200 flash microcontroller writer is an obsolete model but can still be used with the FF201 control module. 57 MB90560/565 Series ■ ELECTRICAL CHARACTERISTICS (MB90560 SERIES) 1. Absolute Maximum Ratings Parameter Symbol (VSS = AVSS = 0.0 V) Rating Unit Remarks Min. Max. VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V VCC ≥ AVCC*1 AVR VSS − 0.3 VSS + 6.0 V AVCC ≥ AVR ≥ 0 V *1 Input voltage VI VSS − 0.3 VSS + 6.0 V *2 Output voltage VO VSS − 0.3 VSS + 6.0 V *2 “L” level maximum output current IOL1 15 mA *3, *4 IOL2 20 mA *3, *5 IOLAV1 4 mA Average value (operating current × operating ratio) *4 IOLAV2 12 mA Average value (operating current × operating ratio) *5 ΣIOL 100 mA ΣIOLAV 50 mA Average value (operating current × operating ratio) “H” level maximum output current IOH −15 mA *3 “H” level average output current IOHAV −4 mA Average value (operating current × operating ratio) “H” level total maximum output current ΣIOH −100 mA ΣIOHAV −50 mA Power consumption Pd 300 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C Power supply voltage “L” level average output current “L” level total maximum output current “L” level total average output current “H” level total average output current Storage temperature Average value (operating current × operating ratio) *1 : AVCC and AVR must not exceed VCC. Also, AVR must not exceed AVCC. *2 : VI and VO must not exceed VCC + 0.3 V. *3 : The maximum output current is the peak value for a single pin. *4 : Pins other than P30/RTO0 to P35/RTO5 *5 : P30/RTO0 to P35/RTO5 pins WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 58 MB90560/565 Series 2. Recommended Operating Conditions Parameter Power supply voltage Input “H” voltage Input “L” voltage (VSS = AVSS = 0.0 V) Value Symbol Unit Remarks Min. Max. 3.0 5.5 V Normal operation (MB90562, 562A, 561, 561A, and V560) 4.5 5.5 V Normal operation (MB90F562 and F562B) VCC 3.0 5.5 V Maintaining state in stop mode VIH 0.7 VCC VCC + 0.3 V CMOS input pin VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin VIHM VCC − 0.3 VCC + 0.3 V MD input pin VIL VSS − 0.3 0.3 VCC V CMOS input pin VILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin VILM VSS − 0.3 VSS + 0.3 V MD input pin Use a ceramic capacitor or other capacitor with equivalent frequency characteristics. The capacitance of the smoothing capacitor connected to the VCC pin must be greater than CS. VCC Smoothing capacitor CS 0.1 1.0 µF Operating temperature TA −40 +85 °C • C pin diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 59 MB90560/565 Series 3. DC Characteristics Parameter Output “H” voltage SymPin Name bol Pull-down resistor Unit Min. Typ. Max. VCC − 0.5 V Remarks VOL1 Pins other than P30/ VCC = 4.5 V RTO0 to IOL1 = 2.0 mA P35/RTO5 0.4 V VOL2 P30/RTO0 VCC = 4.5 V to P35/ IOL2 = 12.0 mA RTO5 0.8 V −5 5 µA For VCC = 5 V, internal frequency = 16 MHz, normal operation 50 80 mA 40 50 mA MB90F562/B For VCC = 5 V, internal frequency = 16 MHz, A/D operation in progress 55 85 mA 45 55 mA MB90F562/B Flash write or erase 45 60 mA MB90F562/B ICCS For VCC = 5 V, internal frequency = 16 MHz, sleep mode 15 20 MB90562/A, mA MB90561/A MB90F562/B* ICCH Stop mode, TA = 25 °C 5 20 µA IIL Power supply current* Pull-up resistor VCC = 4.5 V IOH = −2.0 mA Value All output pins All output pins ICC Input capacitance Condition VOH Output “L” voltage Input leak current (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) VCC VCC = 5.5 V VSS < VI < VCC CIN Other than AVCC, AVSS, C, VCC, and VSS 10 80 pF RUP P00 to P07 P10 to P17 RST, MD0, MD1 15 30 100 kΩ 15 30 100 kΩ RDOWN MD2 MB90562/A, MB90561/A MB90562/A, MB90561/A * : Value when low power mode bits (LPM0, 1) is set to “01” with an internal operating frequency of 4 MHz. Note : Current values are provisional and are subject to change without notice to allow for improvements to the characteristics. The power supply current is measured with an external clock. 60 MB90560/565 Series 4. AC Characteristics (1) Clock Timings Parameter (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Sym CondiPin Name bol tion Value Unit Remarks Min. Typ. Max. 3 16 1 16 62.5 333 62.5 1000 10 ns Recommended duty ratio = 30% to 70% When using an external clock MHz With a PLL circuit Clock frequency fC X0, X1 Clock cycle time tHCYL X0, X1 Input clock pulse width PWH PWL X0 Input clock rise/fall time tcr tcf X0 5 ns Internal operating clock frequency fCP 1.5 16 MHz When using a main clock Internal operating clock cycle time tCP 62.5 333 ns When using a main clock ns Without a PLL circuit With a PLL circuit Without a PLL circuit • X0 and X1 clock timing tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tcf tcr 61 MB90560/565 Series • PLL guaranteed operation range Relationship between internal operating clock frequency and power supply voltage Guaranteed operation range for MB90F562/B Supply Voltage VCC (V) 5.5 PLL guaranteed operation range PLL guaranteed operation range 4.5 A/D converter guaranteed operation range 3.3 3.0 Guaranteed operation range for MB90561/A and MB90562/A Guaranteed operation range for MB90V560 1 3 8 12 16 Internal Clock fCP (MHz) Relationship between oscillation frequency and internal operating clock frequency ×4 Internal Clock fCP (MHz) 16 ×3 ×2 ×1 12 No multiplier 8 4 3 2 0.5 1 2 3 4 6 8 12 16 Source Oscillation Clock fC (MHz) The AC ratings are specified for the following measurement reference voltages. • Input signal waveform Hysteresis input pin Output pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pins other than hysteresis input or MD input pins 0.7 VCC 0.3 VCC 62 • Output signal waveform MB90560/565 Series (2)Reset (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Value Symbol Pin Name Condition Reset input time tRSTH RST Unit Remarks Min. Max. 16 tCP ns In normal operation Oscillator oscillation time* + 16 tCP ms In stop mode *: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several dozen ms; for a FAR/ceramic oscillator, this is several hundred µs to a few ms, and for an external clock this is 0 ms. • In normal operation tRSTL RST 0.2 VCC 0.2 VCC • In stop mode tRSTL RST 0.2Vcc X0 Internal operation clock 0.2Vcc 90 % of amplitude Oscillator oscillation time 16 tcp Oscillator stabilization wait time Execution of the instruction Internal reset 63 MB90560/565 Series (3) Power-On Reset Parameter Power supply rise time Power supply cutoff time (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Symbol Pin Name tR VCC tOFF VCC Condition Value Unit Min. Max. 0.05 30 ms 4 ms Remarks For repeated operation * : VCC must be less than 0.2 V before power-on. Notes : • The above rating values are for generating a power-on reset. • Some internal registers are only initialized by a power-on reset. Always apply the power supply in accordance with the above ratings if you wish to initialize these registers. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. The recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly as shown below. Also, changes to the supply voltage should be performed when the PLL clock is not in use. The PLL clock may be used, however, if the rate of voltage change is 1 V/s or less. VCC Recommended rate of voltage rise is 50 mV/ms or less. 3.0 V Maintain RAM data VSS 64 MB90560/565 Series (4) UART0, UART1, and I/O Expansion Serial Timings (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width Condition Value Unit Remarks Min. Max. SCK0, SCK1 8 tCP ns SCK0, SCK1 SOT0, SOT1 −80 80 ns 100 ns SCK0, SCK1 SIN0, SIN1 60 ns tSHSL SCK0, SCK1 4 tCP ns Serial clock “L” pulse width tSLSH SCK0, SCK1 4 tCP ns SCK ↓ → SOT delay time tSLOV 150 ns Valid SIN → SCK ↑ tIVSH 60 ns SCK ↑ → valid SIN hold time tSHIX 60 ns Internal shift clock mode, output pin load is SCK0, SCK1 CL = 80 pF + 1 TTL SIN0, SIN1 External shift clock SCK0, SCK1 mode, output pin load is SOT0, SOT1 CL = 80 pF + 1 TTL SCK0, SCK1 SIN0, SIN1 SCK0, SCK1 SIN0, SIN1 Notes : • These are the AC ratings for CLK synchronous mode. • CL is the load capacitor connected to the pin for testing. • tCP is the machine cycle period (unit = ns) 65 MB90560/565 Series • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN 66 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB90560/565 Series (5) Timer Input Timings Parameter (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Symbol Pin Name Input pulse width tTIWH, tTIWL FRCK, IN0, IN1, TIN0, TIN1 0.8 VCC Value Condition Min. Max. 4 tCP Remarks ns 0.8 VCC 0.2 VCC tTIWH 0.2 VCC tTIWL (6) Timer Output Timings Parameter Unit (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Value CondiUnit Remarks tion Min. Max. Symbol Pin Name tTO RTO0 to RTO5, PPG0 to PPG5, TO0 to TO1 CLK ↑ → TOUT change time 30 ns 2.4 V CLK tTO 2.4 V 0.8 V TOUT (7) Trigger Input Timings Parameter Input pulse width (TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Symbol tTRGL Pin Name Condition INT0 to INT7, IN0 to IN3 0.8 VCC Value Unit Remarks Min. Max. 5 tCP ns In normal operation 1 µs In stop mode 0.8 VCC 0.2 VCC tTRGH 0.2 VCC tTRGL 67 MB90560/565 Series 5. Electrical Characteristics for the A/D Converter (TA = −40 °C to +85 °C, 3.0 V ≤ AVR, VCC = AVCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Resolution Total error Value Unit Min. Typ. Max. 10 bit ±5.0 LSB Non-linearity error ±2.5 LSB Differential linearity error ±1.9 LSB Zero transition voltage VOT AN0 to AN7 AVSS −3.5 LSB +0.5 AVSS +4.5 LSB mV Full-scale transition voltage VFST AN0 to AN7 AVR AVR AVR −6.5 LSB −1.5 LSB +1.5 LSB mV Conversion time 176 tCP ns Sampling time 64 tCP ns Analog port input current IAIN AN0 to AN7 10 µA Analog input voltage VAIN AN0 to AN7 0 AVR V AVR 2.7 AVCC V IA AVCC 5 mA IAH AVCC 5 µA IR AVR 400 µA IRH AVR 5 µA AN0 to AN7 4 LSB Reference voltage Power supply current Reference voltage supply current Variation between channels Remarks 1 LSB = AVRH/1024 * * * : Current when A/D converter is not used and CPU is in stop mode (VCC = AVCC = AVR = 5.0 V) Notes : • The L reference voltage is fixed to AVSS. The relative error increases as AVR becomes smaller. • Ensure that the output impedance of the external circuit connected to the analog input meets the following condition : Output impedance of external circuit ≤ 10 kΩ (Sampling Time = 4.0 µs) • If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short. • Equivalent circuit of analog input circuit RON C Comparator Analog input MB90561/A, MB90562/A RON = 2.2 kΩ approx. C = 45 pF approx. MB90F562 RON = 3.2 kΩ approx. C = 30 pF approx. MB90F562/B RON = 2.6 kΩ approx. C = 28 pF approx. Note : The values listed are an indication only. 68 MB90560/565 Series 6. Flash Memory Erase and Programming Performance Parameter Condition Sector erase time Chip erase time TA = + 25 °C Vcc = 5.0 V Word (16 bit width) programming time Value Units Remarks 15 s Excludes 00H programming prior erasure 5 s Excludes 00H programming prior erasure 16 3,600 µs Excludes system-level overhead Min Typ Max 1 Erase/Program cycle 10,000 cycle Data holding time 100,000 h 69 MB90560/565 Series ■ ELECTRICAL CHARACTERISTICS (MB90565 SERIES) 1. Absolute Maximum Ratings Parameter (VSS = AVSS = 0.0 V) Rating Symbol Unit Remarks Min. Max. VCC VSS − 0.3 VSS + 4.0 V AVCC VSS − 0.3 VSS + 4.0 V VCC ≥ AVCC*1 AVR VSS − 0.3 VSS + 4.0 V AVCC ≥ AVR ≥ 0 V *1 Input voltage VI VSS − 0.3 VSS + 4.0 V *2 Output voltage VO VSS − 0.3 VSS + 4.0 V *2 “L” level maximum output current IOL 15 mA *3 “L” level average output current IOLAV 4 mA Average value (operating current × operating ratio) “L” level total maximum output current ΣIOL 100 mA ΣIOLAV 50 mA Average value (operating current × operating ratio) IOH −15 mA *3 “H” level average output current IOHAV −4 mA Average value (operating current × operating ratio) “H” level total maximum output current ΣIOH −100 mA ΣIOHAV −50 mA Power consumption Pd 300 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C Power supply voltage “L” level total average output current “H” level maximum output current “H” level total average output current Storage temperature Average value (operating current × operating ratio) *1 : AVCC and AVR must not exceed VCC. Also, AVR must not exceed AVCC. *2 : VI and VO must not exceed VCC + 0.3 V. *3 : The maximum output current is the peak value for a single pin. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 70 MB90560/565 Series 2. Recommended Operating Conditions Parameter Power supply voltage Input “H” voltage Input “L” voltage Operating temperature Symbol (VSS = AVSS = 0.0 V) Value Unit Remarks Min. Max. 3.0 3.6 V Normal operation (MB90V560) 2.7 3.6 V Normal operation (MB90F568, MB90567 and MB90568) 2.5 3.6 V Maintaining state in stop mode VIH 0.7 VCC VCC + 0.3 V CMOS input pin VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin VIHM VCC − 0.3 VCC + 0.3 V MD input pin VIL VSS − 0.3 0.3 VCC V CMOS input pin VILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin VILM VSS − 0.3 VSS + 0.3 V MD input pin TA −40 +85 °C VCC WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 71 MB90560/565 Series 3. DC Characteristics (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) Value Parameter Sym Pin Name bol Output “H” voltage VOH All output pins VCC = 3.0 V IOH = −2.0 mA Output “L” voltage VOL All output pins VCC = 3.0 V IOL = 2.0 mA Input leak current IIL All output pins VCC = 3.0 V VSS < VI < VCC ICC Power supply current* VCC ICCS ICCH Condition Min. Typ. VCC − 0.5 VCC − 0.3 Max. Unit Remarks V 0.2 0.4 V −5 −1 5 µA For VCC = 3.3 V, internal frequency = 8 MHz, normal operation 14 22 mA MB90567/568 For VCC = 3.3 V, internal frequency = 16 MHz, normal operation 27 40 mA MB90567/568 For VCC = 3.3 V, internal frequency = 8 MHz, A/D operation in progress 18 27 mA MB90567/568 For VCC = 3.3 V, internal frequency = 16 MHz, A/D operation in progress 32 45 mA MB90567/568 For VCC = 3.3 V, internal frequency = 8 MHz, normal operation 18 28 mA MB90F568 For VCC = 3.3 V, internal frequency = 16 MHz, normal operation 36 45 mA MB90F568 For VCC = 3.3 V, internal frequency = 8 MHz, A/D operation in progress 23 33 mA MB90F568 For VCC = 3.3 V, internal frequency = 16 MHz, A/D operation in progress 41 50 mA MB90F568 Flash write or erase 40 50 mA MB90F568 For VCC = 3.3 V, internal frequency = 8 MHz, sleep mode 6 10 mA MB90567/568 MB90F568* For VCC = 3.3 V, internal frequency = 16 MHz, sleep mode 14 20 mA MB90567/568 MB90F568* Stop mode, TA = 25 °C 5 20 µA * : Value when low power mode bits (LPM0, 1) are set to “01” with an internal operating frequency of 8 MHz. (Continued) 72 MB90560/565 Series (Continued) Parameter Pull-up resistor Pull-down resistor Symbol RUP Pin Name P00 to P07 P10 to P17 RST, MD0, MD1 RDOWN MD2 Condition Value Unit Min. Typ. Max. 20 65 200 kΩ 20 65 200 kΩ Remarks Note : Current values are provisional and are subject to change without notice to allow for improvements to the characteristics. The power supply current is measured with an external clock. 73 MB90560/565 Series 4. AC Characteristics (1) Clock Timings Parameter (MB90567/568/F568 : TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) (MB90V560 : TA = +25 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) Sym CondiPin Name bol tion Clock frequency fC X0, X1 Clock cycle time tHCYL X0, X1 Input clock pulse width PWH PWL X0 Input clock rise/fall time tcr tcf X0 Internal operating clock frequency Internal operating clock cycle time fCP tCP Value Unit Typ. Max. 3 12 MHz MB90V560 3 16 MHz 83.3 333 ns MB90V560 62.5 333 ns MB90567/568 MB90F568 10 ns Recommended duty ratio = 30% to 70% 5 ns When using an external clock 1.5 12 MHz MB90V560 1.5 16 MHz 83.3 666 ns MB90V560 62.5 666 ns MB90567/568 MB90F568 Remarks Min. MB90567/568 MB90F568 MB90567/568 MB90F568 • X0 and X1 clock timing tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tcf 74 tcr MB90560/565 Series • PLL guaranteed operation range Relationship between internal operating clock frequency and power supply voltage PLL guaranteed operation range (MB90567/568/F568 : 3.0 V to 3.6 V, fCP = 3 MHz to 16 MHz) (MB90V560 : 3.0 V to 3.6 V, fCP = 3 MHz to 12 MHz) Supply Voltage VCC (V) 3.6 PLL guaranteed A/D converter operation range guaranteed operation range 3.0 2.7 Guaranteed operation range for MB90V560 (3.0 V to 3.6 V, fCP = 1.5 MHz to 12 MHz) 1.5 3 Guaranteed operation range for MB90567/568/F568 (3.0 V to 3.6 V, fCP = 1.5 MHz to 16 MHz) (2.7 V to 3.6 V, fCP = 1.5 MHz to 8 MHz) 8 12 16 Internal Clock fCP (MHz) Relationship between oscillation frequency and internal operating clock frequency ×4 Internal Clock fCP (MHz) 16 ×3 ×2 ×1 12 9 8 No multiplier 6 4 3 2 1.5 3 4 6 8 12 16 Source Oscillation Clock fC (MHz) The AC ratings are specified for the following measurement reference voltages. • Input signal waveform Hysteresis input pin • Output signal waveform Output pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pins other than hysteresis input or MD input pins 0.7 VCC 0.3 VCC 75 MB90560/565 Series (2) Reset (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) Parameter Symbol Reset input time tRSTL Value Pin Name Condition RST Unit Remarks Min. Max. 16 tCP ns In normal operation Oscillator oscillation time* + 16 tCP ms In stop mode *: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several dozen ms; for a FAR/ceramic oscillator, this is several hundred µs to a few ms, and for an external clock this is 0 ms. • In normal operation tRSTL RST 0.2 VCC 0.2 VCC • In stop mode tRSTL RST 0.2Vcc X0 Internal operation clock 0.2Vcc 90 % of amplitude Oscillator oscillation time 16 tcp Oscillator stabilization wait time Execution of the instruction Internal reset 76 MB90560/565 Series (3) Power-On Reset Parameter Power supply rise time Power supply cutoff time (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) Symbol Pin Name tR VCC* tOFF VCC Condition Value Unit Min. Max. 0.05 30 ms 4 ms Remarks For repeated operation * : VCC must be less than 0.2 V before power-on. Notes : • The above rating values are for generating a power-on reset. • Some internal registers are only initialized by a power-on reset. Always apply the power supply in accordance with the above ratings if you wish to initialize these registers. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. The recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly as shown below. Also, changes to the supply voltage should be performed when the PLL clock is not in use. The PLL clock may be used, however, if the rate of voltage change is 1 V/s or less. VCC Recommended rate of voltage rise is 50 mV/ms or less. 2.5 V Maintain RAM data VSS 77 MB90560/565 Series (4) UART0 and UART1 Parameter (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) Symbol Pin Name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width Condition Unit Remarks Min. Max. SCK0, SCK1 8 tCP ns SCK0, SCK1 SOT0, SOT1 Internal shift clock mode, output pin SCK0, SCK1 load is SIN0, SIN1 CL = 80 pF + 1 TTL SCK0, SCK1 SIN0, SIN1 −80 80 ns 100 ns 60 ns tSHSL SCK0, SCK1 4 tCP ns Serial clock “L” pulse width tSLSH SCK0, SCK1 4 tCP ns SCK ↓ → SOT delay time tSLOV 150 ns Valid SIN → SCK ↑ tIVSH 60 ns SCK ↑ → valid SIN hold time tSHIX 60 ns SCK0, SCK1 External shift clock SOT0, SOT1 mode, output pin load is SCK0, SCK1 CL = 80 pF + 1 TTL SIN0, SIN1 SCK0, SCK1 SIN0, SIN1 Notes : • These are the AC ratings for CLK synchronous mode. • CV is the load capacitor connected to the pin for testing. • tCP is the machine cycle period (unit = ns) 78 Value MB90560/565 Series • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 79 MB90560/565 Series (5) Timer Input Timings Parameter Input pulse width (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) Symbol Pin Name tTIWH, tTIWL FRCK, TIN0, TIN1 Value Condition Min. Max. 4 tCP 0.8 VCC Unit Remarks ns 0.8 VCC 0.2 VCC FRCK TIN0 to 1 0.2 VCC tTIWH tTIWL (6) Timer Output Timings (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Condition CLK ↑ → TOUT change time tTO RTO0 to RTO5, PPG0 to PPG5 TO0, TO1 Value Min. Max. 30 Unit Remarks ns 2.4 V CLK tTO 2.4 V 0.8 V TOUT (7) Trigger Input Timings Parameter Input pulse width (TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) Symbol tTRGL Pin Name INT0 to INT7, IN0 to IN3 0.8 VCC Value Remarks Max. 5 tCP ns In normal operation 1 µs In stop mode 0.2 VCC tTRGH Unit Min. 0.8 VCC INT0 to INT7 IN0 to IN3 80 Condition 0.2 VCC tTRGL MB90560/565 Series 5. Electrical Characteristics for the A/D Converter (MB90567/568/F568 : TA = −40 °C to +85 °C, 2.7 V ≤ AVR, VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V) (MB90V560 : TA = +25 °C, 3.0 V ≤ AVR, VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Resolution Total error Value Unit Min. Typ. Max. 10 bit ±3.0 LSB Non-linearity error ±2.5 LSB Differential linearity error ±1.9 LSB Zero transition voltage VOT AN0 to AN7 AVSS −1.5 LSB AVSS +0.5 AVSS +2.5 LSB mV VFST AN0 to AN7 AVR AVR AVR −3.5 LSB −1.5 LSB +0.5 LSB mV Conversion time 66 tCP ns Sampling time 32 tCP ns Analog port input current IAIN AN0 to AN7 10 µA Analog input voltage VAIN AN0 to AN7 0 AVR V AVR 2.7 AVCC V IA AVCC 1 5 mA IAH AVCC 5 µA IR AVR 100 200 µA IRH AVR 5 µA AN0 to AN7 4 LSB Full-scale transition voltage Reference voltage Power supply current Reference voltage supply current Variation between channels Remarks 1 LSB = AVRH/1024 * * * : Current when A/D converter is not used and CPU is in stop mode (VCC = AVCC = AVR = 3.3 V) Notes : • The L reference voltage is fixed to AVSS. The relative error increases as AVR becomes smaller. • Ensure that the output impedance of the external circuit connected to the analog input meets the following condition : Output impedance of MB90F568 external circuit ≤ 14 kΩ (Sampling Time = 4 µs) Output impedance of MB90567/568 external circuit ≤ 7 kΩ (Sampling Time = 4 µs) • If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short. 81 MB90560/565 Series • Equivalent circuit of analog input circuit RON C Comparator Analog input MB90567/568/F568 RON = 7.1 kΩ approx. C = 48.3 pF approx. Note : The values listed are an indication only. 82 MB90560/565 Series 6. Flash Memory Erase and Programming Performance Parameter Value Condition Remarks 15 s Excludes 00H programming prior erasure 5 s Excludes 00H programming prior erasure 16 3,600 µs Excludes system-level overhead Typ Max 1 Sector erase time Chip erase time Units Min TA = + 25 °C Vcc = 3.3 V Word (16 bit width) programming time Erase/Program cycle 10,000 cycle Data holding time 100,000 h • Points to note regarding the MB90F568, 567, and 568 specifications This section describes the specification differences between the MB90F568/567/568 and the MB90F562/F562B/ 562/562A/561/561A. (1) Functional differences 1) The 5 V to 3 V regulator has been removed in the MB96565 series. The C pin has been changed to an N.C. pin. 2) The A/D converter unit in the MB96565 series has changed from a 5 V version to a 3 V version. However, the conversion time and sampling time remain the same. 3) The maximum voltage that can be applied to I/O pins has changed from 5 V to 3 V in the MB96565 series. 4) Added transfer counter clear function to UART in the MB96565 series. This function restores the UART to its initial state when “0” is written to the UART reset bit. (2) Points to note when using the devices The MB90F562, F562B, and F568 use P60 (14) as SIN1, P61 (15) as SOT1, and P40 (60) as SCK0 when performing on-board programming. Use the following pin settings when performing on-board programming. Pin Name Pin I/O Level* Remarks MD2 “H” level MD1 “H” level MD0 “L” level SIN1 Serial data input Normally shared with P60 SOT1 Serial data output Normally shared with P61 SCK0 Serial clock Normally shared with P40 P00 “L” level P01 “H” level Serial write mode settings Input “L” level for PC writing * : These settings are for using a Yokogawa Digital Computer Corporation writer for on-board programming. Alternatively, writing can be performed from a PC, but a special write program is required. 83 MB90560/565 Series ■ EXAMPLE CHARACTERISTICS MB90F568 ICC − VCC 60 TA = +25 °C ICC (mA) 50 16 MHz 40 12 MHz 30 8 MHz 20 4 MHz 10 2 MHz 0 2 2.5 3 3.5 4 4.5 VCC (V) MB90568 ICC − VCC 40 TA = +25 °C 35 16 MHz ICC3 (mA) 30 12 MHz 25 20 8 MHz 15 10 4 MHz 5 2 MHz 0 2 2.5 3 3.5 4 4.5 VCC (V) MB90F568 ICCS − VCC 20 TA = +25 °C 18 16 MHz 16 ICCS (mA) 14 12 MHz 12 10 8 MHz 8 6 4 MHz 4 2 MHz 2 0 2 2.5 3 3.5 4 4.5 VCC (V) (Continued) 84 MB90560/565 Series MB90568 ICCS − VCC 18 TA = +25 °C 16 16 MHz 14 12 MHz ICCS (mA) 12 10 8 MHz 8 6 4 4 MHz 2 2 MHz 0 2 2.5 3 3.5 4 4.5 VCC (V) MB90F562 ICC − VCC 40 TA = +25 °C f = 16 MHz 35 ICC (mA) 30 f = 12 MHz 25 f = 10 MHz 20 f = 8 MHz 15 f = 4 MHz 10 f = 2 MHz 5 0 2.5 3 3.5 4 4.5 5 5.5 6 6.5 VCC (V) MB90562 ICC − VCC 70 TA = +25 °C 60 f = 16 MHz ICC (mA) 50 f = 12 MHz 40 f = 10 MHz 30 f = 8 MHz 20 f = 4 MHz 10 0 2.5 f = 2 MHz 3 3.5 4 4.5 5 5.5 6 6.5 VCC (V) (Continued) 85 MB90560/565 Series (Continued) MB90F562 ICCS − VCC 16 14 TA = +25 °C f = 16 MHz ICCS (mA) 12 f = 12 MHz 10 f = 10 MHz 8 f = 8 MHz 6 4 f = 4 MHz 2 f = 2 MHz 0 2.5 3 3.5 4 4.5 5 5.5 6 6.5 VCC (V) MB90562 ICCS − VCC 30 TA = +25 °C 25 f = 16 MHz ICCS (mA) 20 f = 12 MHz f = 10 MHz 15 f = 8 MHz 10 f = 4 MHz 5 f = 2 MHz 0 2.5 3 3.5 4 4.5 VCC (V) 86 5 5.5 6 6.5 MB90560/565 Series ■ ORDERING INFORMATION • MB90560 series Part No. MB90561P MB90562P MB90561AP MB90562AP MB90F562P MB90F562BP Package Remarks 64-pin plastic SH-DIP (DIP-64P-M01) MB90561PF MB90562PF MB90561APF MB90562APF MB90F562PF MB90F562BPF 64-pin plastic QFP (FPT-64P-M06) MB90561PFM MB90562PFM MB90561APFM MB90562APFM MB90F562PFM MB90F562BPFM 64-pin plastic LQFP (FPT-64P-M09) • MB90565 series Part No. Package MB90567PF MB90568PF MB90F568PF 64-pin plastic QFP (FPT-64P-M06) MB90567PFM MB90568PFM MB90F568PFM 64-pin plastic LQFP (FPT-64P-M09) Remarks 87 MB90560/565 Series ■ PACKAGE DIMENSIONS 64-pin plastic QFP (FPT-64P-M06) Note : Pins width and pins thickness include plating thickness. 24.70±0.40(.972±.016) 20.00±0.20(.787±.008) 51 0.17±0.06 (.007±.002) 33 52 32 18.70±0.40 (.736±.016) 14.00±0.20 (.551±.008) INDEX Details of "A" part +0.35 3.00 –0.20 +.014 .118 –.008 64 (Mounting height) 20 0~8° 1 19 1.00(.039) 0.42±0.08 (.017±.003) 0.20(.008) +0.15 M 0.25 –0.20 1.20±0.20 (.047±.008) +.006 .010 –.008 (Stand off) "A" 0.10(.004) C 2001 FUJITSU LIMITED F64013S-c-4-4 Dimensions in mm (inches) (Continued) 88 MB90560/565 Series 64-pin plastic LQFP (FPT-64P-M09) Note : Pins width and pins thickness include plating thickness. 14.00±0.20(.551±.008)SQ 12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.0057±.0022) 33 49 32 0.10(.004) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 (Mounting height) 0.25(.010) INDEX 0~8° 64 17 1 0.65(.026) C "A" 16 0.32±0.05 (.013±.002) 0.13(.005) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) M 2001 FUJITSU LIMITED F64018S-c-2-4 Dimensions in mm (inches) (Continued) 89 MB90560/565 Series (Continued) 64-pin plastic SH-DIP (DIP-64P-M01) Note : Pins width and pins thickness include plating thickness. +0.22 +.009 58.00 –0.55 2.283 –.022 INDEX-1 17.00±0.25 (.669±.010) INDEX-2 +0.70 4.95 –0.20 +.028 .195 –.008 +0.50 0.70 –0.19 +.020 .028 –.007 0.27±0.10 (.011±.004) +0.20 3.30 –0.30 .130 +.008 –.012 1.378 .0543 C +0.40 –0.20 +.016 –.008 1.778(.0700) 0.47±0.10 (.019±.004) 19.05(.750) +0.50 0.25(.010) M 1.00 –0 +.020 0~15° .039 –.0 2001 FUJITSU LIMITED D64001S-c-4-5 Dimensions in mm (inches) 90 MB90560/565 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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