FREESCALE MC146805E2

Freescale Semiconductor, Inc.
*’
MC146805E2
o
[
Advance
Information
CMOS
I
(HIGH PERFORMANCE
8-BIT MICROPROCESSOR
The MCl@05E2
Microprocessor Unit
Family of Microcomputers.
This 8-bit
microprocessor contains a CPU, on-chip
low-power, low-cost processor designed
UNIT
(MPU) belongs to the M6805
fully static and expandable
RAM, 1/0, and TIMER. It is a
for low-end to mid-range ap-
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plications in the consumer, automotive,
industrial, and communications
markets where very low power consumption
constitutes
an important
factor. The following
are the major features of the MC146805E2 MPU:
HARDWARE FEATURES
● Typical Full Speed Operating Power of 35 mW @ 5 V
● Typical WAIT Mode Power of 5 mW
● Typical STOP Mode Power of 25 pW
.112
<’~
,...~
~:1,
~.,l
~!,$&
Bytes of On-Chip RAM
● 16 Bidirectional
1/0 Lines
.,i.~::
O Internal 8-Bit Timer with Software Programmable 7-Bit Pres&i~eX:t
,V.,,1*\<jy, .
● External Timer Input
.?,+
‘$~,,
.*>, .,,.
~~!,~:~
.3.,$$
..
● Full External and Timer Interrupts
,...’~$,
,,
>tt?l\,..,v,,l
.~..l~l
, ,
~..
,.
● Multiplexed Address/Data Bus
..~.,
$:,$?,
● Master Reset and Power-On Reset
,.
●
● Capable of Addressing Up to 8K Bytes of E~:$~RQlMemory
“*:,, ‘~it:t~.
.i$$,-if.s<::,~.+,
,J:;, “,,, . ~
,,,
: , ~:,‘*I,
“i${J! .,,
**;J?,”
..,.$}
......
t...,.,...~+.l
..v.>M4\.
/~\:/l\..,\
,
:.+.
● Single 3- to 6-Volt Supply
● On-Chip Oscillator
● W-Pin Dual-In-Line
Package
● Chip Carrier Also Available
\
o
[M”
m[
DS[
,.~ .;:*
i\,!~’
● +.,.’
T$&$Fo&er
.
,y, *,,~\.?
..
Set
1/0
Saving Standby Modes
!
38 ]OSC2
4
37 ]TIMER
5
36 ]P80
AS [ 6
35 ]P81
PA7 [ 7
34 ]PB2
PA6 [ 8
33 ]PB3
PA5 [ 9
32 ]PB4
R~[
● Addressin@~~~~@ with Indexed Addressing for Tables
● Efficie~~%u&tion
PA4[ 10
31 ]PB5
PA3[ 11
30 ]PB6
PA2~
12
29 ]PB7
PA1 [
13
28 ]BO
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This document
are subject
contains
to change
information
without
notice.
For More Information On This Product,
Specifications
herein
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to:information
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761
39 ]Oscl
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● Versatile lnterrup$~a~ting
~.‘**,{
CARRIER
CASE
40 ]VDD
● Efficient Use of Prog%,#pace
● True Bit Ma~~@ulatrbti
Z SUFFIX
CHIP
PIN ASSIGNMENTS
~h>-,+
.,.\*.
“
..:,~
‘\\w
,,!,.:?.
SOFTWARE FEATURES
,..~-’~qa;$
..,.~%..
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0 Similar to the MC68~ ,~d>.
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● Memq,$~apped
●
‘.!*$
SILICONe$~
INC.,
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ADl~R:
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●
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‘,
Data
Bus
Address
Bus
Address
Data
Strobe
Strobe
Read/Wtite
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DC ELECTRICAL
CHARACTERISTICS
@ 3.0 V (VDD=3.O Vdc, VSS =0, TA= TL to TH, unless otherwise noted)
Charactetiatica
Symbol
Total Supply Current (CL=50 pF – No dc Loads, tcYc=5
Run (VIL=O.2 V, VIH=VDD–
O.2 V)
Wait (Test Conditions
– See Note Below)
Stop (Test Conditions
– See Note Below)
pS)
~. ,,,.,
$:$+$.,’
,+,+ *.7..
~,.
IDD
IDD
Freescale Semiconductor, Inc...
Va@&i$<
mA) pAO-pA7, pBO-pB7
Input High Voltage
PAO-PA7, PBO-PB7, BO-B7
RESET
Frequency of Operation
Crystal
External Clock
Input Current
—
—
RESET, IRQ, TIMER, OSCI
..,,
,.,$,,.,
!$. ,,\kp,
.,~,,
~1j>> ‘~$
a$i~?+
,,,y,,
~, .,:.’.,
,+1
,<\\, ~
Hi-Z Output Leakage
PAO-PA7, PBO-PB7, BO-B7
Capacitance
*.. “i
NOTE: Test conditions for Quiew~~~&ent
~?..~$’
.’ ..*.;.
\i,y.:q.,,
:,* $.~.,ft!~
~~, ,+.,.
~,
‘:,
., *.
.},r
x),. ..f$
*$
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..$iJ\...
t\....
,
t{,~.
t;.
,rt,
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“.?
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.....
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.
,!..\?
,
,-’
~ii~$
.< ; ‘~OL
~t,3~* -.
,:,,, .,.
~S...i,* .,:~:y.
vlH
‘,8:,>.
“~+’;+.
!,
~>f
$%>
i~
vlH
.), + ,1*
.,::$
,,~1
~. \\+.
f!:l:,>,,
,
Oscl
Input Low Voltage (All Inputs)
.
PA
PA
,>.
~1:,
,
2,7
–
v
2,7
–
v
—
0.3
v
2,1
–
v
2,5
–
v
2,1
—
—
v
0.5
v
fosc
–
1.0
MHz
fosc
dc
1.0
MHz
Iin
—
*I
PA
ITSL
–
*10
PA
VIH
vlL
values are:
Port A and B prog@m@d as inputs.
PBO-PB7, and BO-B7.
vIL=O.2 V fo$:~~%~?,
—
—
vlH=vDQ–&~~~,~Or
RESET, IRQ, and TIMER
OSC1 in~~~,js a $~uarewave from VSS +0,2 V to VDD – 0,2 V,
OSC2 ~’h~~~.~ad (including tester) is 35 pF maximum,
‘~4,,,
W~~~r@e~DD
is affected linearly by this capacitance.
;~, i.:ih, ~.,
.0
MOTOROLA
mA
~~y.,Y~.,
Output Low Voltage
(lLoad=0.25 mA) A8-A12, BO-B7, PBO-PB7, DS, AS, R/~, PAO-PA7
TIMER, ~Q,
,, ,:1 .,”y: ‘“
+i +$,,,,<< v
-, ,.,,,,’.. \ .!),:..
*::~,.$.,,?$,
‘~”$’”1.3
$,$}~~
$
~f *,,
~)~$
200
-~~t:t,,,
,_}<:j
100
>
X,*.,,$<
IDD
Output High Voltage
(lLoad=0.25 mA) A8-A12, BO-B7, DS, AS, R/~
(lLoad=O.l
VDD:O,,
vOL
vOH
Output Voltage (1Load< 10,0 vA)
“!$,?<<
Ma&*~# **t
Min
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TABLE 1 – CONTROL TIMING (VSS= O, TA=TL
to TH)
VDD=3.O V
fo~c = 1 MHz
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Characteristics
VDD=5.O
Symbol
Min
1/0 Port Timing – Input Setup Time (Figure 3)
tpVASL
5m
Input Hold Time (Figure 3)
tASLpX
lm
Output Delay Time (Figure 3)
tAS LpV
–
–
Interrupt Setup Time (Figure 6)
tlLASL
2
–
o
—
Typ
Max
Min
Tvp
–
–
250
–
–
100
—
–
—
Crystal Oscillator Startup Time (Figure 5)
toxov
–
30
300
Wait Recovery Startup Time (Hgure 71
tlVASH
–
–
10
Stop Recovery Startup Time (Crystal Oscillator) (Figure 8) tlLASH
–
30
3m
Required Interrupt Release (Figure 6)
tDSLIH
tTH, tTL
0.5
Reset Pulse Width (Figure 5)
tR L
5.5
–
Timer Period (Figure 7)
tT LTL
1.0
–
Interrupt Pulse Width Low (Figure 16)
tlLIH
1.0
Interrupt Pulse Period “(Figure 16)
tlLIL
*
—
.s.%!,,s
,., =$s
~:?:
_ {t;. ..~\ :+.
,F< —
,, <.,
...
Oscillator Cycle Petiod [1/5 of tcyc)
OSCI
tOLOL
-
I
-
,,M’>ia.a+ I
.<,,J
to ~
350 ,#b*
OSCI Pulse Width Low
tOL
3gg:’’~’?i**
,.
:..,
-
,...
–
~$li$
,,*:*;>.,:1,0
kti<.
~
Pulse Width High
.,,.
—!.:$,?,,
,,.,\>N,
~:,,.:! ;5
–
ns
fls
ms
ps
ms
I
tr,,fl
“r-
–
#s
tcyc
–
–
–
–
%
–
—
tcyc
tcyc
200
–
—
ns
75
–
–
ns
–
75
–
—
ns
CMOS Equivalent
1
‘estpoint
1
C=50 pF, PAO-PA7, PBO-PB7
= 130 pF, A8-A12, BO-B7, DS,
with VDD=5 V + 10%
●
MOTOROLA
-
1.0
●
@
I
.!,.
A),
—
‘“ –
.?:> “’*’
1000
I
l<: ,<. \ “~~
— ,...‘1Ii?’
‘“&~:
,.,+J.;. ,.*,*
.,./’
0,4
—,3?:;,.
~,,~.
~y~y:
.:
–
–
,, ‘8“ 100
\?.$
.
..,&,,,,,!
–
,,,
2
,.>,~1~
—<l?s,!:
.~. ,,$ 15
100
., .,. .
Timar Pulse Width (Figure 7)
,I
V + 10%
fo~c = 5.0 MHz
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●
●
●
I
J
●
●
●
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●
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●
~tTL
Internal/External
Clock
#
tTH
~,’,.
TCRb7
n
AS n
DS
Unmux
A8-A12
Address Bus
Mux BO-B7
Address/Data
Bus
Int Routine Starting Addr
x
x x
h~
Addr+
1
k
IF
/
SP
x b///////;////////////////N
x PCL
SP–11
5P–2
X PCH
SP–3
x
SP-4
A
lF
x
F7
F6
cc
New PCti
A
/~
New
x./
XG
x
XK
PCL 1st Op Code Int
RO tine
●
●
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FUNCTIONAL
PIN DESCRIPTION
VDD AND Vss
o
VDD and VSS provide power to the chip. VDD provides
power and VSS is ground.
~Q
(MASKABLE
INTERRUPT REQUEST)
IRQ is both a level-sensitive and edge-sensitive input
which can be used to request an interrupt sequence. The
M PU completes the current instruction before it responds to
the request, If IRQ is low and the interrupt mask bit (1bit) in
the condition code register is clear, the MPU begins an interrupt sequence at the end of the current instruction, The interrupt circuit recognizes both a “wire ORed” level as well as
pulses on the IRQ line (see Interrupt section for more
details). IRQ requires an external resistor to VDD for “wire
OR” operation.
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RESET
0
The RESET input is not required for start-up but can be
used to reset the MPU internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed description.
TIMER
The TIMER input is used for clocking the on-chip timer,
Refer to Timer section for a detailed description.
AS (ADDRESS STROBE)
BUS)
The BO-B7 bidirectional lines constitute the lower order
addresses and data. These lines are multiplexed, with address present at address strobe time and data present at data
strobe time, When in the data mode, these lines are bidirectional, transferring data to and from memory and peripheral
devices as indicated by the R/~pin.
As outputs in either the
data or address modes, these lines are capable of driving one
standard TTL load and 130 pF,
.! ,.
A),,),,
.:$Y:,.,k.,
>...
.,,i~
,...’:t.:.,)i,’
The MC146805E2 provides for two types o~~$~!~qtor inputs – crystal circuit or external clock. T~$~$$bscillator
pins are used to interface to a crystal CLFmIN+aSshown
in
$t~
,.,,,,!*\.\
~sp
Figure 5. If an external clock is used, it~B%t@ connected to
OSCI. The input at these pins is div~@{~five
to form the
cycle rate seen on the AS and D~:~f~.me
frequency range
is specified by fosc. The OS~l ‘?~,,,@~stransitions relationships are provided in FigU{~~~ fot system designs using
oscillators slower than 5 ~~~!?$$
,.~,~.~
,-1,
‘,,..,:..*::
,<p ,,0
CRYSTAL – Theq[@~~@Shown in Figure 5 is recommended when using a wta.~he
internal oscillator is designed to
interface wit~.s~,,n AT-cut parallel resonant quartz crystal
resonator in-ttigtif$equency range specified for fosc in the
electrical~$ti~~~~~eristics table. An external CMOS oscillator
is recw,%:~#ed when crystals outside the specified ranges
are $~i:~e used, The crystal and components should be
M$unte&as close as possible to the input pins to minimize
.,~d~~ut
distortion and start-up stabilization time,
:@\..T<:i
Oscl,
0SC2
Address strobe (AS) is an output strobe used to indicate
::!*“!+w$$~
the presence of an address on the 8-bit multiplexed bus. The
EXTERNAL CLOCK – An external clock should be apAS line is used to demultiplex the eight least significant ad- ‘t$~.~~$:
,.
~lied to the OSCI input with the 0SC2 input not connected,
dress bits from the data bus, A latch controlled by address
“~~
as shown in Figure 10.
strobe should capture addresses on the negative edge,.+Thi@$’
output is capable of driving one standard TTL load 4’&I130
LI (LOAD INSTRUCTION)
~L,,,:@$~
,$t,i,;,
%,$,\:
.Ki?:’~
1,,.*,,.,
DS (DATA STROBE)
.1,3
!},,,..
$V.t,
This output is used to transfer data t@:~#$&& a peripheral
or memory. DS occurs anytime the M~$U’@8s a data read or
write. DS also occurs when the ~~~ ,{b’~k a data transfer to
or from the MPU internal [email protected],t%efer to Table 2 and
bf
Figure 4 for timing charact6ri$J::$This
output is capable
driving one standard T~&k~&and
130 pF. DS is a continuous signal at fosc,k+ 5~,#n the MPU is not in the WAIT
or STOP state. S@&’@bus cycles are redundant reads of
~:,‘$:,il~
<. >y<?$$~
opcode bytes,
,\t+w,
\ ‘,.:,
,..~-..\.,~.
,,,.
Rl~ (READ~t&~Tt)
The ~~~~u~ut
is used to indicate the direction of data
trao:,f~~fo~@6th internal memory and 1/O registers, and exter.ng~{p~.t~heral
devices and memories. This output is used
.:,J (’$~...
,.
,<to@&ate to a selected peripheral whether the M PU is going
‘~~k~~~d or write data on the next data strobe (R/~
I&_= processor write; R/~
high = processor read). The
R/W output is capable of driving one standard TTL load and
130 pF. The normal standby state is read (high).
A8-A12 (HIGH ORDER ADDRESS LINES)
●
BO-B7 (ADDRESS/DATA
The A8-A12 output lines constitute the higher order nonmultiplexed addresses. Each output line is capable of driving
one standard TTL load and 130 pF.
This output is used to indicate tha~ a fetch of the next opcode is in progress. LI remains low during an external or
timer interrupt. The LI output is used only for certain debugging and test systems. For normal operations this pin is not
connected. The LI output is capable of driving two standard
LSTTL loads and 50 pF. This signal overlaps data strobe,
PAO-PA7
These eight pins constitute input/output
port A. Each line
is individually programmed to be either an input or output
under software control via its data direction register as
shown in Figure Ii(b). An 1/0 pin is programmed as an output when the corresponding DDR bit is set to a “l”, and as
an input when it is set to a “O’. In the output mode the bits
are latched and appear on the corresponding output pins. An
M PU read of the port bits programmed as outputs reflects
the last value written to that location, When programmed as
an input, the input data Mt(s) are not latched. An MPU read
of the port bits programmed as inputs reflects the current
status of the corresponding input pins. The 1/0 port timing is
shown in Figure 3, See typical 1/0 port circuitry in Figure 11.
During a power-on reset or external reset, all lines are configured as inputs (zero in data direction register). The output
port register is not initialized by reset. The TTL compatible
three-state output buffers are capable of driving one standard TTL load and 50 pF. The DDR is a re~d/write register.
—
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.. ,,,,., .. ,, ., ,,.
.l .
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FIGURE”9 -.OSCI
TO BUS TRANSITIONS’
~‘. .
,,
,,.j,.~:,,
,,. .
,,.,
,’
.
L’.,
...”
,,,
,-,
.
:,
,.
..-.
,,
.,
.,.
.,.
,’-,..,, ,,, ,
~~
,, :,:
,.
7,
,., .
,,.
“-
:,
,
,
.:
:
,:
,,
,.
0
.,
,,””
,,
,,
,!
..,:~.,
,,,
,.,’
,,.
,,.
,.
. :,,
,“
,,,
,,,
.,
,.
..,:
Freescale Semiconductor, Inc...
,.
,.
,.,
,,
.,.
. -,.
.“.,
,,
,:
...
.,.
.,
r.,,
.,
,,.
,
,,
,.
.,
:,
’., ,,.
:,,
,,, ,,,,
,,
,,
-
........ .
.
! .:
.,-,’
,,
.,,
.,
●-
‘,
,’
BO-B7
,,,
‘:’
,’,
. ..
,,
., .’..,
,,
,,
.,.
Oscl
: ,,,,r.y%ii,~f
- 39g ~iq;:,
,,
...
-’
.
:,,
;,, ,,
.,, .
.
,,
,J ,., ...,
,
,.,
.,
The inter~al ‘memory spade is located within the first 128
“ bytes of ,rnemory (first half of page zero) and is comprised of
the “1/0 port locations, flmer locations, and 112 bytes of
RAM. The MPU can read from or write to anj of,these loca~ ,tions. ”A p~ogra,m write to on-chip locations is repeated on
the external bus to permit off-chip”’memory to duplicate the
content of on-chip me,mory. Program reads to on-chip ioca‘ tions also appear on theextern”al bus, but the MPU accepts
~~ data only from the addressed on-chip location, Any read
-.,
,,
data appearing ‘on the’’input bus. is ignored.
The stack pointer is. used’ to” address data stored on the
stack. Data is stored on the stack during interrupts and
subroutine calls. At power-up, the stack pointer is set to
“$O07F and it ii’ decremented
as data is pushed onto the
,.,
stack. When data is removed from the stack, the stack
., pointar is incremented. A maximum of W bytes of RAM is
.:
,,,
;,
‘MEMOR~’ADDRESSING,
available
,’ .’,
~.,’
‘:},:;’,
,. .,-.
.. :..,’ ,,.
,,.,.’,
,’
,,
,,
,,.
,.;
,’
:,,
~~
,,
‘,’.
for program data storage.
~”
All memory locations above location $007F:are part of the
externalmemory
map. In addition, ten’locations in the 1/0
portion of the lower 128 bytes of memory space, as shown in
,
.
,,
.,
>,
;
..
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:.’.’!-:,
.......
...
.
,,,
,..
~.~
-’ -,, -,.,,,.- .,,,,,
:., .“;.,,
q:.
‘~~~~~~~~
~~ For
~~
use only a
; ,,subrouti,ne stacking purposes,’ the unused bytes are usable
“ The M CI%805E2 is ‘capable of’addressing 8192 bytes of’
rn,amory and 1/0 registers, The address s“pace:is di~ded into
internal memory space ‘and’ external’ memory: spacej as!”
shown in Figure 12.
for stack usage, Since most programs
,small part of the allotted stack locations for interrupts and/or
●
Freescale Semiconductor, Inc.
FIGURE 11 – TYPICAL PORT 1/0 CIRCUITRY
Freescale Semiconductor, Inc...
●
(a)
(~
I
I Data Direction
Register
Bit
I
T
Data Direction
Register
1
1
I
I
7
6
5
4
3
DDA7
DDA6
DDA5
DDA4
DDA3
1,1
~+~:$$;::”~+
,{y
{$:
s,i..,
>*...
DAI
O
DDAO
Port .A
Register
$0004
$0000
!
●
t
PB7
PB6
PB5
PB4
PB3
PB2
PBI
PBO
TABLE 3 – l/O PIN FUNCTIONS
T
R/~
o
I
l/O Pin Functions
DDR
0
o
1
1
0
1
1
The 1/0 pin is in input mode. Data is written
into the output data latch.
Data is written into the output data latch and
output to the 1/0 pin.
The state of the 1/0 pin is read.
The 1/0 pin is in an output mode, The output
data latch is read.
●
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FIGURE
●
13 –
PROGRAMMING
7
MODEL
0
A
Accumulator
7
0
x
Index Register
12
o
Pc
I
12
0
6
00
0
0
0
01
cc
INZC
Freescale Semiconductor, Inc...
h
stack#~;$s?],$ollowed
by PCH, etc. Pulling from the stack is in
‘The stack pointer is a 13-bit r~&~,{3~~ontaining
the -address of the next free location on~he ,fack. When accessing
memory, the seven most sig@%~$&lts
are permanently
set
to 00~001.
They are app~n~~d.~k
the six least significant
register bits to produce ~,,,a~ress
within the range of $O07F
to $0040, The stack ~fea bf&R’AM is used to store the return
address on subrou&@ealls
,,~,..)’.,,v~,
~.. and the machine state during interrupts.
Durin~%@~t&@b) or power-on
reset, and during a
“reset stack ~~t~.’
instruction,
the stack pointer is set to
its upper li,,m~~W7F).
Nested interrupts and/or subroutines
may u~~,,.ti~~ts~~
(decimal)
locations,
beyond which the
,r ,!
stack &oin@t’r’wraps
around”
and points
:{
th:@~y~w.$&sing
the
previously
stored
,:uB~@&*$fie call occupies
two
to its upper limit,
information,
A
RAM bvtes on the stack, while
carry occurs between bits 3 and 4 of the ALU duting an ADD
or ADC instruction.
The H bit is useful in binarv coded
decimal addition subroutines.
INTERRUPT
MASK BIT (1) – When the I bit is set, both
the external interrupt
and the timer interrupt
are disabled.
Clearing this bit enables the above interrupts,
If an interrupt
occurs while the I bit is set, the interrupt
is latched and will
be processed
NEGATIVE BIT (N) – When set, this bit indicates that the
result of the last arithmetic,
logical, or data manipulation
was
negative (bit 7 in the result is a logical one).
ZERO BIT (Z) – When
CARRY
CONDITION
CODE REGISTER
(CC)
These
bits can be individually
tested
BIT (H) – The H bit is set to a one when
m
that the result
or data manipulation
BIT (C) – The C bit is set when
duting
was zero,
a carry or a bor-
an arithmetic
instruction,
The C bit is also modified during bit test, shift,. rotate, and
branch types of instruction,
by a program
and specific action taken as a result of their state. Each of the
five bits is explained below,
CARRY
set, this bit indicates
logical,
row out of the ALU occurs
The condition
code register is a 5-bit register in which each
bit is used to indicate the results of the instruction
just ex-
HALF
the I bit is next cleared.
of the last arithmetic,
.,..
.;,,
ecuted.
when
MOTOROLA
a
RESETS
The MC146805E2 has two reset modes: an active low external reset pin (R ES ET) and a power-on reset function;
refer
to Figure 5,
Semiconductor Producfs Inc.
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,.-~
,,
------
.,. ,
,. ,“’.:
.,,
., -;,,,.,
,:
.,. :.:,..~.,,:,,
!,, ,,,
!...
Freescale Semiconductor, Inc.
.! !,,:,.’
,,
,.
,,
~
(piN’#l)
,,
.,,,,,~~.,,,—
.!,,
,,
.;,~-..”~.
..~..,!
..
.
.
. ,,
’.,,.:
“‘, “’:,, ,:,,, .:
,. ...,
Freescale Semiconductor, Inc...
The RESET input pin is used to re:
en orderly’ s’oftware start-up proc~
external reset mode, the RESET pin must sta~:low fc
mum of one tRL. ,Thl
trigger to improve it:
:.
then the
●
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●
FIGURE 15 – RESET AND INTERRUPT PROCESSING FLOWCHART
I
w
e
Set
I Bit
?
Freescale Semiconductor, Inc...
Clear
07F+S P
O+DDRS
CLR l~Q Logic
FF+Timer
7F;~Ts&ler
~
T
Put lFFE on
Address Bus
Load PC From:
SWI: 1FFC/1 FFD
~:
lFFA/1 FFB
TIMER: lFF8/1 FF9
rimer Wait: lFF6/l FF71
ti
w
●
MOTOROLA
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●
Freescale Semiconductor, Inc...
1
●
1
●
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
●
The multiplexed
address/data
bus goes to the data input
state (as shown in Figure 8). The high order address lines remain at the address of the next instruction,
The MPU remains in the STOP mode until an external interrupt
or reset
occurs,
During
the STOP mode,
and 7 are altered
quests
to remove
and to disable
timer control
register
any pending
any further
timer
timer
remain
(TCR) bits 6
goes to the data input state, and the DS and AS lines go to
the low state (as shown in Figure 7). The high order address
lines remain at the address of the next instruction.
The MPU
remains in this state until an external interrupt,
timer inter-
interrupt
rupt,
interrupts,
interrupts
are enabled in the condition
code
other registers and memory remain unaltered,
which is allowed to count in a normal sequence, The R/~
line goes to a high state, the multiplexed
address/data
bus
re-
External
or a reset occurs,
During the WAIT mode, the I bit in the condi~o~+,code
register is cleared to enable interrupts.
All oth~{~’rws?~rs,
register, All
All 1/O lines
memory,
unchanged.
may
mode.
FIGURE 17 – STOP FUNCTION FLOWCHART
time,
and 1/0 lines remain
be enabled
If an external
the external
rupt) is serviced
mode.
last st~~.t%~’timer
exit
~b@&IW’e WAIT
and a timer interru,pt~~-~at
interrupt
is serviced~r~t;
since the M~
,q>y:;
7
Freescale Semiconductor, Inc...
in their
a petiodic
the same
tb~n,
if the timer
interrupt
request is not cleared,::~:~t,}~~,~j~xternal
interrupt
routine, the normal timer interrupt~$oo}ltie
timer WAIT inter-
stop
Is:#o
longer
in the WAIT
,<;$MER
i
I
The M PU timer co~~*,&&
single 8-bit software programmable counter
wf~:~blt
software
selectable
prescaler.
Figure 19 sho~~,,~ b~&k diagram of the timer. The counter
may be pre~~:~~der
program
control
and decrements
I
Stop Oscillator
And All Clocks
TCR Bit 7-O
TCR Bit 6-1
Clear I Mask
towards
@i~When
the counter decrements
to zero, the
timer ~~t~u~
request bit, i.e., bit 7 of the timer control
regis@gF/~C~),
is set. Then if the timer interrupt
is not
I
I
~@ke&X~.e.,
,,~o~~,,register
#’
Nrupt.
bit 6 of the TCR and the I bit in the condition
are both cleared, the processor receives an in-
completion of the current instruction,
After
the pro-
stack, and then fetches the timer interrupt vector from locations $1 FF8 and $1 FF9 in order to begin servicing the inter-
e
rupt,
If the MPU were interrupted
the interrupt
vector
fetch would
while
in the WAIT
be from locations
mode,
$1 FF6 and
$IFF7.
The counter
continues
to count after it reaches zero,
allowing the software to determine the number of internal or
external input clocks since the timer interrupt request bit was
set. The counter may be read at any time by the processor
without
disturbing
the count. The content
of the counter
becomes stable prior to the read portion of a cycle and does
not change during the read. The timer interrupt
request bit
remains set until cleared by the software.
If a read occurs
before the timer interrupt
is serviced, the interrupt
is lost.
TCR7 may also be used as a scanned status bit in a noninterrupt
Turn on Oscillator
Wait for Time
Delay to Stabilize
%
Timer
somewhat
more power than the STOP mode; refer to Table
1. In the WAIT function,
the internal clock is disabled from
TIMER
18, Thus,
all internal
except
the timer
processing
m
1).
output which is used as the counter input. The processor
cannot write into or read from the prescaler; however,
its
contents are cleared to all “OS” by the write operation
into
TCR when bit 3 of the written data equals 1, which allows for
truncation-free
counting.
The timer input can be configured
for three different
The WAIT instruction
places the MC146805E2
in a low
power consumption
mode, but the WAIT mode consumes
circuitry
(TCR6=
operating
modes, plus a disable mode, depending
on the
value written to the TCR4, TCR5 control bits. Refer to the
WAIT
all internal
mode of operation
The prescaler is a 7-bit divider which is used to extend the
maximum
length of the timer. Bit O, bit 1, and bit 2 of the
TCR are programmed
to choose the appropriate
prescaler
Fetch External Interrupt
or Reset Vector
●
to allow
circuit;
is halted
refer to Figure
except
M070ROLA
the timer
Control
INPUT
Register
MODE
section.
1
If TCR4 and TCR5 are both programmed
put to the timer is from an internal clock
TIMER
input
Semiconductor
is disabled.
The
Products
For More Information On This Product,
19
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internal
Inc.
to a “U’, the inand the external
clock
mode
can be
Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.
●
FIGURE19 – TIMER BLOCK DIAGRAM
Selected by
TCR4, TCR5
External
Input
Selected by TCRO,
#
w
T
Freescale Semiconductor, Inc...
Internal
Clock
[ Cleared by
TCR3
;,..
:.
.$4 .~:.>$,
>
TIMER CONTROL REGISTER (TCR)
7654
TCR7 TCR6 TCR5
321
TCR4
TCR3 TCR2
1 – Set whenever the counter dqc~~~~
‘“$:,,* \
der program control.
,,/$ym,:~t:f*
O – Cleared on external rese$:lp~~er-on
struction, or progra~’’w~bl
TCRI
,$’.\JeR5
.:,.
~:,’:,.
““’ o
.’>$(
~,
..!i<\;
.,..*)
0
.~,,+?,
t:.”t:to-.\,..?:*
o
TCRO “’~;
,.*’:
1
‘
a 1
to zero, or unreset, STOP in-
TCR4
Internal clock (AS) to timer
0
1
AND of internal clock (AS) and TIMER
pin to timer
0
1
Inputs to timer disabled
TIMER pin to timer
TCR3 – Timer Prescaler Reset bit: wtiting a “l” to this bit
resets the prescaler to zero. A read of this location always
indicates a “O” (unaffected by RESET).
TCR2, TCRI, TCRO– Prescaler address bits: decoded to
select one of eight outputs of the prescaler (unaffected by
RESET).
TCR1
0
0
0
1
o
1
0
“ 1 – Select external clock source.
O – Select internal clock source (AS).
●
TCR4 – External enable bit: control bit used to enable the
external TIMER pin (unaffected by RESET).
1 – Enable external TIMER pin.
O – Disable external TIMER pin.
m
MOTOROLA
TCRO I Result
+ 1
0
TCR2
o
0
1
1
+2
+4
+8
1
0
0
-16
1
0
1
+32
1
1
0
-64
1
1
i
+128
INSTRUCTION
SET
The MPU has a set of 61 basic instructions. They can be
divided into five different types: register/memory,
readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the instructions within a given type are presented in individual
tables.
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Inc.
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5es of the processor are
sed to indicate “contents
is replace-d by, ” and a colon indi.
●
all the
,, information-necessary
to ex~the opcode. Operations
Freescale Semiconductor, Inc...
:.r6aiSteror acct)mulator,
and
no
RAM and 1/0 registers
chip ROM, Direct addressing is ef-
1)
ing mode, theeffective
addrassof
in the”two bytes following the opextended addressing modes are
urnents anywhere in memory with
ction. When using the Motorola
]ot specify whether an instruction
?d addressing,
The
assembler
nest efficient
addressing
mode,
(PC+2);PC+PC+3
1); Address Bus Low-(PC
+ 2)
;t :addressing mode, the effective
is contained in the 8-bit index
is addressing mode can access the first 256
instructions are only one byte
move a pointer through a table or
erenced RAM or 1/0 location.
)y,adding th,e contents of the byte
]t of the index register; therefore,
nywhere, within the lowest 511
mple, thi,s mode of addressing is
th element in an n element table.
vtes. The contents of the index
ntents of (PC+I) is an
le bvte “offset indexing permits
in either RAM or ROM,
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INDEXED, 16-BIT OFFSET
●
In the indexed, 16-bit offset addressing mode the effective
address is the sum of the contents of the unsiged 8-bit index
register and the two unsigned bytes following the opcode.
This addressing mode can be used in a manner similar to indexed 8-bit offset, except that this three byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM). As with direct and extended, the M6805 assembler
determines the most efficient form of indexed offset – 8 or
16 bit. The content of the index register is not changed.
EA=X+[(PC+
I):(PC+2)];
PC+PC+3
Address Bus High-( PC+ 1)+ K
Address Bus Low+K+ (PC+2)
where: K = The carry from the addition of X + (PC + 2)
Freescale Semiconductor, Inc...
RELATIVE
●
Relative addressing is used only in branch instructions. In
relative addressing the content of the 8-bit signed byte
following the opcode (the offset) is added to the PC if and
only if the branch condition is true, Otherwise, control proceeds to the next instruction. The span of relative addressing
is limited to the range of – 126 to + 129 bytes from the
branch instruction opcode location, The Motorola assembler
calculates the proper offset and checks to see if it is within
the span of the branch.
opcode. The bit set and clear instructions occupy two bytes,
one for the opcode (including the bit number) and the second to address the byte which contains the bit of interest.
EA=(PC+I);
PC~PC+2
Address Bus High YO; Address Bus Low+(PC
+ 1)
BIT TEST AND BRANCH
‘.!$>,
Bit test and branch is a combination of direct ad~$$$~g,
bit addressing, and relative addressing. The bit ,@d~% and
condition (set or clear) to be tested are part ~f,%$<~pcode.
The address of the byte to be tested is in tQ@:~~~&byte immediately following the opcode byte,<JP&$P&The signed
relative 8-bit offset is in the third byte .#~&2)~&fiNd
is added to
the PC if the specified bit is set,?@:$~~@]n the specified
memory location. This single thr#~~$@ instruction allows
the program to branch based3$~Jthe’~ondition of any bit in
. ~‘~”
the first 256 locations of m~~~~$r
541+*’(R + 1)
Address Bus Hig~:<~~q@8dress Bus Low~(PC+ 1)
EA2= PC + 3+$~~~Q);
PC~EA2 if branch taken;
,s~,oth&Wise,
PC+ PC + 3
..{.}..
,\\
\i\,,
\\*f\i...
.4.,\>~
CONFIGURATION
. f“:$~sTEM
Figu~~,*~firough
25 show in general terms how the
M C~468~52 bus structure may be utilized. Specified interEA= PC+2+ (PC+ 1); PC~EA if branch is taken;
fat~{~etails vary with the various peripheral and memory
otherwise, PC+ PC+ 2
#~&c~k emnloved.
:%~t,i~$.$able11 pro~ides a detailed description of the information
BIT SET/CLEAR
~t~~’!~$,present on the bus, read/write (R/~) pin and the load inDirect addressing and bit addressing are combined in in‘“:S struction (Ll) pin during each cycle for each instruction.
structions which set and clear individual memory and MO Y>
This information is useful in comoaring actual with expetted results during debug of both softw~re and hardware
as the control,, program is executed. The information is
categorized in groups according to addressing mode and
number of cycles per instruction.
●
MOTOROLA
Semiconductor
Products Inc,
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On This Product,
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23
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Freescale Semiconductor, Inc.
TABLE6–
●
BRANCH INSTRUCTIONS
Function
Mnemonic
Mode
Op
Code
#
Bytes
#
Cycles
3
Branch Always
BRA
20
2
Branch Never
BRN
21
2
3
Branch IFF Higher
BHI
22
2
3
Branch IFF Lower or Same
BLS
23
2
3
Branch IFF CarrV Clear
BCC
24
2
3
(BHS)
24
2
3
BCS
25
2
3
(B LO)
25
2
BNE
26
2
3
3
(Branch IFF Higher or Same)
Branch lFFCarrV Set
(Branch IFF Lower)
Branch lFF Not Equal
Branch IFF Equal
Freescale Semiconductor, Inc...
Relative Addressing
:;~:*’&”””
,g ~,, <$
. .$,
~, “ y,
BEQ
27
2
Branch lFF Half CarrV Clear
BHCC
28
Branch lFF Half CarrV Set
BHCS
29
2
“, k~%$>,
2 +$ci’y<;& ‘
Branch IFF Plus
BPL
I
Branch lFF Minus
t
BMI
“!$,?<<
skr.\:27,,
,* ‘~,;:”:
,,$’’” ~.,,,?*.,
.;3>::>
~t.,.?: ~<$.it
~i:\,,,l.,.,~,i,.,.
.,
,y..,.1. l!?
., ,.,,.
~:w~ ‘;@ 3
2A
2B
I ‘::$2:Y*I
3
I
3
3
3
3
3
6
~..{.
,,:$:
,..~k.;,
~.t.
. ‘*?t*,
~$%
Mne~’~~J$k$
Function
Branch IFF Bit nis Set
Branch IFF Bit n is Clear
Set Bit n
qR~3:&’rh
= 0.. .7)
+,,B’%$F%n[n= O...7)
Clear Bit n
“’” %@~R n (n= O...7)
,l:t~
,.,:,1 ,{,
Function
Bit Test and Branch
Op
Code
#
Bytes
#
CVcles
–
–
–
—
–
—
10+2*n
2.
5
ll+2*n
2
5
Mnemonic
Op
Code
2. n
01+2*n
—
—
Op
Code
#
Bytes
#
Bytes
#
Cvcles
3
5
3
—
5
—
—
—
#
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set CarrV Bit
SEC
99
1
2
Clear CarrV Bit
CLC
9a
1
2
Set Interrupt Mask Bit
SEI
9B
1
2
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interruot
Swl
a3
1
10
WAIT
aF
1
2
~ Wait
@
Addressing Modes
Bit Set/Clear
MOTOROLA
Semiconductor
Products Inc.
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On This Product,
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For More Information On This Product,
Go to: www.freescale.com
●
TABLE
Bit Manipulation
BTB
BSC
m
ml
DIR
W1O
ml 1
INH
4
01w
3
BRCLR05
aTB
2
0310
3
BRSET15
BTB
3
ml 1
3
BRCLR15
BTa
4
Olw
3
B R S ET25
BTB
BCLRO 5
BSC
5
BSET1
2
asc
5
BCLR1
BSC
2
5
BSET2
2
BS:
5
0101
3
BRCLR25
BTB
2
~
Freescale Semiconductor, Inc...
o
0
0
6
0110
a
:BcL~~:
BR SET45
3
BTB
BSET45
BSC
2
BRCLR45
BTB
3
B
1o11
c“
llm
o
0
1101
3
$
E
1110
g
F
1111
-
B R S ET55
BTB
BRCLR55
3
aTa
3
3
B R S ET65
BTB
3
Abbreviations
INH
A
x
IMM
DIR
EXT
NEG
NEG
1
INH
5
2
3
REL
3
2
INH
3
COMX
INH
3
LSRX
1
INH
3
3
COMA
DIR
5
LSR
DTR
INH
3
1
LSRA
1
1
REL
3
5
BNE
RORA
ROR
2
2
2
BCLR65
2
‘E~::
:
BHCC
REL
3
BHCS
REL
3
BPL
REL
3
BMI
REL
3
BMC
REL
3
BMS
REL
3
BIL
2
‘s~;
1X1
2
BCLR75
BSC
1
1
6
1
1X1
1
LSR
2
1
lx
ROR
2
DIR
1
DIR
1
DECA
INH
3
INCA
DIR
4
1
DIR
1
INH
3
INH
REL
1
6
ROL
INH
LSL
2
DECX
INH
TSTX$$:
::
<:’?.
NH
I
t:~,x&T
1
‘
k; ~%,,
‘:> , w: , ,
~’l:;.,t,
“’kc’
,:<=.“
..
...’.., ...:~{.
5
1X1
>> ‘“
SEC
$%,
1
lx
1
INH
2
CLI
,
INH
2
SEI
INH
2
5
:
cMp
IF
1111
Hi
4
EXT
4
SUB
3
3
EXT
4
3
EXT
4
3
1X2
5
2
1X2
5
2
1X2
5
2
EXT
4
3
1X2
5
2
1
1X1
I
lx
3
lx
1
ml
lx
2
0310
CMP
4
SBC
SBC
1X1
4
1
1X1
4
1
1X1
4
1
1
4
1
CPX
CPX
lx
3
BIT
BIT
LDA
lx
3
AND
AND
BIT
LDA
1X1
4
CMP
AND
BIT
3
2
CPX
AND
3
1X2
5
SBC
EXT
4
CPX
3
2
o
SUB
SUB
1X2
5
CMP
3
3
4
5
SBC
3
1
ADC
IMM
2
ORA’
2
IMM
2
ADD
IMM
2
2
2
DIR
3
3
DIR
3
DIR
3
3
DIR
2
3
DIR
5
3
BSR
INH
lx
3
LDA
LDA
2
DIR
3
‘TAT
EOR
~ ‘TA
;
EOR
3
0311
4
Olw
5
0101
1X2
1X1
2
3
EXT
4
3
EXT
3
3
EXT
3
2
1X2
2
1X2
4
2
1X2
2
ORA
ADC
1X1
1
1X1
1
1X1
3
1
1X1
1
ORA
ADO
lx
9
1021
lx
A
1010
ORA
ADO
ADD
JMP
JMP
lm
3
ADC
1X2
8
lx
4
ADC
ExT
1
::
lx
2
JMP
8
1o11
c
1102
5
JSR
EX;
3
LDX
LDX
LDX
STOP
~
5
JMP
JSR
REL
2
2
2
‘T~:
EOR
3
ADO
JMP
6
EXT
ORA
ADO
2
:
ADC
ORA
2
‘TA
EOR
4
ADC
2
2
[NH
2
1
:
2
NOP
lx
‘T{;
EOR
RSP
lx
4
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1
2
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2
2
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2
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1
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1
1
2
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1
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2
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2
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
●
●
●
For More Information On This Product,
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Freescale Semiconductor, Inc.
FIGURE 2
– CONNECTION TO M~OO PERIPHERALS
●
Address
Decode
Chip
Select
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1
1
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Non-Muxed
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●
TABLE 11 – SUMMARY
Address Mode
Instructions
OF CYCLE-BY-CYCLE
OPERATION
R/w
Pin
LI
Pin
Op Code Address
Op Code Address + 1
Op Code Address + 1
1
1
1
1
0
0
2
Op Code Address
Op Code Address + 1
1
1
1
0
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
New Op Code Address
1
2
3
4
5
6
7
8
9
Op Code Address
.@~’
Op Code Address + 1
‘:.,ft,:t,,>
!t~,tt..+
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Stack Pointer
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Stack Pointer – 1
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0
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Stack Pointer – 4
o
Vector Address 1FFC (He~’P’’’s$:yqJ
1
Vector Address 1FFD (fi[x)’k~
1
Interrupt Routine StaF~&~Mress
1
*$$x{!,<;..
Op Code Address ~ ~$:
1
Cycles
Cycle #
3.
2
3
Address Bus
Data Bus
. . .. . .
Inh-r-nt
LSR LSL
ASR NEG
CLR ROL
COM ROR
DEC INC TST
1
TAX CLC SEC
STOP CLI SEl
1
2
Freescale Semiconductor, Inc...
RSP WAIT NOP TXA
RTS
6
I
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10
10
1
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TI
1
1
“1
1
1
1 ,$<
@ Code Next Instruction
~~levant Data
#rrelevant Data
Irrelevant Data
New Op Code
Op Code
Op Code Next Instruction
Return Address (LO Byte)
Return Address (Hi Byte)
Contents of Index Register
Contents of Accumulator
Contents of CC Register
Address of Int. Routine (H1 Byte
Address of Int. Routine (LO BytE
Interrupt Routine First Opcode
Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
New Op Code
2
3
4
5
6
7
8
9
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Op Code Address
Op Code Address + 1
1
1
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand
Address of Operand
1
1
1
1
o
5
Op Code Address
Op Code Address + 1
Address of Operand
Op Code Address + 2
Op Code Address t 2
1
1
1
1
1
3
1
2
3
Op Code Address
Op Code Address + 1
Op Code Address + 1
1
1
1
6
1
2
3
4
5
6
Op Code Address
OD Code Address + 1
Op Code Address + 1
Subroutine Starting Address
Stack Pointer
Stack Pointer – 1
,!
1
~!;ys”
2
3
4
5
5
1
2
3
4
5
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,,,..
1
0
1
0
0
0
0
1
Op Code
Operand Data
Op Code
Address of Operand
Operand Data
Operand Data
Manipulated Data
0
0
Op Code
Address of Operand
Operand Data
Brench Offset
Branch Offset
1
0
0
Op Code
Branch Offset
Branch Offset
1
Op Code
Branch Offset
Branch Offset
First Subroutine Op Code
Return Address (LO Byte)
Return Address (Hl Byte)
0
0
Relative
BCC BHI BNE BEQ
BCS BPL BHCC BLS
BIL BMC BRN BHCS
BIH BMI BMS BRA
●
BSR
1
I
m
1
1
1
1
o
1010
t
0
0
0
0
I
M070ROLA
Semjconducfor
Producfs Inc.
For More Information
On This Product,
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Freescale Semiconductor, Inc.
1
Freescale Semiconductor, Inc...
●
1
:’
I
1
1
1
A~dress
‘of Operand
(HI Byte)
Address
Address
of Operand
of Operand
(LO Byte)
(LO Bvte)
0
Address of Subroutine
(H1 Byte:
Address of Subroutine
(LO Byte
1st Subroutine OD Code
0
1
1
‘o
0
! Op
11’
0
I Op Code Next Instruction
1
1’0
0
Op Code Next Instruction
Op Code Next Instruction
1
I
I
o“
0
0
I
For More Information On This Product,
Go to: www.freescale.com
Code Next
Instruction
●
Freescale Semiconductor, Inc.
TABLE
.0
Address Mode
Instructions
Indexed
8-Bit
Cycles
SUMMARY
Cvcle #
I
3
1
Op Code Address
2
Op Code Address
Op Code Address
3
EOR CPX
1
Freescale Semiconductor, Inc...
2
3
4
0
5
TST
LSL
ASR
CLR
COM
DEC
Address
Bus
OPERATION
(CONTINUED)
R/~
Pin
LI
Pin
LSR
NEG
ROL
ROR
INC
z
6
+ 1
+ 1
Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
1
Op Code Address
2
Op Code Address
3
4
5
Index
1
Op Code Address
2
Op Code Address
t 1
3
Op Code Address
+ 1
4
Index
5
Op Code Address
1
Op Code Address
Op Code Address
Op Code Address
2
3
4
5
6
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
+ 1
1
0
Op Code Address
+ 1
Op Code Address
+ 1
1
1
o
,$~,::
+ Offset
Register
Register
1
+ Offset
+ 2
+ 1
+ 1
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1
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0
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1
0
1
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6
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Operand
Data
,,;$” Op Code
Offset
Offset
Operand
Data
Op Code Next
Instruction
Op Code
Offset
Offset
Current Operand Data
Current Operand Data
New ODerand Data
Op Code
2
Indexed,
Data Bus
Offset
I
,
OF CYCLE-BY-CYCLE
I
JMP
ADC
11 –
Offset
3
4
1
1
0
5
0
Return
Address
LO Bvte
6
0
0
0
Return
Address
HI Bvte
Op Code
Offset
~i,
,!,*~
1
,s,
0
Op Code
‘.+.,O
Op Code Address
+ 1
1
Op Code Address
+ 2
1
1
0
0
0
1
0
0
Op Code Address
+ 2
1
+ Offset
1
~$$%~
1
Address
,~~,~bde
Address
b Code Address
+ 1
1
+2
1
‘bpCode
+ 2
1
Address
Op Code Address
Index
Offset
Ist Subroutine
Register
1
Op Code Address
Op Code Address
+ 1
1
1
Op Code Address
Op Code Address
+ 2
+ 2
1
1
+ 2
1
+ Offset
o
5
Op Code Address
6
Index
Register
1
Op Code Address
2
Op Code Address
+ 1
1
3
Op Code Address
+ 2
1
4
Op Code Address
+ 2
1
5
6
Index Register + Offset
Stack Pointer
Stack Pointer – 1
1
1
o
0
Offset
Offset
(H1 BVte)
(LO BVtel
Offset
(LO Byte)
Op Code
Offset
(H1 Byte)
Offset
(LO BVte)
0
Offset
(LO Byte)
0
1
0
0
0
0
0
1
0
0
0
0
0
0
Operand
Data
Op Code
Offset (H1 BVte)
Offset
Offset
(LO BVte)
(LO BVte)
Offsat (LO Byte)
Operand Data
Op Code
Offset
(H1 BVte)
Offset
(LO BVte)
Offset
(LO Bvtel
Ist
Subroutine
Return
Return
Address
Address
Op Code
(LO Byte)
(HO BVte)
●
—
I
MOTOROLA
@
Semiconductor Products Inc.
For More Information
On This Product,
33
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
O
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
Freescale Semiconductor, Inc...
NOTES:
1. DIMENSION~lS
●
DATUM.
,?:::!
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1. POSITIONAL TOLERANCE OF LEAOS (0),
SHALL BE WITHIN 0.25 mm (O.O1OI AT
MAXIMUM MATERIAL CONOITION, IN
2. OIMENSION
L TO CENTER OF LEADS
3. OIMENSION
B DOES NOT INCLUOE
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CASE 711-01
~~n
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1.02
1.52
2.54 Bsc
1.65 I 2.16
0.20 I 0.3B
2.92 I 3.43
15.24 BSC
w
150
0.51 I 1.02
i
‘i
0.040 0.060
0.100 BSC
0.065 I 0.085
0.00B I 0.015
0.115 I 0.135.
0,600 BSC
,50
00
0,0201 0.040
MILLIMETERS
OIM MIN
MAX
A 11.94 12,57
s 11.05
11.30
C
1.60
2.OB
o
0,33
0,69
F
1.07
1.47
G
1.02 BSC
H
0,S4
1.19
N
1.27
1,79
R 11.94
12.57
INCHES
MIN
MAX
0,470 0.495
0.435 0.445
0.063 O.OS2
0.013 0,027
0.042 0.05S
0,040 GSC
0.033 0.047
0.050 0.070
0.470 0.495
F
G
H
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J
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NOTES:
1. DIMENSIONS A& RARE DATUMS.
2, ~lS
GAUGE PLANE,
3, POSITIONAL TOLERANCE FOR
TERMINALS (0): 40 PLACES:
[email protected](0,010] @l T lA@l
R@
4, DIMENSIONING ANOTOLERANCING
PER ANSI Y14.5, 1973,
~~D
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CHIP CARRIER
CASE 761-01
‘m
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.@
MOTOROLA
Semiconductor
Products
For More Information
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35
www.freescale.com
Inc.
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Motorola reserves the rightto make changes.to any prod ucts,herein to improve ieliabilitv, function ordesign. Motorola does not assume anv Iiabilitvarising
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3501 ED BLUESTEINBLVD,, AUSTIN, TEXAS 78721
A SUBSIDIARY ‘OF MOTOROLA
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