MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14LC5002 MC14LC5003 MC14LC5004 72-Segment / 128-Segment LCD Drivers QFP FU SUFFIX CASE 848B TQFP FB SUFFIX CASE 873A CMOS The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Drivers. The MC14LC5002 is the same as MC14LC5003 except for 72 segments. The three devices are functionally the same except for their data input protocols. The MC14LC5002/5003 use a serial interface data input protocol. The devices may be interfaced to the MC68HCXX product families using a minimal amount of software (see example). The MC14LC5004 has a IIC interface and has essentially the same protocol, except that the device sends an acknowledge bit back to the transmitter after each eight-bit byte is received. MC14LC5004 also has a “read mode”, whereby data sent to the device may be retrieved via the IIC bus. The MC14LC5002/5003/5004 drive the liquid crystal displays in a multiplexed-by-four configuration. The devices accept data from a microprocessor or other serial data source to drive one segment per bit. The chip does not have a decoder, allowing for the flexibility of formatting the segment data externally. Devices are independently addressable via a two-wire (or three-wire) communication link which can be common with other peripheral devices. The MC14LC5003/5004 are low cost version of MC145003 and MC145004 without cascading function. • Drives 72 Segments Per MC14LC5002’s Package • • Drives 128 Segments Per MC14LC5003/5004’s Package May Be Used with the Following LCDs: Segmented Alphanumeric, Bar Graph, Dot Matrix, Custom Quiescent Supply Current: 30 µA @ 2.7 V VDD Operating Voltage Range: 2.7 to 5.5 V Operating Temperature Range: - 40 to 85°C Separate Access to LCD Drive Section’s Supply Voltage to Allow for Temperature Compensation See Application Notes AN1066 and AN442 • • • • • ORDERING INFORMATION MC14LC5002FB TQFP MC14LC5003FU QFP MC14LC5004FU QFP MCC14LC5003 MCC14LC5004 MCC14LC5003Z MCC14LC5004Z BARE DIE BARE DIE AU BUMP DIE AU BUMP DIE REV 7 02/98 MOTOROLA MC14LC5002 • MC14LC5003 • MC14LC5004 3–3 MC14LC5002 BLOCK DIAGRAM VLCD OSC1 OSC2 BP1-BP4 FP1-FP4, FP9-FP12, FP17-FP20, FP25-FP28 & FP31-FP32 OSCILLATOR DRIVERS FRAME SYNC GENERATOR A2 ENB DATA AND ADDRESS A0/A1 CONTROL AND TIMING POR DCLK Din LCD VOLTAGE WAVEFORM AND TIMING GENERATOR DRIVERS 128 - 32 MULTIPLEX 128-BIT LATCH 128-BIT SHIFT REGISTER 32 31 30 29 28 27 26 25 OSC2 VDD BP1 BP2 BP3 BP4 A0/A1 A2 MC14LC5002 PIN ASSIGNMENT 1 2 3 4 5 6 7 8 MC14LC5002 24 23 22 21 20 19 18 17 ENB Din DCLK FP1 FP2 FP3 FP4 FP9 MC14LC5002 • MC14LC5003 • MC14LC5004 3–4 V SS FP12 FP11 FP10 FP19 FP18 FP17 VLCD 9 10 11 12 13 14 15 16 OSC1 FP32 FP31 FP28 FP27 FP26 FP25 FP20 MOTOROLA MC14LC5003/MC14LC5004 BLOCK DIAGRAM VLCD OSC1 OSC2 BP1-BP4 FP1-FP32 OSCILLATOR DRIVERS A0 A1 A2 ENB POR CONTROL AND TIMING DCLK Din DATA AND ADDRESS FRAME SYNC GENERATOR DRIVERS LCD VOLTAGE WAVEFORM AND TIMING GENERATOR 128 - 32 MULTIPLEX 128-BIT LATCH 128-BIT SHIFT REGISTER 52 51 50 49 48 47 46 45 44 43 42 41 40 NC OSC1 OSC2 VDD BP1 BP2 BP3 BP4 A0 A1 A2 ENB NC MC14LC5003/MC14LC5004 PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 MC14LC5003 OR MC14LC5004 Din DCLK NC FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 NC FP19 FP18 FP17 FP16 FP15 V LCD VSS FP14 FP13 FP12 FP11 NC 14 15 16 17 18 19 20 21 22 23 24 25 26 FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 NC=NO CONNECTION MOTOROLA MC14LC5002 • MC14LC5003 • MC14LC5004 3–5 ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Symbol Value Unit VDD DC Supply Voltage - 0.5 to + 6.5 V Vin Input Voltage, Din, and Data Clock - 0.5 to + 15 V - 0.5 to VDD + 0.5 V ± 10 mA Vin osc Input Voltage, OSCin of Master Iin DC Input Current, per Pin TA Operating Temperature Range - 40 to + 85 °C Storage Temperature Range - 65 to + 150 °C Tstg This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA= 25°C) Symbol VDD V VLCD V Min Typical Max VO = 0.15 V IFH IFL 5 5 2.7 2.7 260 260 — — — — VO = 2.65 V IFH IFL 5 5 2.7 2.7 -240 -240 — — — — VO = 1.72 V IFH IFL 5 5 2.7 2.7 -40 — — — — -1.5 VO = 1.08 V IFH IFL 5 5 2.7 2.7 40 — — — — 2 VO = 0.15 V IFH IFL 5 5 5.5 5.5 600 600 — — — — VO = 5.35 V IFH IFL 5 5 5.5 5.5 -520 -520 — — — — VO = 3.52 V IFH IFL 5 5 5.5 5.5 -35 — — — — -1.5 VO = 1.98 V IFH IFL 5 5 5.5 5.5 55 — — — — 1 Supply Standby Currents (No Clock) IDD = Standby @ Iout = 0 µA ILCD = Standby @ Iout = 0 µA IDD = Standby @ Iout = 0 µA ILCD = Standby @ Iout = 0 µA IDDS ILCDS IDDS ILCDS 2.7 — 5.5 — — 2.7 — 5.5 — — — — — — — — 30 800 50 1500 Supply Currents (fOSC) = 110 kHz IDD = Quiescent @ Iout = 0 µA, no loading IDD = Quiescent @ loading = 270pF IDD = Quiescent @ Iout = 0 µA, no loading IDD = Quiescent @ loading = 270pF ILCD = Quiescent @ Iout = 0 µA, no loading ILCD = Quiescent @ Iout = 0 µA, no loading IDDQ IDDQ IDDQ IDDQ ILCDQ ILCDQ 2.7 2.7 5.5 5.5 — — — — — — 2.7 5.5 — — — — — — 30 — 170 — — — — 70 — 400 40 70 Input Current Iin — — -0.1 — 0.1 µA Input Capacitance Cin — — — — 7.5 pF Characteristic Unit µA Output Drive Current — Frontplanes µA µA (continued) MC14LC5002 • MC14LC5003 • MC14LC5004 3–6 MOTOROLA ELECTRICAL CHARACTERISTICS (Continued) Symbol VDD V VLCD V Min Typical Max Unit fOSC2 fBP fOSC2 5 5 5 5 5 5 100 100 23 — — — 150 150 33 kHz Hz kHz Average DC Offset Voltage (BP Relative to FP) VOO 5 2.8 -50 — +50 mV Input Voltage “0” Level VIL VIL 2.8 5.5 5 5 — — — — 0.85 1.65 V “1” Level VIH VIH 2.8 5.5 5 5 2 3.85 — — — — Output Drive Current — Backplanes VO = 2.65 V IBH * IBL 5 5 2.8 2.8 -240 -240 — — — — VO = 0.15 V IBH IBL 5 5 2.8 2.8 260 260 — — — — VO = 1.08V IBH IBL 5 5 2.8 2.8 40 — — — — 2 VO = 1.72 V IBH IBL 5 5 2.8 2.8 -40 — — — — -1 VO = 5.35 V IBH IBL 5 5 5.5 5.5 -520 -520 — — — — VO = 0.15 V IBH IBL 5 5 5.5 5.5 600 600 — — — — VO = 1.98 V IBH IBL 5 5 5.5 5.5 55 — — — — 1 VO = 3.52 V IBH IBL 5 5 5.5 5.5 -35 — — — — -1 Pulse Width, Data Clock (Figure 1) tw 5 3 100 100 — — — — ns DCLK Rise/Fall Time (Figure 1) tr, tf 5 3 — — — — 120 120 µs Setup Time, Din to DCLK (Figure 2) tsu 5 3 20 20 — — — — ns Hold Time, Din to DCLK (Figure 2) th 5 3 40 60 — — — — ns Hold Time for START condition (Figure 2) tstart 5 3 100 100 — — — — ns Hold Time for STOP condition (Figure 2) tstop 5 3 100 100 — — — — ns DCLK Low to ENB High (Figure 3) th 5 3 20 20 — — — — ns ENB High to DCLK High (Figure 3) trec 5 3 20 20 — — — — ns ENB High Pulse Width (Figure 3) tw 5 3 100 100 — — — — ns ENB Low to DCLK High (Figure 3) tsu 5 3 20 20 — — — — ns Characteristic Frequencies OSC2 Frequency @ R1; R1 = 200 kΩ BP Frequency @ R1 OSC2 Frequency @ R2; R2 = 996 kΩ µA NOTE: Timing for Figures 1, 2, and 3 are design estimates only. * For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to allow the load capacitances to charge quickly. The circuit is then returned to the low-current state until the next voltage change. MOTOROLA MC14LC5002 • MC14LC5003 • MC14LC5004 3–7 SWITCHING WAVEFORMS tf tr VDD 90% CLK 50% 10% GND tw tw Figure 1. VALID VDD 50% Din GND tsu tstart tstop th CLK VDD GND Figure 2. tw ENB tw VDD 50% tsu GND th trec CLK 50% FIRST CLK LAST CLK VDD GND Figure 3. MC14LC5002 • MC14LC5003 • MC14LC5004 3–8 MOTOROLA FUNCTIONAL DESCRIPTION The MC14LC5002/5003/5004 have essentially two sections which operate asynchronously from each other; the data input and storage section and the LCD drive section. The LCD drive and timing is derived from the oscillator, while the data input and storage is controlled by the Data In (Din), Data Clock (DCLK), Address (A0, A1, A2), and Enable (ENB) pins. Data is shifted serially into the 128-bit shift register and arranged into four consecutive blocks of 32 parallel data bits. A time-multiplex of the four backplane drivers is made (each backplane driver becoming active then inactive one after another) and, at the start of each backplane active period, the corresponding block of 32 bits is made available at the frontplane drivers. A high input to a plane driver turns the driver on, and a low input turns the driver off. Figure 4 shows the sequence of backplanes. Figure 5 shows the possible configurations of the frontplanes relative to the backplanes. When a backplane driver is on, its output switches from VLCD to 0 V, and when it is off, it switches from 1/3 VLCD to 2/3 VLCD. When a frontplane driver is on, its output switches from 0 V to VLCD, and when it is off, it switches from 2/3 VLCD to 1/3 VLCD. The LCD drive and timing section provides the multiplex signals and backplane driver input signals and formats the frontplane and backplane waveforms. The address pins are used to uniquely distinguish LCD driver from any other chips on the same bus and to define LCD driver as the “master” in the system. There must be one master in any system. The enable pin may be used as a third control line in the communication bus. It may be used to define the moment when the data is latched. If not used, then the data is latched after 128 bits of data have been received. TIME FRAME VLCD 2/3 (VLCD) 1/3 (VLCD) BP1 0V VLCD 2/3 (VLCD) 1/3 (VLCD) BP2 0V VLCD 2/3 (VLCD) 1/3 (VLCD) BP3 0V VLCD 2/3 (VLCD) 1/3 (VLCD) BP4 0V Figure 4. Backplane Sequence MOTOROLA MC14LC5002 • MC14LC5003 • MC14LC5004 3–9 TIME FRAME TIME FRAME VLCD VLCD BP1 BP1 0V FP DATA BITS 4321 0000 VLCD 2/3 (VLCD) 1/3 (VLCD) 0V 0V FP DATA BITS 4321 0001 VLCD 1000 0100 1100 0010 1010 0110 1110 2/3 (VLCD) 1/3 (VLCD) VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 1001 2/3 (VLCD) 1/3 (VLCD) 0V 0V VLCD VLCD 2/3 (VLCD) 1/3 (VLCD) 0101 2/3 (VLCD) 1/3 (VLCD) 0V 0V VLCD VLCD 2/3 (VLCD) 1/3 (VLCD) 1101 2/3 (VLCD) 1/3 (VLCD) 0V 0V VLCD VLCD 2/3 (VLCD) 1/3 (VLCD) 0011 2/3 (VLCD) 1/3 (VLCD) 0V 0V VLCD VLCD 2/3 (VLCD) 1/3 (VLCD) 1011 2/3 (VLCD) 1/3 (VLCD) 0V 0V VLCD VLCD 2/3 (VLCD) 1/3 (VLCD) 0111 2/3 (VLCD) 1/3 (VLCD) 0V 0V VLCD VLCD 2/3 (VLCD) 1/3 (VLCD) 1111 0V 2/3 (VLCD) 1/3 (VLCD) 0V Figure 5. Frontplane Combinations MC14LC5002 • MC14LC5003 • MC14LC5004 3–10 MOTOROLA PIN DESCRIPTIONS A0/A1,A2 for MC14LC5002 Address Inputs The address pins must be tied to VDD. This defines the normal operation mode. CAUTION The configuration A0, A1, A2 = 111 must be used. The configuration A0, A1, A2 = 000 is reserved for Motorola’s use only. All three address pins should never be tied to 0 V simultaneously. ENB Enable Input If the ENB pin is tied to VDD, the MC14LC5002/5003/5004 will always latch the data after 128 bits have been received. The latched data is multiplexed and fed to the frontplane drivers for display. If external control of this latching function is required, then the ENB pin should be held low, followed by one high pulse on ENB when data display is required. (This may be useful in a system where MC14LC5002/5003/5004 is permanently addressed and only the last 128 bits of data sent are required to be latched for display). The pulse on the ENB pin must occur while DCLK is high. DCLK, Din Data Clock and Data Input Address input and data input controls. See Data Input Protocol sections for relevant option. OSC1, OSC2 Oscillator Pins To use the on-board oscillator, an external resistor should be connected between OSC1 and OSC2. Optionally, the OSC1 pin may be driven by an externally generated clock signal. A resistor of 680 kΩ connected between OSC1 and OSC2 pins gives an oscillator frequency of about 30 kHz, giving approximately 30 Hz as seen at the LCD driver outputs. A resistor of 200 kΩ gives about 100 kHz, which results in 100Hz at the driver outputs. LCD manufacturers recommend an LCD drive frequency of between 30 Hz and 100 Hz. See Figure 6. MOTOROLA EXTERNAL RESISTOR VALUE A0, A1,A2 for MC14LC5003/5004 10 M 1M 100 k 10 k 1k 10 k 100 k 1M 10 M OSCILLATOR FREQUENCY Figure 6. Oscillator Frequency vs. Load Resistance (Approximate) FP1-FP32 Frontplane Drivers Frontplane driver outputs. BP1-BP4 Backplane Drivers Backplane driver outputs. VLCD LCD Driver Supply Power supply input for LCD drive outputs. May be used to supply a temperature-compensated voltage to the LCD drive section, which can be separate from the logic voltage supply, VDD. VDD Positive Power Supply This pin supplies power to the main processor interface and logic portions of the device. The voltage range is 2.7 to 5.5 V with respect to the VSS pin. For optimum performance, VDD should be bypassed to VSS using a low inductance capacitor mounted very closely to these pins. Lead length on this capacitor should be minimized. VSS Ground Common ground. MC14LC5002 • MC14LC5003 • MC14LC5004 3–11 DATA INPUT PROTOCOL Two-wire communication bus DCLK, Din; three-wire communication bus DCLK, Din, ENB. MC14LC5002/5003 — SERIAL INTERFACE DEVICE (FIGURE 7) Before communication with an MC14LC5002/5003 can begin, a start condition must be set up on the bus by the transmitter. To establish a start condition, the transmitter must pull the data line low for at least one clock-pulse time while the clock line is high. The “idle” state for the clock line and data line is the high state. After the start condition has been established, an eight-bit address (01111110) should be sent by the transmitter. If the a d d re s s s e n t c o rre s p onds to the address of the MC14LC5002/5003 then on each successive clock pulse, the addressed device will accept a data bit. If the ENB pin is permanently high, then the addressed MC14LC5002/5003’s internal counter latches the data to be displayed after 128 data bits have been received. Otherwise, the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC14LC5002/5003, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). To establish a stop condition, the transmitter must pull the data line high for at least one clock-pulse time while the clock line is high. Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case, the 129th rising DCLK edge, which normally would be used to set up the stop or start condition, is ignored by the MC14LC5002/5003 and data continues to be received on the 130th rising DCLK. The latch function continues to work as normal (i.e., data is be latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. MC14LC5004 — IIC DEVICE (FIGURE 8) Before communication with an MC14LC5004 can begin, a start condition must be set up on the bus by the controller. To establish a start condition, the controller must pull the data MC14LC5002 • MC14LC5003 • MC14LC5004 3–12 line low for at least one clock-pulse time while the clock line is high. After the start condition has been established, an eight-bit address (0111111X0) should be sent by the controller followed by an extra clock pulse while the data line is left high. In this option, only the seven most significant bits of the address are used to uniquely define devices on the bus, the least significant bit X0 is used as a read/write control: if the least significant bit is 0, then the controller writes to the LCD driver; if it is 1, then the controller reads from the LCD driver’s 128-bit shift register on a first-in first-out basis. If the seven most significant address bits sent correspond to the address of the LCD driver then the addressed LCD driver responds by sending an “acknowledge” bit back to the controller (i.e., the LCD driver pulls the data line low during the extra clock pulse supplied by the controller). If the least significant address bit was 0, then the controller should continue to send data to the LCD driver in blocks of eight bits followed by an extra ninth clock pulse to allow the LCD driver to pull the data line Din low as an acknowledgment. If the least significant address bit was 1, then the LCD driver sends data back to the controller (the clock is supplied by the controller). After each successive group of eight bits sent, the LCD driver leaves the data line high for one pulse. If the ENB pin is permanently high, then the addressed MC14LC5004’s internal counter latches the data to be displayed after 128 data bits have been received. Otherwise the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC14LC5004, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). To establish a stop condition, the transmitter must pull the data line high for at least one clock-pulse time while the clock line is high. Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case the rising DCLK edge which comes after all 128 data bits have been sent and after the last acknowledge-related clock pulse has been made is ignored; data continues to be received on the following DCLK high. The latch function continues to work as normal (i.e., data is latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. MOTOROLA MOTOROLA FP1 DIN FP32 FP2 BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 MC14LC5002 • MC14LC5003 • MC14LC5004 3–13 Figure 7. MC14LC5002/5003(SERIAL INTERFACE DEVICE) DCLK START 8-BITS ADDRESS 128-BITS DATA STOP ENABLE PULSE MAY OCCUR AS REQUIRED BUT MUST BE DURING DCLK HIGH. ENB (IF USED) Figure 7a. Data Input—MC14LC5002/5003 Figure 8 . Data Input MC14LC5004 (IIC Device) MC14LC5002 • MC14LC5003 • MC14LC5004 3–14 MOTOROLA START (FROM LCD DRIVER) D in START DCLK D in (FROM CONTROLLER) READ FROM LCD DRIVER ENB (IF USED) D in (FROM LCD DRIVER) DCLK (FROM CONTROLLER) DIN WRITE TO LCD DRIVER 8-BITS ADDRESS FP1 FP2 LEFT HIGH BY CONTROLLER PULLED LOW BY DRIVER ENTIRE CLK FOR ACKNOWLEDGE 8-BITS DATA LAST DCLK PULSE (DOES NOT SHIFT DATA) BP4 BP3 BP2 BP1 LEFT HIGH BY DRIVER BP4 BP3 BP2 BP1 LEFT HIGH BY DRIVER STOP LAST DCLK PULSE (DOES NOT SHIFT DATA) CONTINUES TO CLOCK DATA AND ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE ENABLE PULSE MAY OCCUR AS REQUIRED; BUT MUST BE DURING DCLK HIGH. STOP CONTINUES TO CLOCK DATA AND ACKNOWLEDGE PULLED LOW BY DRIVER BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 ADDRESS ACKNOWLEDGED BY DRIVER ENTIRE CLK FOR ACKNOWLEDGE 8-BITS DATA ENTIRE CLK FOR ACKNOWLEDGE BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 LEFT HIGH BY CONTROLLER (LOW-ORDER BIT=1) 8-BITS ADDRESS (LOW-ORDER BIT =0) APPLICATION INFORMATION Figure 9 shows an interface example for serial data interface. Example 1 contains the software to use HC05 with MC14LC5003 in serial data interface. VDD A0 A2 OSC1 DOUT MC68HC05 A1 Din SCK R = 470 kΩ MC14LC5003 DCLK OSC2 ENB STROBE BP1-BP4 FP1-FP32 1/4 MUX DISPLAY Figure 9. Serial Interface Example Between MC68HC05 and MC14LC5003 PORTC DDRC SEN SCL SDA DOUT W1 COUNT EQU EQU EQU EQU EQU EQU $02 $06 $07 $06 $05 $FF ORG $0050 RMB RMB 1 1 ORG FCB FCB $1FFE #$01 #$00 PORTC PORTDC ENABLE PIN, PC7 CLOCK PIN, PC6 DATA PIN, PC5 OUTPUT DATA ADDRESS OF RESET VECTOR OF MC68HC805C4 RESET VECTOR *** Main Program start at 0100 *** START ORG LDA STA $0100 #DOUT DDRC LDX BSET BSET #$00 SDA,PORTC SCL,PORTC BSET LDA STA BCLR SEN,PORTC #$11 W1 SDA,PORTC CLC LDA STA LDA INCX #$08 COUNT SEND,X SET DATA LINE OUTPUT AGAIN READY LBYTE MOTOROLA IDLE STATE CLOCK AND DATA ARE HIGH EN=1 SET ADDRESS AND 8 CHARACTERS START CONDITION, DATA LOW WHILE CLOCK HIGH 8 BITS TO SHIFT GET A BYTE MC14LC5002 • MC14LC5003 • MC14LC5004 3–15 LBIT DZERO CLKHI STOP BCLR ROLA BCC BSET JMP BCLR BSET DEC BNE DEC BNE BCLR BCLR BSET BSET BCLR RTS SCL,PORTC CLOCK LOW DZERO SDA,PORTC CLKHI SDA,PORTC SCL,PORTC COUNT LBIT W1 LBYTE DATA BIT=0 ? NO, BIT=1 AND DATA HIGH SCL,PORTC SDA,PORTC SCL,PORTC SDA,PORTC SEN,PORTC DATA LOW CLOCK HIGH LAST BYTE ? STOP CONDITION DATA GOES HIGH WHILE CLOCK HIGH EN=0 *** End of Program *** *** LCD Address and Data *** SEND FCB FCB FCB RTS $7E $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF LCD DRIVER ADDRESS DATA TO SENT Example 1. Serial Data Interface Method Figure 10 shows an interface example for IIC interface. VDD VDD 1kΩ A0 A2 OSC1 DOUT MC68HC05 A1 Din SCK R = 470 kΩ MC14LC5004 DCLK OSC2 ENB STROBE BP1-BP4 FP1-FP32 1/4 MUX DISPLAY Figure 10. IIC Interface Example Between MC68HC05 and MC14LC5004 MC14LC5002 • MC14LC5003 • MC14LC5004 3–16 MOTOROLA PACKAGE DIMENSIONS QFP FU SUFFIX CASE 848B-02 L B DETAIL A 52 V 0.20 (0.008) M C A-B S L 0.20 (0.008) M H A-B S -D- -A- 0.05 (0.002) A-B D S 26 40 D S 27 39 14 B 13 1 B -DB 0.20 (0.008) M H A-B S 0.05 (0.002) A-B D S -A,B,DDETAIL A V 0.20 (0.008) M C A-B S D S F DETAIL C M C E J -H- -CH SEATING N DATUM BASE METAL 0.10 (0.004) G D M D S 0.02 (0.008) M C A-B S SECTION B-B MILLIMETERS U T DATUM -H- R K W X DETAIL C Q NOTES: 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 3.DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4.DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE DIM A MAX 10.10 MIN MX 0.390 0.398 B 9.90 10.10 0.390 0.398 C 2.10 2.45 0.083 0.096 D 0.22 0.38 0.009 0.015 E 2.00 2.10 0.079 0.083 F 0.22 0.33 0.009 0.013 G 0.65 BSC H -- 0.25 J 0.13 0.23 0.005 0.009 K 0.65 0.95 0.026 0.037 L 7.80 REF M 5˚ 10˚ N 0.13 0.17 0.026 BSC -- 0.010 0.307 REF 5˚ 10˚ 0.005 0.007 Q 0˚ 7˚ R 0.13 0.30 S 12.95 13.45 T 0.13 -- 0.005 -- U 0˚ -- 0˚ -- V 12.95 13.45 0.510 0.530 W 0.35 0.45 0.014 0.018 X MOTOROLA INCHES MIN 9.90 1.6 REF 0˚ 7˚ 0.005 0.012 0.510 0.530 0.063 REF MC14LC5002 • MC14LC5003 • MC14LC5004 3–17 PACKAGE DIMENSIONS TQFP FB SUFFIX CASE 873A-02 NOTES: 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 3.DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4.DATUMS -T-, -U- AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8.MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9.EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MC14LC5002 • MC14LC5003 • MC14LC5004 3–18 MILLIMETERS INCHES DIM A MIN MAX 7.000 BSC MIN MAX 0.276 BSC AI 3.500 BSC 0.138 BSC B 7.000 BSC 0.276 BSC BI 3.500 BSC 0.138 BSC C 1.400 1.600 0.055 0.063 D 0.300 0.450 0.012 0.018 E 1.350 1.450 0.053 0.057 F 0.300 0.400 0.012 0.016 G 0.800 BASIC 0.031 BASIC H 0.050 0.150 0.002 0.006 J 0.090 0.200 0.004 0.008 K 0.500 0.700 0.020 0.028 M 12˚ REF 12˚ REF N 0.090 0.160 0.004 0.006 P 0.400 BASIC 0.016 BASIC Q 1˚ 5˚ 1˚ 5˚ R 0.150 0.250 0.006 0.010 S 9.000 BSC 0.354 BSC SI 4.500 BSC 0.014 BSC V 9.000 BSC 0.354 BSC VI 4.500 BSC 0.014 BSC W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF MOTOROLA BOND PAD LAYOUT -X +X For MCC14LC5003 / MCC14LC5004 BARE DIE & MCC14LC5003Z / MCC14LC5004Z AU BUMP DIE : DIE SIZE : 1981.2 x 3022.6 µm2 (78 x 119 mil2, 1 mil ~ 25.4µm) AU BUMP SIZE : 70 x 70 µm2 RESERVED AREA : PIN 1 +Y AREA A COORDINATES AREA X A 193 -445 45 -300 45 -300 193 B -Y AREA B © Y -445 HONG KONG I.C. DESIGN CENTER -74 -910 -74 -1100 368 -1100 368 -910 Dimensions in µm Note : 1. Reserved area contains dummy bumps for IC bumping process alignment and IC identifications. 2. No conductive tracks should be laid underneath reserved area to avoid short circuit. 3. Reserved area applies to Au bump die only. It does not apply to bare die. Die Pad Coordinates Die Pad No. Coordinates Die Pad No. Pin Name X Y Coordinates Pin Name X Y 1 FP32 -736.002 929.199 25 FP10 735.998 -837.201 2 FP31 -736.002 781.999 26 FP9 735.998 -690.001 3 FP30 -736.002 634.799 27 FP8 735.998 -542.801 4 FP29 -736.002 487.599 28 FP7 735.998 -395.601 5 FP28 -736.002 340.399 29 FP6 735.998 -248.401 6 FP27 -736.002 193.199 30 FP5 735.998 -101.201 7 FP26 -736.002 45.999 31 FP4 735.998 45.999 8 FP25 -736.002 -101.201 32 FP3 735.998 193.199 9 FP24 -736.002 -248.401 33 FP2 735.998 340.399 10 FP23 -736.002 -395.601 34 FP1 735.998 487.599 11 FP22 -736.002 -542.801 35 NC 736.000 634.800 12 FP21 -736.002 -690.001 36 DCLK 736.000 782.000 13 FP20 -736.002 -837.201 37 DIN 736.000 929.200 14 FP19 -736.002 -1205.601 38 ENB 736.000 1205.600 15 FP18 -588.802 -1205.601 39 A2 588.800 1205.600 16 FP17 -441.602 -1205.601 40 A1 441.600 1205.600 17 FP16 -294.402 -1205.601 41 A0 294.400 1205.600 18 FP15 -147.202 -1205.601 42 BP4 147.198 1205.599 19 VLCD 0.000 -1205.600 43 BP3 -0.002 1205.599 20 VSS 147.200 -1205.600 44 BP2 -147.202 1205.599 21 FP14 294.398 -1205.601 45 BP1 -294.402 1205.599 22 FP13 441.598 -1205.601 46 VDD -441.600 1205.600 23 FP12 588.798 -1205.601 47 OSC2 -588.800 1205.600 24 FP11 735.998 -1205.601 48 OSC1 -736.000 1205.600 Dimensions in µm MOTOROLA MC14LC5002 • MC14LC5003 • MC14LC5004 3–19