FREESCALE MC33486ADHR2

Freescale Semiconductor
Technical Data
MC33486A
Rev 2.0, 12/2005
Document order number:
Dual High-Side Switch for
H-Bridge Applications
33486A
This 33486A is a self-protected dual 15 mΩ high-side switch that
incorporates a dual low-side switch control and protection features.
This device is used to replace electromechanical relays and discrete
devices in power management applications. It is designed for typical
DC-motor control in an H-Bridge configuration.
The 33486A can directly interface with a microcontroller for control
and diagnostic functions. It is PWM-capable and has a self-adjusting
switching speed for minimizing electromagnetic emission.
DUAL HIGH-SIDE SWITCH
Features
•
•
•
•
•
•
•
•
•
•
Dual 15 mΩ High-Side Switch with Dual Low-Side Control
10 A Nominal DC Current
8.0 V to 28 V Operating Voltage with Standby Current < 10 µA
High-Side Overtemperature Protection
High-Side and Low-Side Overcurrent Protection
Current Recopy to Monitor High-Side Current
PWM Capability up to 30 kHz
Common Diagnostic Output
Overvoltage and Undervoltage Detection
Cross-Conduction Management
5.0 V
DH SUFFIX
98ASH70702A
20-TERMINAL HSOP
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33486ADH/R2
-40°C to 125°C
20 HSOP
VBAT
5.0 V
33486A
VBAT
MCU
ST
IN1
IN2
WAKE
Cur R
GND
OUT2
GLS2
OUT1
GLS1
GND
Figure 1. 33486A Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VBAT
OUT2
CHANNEL 1
GLS2
CHANNEL 2
Thermal
Sensor
Over
temperature
Switching
Speed
Adjust
Charge
Pump
IN2
OUT1
2
Input
Trigger
IN1
Cur R
Undervoltage/
Overvoltage
Lockout
Current
Recopy
Over
current
ST
IN2
WAKE
Sleep
Mode
Driver
Overload and
Cross-Conduction
Management
GLS1
GND
Figure 2. 33486A Simplified Internal Block Diagram
33486A
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
VBAT
GND
1
20
WAKE
Cur R
2
19
ST
IN1
3
18
IN2
GLS1
4
17
GLS2
OUT1
5
16
OUT2
OUT1
6
15
OUT2
OUT1
7
14
OUT2
OUT1
8
13
OUT2
NC
9
12
NC
NC
10
11
NC
VBAT
Figure 3. 33486A Terminal Locations
Table 1. TERMINAL DEFINITIONS
Terminal
Terminal Name
Formal Name
Definition
1
GND
Ground
2
Cur R
Load Current Sense
3
18
IN1
IN2
Input Channel 1
Input Channel 2
These are the device input terminals that directly control their associated
outputs. Each input terminal has an internal active pull-down so that the
input terminal will not float if disconnected.
4
17
GLS1
GLS2
Gate Low-Side 1
Gate Low-Side 2
Each terminal must be connected to one gate of an external low-side
MOSFET.
5–8
OUT1
Output Channel 1
Terminals 5, 6, 7, and 8 are the source of the Output Channel 1 15 mΩ
high-side MOSFET1.
9 – 12
NC
No Connect
13 – 16
OUT2
Output Channel 2
19
ST
Status for Both Channels
The status output goes low when a fault mode is detected. It is an open
drain with an internal clamp at 6.0 V. An external pull-up resistor
connected to VDD (5.0 V) is needed.
20
WAKE
Wake
This logic input enables control of the device. (Wake logic LOW = Sleep
Mode, Wake logic HIGH = full operation.) The WAKE terminal has a pulldown resistor.
TAB
VBAT
Supply Voltage
This is the ground terminal of the device.
The Current Sense terminal delivers a ratio amount of the sum of the
high-side currents.
These terminals are not used.
Terminals 13, 14, 15, and 16 are the source of the Output Channel 2
15 mΩ high-side MOSFET2.
The backside TAB is connected to the power supply of the 33486A.
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Power Supply Voltage: Continuous / Pulse
VBAT
- 0.3 to 40
V
OUT1, OUT2 to VBAT Voltage: Continuous / Pulse
VOUT
- 0.3 to 40
V
IN1, IN2, WAKE, ST Input DC Voltage: Continuous / Pulse
VIN
- 0.3 to 7.0
V
IN1, IN2, WAKE Input Current
IIN
± 5.0
mA
IOUTDC
10
A
IOUTP
Self-Limited
A
Operating Junction Temperature
TJ
- 40 to 150
°C
Operating Ambient Temperature
TA
- 40 to 125
°C
TSTG
- 65 to 150
°C
Junction to Case
RθJC
2.0
Junction to Ambient (1)
RθJA
25
PD
5.0
Human Body Model (4)
VESD1
±2000
Machine Mode (5)
VESD2
±200
TSOLDER
240
Output DC Output Current, 1 Channel ON, TA = 85°C
Output Current: Pulse (2)
Storage Temperature
(1)
Thermal Resistance
°C/W
Power Dissipation at TCASE 140°C (3)
ESD All Terminals
Terminal Soldering Temperature
W
V
(6)
°C
Notes
1.
Device mounted on dual-side printed circuit board with 70 µm copper thickness and 10 cm2 copper heatsink (2.5 cm2 on top side and
2.
7.5 cm2 on down side).
See high-side output current shutdown, ILIM.
3.
4.
Assuming a 150°C maximum junction temperature.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
5.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
6.
The maximum peak temperature during the soldering process should not exceed 235°C (+5.0°C / -0°C). The time within 5.0°C of actual
peak temperature should range from 10 s to 30 s max.
33486A
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Analog Integrated Circuit Device Data
Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 9.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TJ = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VBAT
VUV
–
VOV
V
SUPPLY
Nominal Operating Voltage
Standby Current
µA
ISTDBY
–
–
10
–
9.0
15
–
15
–
IOUT = 5.0 A, VBAT > 10 V, TJ = 25°C
–
12
15
IOUT = 5.0 A, VBAT > 10 V, TJ = 150°C
–
21
30
–
–
0.7
–
–
14
VBAT < 13.5 V, WAKE = 0 V, IN1 = IN2 = 0 V
Supply Current in Operation Mode
ION
No PWM, IN1 or IN2 = 5.0 V, WAKE = 5.0 V
Supply Current in Operation Mode
mA
IONPWM
PWM = 20 kHz, d = 50% Without Load
mA
OUTPUTS
High-Side Drain to Source On Resistance
High-Side Body Diode Voltage (OUTn to VBAT)
RDS(ON)
VBD
IOUT = -5.0 A, TJ = 150°C
Low-Side Gate Output Voltage
mΩ
V
VGS
Internally Clamped
V
IN1, IN2, WAKE
Input Low Levels
VIL
–
–
1.5
V
Input High Levels
VIH
3.5
–
–
V
Input Hysteresis
VHYST
0.2
0.6
1.0
VIN = 1.5 V
1.0
–
–
VIN = 3.5 V
–
–
50
–
–
0.5
IN1 and IN2 Terminals Only
Logic Input Current
V
µA
IIN
STATUS
Status Voltage
VST
IST = 1.0 mA, Output in Fault
Status Leakage
VST = 5.0 V
V
µA
ISTLK
–
–
10
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 9.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TJ = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
ILIM
20
35
50
A
OVERLOAD PROTECTION
High-Side Output Current Shutdown
Low-Side Over Load Detection (VOUT - GND)
VOUT - FAULT
1.0
–
1.6
V
Thermal Shutdown
TSHUT
150
175
190
°C
Thermal Shutdown Hysteresis
THYST
–
10
–
°C
Undervoltage Shutdown Threshold
VUV
6.0
7.0
8.0
V
Undervoltage Shutdown Hysteresis
VUYST
–
0.15
–
V
Overvoltage Shutdown Threshold
VOV
27
29
31
V
Overvoltage Shutdown Hysteresis
VOV - HYST
–
0.15
–
V
IOUT from 4.0 A to 8.0 A, TJ = -40°C to 105°C
3145
3700
4255
IOUT from 2.0 A to 4.0 A, TJ = -40°C to 105°C
2960
3700
4440
CURRENT RECOPY
Current Recopy Ratio
CR
–
33486A
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Analog Integrated Circuit Device Data
Freescale Semiconductor
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 9.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TJ ≤ 150°C, unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TJ = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
t ILIM
–
3.0
20
µs
t OUT-FAULT
–
3.0
10
µs
High-/ Low-Speed Mode to Low-/ High-Speed Mode Transition Pulse Width
t SMOD
150
250
350
µs
Gate Low-Side Rise Time in High Speed Mode
t PSRLS
–
3.6
–
–
0.25
–
–
10
–
–
40
–
–
2.5
–
–
1.5
–
–
1.0
–
–
0.5
–
–
10
–
–
80
–
OVERLOAD PROTECTION
High-Side Overcurrent Shutdown Delay (7)
Low-Side Over Load Detection (VOUT - GND) Shutdown Delay (8)
OUTPUT TIMING
From 10% to 90% VOUT, Load = 3.3 nF and 10 Ω
Gate Low-Side Fall Time in High Speed Mode
µs
µs
t NSRLS
From 90% to 10% VOUT, Load = 3.3 nF and 10 Ω
HIGH-SPEED MODE
High-Side Positive Slew Rate
t HR
From 10% to 65% VOUT, Load = 3.0 Ω
High-Side Negative Slew Rate
t HF
From 90% to 35% VOUT, Load = 3.0 Ω
High-Side Turn-On Delay Time
V/µs
µs
t HDON
To 10% VOUT, Load = 3.0 Ω
High-Side Turn-Off Delay Time
V/µs
µs
t HDOFF
To 90% VOUT, Load = 3.0 Ω
LOW-SPEED MODE
High-Side Maximum Output Positive Slew Rate
tLR
From 10% to 65% VOUT, Load = 3.0 Ω
High-Side Maximum Output Negative Slew Rate
tLF
From 90% to 35% VOUT, Load = 3.0 Ω
High-Side Turn On Delay TIme
To 90% VOUT, Load = 3.0 Ω
V/µs
µs
tLDON
To 10% VOUT, Load = 3.0 Ω
High-Side Turn Off Delay Time
V/µs
µs
tLOFF
Notes
7. Time between fault occurrence and output shutdown.
8. Time between fault occurrence and gate low-side (GLS) shutdown.
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
TIMING DIAGRAMS
TIMING DIAGRAMS
IN
In
V
BAT
Vbat
90% of
90%
of Vbat
VBAT
Vbat
60%60%
of Vof
BAT
40%
40% of
of V
Vbat
BAT
tthr
HRAA
tthf
HFAA
10% of
of V
Vbat
10%
BAT
20%of
ofVVbat
20%
BAT
OUT
t HDON
thdon
t HDOFF
thdoff
Out
Figure 4. Outputs Slew Rate and Timing Delay
33486A
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The full bridge is partitioned into three blocks, the 33486A
and two low-side MOSFETS. Each block has a dedicated
package.
The 33486A incorporates two 15 mΩ N-channel high-side
power MOSFETS and two low-side gate drivers. The outputs
are fully protected against shorts to ground, shorts to VBAT,
shorted loads, overvoltage / undervoltage, and
overtemperature. The device can directly interface with a
microcontroller for control and diagnostic functions.
The 33486A is designed for typical DC-motor control in an
H-Bridge configuration.
FUNCTIONAL TERMINAL DESCRIPTION
SUPPLY VOLTAGE (VBAT)
WAKE
The backside of the 33486A, called the tab, is the power
supply of the device. It has undervoltage and overvoltage
detection. In addition to its supply function, the tab
contributes to the thermal behavior of the device by
conducting the heat from the switching MOSFET to the
printed circuit board.
The WAKE terminal is used to place the device in a sleep
mode. When WAKE terminal voltage is a logic LOW state, the
device is in sleep mode and its bias current is at a minimum.
The device is enabled and fully operational when WAKE
terminal voltage is logic HIGH.
STATUS (ST)
INPUTS (IN1 AND IN2)
IN1 and IN2 terminals are input control terminals used to
control the outputs (OUT1 and OUT2) and the gates of the
low-side power MOSFETs (GLS1 and GLS2). When the input
is a logic LOW, the associated output is low (high-side
internal MOSFETs OFF and low-side external MOSFETs
ON). (Refer to Table 5, TRUTH TABLE, page 21, for more
information.) These terminals are 5.0 V CMOS-compatible
inputs.
OUTPUTS (OUT1 AND OUT2)
OUT1 and OUT2 terminals are the sources of the internal
high-side MOSFETs. OUT1 and OUT2 are controlled using
the IN1 and IN2 inputs, respectively. These outputs are
current limited and thermally protected.
GATE LOW SIDE (GLS1 AND GLS2)
The status terminal indicates when the device is in fault
mode. It reports overtemperature and / or overcurrent faults. It
goes active low when a fault mode is detected by the device
on either one channel or both simultaneously. Its internal
structure is an open-drain architecture with an internal clamp
at 6.0 V. An external 10 kΩ pull-up resistor connected to VDD
(5.0 V) is needed. Refer to Table 5, TRUTH TABLE.
CURRENT SENSE (CUR R)
The Current Sense terminal delivers a ratio amount (1/
3700) of the sum of the high-side currents that can be used
to generate signal ground-referenced output voltages for use
by the microcontroller with a 1.0 kΩ pull-down resistor.
GROUND (GND)
This terminal is the ground of the device.
GLS1 and GLS2 terminals are the gates of the external
low-side MOSFETs. These MOSFETs are controlled using
IN1 and IN2 inputs. When the input (INn) is logic HIGH, the
associated GLS is grounded to turn off the external low-side
MOSFET. (Refer to Table 5, TRUTH TABLE for more
information.)
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Power Supply
The 33486A can be directly connected to the power supply
line. The device has a standby mode (Wake at low logic level)
with a ultra-low consumption (10 µA max). In operation when
inputs are active, the supply current is up to 20 mA.
With the high current and fast switching ability of the
33486A, it is recommended that sufficient capacitance (tens
of microfarads) be placed between VBAT and GND of the IC.
This will help ensure that the power supply stays within the
specified limits.
The internal charge pump is activated when Wake is at
high logic level. It is self-oscillating with a frequency that can
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
vary typically from 1.0 MHz to 7.0 MHz. It starts operating at
low frequency.
Reverse Battery Protection
During reverse battery the current flows in the body diodes
of the power MOSFETs, which are forward biased. Figure 5
shows the specific protection that must be implemented.
33486
C
Vbat
VBAT
External Low-Side
Power MOSFETs
Self-Adjusting Switching Speed Mode
This feature allows for reduction in EMC and power
dissipation depending on the application. The 33486A has
two switching speeds (high and low) depending on the input
pulse width. The high-speed condition is active when the
delay between two consecutive input edges is below 250 µs
typical. The low-speed mode is active when the delay
between two consecutive input edges is above 250 µs
typical. The 250 µs delay corresponds about to a 2.0 kHz
frequency with a duty cycle of 50%.
Current Recopy
This feature provides a current mirror with the ratio of 1/
3700 of the sum of the high-side output current. An external
resistor must be connected to the Cur R terminal, then tied to
a microcontroller A / D input for analog voltage measurement
(see Figure 6). This current recopy uses the well-known
Wheatstone bridge principle with the Sense, the Power, and
the load as the three known resistances.
MC33486
gnd
GND
VBAT
Owing to the internal zener clamp in the gate of the M1
transistor, the Cur R max voltage is typically 11 V.
.
Reverse Battery Protection
Sense
Power
Figure 5. Reverse Battery Protection Schematic
1
A reverse battery component might be needed in the GND
or in the VBAT terminal of the application (i.e., diode or
MOSFET) in order to achieve both reverse battery and
negative transient pulses immunity. If a polarized capacitor is
used, it can be placed as shown in in Figure 5.
I COPY
copy
I LOAD
load
M1
Loss of Ground Protection
As Figure 5 shows, a loss of ground will not damage the
33486A because the ground terminal of the device is the
same as the ground of the low side.
5000
A
To A/D
+
-
M
Cur R
Cur
R
External
External
resistor
Resistor
R
MC33486
33486A Ground
gnd
Overvoltage/Undervoltage Protection
If the battery voltage falls below 7.0 V typical, the outputs
are turned low (low-side MOSFETs ON) in a low-speed
mode. The 33486A goes back into normal operation mode as
soon as VBAT rises above the undervoltage threshold. The
undervoltage protection circuitry has hysteresis.
The control circuitry also has an overvoltage detection that
turns the external low-side MOSFETs ON and protects the
load in case VBAT exceeds 29 V typical. The gate drivers will
also be clamped to 14 V to protect the external low-side
MOSFETs. The low-side MOSFETs remain in the ON state
until the overvoltage condition is removed.
Undervoltage and overvoltage are not reported on the
status output.
Logic Ground
Logic
gnd
Figure 6. Current Recopy Principle
In case a ground shift occurs between the MCU and the
33486A, the amplifier A (Figure 6, page 10) will adapt its
output to keep the same ICOPY. Of course the shift has to
keep between ±1.0 V.
Overtemperature Protection
The 33486A incorporates overtemperature protection.
Overtemperature detection occurs when an internal high-side
MOSFET is in the ON state. When an overtemperature
condition occurs, both outputs are affected. Both high-side
MOSFETs are turned OFF to protect the 33486A from
33486A
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
damage (low-side MOSFETs ON). The overtemperature
protection circuitry incorporates hysteresis.
Overtemperature fault condition is reported on the status
output.
As VGS and VDS are measured in respect to the 33486A
ground terminal, it is essential that the low-side source is
connected to this same ground in order to prevent false
overcurrent detection due to ground shifts.
High-Side Overcurrent Protection
Thermal Management
The 33486A incorporates a current shutdown threshold of
35 A typical. When this limit is reached due to an overload
condition or a short to ground, the faulty output is tri-stated.
To clear the fault, the input (INn) line needs to return low, then
on the next high transition the output will be enabled.
The high-side block is assembled into a power surface
mount package. This package offers high thermal
performances and high current capabilities. It offers
10 terminals on each package side and one additional
connection, which is the package heat sink (called terminal
21). The heatsink acts as the device power VBAT connection.
This information is reported on the status output.
Low-Side Block
The low-side block has control circuitry for two external
N-channel power MOSFETs. The low-side control circuitry is
PWM capable and protects the low-side MOSFETs in case of
overcurrent (short to VBAT). This information is reported on
the status output.
The low-side gate controls are clamped at 14 V maximum
to protect the gates of the low-side MOSFETs. Figures 13,
page 15, and 14, page 15, depict the characteristics of the
low-side block when a current is sourced from the GLS pin or
sinked from the GLS pin, respectively.
During normal operation, the outputs OUT1 and OUT2 are
driven by the high side. The low-side gate driver will only turn
on when the voltage (same connection as OUT1 or OUT2) of
the internal high sides is less than 2.0 V, which prevents any
cross-conduction in the bridge.
Low-Side Overcurrent Protection
Unlike the high-side overcurrent circuitry, this overcurrent
protection does not measure the current; rather, it measures
the effect of current on the low-side power MOSFETs through
a condition: VGS > 4.3 V and VDS > 1.0 V. When this set of
conditions occurs for 3.0 µs typical (blanking time), both
outputs OUT1 and OUT2 are tri-stated. The full bridge is tristated to prevent the motor running in case of short to VBAT.
Once the fault is removed, the input INn of the OUTn that
experienced the fault must be reset in order to recover normal
mode operation.
The 33486A can be used without the external low-side
MOSFETs only if the overcurrent protection condition is not
reached. If the external low-side power MOSFETs are not
used, a 470 pF capacitor in parallel with a 100 kΩ resistor
can be connected at the GLSn pin to prevent the activation of
the low-side MOSFET overcurrent protection.
The junction-to-case thermal resistance is 2.0°C/W
maximum. The junction-to-ambient thermal resistance is
dependant on the mounting technology and if an additional
heat sink is used. One of the most commonly used mounting
technique consists of using the printed circuit board and the
copper lines as heatsink.
Figure 7 is an example of printed circuit board layout. It
has a total of 10 cm2 additional copper on two sides (2.5 cm2
on the top side and 7.5 cm2 on the down side).
Top-side PCB
2.0 cm2
Bottom-side PCB
8.0 cm2
33486A
Thermal
via from
top to downside PCB
External PCB (4 x 4 cm)
Figure 7. Printed Board Layout Example (not to scale)
With the above layout, thermal resistance junction-toambient of 25°C/W can be achieved. This value is split into:
•Junction to case (RθJC) = 2.0°C/W
•Case to ambient (RθCA) = 23°C/W
Lower value can be reached with the help of larger and
thicker copper metal, higher number of thermal via from top
to bottom side PCB, and the use of additional thermal via
from the circuit board to the module case.
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Thermal Model
The junction-to-ambient thermal resistance of the circuit
mounted on a printed circuit board can be spit into two main
parts: junction-to-case and case-to-ambient resistances.
Figure 8 shows a simplified steady state model.
Junction Temperature Node
(Volts represent Die
Surface Temperature)
Switch
Power (W)
(1.0 A = 1.0 W of
Power Dissipation)
Any node temperature can easily be calculated knowing
the amount of power flowing through the thermal resistances.
Example
1. Numerical Value
•Junction-to-case thermal resistance (RθJC): 2.0°C/W
•Power into the switch: Assuming the device is driving
8.0 A at 150°C junction temperature (RDS(ON) at
150°C is 40 mΩ), the total power dissipation is 0.04 *
8 * 8 = 2.56 W
•Case-to-ambient thermal resistance (RθCA): 20°C/W
2. Results
RθJC
Case Temperature Node
RθCA
(1.0 Ω = 1.0°C/W)
Ambient Temperature Node
(1.0 V = 1.0°C Ambient Temperature)
Figure 8. Simplified Thermal Model
(Electrical Equivalent)
The use of this model is similar to the electrical Ohm law
(voltage = resistance x current), where:
•Voltage represents temperature.
•Current represents power dissipated by the device.
•Resistance represents thermal resistance.
We finally have:
Temperature or delta temperature = power dissipation
times thermal resistance; that is, °C = W x °C/W.
•Junction-to-case delta temperature: 5.0°C (2.5 W x
2.0°C/W)
•Case delta temperature from ambient: 50°C (20°C/W x
2.5 W)
•Actual junction temperature node will be:
50°C + 5.0°C = 55°C above the ambient
temperature.
Assuming an 85°C ambient temperature, the junction
temperature is 85°C + 55°C = 140°C.
The above example takes into account the junction-toambient thermal resistance, assuming that ambient
temperature is 85°C.
In the case where the device plus its printed circuit board
are located inside a module, the ambient temperature of the
module should be taken into account. Or an additional
thermal resistance from inside module to external ambient
temperature must be added. The calculation method remains
the same.
The low-side block is packaged into D2PAK or DPAK
package. Junction-to-case thermal resistance is
approximately 2/0°C/W. The junction-to-ambient thermal
resistance follows the same rules as for the high-side block
and is in the same range.
33486A
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION
TYPICAL ELECTRICAL CHARACTERISTICS
Note tHF A is measured from 60% VBAT to 20% VBAT.
45.0
40.0
t HRA
(V/µ
s)
Thr
(V/µs)
35.0
30.0
0.5
25°C
0.5Ohm
Ω 25°C
11.0
Ohm
25°C
Ω 25°C
25.0
22.0
Ohm
25°C
Ω 25°C
33.0
Ohm
25°C
Ω 25°C
20.0
15.0
10.0
5.0
0.0
8
8.0
10
12
14
16
Vbat ( V)
VBAT (V)
Note tHRA is measured from 10% VBAT to 40% VBAT.
Figure 9. High-Speed Positive Slew Rate (tHRA) at 25°C for Different Loads
160.0
140.0
µs)
t HFA
Thf(V/(V/µs)
120.0
0.5
at 25°C
0.5Ohm
Ω 25°C
1 1.0
Ohm
25°C
Ω at
25°C
100.0
2 2.0
Ohm
25°C
Ω at
25°C
80.0
3 3.0
Ohm
25°C
Ω at
25°C
60.0
40.0
20.0
8
8.0
10
12
14
16
V
(V)
Vbat
BAT (V)
Note tHFA is measured from 60% VBAT to 20% VBAT.
Figure 10. High-Speed Negative Slew Rate (tHFA) at 25°C for Different Loads
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
Figure 11. Low-Speed Mode, Oscilloscope Format
IN
OUT
Figure 12. High-Speed Mode, Oscilloscope Format
33486A
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ISOURCED
Isourced(mA)
(mA)
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
30
30
25
25
20
20
Vbat=9V
VBAT = 9.0
25°C
V 25°C
15
15
10
10
5.0
5
00
V 25°C
VBAT = 12 25°C
Vbat=12V
VBAT = 16 25°C
V 25°C
Vbat=16V
00
5.0
5
10
10
15
15
VGLS (V)
VGLS(V)
Figure 13. Gate Low-Side (GLS) Sourced Current Capability (High-Speed Mode)
70
Vbat=9V 25°C
ISINKED (mA)
Isinked ( mA)
60
50
VBAT = 9.0 V 25°C
vbat=12V
VBAT = 12 V 25°C
25°C V = 16 V 25°C
40
30
BAT
Vbat=16V
25°C
20
10
0
0
5
5.0
10
15
20
VGLS (V)
(V)
VGLS
Figure 14. Gate Low-Side (GLS) Sinked Current Capability (High-Speed Mode)
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
6.0
6
tPSRLS ( µs)
Tpsrls(us)
5.0
5
4.0
4
3.0
3
2.0
2
8.0
8
10
12
14
16
18
VBAT (V)
Vbat(V)
Note Curve is obtained with a load at GLS of 3.3 nF and 10 Ω at 25°C.
1 111
1 010
9
9.0
8
8.0
7
7.0
6
6.0
tPSRLS ( µs)
Tpsrls(us)
Figure 15. Gate Low-Side (GLS) Rise Time (High-Speed Mode)
8.0
8
10
12
13
14
16
1188
VBAT (V)
V b a t (V )
Note Curve is obtained with a load at GLS of 3.3 nF and 10 Ω at 25°C.
Figure 16. Gate Low-Side (GLS) Rise Time (Low-Speed Mode)
tNSRLS
(µ s)
Tnsrls(us)
0.3
0.28
0.26
0.24
0.22
0.2
8
8.0
10
12
14
16
18
VVbat(V)
BAT (V)
Note Curve is obtained with a load at GLS of 3.3 nF and 10 Ω at 25°C.
Figure 17. Gate Low-Side Fall Time (High-Speed Mode)
33486A
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
tTnsrls(us)
NSRLS (µ s)
3
3.0
2.5
2.0
2
1.5
1
1.0
1.0
8
8.0
10
12
14
16
18
V
Vbat(V)
BAT (V)
Note Curve is obtained with a load at GLS of 3.3 nF and 10 Ω at 25°C.
Figure 18. Gate Low-Side Fall Time (Low-Speed Mode)
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL CURVES
In2
IN2
IN1
In1
IN2
In2
Out1
OUT1
In1
IN1
Direction1
Direction1
High
HighImpedance
Impedance
Out1
OUT1
Break
Brake to
toGround
Ground
OUT2
Out2
Direction2
Direction2
GLS2
GLS2
GLS1
GLS1
Ihs1
I
HS1
Low
Low
Current
Currentshutdown
Shutdown
IIlim
LIM
GLS1
GLS1
St
Figure 19. Normal Operation
ST
Low
Low
Figure 21. Overcurrent on High-Side 1
In 2
IN2
IN1
In1
IN1
In
1
OUT1
O u t1
HS1
H
S 1 Off
o ff
O u t2
OUT2
HS2
H S 2Off
o ff
OUT2
Out2
LLS1
S 1 On
on
Out1
OUT1
GGLS1
LS1
GLS2
GL
S2
St
ST
SHUT
High
High Impedance
Impedance
VOUT
Vout
-Fault
-fault
High
HighImpedance
Impedance
Vds>2V
VDS > Vgs>4.3V
2.0 V, VGS > 4.3 V
least
AtAt
least
8µs8.0 µs
L S 2On
on
LS1
T
h e r m a lShutdown
s h u td o w n
Thermal
TTs h u t
TT°C
°C
HHS1
S1
IN2
In2
GLS1
GLS1
HHysteresis
y s te r e s is
TThHYST
yst
LOW
L
ow
Figure 20. Overtemperature on High-Side 1
GLS2
GLS2
StST
Low
Low
Low
Low
Figure 22. Overload on Low-Side 1
33486A
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
ELECTRICAL PERFORMANCE
Temperat ure=25°C
Temperature
= 25°C
21
Temperat ure=125°C
Temperature
= 125°C
Temperat ure=-40°C
Temperature
= -40°C
19
4200
4100
15
4000
13
3900
11
3800
CR
RDS(ON) in m
17
9
3700
3600
7
3500
5
-50
3400
0
50
100
3300
150
3200
Tem perature (°C)
0
2.0
2
4.0
4
6.0
6
8.0
8
10
IOUT
I( A ) (A)
Figure 23. RDS(ON) versus Temperature
for VBAT > 10 V
Figure 25. CR versus IOUT Overtemperature
for VBAT = 10 V
Temper at ur e==25°C
25°C
Temperature
Temper at ur e==125°C
Temperature
125°C
Temperature
= 25°C
Temper atur e=25°C
Temper at ur e==--40°C
40°C
Temperature
Temperature
= 125°C
Temper atur e=125°C
Temper atur e=-40°C
Temperature
= -40°C
4200
4100
4000
3900
3700
3600
Cr
CCr
R
3800
3500
3400
3300
3200
0
2
2.0
4
4.0
6
6.0
8
8.0
10
10
IOUT
I(A)(A)
Figure 24. CR versus IOUT Overtemperature
for VBAT = 12 V
4200
4100
4000
3900
3800
3700
3600
3500
3400
3300
3200
00
2.0
2
4.0
4
6.0
6
8.0
8
10
IOUT
I(A) (A)
Figure 26. CR versus IOUT Overtemperature
for VBAT = 16 V
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
I(A) (A)
IOUT
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
16
14
12
10
8
6
4
2
0
-50
0
50
100
150
200
Temperature
(°C)
Tem
perature(°C)
Figure 27. Continuous Current versus
Temperature with RθJA = 27.5°C/W
Figure 28.
33486A
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 5. TRUTH TABLE
Standard H-Bridge Conditions
Normal Operation
IN1
IN2
WAKE
OUT1
OUT
GLS1
GLS2
ST
Comment
X
X
0
Z
Z
L
L
1
Standby Mode
0
0
1
L
L
H
H
1
Brake to Ground
1
0
1
H
L
L
H
1
Direction 1
0
1
1
L
H
H
L
1
Direction 2
1
1
1
H
H
L
L
1
Not Recommended
(9)
Undervoltage
X
X
1
L
L
H
H
1
(10)
Overvoltage
X
X
1
L
L
H
H
1
(10)
Overtemperature High-Side 1
H
L
1
L
L
H
H
0
(11)
Overtemperature High-Side 2
L
H
1
L
L
H
H
0
(11)
Overcurrent High-Side 1
1
X
1
Z
X
L
X
0
(12)
Overcurrent High-Side 2
X
1
1
X
Z
X
L
0
(12)
Overcurrent Low-Side 1
X
X
1
Z
Z
L
L
0
(13)
Overcurrent Low-Side 2
X
X
1
Z
Z
L
L
0
(13)
Legend
0, L = Low level.
1, H = High level.
X = Don’t care.
Z = High impedance.
Notes
9. In H-Bridge configuration it is not advisable to short the motor to VBAT . If an overvoltage condition occurred in this mode, it would
damage the 33486A. The current recirculation in the low-side MOSFET is a preferred solution, with IN1 = 0 and IN2 = 0.
10. Once the overvoltage condition or undervoltage condition is removed, the H-Bridge recovers its normal operation mode.
11. When the thermal shutdown is reached on one of the high-side MOSFETs, both high sides are turned off with the motor tied to ground.
When the overtemperature condition is finished, the H-Bridge recovers it previous normal operation mode.
12. The high-side MOSFET HSn that experienced an overcurrent is latched off. The corresponding output OUTn is open. Once the highside overcurrent condition is removed, the input INn must be reset in order to recover the normal operation mode.
13. When a short to VBAT of one of the low-side MOSFETs occurs, both outputs are opened to prevent the motor from running. Once the
low-side overcurrent is removed, the input INn of the output that experienced the fault must be reset in order to recover the normal
operation mode. Figure 22, Overload on Low-Side 1, page 18, shows an example. If an overload happens in low-side 1, OUT1 and
OUT2 are both put in high impedance. IN2 must be reset to recover normal mode.
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
5.0 V
VBAT
5.0 V
33486A
10 kΩ
OUT2
ST
IN1
GLS2
IN2
MCU
470 µF
VBAT
WAKE
OUT1
Cur R
GLS1
GND
1.0 kΩ
GND
Figure 29. 33486A Typical Application Diagram
33486A
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
For the most current revision of the package, visit www.freescale.com and do a keyword search using the 98A number for the
specific device related to the data sheet.
DW SUFFIX
20-TERMINAL HSOP
98ASH70702A
ISSUE B
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
PACKAGING
PACKAGING DIMENSIONS (CONTINUED)
PACKAGING DIMENSIONS (CONTINUED)
DW SUFFIX
20-TERMINAL HSOP
98ASH70702A
ISSUE B
33486A
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
Revision
2.0
Date
12/2005
Description of Changes
Updated to Freescale Format
Added Thermal Addendum
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
33486A
THERMAL ADDENDUM (REV 1.0)
DUAL HIGH-SIDE SWITCH FOR H-BRIDGE APPLICATIONS
Introduction
This thermal addendum is provided as a supplement to the MC33486
technical datasheet. The addendum provides thermal performance
information that may be critical in the design and development of
system applications. All electrical, application, and packaging
information is provided in the datasheet.
20-TERMINAL
HSOP
Packaging and Thermal Considerations
The MC33486A package is a dual die package. There are two heat
sources in the package independently heating with P1 and P2. This
results in two junction temperatures, TJ1 and TJ2, and a thermal
resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the
reference temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to
the reference temperature while heat source 2 is heating with P2. This
applies to RθJ21 and RθJ22, respectively.
TJ1
TJ2
=
RθJA11 RθJA12
RθJA21 RθJA22
.
DH SUFFIX
98ASH70702A
20-TERMINAL HSOP
Note For package dimensions, refer to the
33486A device datasheet.
P1
P2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
Standards
Table 6.
1.0
Thermal Performance Comparison
1.0
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
Resistance
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
(1)(2)
19
18
21
RθJBmn(2)(3)
7.0
6.0
10
RθJAmn(1)(4)
51
50
53
RθJCmn(5)
< 0.5
0
3.0
RθJAmn
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
20 Terminal HSOP-EP
1.27 mm Pitch
16.0 mm x 11.0 mm Body
12.2 mm x 6.9 mm Exposed Pad
Thermal vias
connected to top
buried plane
Figure 30. Thermal Land Pattern for Direct Thermal
Attachment per JESD51-5
33486A
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
A
VBAT
GND
1
20
WAKE
Cur R
2
19
ST
IN1
3
18
IN2
GLS1
4
17
GLS2
OUT1
5
16
OUT2
OUT1
6
15
OUT2
OUT1
7
14
OUT2
OUT1
8
13
OUT2
NC
9
12
NC
NC
10
11
NC
VBAT
33486A Terminal Connections
20-Terminal HSOP
1.27 mm Pitch
16.0 mm x 11.0 mm Body
12.2 mm x 6.9 mm Exposed Pad
Figure 31. Thermal Test Board
Device on Thermal Test Board
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Table 7.
Material:
Outline:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
80 mm x 100 mm board area,
including edge connector for thermal
testing
Area A:
Cu heat-spreading areas on board
surface
Ambient Conditions:
Natural convection, still air
Thermal Resistance Performance
1 = Power Chip, 2 = Logic Chip (°C/W)
Thermal
Resistance
Area A
(mm2)
RθJA
RθJS
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
0
51
50
53
300
35
34
38
600
31
30
33
0
11
10
13
300
7.0
7.0
10
600
7.0
6.0
9.0
RθJA is the thermal resistance between die junction and
ambient air.
RθJS is the thermal resistance between die junction and
the reference location on the board surface near a center
lead of the package (see Figure 31).
33486A
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Thermal Resistance [ºC/W]
60
50
40
30
20
x
10
0
0
RθJA11
RθJA22
RθJA12 = RθJA21
300
Heat spreading area A [mm²]
600
Figure 32. Device on Thermal Test Board RθJA
Thermal Resistance
(°CW)
100
10
1
x
0.1
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.00E+02
RθJA11
RθJA22
RθJA12 = RθJA21
1.00E+03
1.00E+04
Time(s)
Figure 33. Transient Thermal Resistance RθJA (1.0 W Step Response)
Device on Thermal Test Board Area A = 600 (mm2)
33486A
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
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MC33486A
Rev 2.0
12/2005
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
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