Freescale Semiconductor Advance Information Document Number: MC33981 Rev. 8.0, 6/2009 Single High Side Switch (4.0 mΩ), PWM clock up to 60 kHz 33981 The 33981 is a high frequency, self-protected 4.0 mΩ RDS(ON) high side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33981 can be controlled by Pulse-width Modulation (PWM) with a frequency up to 60 kHz. It is designed for harsh environments, and it includes self-recovery features. The 33981 is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. The 33981 is packaged in a 12 x 12 non-leaded power-enhanced Power QFN package with exposed tabs. Features • Single 4.0 mΩ RDS(ON) maximum high side switch • PWm capability up to 60 kHz with duty cycle from 5% to 100% • Very low standby current • Slew rate control with external capacitor • Over-current and over-temperature protection, under-voltage shutdown and fault reporting • Reverse battery protection • Gate drive signal for external low side N-channel MOSFET with protection features • Output current monitoring • Temperature feedback • Pb-free packaging designated by suffix code PNA VDD HIGH SIDE SWITCH Bottom View PNA (Pb-Free Suffix) 98ARL10521D 16-PIN PQFN (12 X 12) ORDERING INFORMATION Device Temperature Range (TA) Package MC33981BPNA/R2 - 40°C to 125°C 16 PQFN VPWR VDD 33981 CONF MCU I/O FS I/O INLS I/O EN I/O A/D INHS TEMP A/D CSNS VPWR CBOOT OUT DLS GLS OCLS SR GND Figure 1. 33981 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007 - 2008. All rights reserved. M INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VPWR Under-voltage Detection Temperature Feedback TEMP CBOOT Bootstrap Supply SR Gate Driver Slew Rate Control FS EN Logic INHS INLS Current Protection Over-temperature Detection OUT Current Recopy Low Side Gate Driver and Protection 5.0V RDWN OUT IDWN 5.0 V GLS DLS ICONF CONF IOCLS CrossConduction GND CSNS OCLS Figure 2. 33981 Simplified Internal Block Diagram 33981 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS Package Transparent Top View CSNS TEMP EN INHS FS INLS CONF OCLS DLS GLS SR CBOOT 4 5 6 7 8 9 1 2 3 10 11 12 GND 13 VPWR 14 15 16 OUT OUT Figure 3. Pin Connections Table 1. PIN DEFINITIONS Descriptions of the pins listed in the table below can be found in the Functional Description section located on page 12. Pin Number Pin Name Pin Function Formal Name 1 CSNS Reports Output Current Monitoring 2 TEMP Reports Temperature Feedback 3 EN Input Enable (Active High) 4 INHS Input Serial Input High Side 5 FS Reports Fault Status (Active Low) 6 INLS Input Serial Input Low Side 7 CONF Input Configuration Input This input manages MOSFET N-channel cross-conduction. 8 OCLS Input Low Side Overload This pin sets the VDS protection level of the external low side MOSFET. 9 DLS Input Drain Low Side This pin is the drain of the external low side N-channel MOSFET. 10 GLS Output Low Side Gate This output pin drives the gate of the external low side N-channel MOSFET. 11 SR Input Slew Rate Control 12 CBOOT Input Bootstrap Capacitor 13 GND Ground Ground 14 VPWR Input Positive Power Supply 15, 16 OUT Output Output Definition This pin is used to generate a ground-referenced voltage for the microcontroller (MCU) to monitor output current. This pin is used by the MCU to monitor board temperature. This pin is used to place the device in a low-current Sleep Mode. This input pin is used to control the output of the device. This pin monitors fault conditions and is active LOW. This pin is used to control an external low side N-channel MOSFET. This pin controls the output slew rate. This pin provides the high pulse current to drive the device. This is the ground pin of the device. This pin is the source input of operational power for the device. These pins provide a protected high side power output to the load connected to the device. 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit ELECTRICAL RATINGS Power Supply Voltage VPWR V Steady-state -16 to 41 Input/Output Pins Voltage(1) Output Voltage INHS, INLS, CONF, CSNS, FS, TEMP, EN - 0.3 to 7.0 VOUT Positive V V 41.0 Negative -5.0 Continuous Output Current (2) CSNS Input Clamp Current EN Input Clamp Current SR Voltage IOUT 40.0 A ICL(CSNS) 15.0 mA ICL(EN) 2.5 mA VSR - 0.3 to 54.0 V CBOOT Voltage CBOOT - 0.3 to 54.0 V OCLS Voltage VOCLS - 5.0 to 7.0 V Low Side Gate Voltage VGLS - 0.3 to 15.0 V Low Side Drain Voltage VDLS - 5.0 to 41.0 V ESD Voltage(3) VESD Human Body Model (HBM) V ± 2000 Charge Device Model (CDM) Corner Pins (1, 12, 15, 16) ± 750 All Other Pins (2-11, 13-14) ± 500 THERMAL RATINGS Operating Temperature °C Ambient TA - 40 to 125 Junction TJ - 40 to 150 TSTG - 55 to 150 RθJC 1.0 Storage Temperature (4) Thermal Resistance Junction to Power Die Case Junction to Ambient Peak Package Reflow Temperature During Reflow(5), (6) RθJA 30.0 TPPRT Note 6 °C °C/W °C Notes 1. Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN pins may cause a malfunction or permanent damage to the device. 2. Continuous high side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 4. 5. 6. Device mounted on a 2s2p test board per JEDEC JESD51-2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33981 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Fully Operational 6.0 – 27.0 Extended(7) 4.5 – 27.0 – 10.0 12.0 – 10.0 12.0 Unit POWER INPUT (VPWR) Battery Supply Voltage Range VPWR Supply Current VPWR V IPWR(ON) INHS = 1 and OUT Open mA INLS = 0 VPWR Supply Current IPWR(SBY) INHS = INLS = 0, EN = 5.0 V, OUT Connected to GND Sleep-state Supply Current mA μA IPWR(SLEEP) (VPWR < 14 V, EN = 0 V, OUT Connected to GND) TA = 25°C – – 5.0 TA = 125°C – – 50.0 Under-voltage Shutdown VPWR(UV) 2.0 4.0 4.5 V Under-voltage Hysteresis VPWR(UVHYS) 0.05 0.15 0.3 V POWER OUTPUT (IOUT, VPWR) Output Drain-to-Source ON Resistance (IOUT = 20 A, TA = 25°C) RDS(ON)25 mΩ VPWR = 6.0 V – – 6.0 VPWR = 9.0 V – – 5.0 VPWR = 13.0 V – – 4.0 VPWR = 6.0 V – – 10.2 VPWR = 9.0 V – – 8.5 VPWR = 13.0 V – – 6.8 – – 8.0 75 100 125 Output Drain-to-Source ON Resistance (IOUT = 20 A, TA = 150°C) Output Source-to-Drain ON Resistance (IOUT = -20 A, TA = 25°C)(8) RDS(ON)150 RSD(ON) VPWR = - 12 V Output Overcurrent Detection Level A CSR 9.0 V < VPWR < 16 V, CSNS < 4.5 V Current Sense Ratio (CSR) Accuracy mΩ I OCH 9.0 V < VPWR < 16 V Current Sense Ratio mΩ – – 1/20000 – CSR_ACC % 9.0 V < VPWR < 16 V, CSNS < 4.5 V Output Current 5.0 A -20 – 20 15 A, 20 A and 30 A -15 – 15 4.5 6.0 7.0 Current Sense Voltage Clamp I CSNS = 15 mA VCL(CSNS) V Notes 7. OUT can be commanded fully on, PWM is available at room. Low Side Gate driver is available. Protections and Diagnosis are not available. Min/max parameters are not guaranteed. 8. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR. 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit 0 13 17 TSD 160 175 190 °C TSDHYS 5.0 – 20 °C 5.0 5.4 6.0 POWER OUTPUT (VPWR) (continued) Current Sense Leakage(9) Over-temperature Shutdown Over-temperature Shutdown μA ILEAK(CSNS) I NHS = 1 with OUT opened of load or INHS = 0 Hysteresis(10) LOW SIDE GATE DRIVER (VPWR, VGLS, VOCLS) Low Side Gate Voltage VGLS VPWR = 6.0 V V VPWR = 9.0 V 8.0 8.4 9.0 VPWR = 13 V 12.0 12.4 13.0 VPWR = 27 V 12.0 12.4 13.0 Low Side Gate Sinked Current I GLSNEG VGLS = 2.0 V, VPWR = 13 V Low Side Gate Sourced Current – 100 – – 100 – -50 – +50 3.3 – – I GLSPOS VGLS = 2.0 V, VPWR = 13 V Low Side Overload Detection Level versus Low Side Drain Voltage mA mA VDS_LS VOCLS - VDLS, (VOCLS ≤ 4.0 V) mV CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS) Input Logic High-voltage (CONF, INHS, INLS) Input Logic Low-voltage (CONF, INHS, INLS) VIH V VIL – – 1.0 V VINHYS 100 600 1200 mV Input Logic Active Pull-down Current (INHS, INLS) IDWN 5.0 10 20 μA Enable Pull-down Resistor (EN) RDWN 100 200 400 kΩ Enable Voltage Threshold (EN) VEN Input Logic Voltage Hysteresis (CONF, INHS, INLS) Input Clamp Voltage (EN) 2.5 V VCLEN IEN < 2.5 mA V 7.0 – 14 Input Forward Voltage (EN) VF(EN) -2.0 – -0.3 V Input Active Pull-up Current (OCLS) IOCLS p 50 100 200 μA Input Active Pull-up Current (CONF) I CONF 5.0 10 20 μA FS Tri-state Capacitance(10) CFS – – 20 pF FS Low-state Output Voltage VFSL IFS = -1.6 mA Temperature Feedback – 0.2 0.4 3.35 3.45 3.55 -8.5 -8.9 -9.3 V VTFEED TA = 25°C for VPWR = 14 V Temperature Feedback Derating(10) V DTFEED mV/°C Notes 9. This parameter is achieved by the design characterization by measuring a statistically relevant sample size across process variations but not tested in production. 10. Parameter is guaranteed by process monitoring but is not production tested. 33981 6 Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Charge Blanking Time (CBOOT)(12) t ON 10 25 50 μs Output Rising Slew Rate SRR CONTROL INTERFACE AND POWER OUTPUT TIMING (CBOOT, VPWR) VPWR = 13 V, from 10% to 90% of VOUT, SR Capacitor = 4.7 nF, RL= 5.0 Ω Output Falling Slew Rate 8.0 Time(13) 35 Output Turn-OFF Delay Time(14) (15) Time to Reset Fault Diagnosis 35 ns 200 400 700 500 1000 1500 f PWM – 20 60 kHz R PWM 5.0 95 % t DLYOFF ns t RSTDIAG (overload on high side or external low side) Output Over-current Detection Time 16 t DLYON VPWR = 13 V, SR Capacitor = 4.7 nF Input Switching Frequency(11) V/μs 8.0 VPWR = 13 V, SR Capacitor = 4.7 nF Output PWM ratio @ 60 kHz 16 SRF VPWR = 13 V, from 90% to 10% of VOUT, SR Capacitor = 4.7 nF, RL= 5.0 Ω Output Turn-ON Delay V/μs t OCH μs 100 200 400 1.0 10 20 μs Notes 11. The MC33981 can work down (~100Hz). The fault management reset can not be guaranteed with PWM frequency lower than 5.0 kHz (INHS=0 during 200 μs typ) 12. Values for CBOOT=100 nF. Refer to the paragraph entitled Sleep Mode on page 13. Parameter is guaranteed by design and not production tested. 13. Turn-ON delay time measured from rising edge of INHS that turns the output ON to VOUT = 0.5 V with RL= 5.0 Ω resistive load. 14. Turn-OFF delay time measured from falling edge of INHS that turns the output OFF to VOUT = VPWR -0.5 V with RL= 5.0 Ω resistive load. 15. The ratio is measured at VOUT = 50% VPWR without SR capacitor. The device is capable of 100% duty cycle. 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 7 DYNAMIC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS INHS 5.0 V 0.0 V VOUT RPWM VPWR - 0.5 V 50%VPWR 0.5 V t DLY(ON) t DLY(OFF) VOUT 90% Vout 10% Vout SR R SR F Figure 4. Time Delays Functional Diagrams EN FS t ON After 5.0 V CONF INHS INLS OUT GLS Figure 5. Normal Mode, Cross-Conduction Management 33981 8 Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS EN FS t ON After CONF INHS 0.0 V High Side ON High Side OFF INLS OUT GLS Figure 6. Normal Mode, Independent High Side and Low Side 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 9 DYNAMIC ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES 7.0 RDS(ON) (mΩ) RdsON (mOhm) 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -50 0 50 100 150 200 Temperature (°C) Temperature (°C) IIpwr(sleep)(µA) PWR(SLEEP) (μA) Figure 7. Typical RDS(ON) vs. Temperature at VPWR = 13 V 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 4.5 6.0 9.0 12.0 12.5 13.0 14.0 17.0 21.0 V Vpwr(V) PWR (V) Figure 8. Typical Sleep-state Supply Current vs. VPWR at 150°C Vout Rise Time (ns) 1600 1400 1200 1000 800 600 400 200 0 0 2.0 4.0 6.0 8.0 10 SR Capacitor (nF) Figure 9. VOUT Rise Time vs. SR Capacitor From 10% to 90% of VOUT at 25°C and VPWR = 13 V 33981 10 Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES Vout Fall Time (ns) 1600 1400 1200 1000 800 600 400 200 0 0 2.0 4.0 6.0 8.0 10 SR Capacitor (nF) Figure 10. VOUT Fall Time vs. SR Capacitor From 10% to 90% of VOUT at 25°C and VPWR = 13 V 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33981 is a high-frequency self-protected silicon 4.0 mΩ RDS(ON) high side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33981 can be controlled by pulse-width modulation (PWM) with a frequency up to 60 kHz. It is designed for harsh environments, and it includes self-recovery features. The 33981 is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. A dedicated parallel input is available for an external low side control with protection features and cross-conduction management. FUNCTIONAL PIN DESCRIPTIONS OUTPUT CURRENT MONITORING (CSNS) This pin is used to output a current proportional to the high side OUT current and is used externally to generate a ground-referenced voltage for the microcontroller (MCU) to monitor OUT current. TEMPERATURE FEEDBACK (TEMP) This pin reports an analog value proportional to the temperature of the GND flag (pin 13). It is used by the MCU to monitor board temperature. ENABLE [ACTIVE HIGH] (EN) This is an input used to place the device in a low-current Sleep Mode. This pin has an active passive internal pulldown. INPUT HIGH SIDE (INHS) The input pin is used to directly control the OUT. This input has an active internal pull-down current source and requires CMOS logic levels. two MOSFETs are controlled independently. When CONF is at VDD 5.0 V, the two MOSFETs cannot be on at the same time. LOW SIDE OVERLOAD (OCLS) This pin sets the VDS protection level of the external low side MOSFET. This pin has an active internal pull-up current source. It must be connected to an external resistor. DRAIN LOW SIDE (DLS) This pin is the drain of the external low side N-channel MOSFET. Its monitoring allows protection features: low side short protection and VPWR short protection. LOW SIDE GATE (GLS) This pin is an output used to drive the gate of the external low side N-channel MOSFET. SLEW RATE CONTROL (SR) A capacitor connected between this pin and ground is used to control the output slew rate. FAULT STATUS (FS) This pin is an open drain-configured output requiring an external pull-up resistor to VDD (5.0 V) for fault reporting. When a device fault condition is detected, this pin is active LOW. INPUT LOW SIDE (INLS) This input pin is used to directly control an external low side N-channel MOSFET and has an active internal pulldown current source and requires CMOS logic levels. It can be controlled independently of the INHS depending of CONF pin. CONFIGURATION INPUT (CONF) This input pin is used to manage the cross-conduction between the internal high side N-channel MOSFET and the external low side N-channel MOSFET. The pin has an active internal pull-up current source. When CONF is at 0 V, the BOOTSTRAP CAPACITOR (CBOOT) A capacitor connected between this pin and OUT is used to switch the OUT in PWM mode. GROUND (GND) This pin is the ground for the logic and analog circuitry of the device. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package. OUTPUT (OUT) Protected high side power output to the load. Output pins must be connected in parallel for operation. 33981 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES NORMAL MODE The 33981 has 2 operating modes: Sleep and Normal depending on EN input. SLEEP MODE Sleep Mode is the state of the 33981 when the EN is logic [0]. In this mode, OUT, the gate driver for the external MOSFET, and all unused internal circuitry are off to minimize current draw. The 33981 will go to the Normal operating mode when the EN pin is logic [1]. The INHS and INLS commands will be disabled t ON after the EN transitions to logic [1] to enable the charge of the bootstrap capacitor. Table 5. Operating Modes Condition CONF INHS INLS OUT GLS FS EN Comments Sleep x x x x x H L Device is in Sleep Mode. The OUT and low side gate are OFF. Normal L H H H H H H Normal Mode. High side and low side are controlled independently. The high side and the low side are both on. Normal L L L L L H H Normal Mode. High side and low side are controlled independently. The high side and the low side are both off. Normal L L H L H H H Normal Mode. Half-bridge configuration. The high side is off and the low side is on. Normal L H L H L H H Normal Mode. Half-bridge configuration. The high side is on and the low side is off. Normal H PWM H PWM PWM_bar H H Normal Mode. Cross-conduction management is activated. Half-bridge configuration. H = High level L = Low level x = Don’t care PWM_bar = Opposite of pulse-width modulation signal. PROTECTION AND DIAGNOSTIC FEATURES UNDER-VOLTAGE The 33981 incorporates under-voltage protection. In case of VPWR<VPWR(UV), the OUT is switched OFF until the power supply rises to VPWR(UV)+VPWR(UVHYS). The latched fault are reset below VPWR(UV). The FS output pin reports the undervoltage fault in real time. temperature falls below TSD. This cycle will continue until the offending load is removed. FS pin transition to logic [1] will be disabled typically t ON after to enable the charge of the bootstrap capacitor. Over-temperature faults force the TEMP pin to 0 V. OVER-CURRENT FAULT ON HIGH SIDE OVER-TEMPERATURE FAULT The 33981 incorporates over-temperature detection and shutdown circuitry on OUT. Over-temperature detection also protects the low side gate driver (GLS pin). Over-temperature detection occurs when OUT is in the ON or OFF state and GLS is at high or low level. For OUT, an over-temperature fault condition results in OUT turning OFF until the temperature falls below TSD. This cycle will continue indefinitely until the offending load is removed. Figure 12 and Figure 18 show an over-temperature on OUT. An over-temperature fault on the low side gate drive results in OUT turning OFF and the GLS going to 0V until the The OUT pin has an over-current high-detection level called I OCH for maximum device protection. If at any time the current reaches this level, OUT will stay OFF and the CSNS pin will go to 0V. The OUT pin is reset (and the fault is delatched) by a logic [0] at the INHS pin for at least t RST(DIAG). When INHS goes to 0 V, CSNS goes to 5.0 V. In Figure 15, the OUT pin is short-circuited to 0V. When the current reaches I OCH , OUT is turned OFF within t OCH owing to internal logic circuit. OVER-LOAD FAULT ON LOW SIDE This fault detection is active when INLS is logic [1]. Low side overload protection does not measure the current 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES directly but rather its effects on the low side MOSFET. When VDLS > VOCLS, the GLS pin goes to 0V and the OCLS internal current source is disconnected and OCLS goes to 0V. The GLS pin and the OCLS pin are reset (and the fault is delatched) by a logic [0] at the INLS pin for at least t RST(DIAG). Figure 13 and Figure 14 illustrate the behavior in case of overload on Low Side Gate driver. When connected to an external resistor, the OCLS pin with its internal current source sets the VOCLS level. By changing the external resistance, the protection level can be adjusted depending on low side characteristics. A 33 kΩ resistor gives a VDS level of 3.3 V typical. This protection circuitry measures the voltage between the drain of the low side (DLS pin) and the 33981 ground (GND pin). For this reason it is key that the low side source, the 33981 ground, and the external resistance ground connection are connected together in order to prevent false error detection due to ground shifts. The maximum OCLS voltage being 4.0 V, a resistor bridge on DLS must be used to detect a higher voltage across the low side. CONFIGURATION The CONF pin manages the cross-conduction between the internal MOSFET and the external low side MOSFET. With the CONF pin at 0V, the two MOSFETs can be independently controlled. A load can be placed between the high side and the low side. With the CONF pin at 5.0 V, the two MOSFETs cannot be on at the same time. They are in half-bridge configuration as shown in the simplified application diagram on page 1. If INHS and INLS are at 5.0 V at the same time, INHS has priority and OUT will be at VPWR. If INHS changes from 5.0 V to 0 V with INLS at 5.0 V, GLS will go to high state as soon as the VGS of the internal MOSFET is lower than 2.0 V typically. A half-bridge application could consist in sending PWM signal to the INHS pin and 5.0 V to the INLS pin with the CONF pin at 5.0 V. Figure 20, illustrates the simplified application diagram on page 1 with a DC motor and external low side. The CONF and INLS pins are at 5.0 V. When INHS is at 5.0 V, current is flowing in the motor. When INHS goes to 0 V, the load current recirculates in the external low side. BOOTSTRAP SUPPLY Bootstrap supply provides current to charge the bootstrap capacitor through the VPWR pin. A short time is required after the application of power to the device to charge the bootstrap capacitor. A typical value for this capacitor is 100 nF. An internal charge pump allows continuous MOSFET drive. When the device is in the sleep mode, this bootstrap supply is off to minimize current consumption. HIGH SIDE GATE DRIVER The high side gate driver switches the bootstrap capacitor voltage to the gate of the MOSFET. The driver circuit has a low-impedance drive to ensure that the MOSFET remains OFF in the presence of fast falling dV/dt transients on the OUT pin. This bootstrap capacitor connected between the power supply and the CBOOT pin provides the high pulse current to drive the device. The voltage across this capacitor is limited to about 13 V typical. An external capacitor connected between pins SR and GND is used to control the slew rate at the OUT pin. Figure 9 and Figure 10 give VOUT rise and fall time versus different SR capacitors. LOW SIDE GATE DRIVER The low side control circuitry is PWM capable. It can drive a standard MOSFET with an RDS(ON) as low as 10.0 mΩ at a frequency up to 60 kHz. The VGS is internally clamped at 12 V typically to protect the gate of the MOSFET. The GLS pin is protected against short by a local over temperature sensor. THERMAL FEEDBACK The 33981 has an analog feedback output (TEMP pin) that provides a value in inverse proportion to the temperature of the GND flag (pin 13). The controlling microcontroller can “read” the temperature proportional voltage with its analogto-digital converter (ADC). This can be used to provide realtime monitoring of the PC board temperature to optimize the motor speed and to protect the whole electronic system. TEMP pin value is VTFEED with a negative temperature coefficient of DTFEED. REVERSE BATTERY The 33981 survives the application of reverse battery voltage as low as -16 V. Under these conditions, the output’s gate is enhanced to decrease device power dissipation. No additional passive components are required. The 33981 survives these conditions until the maximum junction rating is reached. In the case of reverse battery in a half-bridge application, a direct current passes through the external freewheeling diode and the internal high side. As Figure 11 shows, it is essential to protect this power line. The proposed solution is an external N-channel low side with its gate tied to battery voltage through a resistor. A high side in the VPWR line could be another solution. 33981 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES GROUND (GND) DISCONNECT PROTECTION VDD MCU VPWR No current If the DC motor module ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the output state at the time of disconnection. A 10 k resistor needs to be added between the EN pin and the rest of the circuitry in order to ensure the device turns off in case of ground disconnect and to prevent exceeding this pin’s maximum ratings. 33981 GND OUT FAULT REPORTING Diode VPWR M This 33981 indicates the faults below as they occur by driving the FS pin to logic [0]: • Over-temperature fault • Over-current fault on OUT • Overload fault on the external low side MOSFET The FS pin will return to logic [1] when the over temperature fault condition is removed. The two other faults are latched. 10.0 kΩ Figure 11. Reverse Battery Protection Table 6. Functional Truth Table in Fault Mode Conditions CONF INHS INLS OUT GLS FS EN TEMP CSNS OCLS Comments Over-temperature on OUT x x x L H L H L x x The 33981 is currently in Fault Mode. The OUT is OFF. TEMP at 0V indicates this fault. Once the fault is removed 33981 recovers its normal mode. Over-temperature on GLS x x x L L L H L x x The 33981 is currently in Fault Mode. The OUT is OFF and GLS is at 0V. TEMP at 0V indicates this fault. Once the fault is removed 33981 recovers its Normal Mode. Over-current on OUT x H L L x L H x L x The 33981 is currently in Fault Mode. The OUT is OFF. It is reset by a logic [0] at INHS for at least t RST(DIAG). When INHS goes to 0V, CSNS goes to 5.0 V. Overload on External Low Side MOSFET L L H x L L H x x L The 33981 is currently in Fault Mode. GLS is at 0 V and OCLS internal current source is off. The external resistance connected between OCLS and GND pin will pull OCLS pin to 0V. The fault is reset by a logic [0] at INLS for at least t RST(DIAG). H = High level L = Low level x = Don’t care 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES EN 5.0 V CONF 5.0 V INHS INLS OUT 0.0 V GLS 5.0 V FS 5.0 V 0.0 V TEMP 0.0 V 0.0 V TSD Temperature Hysteresis TSD Hysteresis OUT Thermal Shutdown on OUT High Side ON Thermal Shutdown on OUT High Side OFF Figure 12. Over-temperature on Output 33981 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES 5.0 V EN 5.0 V INLS 0.0 V t RST(DIAG) GLS 0.0 VLow Side OFF 5.0 V FS 0.0 V OCLS 0.0 V VDS_LS = VOCLS VDS_LS Case 1: Overload Removed Overload on Low Side Figure 13. Overload on Low Side Gate Drive, Case 1 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES 5.0 V EN INLS 0.0 V t RST(DIAG) GLS 0.0 V Low Side OFF FS 0.0 V OCLS VDS_LS 0.0 V VDS_LS = VOCLS Case 2: Low Side Still Overloaded Overload on Low Side Figure 14. Overload on Low Side Gate Drive, Case 2 33981 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES 5.0 V EN INHS 0.0 V t RST(DIAG) OUT 0.0 V 5.0 V FS 0.0 V VCL (CSNS) CSNS 0.0 V IOCH Fault Removed IOUT Over-current on High Side Figure 15. Over-current on Output Figure 16. High Side Over-current 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES Current in Motor Recirculation in Low Side Figure 17. Cross-Conduction with Low Side Over-temperature INHS TEMP OUT IOUT Figure 18. Over-temperature on OUT 33981 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES Figure 19. Maximum Operating Frequency for SR Capacitor of 4.7 nF 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 21 TYPICAL APPLICATIONS INTRODUCTION TYPICAL APPLICATIONS INTRODUCTION Figure 20 shows a typical application for the 33981. A brush DC motor is connected to the output. A low side gate driver is used for the freewheeling phase. Typical values for external capacitors and resistors are given. . VPWR VPWR VDD VDD 33981 VPWR SR Voltage regulator 2.2 nF 1.0 kΩ 10 kΩ I/O 10 kΩ I/O 10 kΩ I/O MCU 10 kΩ I/O 100 nF CBOOT 100 nF CONF FS INLS EN OUT DLS INHS A/D TEMP A/D CSNS GLS OCLS GND 1.0 kΩ 330 μF M 33 kΩ Figure 20. 33981 Typical Application Diagram EMC AND EMI RECOMMENDATIONS INTRODUCTION This section relates the EMC capability for 33981, High Frequency High-current High Side Switch. This device is a self-protected silicon switch used to replace electromechanical relays, fuses, and discrete circuits in power management applications. This section presents the key features of the device and its targeted applications. The automotive standard to measure conducted and radiated emissions is provided. Concrete measurements on the 33981 and improvements to reduce electromagnetic emission are described. DEVICE FEATURES This 33981 is a 4.0 mΩ self-protected, high side switch digitally controlled from a microcontroller (MCU) with extended diagnostics, able to drive DC motors up to 60 kHz. A bootstrap architecture has been used to provide fast transient gate voltage in order to reach 4.0 mΩ RDS(ON) maximum at room temperature. In parallel, a charge pump is implemented to offer continuous on-state capability. This dual current supply of the high side MOSFET allows a duty cycle from 5% to 100%. An external capacitor connected between pins SR and GND is used to control the slew rate at the output and, therefore, reduce electromagnetic perturbations. In standard configuration, the motor current recirculation is handled by an external freewheeling diode. To reduce global power dissipation, the freewheeling diode can be replaced by an external discrete MOSFET in low side configuration. The IC integrates a gate driver that controls and protects this external MOSFET in the event of short-circuit to battery. The product manages the cross conduction between the internal high side and the external low side when used in a half-bridge configuration. The two MOSFETs can be controlled independently when the CONF pin is at 0V. To eliminates fuses, the device is self-protected from severe short-circuits (100A typical) with an innovative over-current strategy. The 33981 has a current feedback for real-time monitoring of the load current through an MCU analog/digital converter to facilitate closed-loop operation for motor speed control. The 33981 has an analog thermal feedback that can be used by the MCU to monitor PC board temperature to optimize the motor control and to protect the entire electronic system. Therefore, an over-temperature shutdown feature protects the IC against high overload condition. 33981 22 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS EMC AND EMI RECOMMENDATIONS Figure 21 illustrates the typical application diagram. measurement method to measure both conducted and radiated emission. CONDUCTED EMISSION MEASUREMENT Conducted emission is the emission produced by the device on the battery cable. The test bench is described by CISPR25 (see Figure 23, Test Bench for Conducted Emission, on page 23). The Line Impedance Stabilization Network (LISN), also called Artificial Network (AN), in a given frequency range (150 kHz to 108 MHz) provides a specified load impedance for the measurement of disturbance voltages and isolates the equipment under test (EUT) from the supply in that frequency range. Figure 21. Typical Application Diagram APPLICATION O UT Im otor (10A/div) M C 33981 O FF M C 33981 O N C ontactto Ground Plan Power Supply + - 200 0+ 200m m Supply Engine cooling, air conditioning, and fuel pump are the targeted automotive applications for the 33981. Conventional solutions are designed with discrete components that are not optimized in terms of component board size, protection, and diagnostics. The 33981 is the right candidate to develop lighter and more compact units. DC motor speed adjustment allows optimization of energy consumption by reducing supply voltage, hence the mean voltage, applied to the motor. The commonly used control technique is pulse wide modulation (PWM) where the average voltage is proportional to the duty cycle. Most applications require a PWM frequency of at least 20 kHz to avoid audible noise. Figure 22 illustrates typical waveforms when switching the 33981 at 20 kHz with a duty cycle of 80%. The output voltage (OUT) and current in the motor (IMOTOR) waveforms are represented. LISN G round O ut BF G enerator Load EU T Non-Conductive Material H igh Si de Driver Si gnal Electricalto Optic Converter C oaxial Cable G round Pl ane in Copper 12V Pow erSupply Spectrum Analyzer Figure 23. Test Bench for Conducted Emission The EUT must operate under typical loading and other conditions just as it must in the vehicle so maximum emission state occurs. These operating conditions must be clearly defined in the test plan to ensure that both supplier and customer are performing identical tests. For the testing described in this application note, the out pin of the 33981 was connected to an inductive load (0.47 Ω + 1.0 μH) switching at 20 kHz with a duty cycle of 80%. The output current was 17 A continuous. The ground return of the EUT to the chassis must be as short as possible. The power supply is 13.5 V. RADIATED EMISSION MEASUREMENT Figure 22. Current and Voltage waveforms HOW TO MEASURE ELECTROMAGNETIC EMISSION ACCORDING TO THE CISPR25 One EMC standard in the automotive world (at system level) is the CISPR25, edited by the International Electrotechnical Commission. This standard describes the The radiated emission measurement consists of measuring the electromagnetic radiation produced by the equipment under test. CISPR 25 gives the schematic test bench described in Figure 24, Test Bench for Radiated Emission, on page 24. To measure radiated emission over all frequency ranges, several antenna types must be used: • 0.15 MHz to 30 MHz: 1.0 m vertical monopole in vertical polarization. • 30 MHz to 200 MHz: a biconical antenna used in vertical and horizontal polarization. • 200 MHz to 1,000 MHz: a log-periodic antenna used in vertical and horizontal polarization. 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 23 TYPICAL APPLICATIONS EMC AND EMI RECOMMENDATIONS No SR capacitor is used. Therefore, the obtained switching times are the maximum values. A capacitor of 1000 μF is connected between VPWR and GND. GND Out V PWR 33981 Figure 25. 33981 Initial Configuration Key 1 EUT (grounded locally if required in test plan) 8 Biconical antenna 2 Test harness – – 3 Load simulator (placement and ground connection) 10 High quality doubleshielded coaxial cable (50 Ω) 4 Power supply (location optional) 11 Bulkhead connector 5 Artificial Network (AN) 12 Measuring instrument 6 Ground plane (bonded to shielded enclosure) 13 RF absorber material 7 Low relative permittivity support (ερ ≤ 1.4) 14 Stimulation and monitoring system CONDUCTED MEASUREMENTS TEST SETUP To perform a conducted emission measurement in accordance with the CISPR 25 standard, the test bench in Figure 26, Conducted Emission Test Setup, on page 24 was developed. Power Supply LISN Measurement Point for Conducted Emission Figure 24. Test Bench for Radiated Emission EUT EMC RESULTS AND IMPROVEMENTS Non-Conductive Material The 33981 OUT is connected to an inductive load (0.47 Ω + 1.0mH) switching at 20 kHz with duty = 80%. The current in the load was 17 A continuous. Load (1.0 mH + 0.4 Ω) Optical PWM Signal BOARD SETUP The initial configuration of our 33981 board is represented in Figure 25. Figure 26. Conducted Emission Test Setup EFFECTS OF SOME PARAMETERS The conducted emissions level rise with the duty cycle. When the duty increases the di/dt on the VPWR line is higher. The device has to deliver more current and provide more energy. Figure 27 describes the effect of duty cycle increase on the VPWR current waveform. The conducted emission level rises with the output frequency. This is due to the increasing number of commutations. 33981 24 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS EMC AND EMI RECOMMENDATIONS RC Out FilterC2 di/dt di/dt BATV I(t) on Duty Cycle Increase RC In Filter PI Filter t Figure 27. VPWR Current HOW TO REDUCE ELECTROMAGNETIC EMISSION By adjusting the slew rate of the device during turn ON and turn OFF with SR capacitor, the electromagnetic emissions can be reduced. Conductive emission tests were performed (taking care of the board filtering and routing that have a big impact on EMC performances). An optimized solution was found by adding the following external components to the initial board: • PI filter on the VPWR: 2 x 3 μF and 3.5μH • RC IN filter between VPWR and GND: a 2.0 Ω resistor in series with a 100 nF capacitor • RC Out filter between OUT and GND: a 4.7 Ω resistor in series with a 100 nF capacitor • Capacitor C1 of 10 nF between VPWR and GND • Capacitor C2 of 10 nF between OUT and GND • Capacitor C3 of 10 nF between OUT and VPWR • Capacitor SR of 3.3 nF C3 C1 SR Figure 29. Enhanced Board The chart in Figure 30 shows the spectrum of the enhanced board and the initial board. The improvement is appreciatively 15 dB to 20 dB in the all frequency range. The enhanced board is now in accordance with the Class 3 limits of the CISPR25 standard for conducted emission. C 3 = 10 nF R C In Filter GND Figure 28. 33981 with Filter The EMC enhanced board with adapted value filter is represented in Figure 29. Inductive Load SR 3.3 nF 100 nF 33981 33891 4.7Ω C 2 = 10 nF 100 nF 2Ω 3000 µF Free Wheel Di ode R C Out Filter O UT C 1 = 10 nF PI i flter 3.5µH V BAT Figure 30. Conducted Emission Spectrum for 33981 RADIATED MEASUREMENTS This test was performed in order to evaluate the characteristic of the device relating to radiated emission. Measurements have been done in accordance with the 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 25 TYPICAL APPLICATIONS POWER DISSIPATION CISPR 25 standard as shown in Figure 31. The tested board was the EMC enhanced board. 1.5 m Length of Cable The results of these measurements are represented in Figure 32. The enhanced board is in accordance with the Class 3 limits of the CISPR25 standard for radiated emission. Anechoic Chamber CISPR Class 3 Limits LISN and Inductive Load 33981 Emission EUT Figure 32. Radiated Emission Spectrum for 33981 1 m Vertical Monopole Antenna Figure 31. Radiated Emission Test Set Up CONCLUSION This document explains how to measure conducted and radiated emission in accordance with the automotive CISPR25 standard. Measurements were performed on the 33981 in real application conditions, when driving an inductive load. An optimized filtering solution was put in place to have the tested system in accordance with the Class 3 limits. The same method can be used with other PC boards. POWER DISSIPATION INTRODUCTION This section relates to the power dissipation capability for 33981, High Frequency High-current High Side Switch. This device is a self-protected silicon switch used to replace electromechanical relays, fuses, and discrete circuits in power management applications. This section presents the key features of the device and its targeted applications. The theoretical calculations for power dissipation and die junction temperatures are determined in this document for inductive loads. A concrete example with DC motor driven by the 33981 is analyzed in section DC Motor 200 W. DEVICE FEATURES This 33981 is a 4.0 mΩ self-protected, high side switch digitally controlled from a microcontroller (MCU) with extended diagnostics, able to drive DC motors up to 60 kHz. A bootstrap architecture has been used to provide fast transient gate voltage in order to reach 4.0 mΩ RDS(ON) maximum at room temperature. In parallel, a charge pump is implemented to offer continuous on-state capability. This dual current supply of the high side MOSFET allows a duty cycle from 5% to 100%. An external capacitor connected between pins SR and GND is used to control the slew rate at the output and, therefore, reduce electromagnetic perturbations. In standard configuration, the motor current recirculation is handled by an external freewheeling diode. To reduce global power dissipation, the freewheeling diode can be replaced by an external discrete MOSFET in low side configuration. The IC integrates a gate driver that controls and protects this external MOSFET in the event of short-circuit to battery. The product manages the cross conduction between the internal high side and the external low side when used in a half-bridge configuration. The two MOSFETs can be controlled independently when the CONF pin is at 0 V. To eliminates fuses, the device is self-protected from severe short-circuits (100 A typical) with an innovative over-current strategy. The 33981 has a current feedback for real-time monitoring of the load current through an MCU analog/digital converter to facilitate closed-loop operation for motor speed control. The 33981 has an analog thermal feedback that can be used by the MCU to monitor PC board temperature to optimize the motor control and to protect the entire electronic system. Therefore, an over-temperature shutdown feature protects the IC against high overload condition. 33981 26 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS POWER DISSIPATION Figure 33 illustrates the typical application diagram. POWER DISSIPATION The 33981 power dissipation is the sum of two kinds of losses: • On-State losses when device is fully ON, • Switching losses when the device switches ON and OFF. The analysis that follows assumes an inductive load and assumes that the current is constant in the load. The case being considered in this paper is inductive load and the hypothesis is that the current is constant in the load. ON-STATE LOSSES APPLICATION Engine cooling, air conditioning, and fuel pump are the targeted automotive applications for the 33981. Conventional solutions are designed with discrete components that are not optimized in terms of component board size, protection, and diagnostics. The 33981 is the right candidate to develop lighter and more compact units. The adjustment of the DC motor speed allows optimizing of energy consumption. It is realized by chopping the supply voltage, hence the mean voltage, applied to the motor. The commonly used control technique is pulse wide modulation (PWM) where the average voltage is proportional to the duty cycle. Most applications require a PWM frequency of at least 20 kHz to avoid audible noise. Figure 34 illustrates typical waveforms when switching the 33981 at 20 kHz with a duty cycle of 80%. The output voltage (OUT) and current in the motor (IMOTOR) waveforms are represented. The mean on-state loss periods in the 33981 can be calculated as follows: Pon_state = a · RDS(ON) · IOUT2 where ‘a’ is the duty cycle. The critical parameter is the on resistance (RDS(ON)) that increases with temperature. The 33981 has a maximum RDS(ON) at 25ºC of 4.0 mΩ and its deviation with temperature is only 1.7 as shown in Figure 35. 7 6 R DSON m ( O hm ) Figure 33. Typical Application Diagram 5 4 3 2 1 0 -50 0 50 100 150 200 Tem perature (°C) Figure 35. RDS(ON) vs. Temperature SWITCHING LOSSES O UT Im otor (10A/div) M C 33981 O FF M C 33981 O N The mean switching losses in the 33981 can be calculated as follows: Pswitching = (tON . FREQ . VPWR . IOUT) / 2 + (tOFF . FREQ . VPWR . IOUT) / 2 where tON/tOFF is the turn on/off time. The switching time is a critical parameter. The 33981 provides adjustable slew rates through an external capacitor (SR) that slow down the rise and fall times to reduce the electromagnetic emissions. However, this adjustment will have an impact on power dissipation. Figure 36 gives the positive (SRR) and negative (SRF) slew rate versus different values of SR. This is illustrated in Figure 37. Figure 34. Current and Voltage waveforms 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 27 TYPICAL APPLICATIONS POWER DISSIPATION SRr(V/µs) 120 100 0 80 1 2.2 60 3.3 40 4.7 20 6.8 0 4.5 6 9 14 27 SRf(V/µs) Vbat the freewheeling diode can be replaced by an external lowside discrete MOSFET. The power dissipation during the recirculation phase is calculated as follows for the diode and the low-side MOSFET respectively: Pdiode = (1-a) . VF . IOUT where ‘a’ is the duty cycle Pmosfet_ls = (1-a) . RDS(ON)_ls . IOUT2 where RDS(ON)_ls is the on resistance of the low side. APPLICATIONS EXAMPLES 90 80 70 60 50 40 30 20 10 0 EXCEL TOOL 0 1 2.2 3.3 4.7 6.8 4.5 6 9 14 27 Vbat An excel tool has been created with all the above formulas to calculate the dissipated power and the junction temperature knowing the application conditions. An example of the interface is given in Figure 38. The parameters to enter concern the load, the high-side device, the recirculation, and the board. They are VPWR, DC current in the load (Imax for 100% of duty cycle), PWM frequency, 33981 RDS(ON) at 150ºC, SR capacitor, low-side RDS(ON) at 150ºC, ambient temperature, and thermal impedance. Figure 36. Positive and Negative Slew Rate vs. SR Capacitor IN PU TS Load Vpw r 12 V Im ax 20 A Frequency H igh Side D evice (H S) 20 KH z R DSON @ 150°C 6.8 m O hm SR C apacitor 0 nF Low Si de Characteristics R ecirculati on Figure 37. OUT switching vs. SR Capacitor JUNCTION TEMPERATURE The junction temperature of the 33981 can be calculated knowing the power dissipation and the thermal characteristics of the PC board with this formula: TJ = TA + (Pon_state + Pswitching). RTHJA where TJ is the junction temperature, TA the ambient temperature, and RTHJA the thermal impedance junction to ambient. RECIRCULATION PHASE R DSON @ 150°C R thja 20 m O hm 15°C /W B oard T am biant 85°C Figure 38. Excel Tool The calculations are done with the maximum RDS(ON) for the 33981 and the low side. The current is also considered constant in the load. The model taken for the VF of the diode is (0.4 + 0.01 . IOUT) Volts. The listed conditions in Figure 38 are the ones chosen for the entire document. In standard configuration, the motor current recirculation is handled by an external freewheeling diode. With the 33981, 33981 28 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS POWER DISSIPATION DC MOTOR 200W INFLUENCE OF SR CAPACITOR A concrete example is the 33981. A 200 W DC motor, a frequency of 20 kHz, and an ambient temperature of 85ºC are chosen. The 33981 is evaluated using the following board. The thermal impedance of the board is in the range of 15ºC/W. The SR capacitor value has an impact on these switching losses. Figure 41 illustrates the percentage of the switching losses versus the total power dissipation for the same load conditions as Figure 38. The higher the SR capacitor value, the higher the switching losses. They can be more than 50% of the total power dissipation in the 33981 with a 4.7 nF capacitor and is a basic applications trade-off. A compromise should be found between the power dissipation and the electromagnetic capability (EMC) performance. 6 P switch in g Pon Power Dissipation (W) 5 4 3 2 1 0 Figure 39. 33981 Evaluation Board 0 2 .2 3 .3 4 .7 C s r (n F ) POWER DISSIPATION Figure 41. Power Switching vs. SR Capacitor Figure 40 illustrates the power dissipation in the 33981. The conditions are listed in Figure 38. Maximum power dissipation of 3.1 W is obtained with a duty of 95%. M C 33981 Pow er D issipati on 3.5 P switching Figure 42 illustrates the power dissipation for the two recirculation approaches, diode or low side MOSFET. The power dissipation gain for the entire system when using the low side instead of the diode can reach up to 1.5 W with a duty cycle of 50%. Ptotal Total Board Power Dissipation 4.5 2.5 Power Dissipation (W) MC33981 Power Dissipation (W) Pon_state 3.0 RECIRCULATION PHASE 2.0 1.5 1.0 4.0 3.5 3.0 Pow erH S Pow erD iode 2.5 Pow erTotalBoard w ith D iode 2.0 Pow erLS 1.5 Pow erTotalBoard w ith LS 1.0 0.5 0.5 0.0 0 0 0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 Ratio PWM % Duty Cycle (%) Figure 40. Power Dissipation (Pon and Pswitching) vs. Duty Cycle Figure 42. Total Board Power Dissipation JUNCTION TEMPERATURE The junction temperature of the 33981 versus duty cycle for the condition listed in Figure 38, is given in Figure 43. The maximum obtained junction temperature is 132ºC with a duty 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 29 TYPICAL APPLICATIONS POWER DISSIPATION CONCLUSION cycle of 95%. This value is far from the 150ºC maximum guaranteed junction. Knowing the application conditions, this document explained how to calculate power dissipation during on-state and switching phases and the junction temperature for the 33981 when controlling a DC motor. A concrete example with a 200 W DC motor was given in section DC Motor 200 W. The same principle can be used for other DC motor and other environmental conditions. 140.00 Juncti on Tem perature (°C ) 120.00 100.00 80.00 60.00 40.00 20.00 0.00 0 10 20 30 40 50 60 70 80 90 100 D utycycle (%) Figure 43. Junction Temperature vs. Duty Cycle 33981 30 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOLDERING INFORMATION PACKAGING SOLDERING INFORMATION The 33981 is not designed for immersion soldering. The maximum peak temperature during the soldering process should not exceed 245oC. Pin soldering limit is for 10 seconds maximum duration. Exceeding these limits may cause malfunction or permanent damage to the device. PACKAGING DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using “98ARL10521D”. PNA SUFFIX 16-PIN PQFN PLASTIC PACKAGE 98ARL10521D ISSUE C 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 31 PACKAGING PACKAGING DIMENSIONS PNA SUFFIX 16-PIN PQFN PLASTIC PACKAGE 98ARL10521D ISSUE C 33981 32 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) ADDITIONAL DOCUMENTATION 33981 THERMAL ADDENDUM (REV 2.0) INTRODUCTION This thermal addendum is provided as a supplement to the 33981 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. 16-PIN PQFN PACKAGING AND THERMAL CONSIDERATIONS This package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RθJ21 and RθJ22, respectively. TJ1 TJ2 = RθJA11 RθJA12 RθJA21 RθJA22 . PNA SUFFIX 98ARL10521D 16-PIN PQFN 12 MM X 12 MM Note For package dimensions, refer to the 33981 device datasheet. P1 P2 The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. STANDARDS Table 7. Thermal Performance Comparison 1 = Power Chip, 2 = Logic Chip [°C/W] Thermal Resistance m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 ΡθJAmn(1), (2) 22 18 41 (2), (3) 7.0 4.0 27 ΡθJAmn(1), (4) 62 48 81 <1.0 0.0 1.0 ΡθJBmn ΡθJCmn (5) Notes 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, “infinite” heat sink attached to exposed pad. 0.2 mm spacing between PCB pads 0.2 mm spacing between PCB pads Note: Recommended via diameter is 0.5 mm. PTH (plated through hole) via must be plugged / filled with epoxy or solder mask in order to minimize void formation and to avoid any solder wicking into the via. Figure 44. Surface mount for power PQFN with exposed pads 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 33 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) Transparent Top View CSNS TEMP EN INHS FS INLS CONF OCLS DLS GLS SR CBOOT 4 5 6 7 8 9 1 2 3 10 11 12 GND 13 A VPWR 14 15 16 OUT OUT 33981 Pin Connections 16-Pin PQFN 0.90 mm Pitch 12.0mm x 12.0mm Body with exposed pads Figure 45. Thermal Test Board Device on Thermal Test Board Material: Outline: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Area A: Cu heat-spreading areas on board surface Ambient Conditions: Natural convection, still air Table 8. Thermal Resistance Performance Thermal Resistance ΡθJAmn Area A 1 = Power Chip, 2 = Logic Chip (°C/W) (mm2) m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 0 66 51 84 300 47 37 73 600 43 34 70 RθJA is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed. 33981 34 Analog Integrated Circuit Device Data Freescale Semiconductor Thermal Resistance [ºC/W] ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) 90 80 70 60 50 40 30 20 10 0 x 0 RθJA11 RθJA22 RθJA12 = RθJA21 300 600 Heat spreading area A [mm²] Figure 46. Device on Thermal Test Board RθJA Thermal Resistance [ºC/W] 100 10 1 0.1 1.00E-03 x 1.00E-02 RθJA11 RθJA22 RθJA12 = RθJA21 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 47. Transient Thermal Resistance RθJA, 1 W Step response,Device on Thermal Test Board Area A = 600(mm2) 33981 Analog Integrated Circuit Device Data Freescale Semiconductor 35 REVISION HISTORY REVISION HISTORY Revision Date Description of Changes 3.0 1/2006 • • • • Implemented Revision History page Made content updates and changes Converted to Freescale format Added Thermal Addendum 4.0 3/2006 • • Made minor content changes to pages 6 and 7. Updated to Product Preview status 5.0 5/2006 • • • Changed Part Number from PC33981PNA to MC33981BPNA (page 1) Changed Electrical Characteristics, Maximum Ratings, Table 2, Maximum Ratings, Electrical Ratings, OCLS Voltage, from “-5.0 to 5.0” to “-5.0 to 7.0” (page 4). Changed Electrical Characteristics, Static Electrical Characteristics, Table 3, Static Electrical Characteristics, Low Side Gate Driver (VPWR, VGLS, VOCLS), Low-Side Overload Detection Level versus Low-Side Drain Voltage Minimum, from “-75” to “-50” and Maximum from “+75” to “+50” (page 6). Changed Electrical Characteristics, Dynamic Electrical Characteristics, Table 4, Dynamic Electrical Characteristics, Control Interface and Power Output Timing (CBOOT, VPWR), Input Switching Frequency, Minimum from “20” to “-” and Typical from “-” to “20” (page 7). Updated to Advanced status 6.0 5/2007 • • • • Changed CSNS Input Clamp Current in MAXIMUM RATINGS Changed Figure 11, Reverse Battery Protection Removed unnecessary line in Figure 14, Overload on Low Side Gate Drive, Case 2 Corrected label in Figure 28, 33981 with Filter 7.0 10/2008 • • • Updated Freescale form and style Minor text corrections. Added Current Sense Leakage(9) 8.0 6/2009 • Corrected Reference to Figure 15 on Page 13. • • 33981 36 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. MC33981 Rev. 8.0 6/2009