SEMICONDUCTOR TECHNICAL DATA &-&$*! #* %#, ()$ +) (%) #, ( #*" &$ (%* %'+*) % +*'+*) ** &%%, (*#%! The MC74LCX16501 is a high performance, non–inverting 18–bit universal bus transceiver operating from a 2.7 to 3.6V supply. This part is not byte controlled; it is “18–bit” controlled. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX16501 inputs to be safely driven from 5V devices. The MC74LCX16501 is suitable for memory address driving and all TTL level bus oriented transceiver applications. LOW–VOLTAGE CMOS 18–BIT UNIVERSAL BUS TRANSCEIVER Data flow in each direction is controlled by Output Enable (OEAB, OEBA), Latch Enable (LEAB, LEBA) and Clock inputs (CAB, CBA). When LEAB is HIGH, the A–to–B dataflow is transparent. When LEAB is LOW, and CAB is held at LOW or HIGH, the data A is latched; on the LOW–to–HIGH transition of CAB the A–data is stored in the latch/flip–flop. The outputs are active when OEAB is HIGH. When OEAB is LOW the B–outputs are in 3–state. Similarly, the LEBA, OEBA and CBA control the B–to–A dataflow. Please note that the output enables are complementary; OEAB is active HIGH, OEBA is active LOW. • • • • • • • • • Designed for 2.7 to 3.6V VCC Operation DT SUFFIX 56–LEAD PLASTIC TSSOP PACKAGE CASE 1202–01 6ns tpd Maximum 5V Tolerant — Interface Capability With 5V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0V LVTTL Compatible LVCMOS Compatible 24mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (20µA) Substantially Reduces System Power Requirements • Latchup Performance Exceeds 500mA • ESD Performance: Human Body Model >2000V; Machine Model >200V PIN NAMES Pins Function OEAB, OEBA CAB, CBA LEAB, LEBA A0–A17 B0–B17 Output Enable Inputs Clock Pulse Inputs Latch Enable Inputs Side A Inputs/Outputs Side B Inputs/Outputs 3/97 Motorola, Inc. 1997 1 REV 1 MC74LCX16501 OEAB 1 56 GND LEAB 2 55 CAB A0 3 GND 4 54 B0 53 GND A1 5 52 B1 A2 6 51 B2 VCC 7 50 VCC OEAB A3 8 49 B3 CBA A4 9 48 B4 LEBA A5 10 47 B5 GND 11 46 GND OEBA A6 12 45 B6 CAB A7 13 44 B7 LEAB A8 14 43 B8 A9 15 42 B9 A10 16 41 B10 A11 17 40 B11 GND 18 39 GND A12 19 38 B12 A13 20 37 B13 A14 21 36 B14 VCC 22 35 VCC A15 23 34 B15 A16 24 33 B16 GND 25 32 GND A17 26 31 B17 OEBA 27 30 CBA LEBA 28 29 GND A0 1 30 28 27 55 2 C1 1D 1D 54 3 C1 C1 1D 1D B0 To 17 Other Channels Figure 1. 56-Lead Pinout (Top View) MOTOROLA C1 Figure 2. Logic Diagram 2 LCX DATA BR1339 — REV 3 MC74LCX16501 FUNCTION TABLE Data Ports Inputs OEAB OEBA L H LEAB LEBA CAB H or L L H L H L ↑ CBA Bn Input Input H or L X X Hold Data; A and B Outputs Disabled ↑ l h l h Clock A and/or B Data; A and B Outputs Disabled Input Output H L X H X H or L X* X QA ↑ X* l h L H Clock A Data to B Bus; Store A Data X X* L H L H A Data to B Bus; (Transparent) Output Input X* H or L QB X Hold and Display A Data X* ↑ L H l h Clock B Data to A Bus; Store B Data X* X L H L H B Data to A Bus; (Transparent) Output Output QB QA L X L X H L L L Operating Mode An H or L H or L Hold and Display B Data Stored A Data to B Bus; Stored B Data to A Bus H = High Voltage Level; L = Low Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable or Clock Low–to–High Transition; l = Low Voltage Level One Setup Time Prior to the Latch Enable or Clock Low–to–High Transition; X = Don’t Care; ↑ = Low–to–High Clock Transition; QA = A input storage register; QB = B input storage register; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs. LCX DATA BR1339 — REV 3 3 MOTOROLA MC74LCX16501 BUS A BUS A BUS B Real Time Transfer – Bus A to Bus B BUS B Real Time Transfer – Bus B to Bus A OEAB OEBA CAB CBA LEAB LEBA OEAB OEBA CAB CBA LEAB LEBA L L X X X H H H X X H X BUS A BUS B BUS A BUS B Transfer A Stored Data to Bus B or B Stored Data to Bus A or Both at the Same Time Store Data from Bus A, Bus B or Bus A and Bus B OEAB OEBA CAB CBA LEAB LEBA OEAB OEBA CAB CBA LEAB LEBA X L L H X H ↑ X X X ↑ X L X L X L L H L H H L L ↑ X H or L X ↑ H or L L X L X L L Store Bus A in Both Registers or Store Bus B in Both Registers BUS B BUS A BUS A BUS B Isolation OEAB OEBA CAB CBA LEAB LEBA OEAB OEBA CAB CBA LEAB LEBA H L H L X X X X L L L L L H H or L H or L L L Figure 3. Bus Applications MOTOROLA 4 LCX DATA BR1339 — REV 3 MC74LCX16501 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter VCC DC Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Condition Unit –0.5 to +7.0 V –0.5 ≤ VI ≤ +7.0 V –0.5 ≤ VO ≤ +7.0 Output in 3–State V –0.5 ≤ VO ≤ VCC + 0.5 Note 1. V IIK DC Input Diode Current –50 VI < GND mA IOK DC Output Diode Current –50 VO < GND mA +50 VO > VCC mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range –65 to +150 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. 1. Output in HIGH or LOW State. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Operating Data Retention Only Min Typ Max Unit 2.0 1.5 3.3 3.3 3.6 3.6 V 0 5.5 V 0 0 VCC 5.5 V VCC Supply Voltage VI Input Voltage VO Output Voltage IOH HIGH Level Output Current, VCC = 3.0V – 3.6V –24 mA IOL LOW Level Output Current, VCC = 3.0V – 3.6V 24 mA IOH HIGH Level Output Current, VCC = 2.7V – 3.0V –12 mA IOL LOW Level Output Current, VCC = 2.7V – 3.0V 12 mA TA Operating Free–Air Temperature ∆t/∆V Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V, VCC = 3.0V (HIGH or LOW State) (3–State) –40 +85 °C 0 10 ns/V DC ELECTRICAL CHARACTERISTICS TA = –40°C to +85°C Symbol Characteristic VIH HIGH Level Input Voltage (Note 2.) VIL LOW Level Input Voltage (Note 2.) VOH HIGH Level Output Voltage VOL LOW Level Output Voltage Condition Min 2.7V ≤ VCC ≤ 3.6V 2.0 2.7V ≤ VCC ≤ 3.6V Max V 0.8 2.7V ≤ VCC ≤ 3.6V; IOH = –100µA VCC – 0.2 VCC = 2.7V; IOH = –12mA 2.2 VCC = 3.0V; IOH = –18mA 2.4 VCC = 3.0V; IOH = –24mA 2.2 Unit V V 2.7V ≤ VCC ≤ 3.6V; IOL = 100µA 0.2 VCC = 2.7V; IOL= 12mA 0.4 VCC = 3.0V; IOL = 16mA 0.4 VCC = 3.0V; IOL = 24mA 0.55 V 2. These values of VI are used to test DC electrical characteristics only. LCX DATA BR1339 — REV 3 5 MOTOROLA MC74LCX16501 DC ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to +85°C Symbol Characteristic Condition Min Max Unit II Input Leakage Current 2.7V ≤ VCC ≤ 3.6V; 0V ≤ VI ≤ 5.5V ±5.0 µA IOZ 3–State Output Current 2.7 ≤ VCC ≤ 3.6V; 0V ≤ VO ≤ 5.5V; VI = VIH or V IL ±5.0 µA IOFF Power–Off Leakage Current VCC = 0V; VI or VO = 5.5V 10 µA ICC Quiescent Supply Current 2.7 ≤ VCC ≤ 3.6V; VI = GND or VCC 20 µA 2.7 ≤ VCC ≤ 3.6V; 3.6 ≤ VI or VO ≤ 5.5V ±20 µA 2.7 ≤ VCC ≤ 3.6V; VIH = VCC – 0.6V 500 µA ∆ICC Increase in ICC per Input AC CHARACTERISTICS (Note 3.; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω) Limits TA = –40°C to +85°C VCC = 3.0V to 3.6V Symbol Parameter Waveform Min Max VCC = 2.7V Min Max Unit fmax Maximum Clock Frequency 3 170 MHz tPHL tPLH Propagation Delay Input to Output 1 1.5 1.5 6.0 6.0 1.5 1.5 7.0 7.0 ns tPHL tPLH Propagation Delay Clock to Output 3 1.5 1.5 6.7 6.7 1.5 1.5 8.0 8.0 ns tPHL tPLH Propagation Delay LExx to Output 4 1.5 1.5 7.0 7.0 1.5 1.5 8.0 8.0 ns tPZH tPZL Output Enable Time to High and Low Level 2 1.5 1.5 7.2 7.2 1.5 1.5 8.2 8.2 ns tPHZ tPLZ Output Disable Time From High and Low Level 2 1.5 1.5 7.0 7.0 1.5 1.5 8.0 8.0 ns ts Setup Time 3,4 2.5 2.5 ns th Hold Time 3,4 1.5 1.5 ns tw Pulse Width Time 3,4 3.0 3.0 ns tOSHL tOSLH Output–to–Output Skew (Note 4.) 1.0 1.0 ns 3. These AC parameters are preliminary and may be modified prior to release. 4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter guaranteed by design. DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition Min Typ Max Unit VOLP Dynamic LOW Peak Voltage (Note 5.) VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V VOLV Dynamic LOW Valley Voltage (Note 5.) VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V 5. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is measured in the LOW state. MOTOROLA 6 LCX DATA BR1339 — REV 3 MC74LCX16501 CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit CIN Input Capacitance VCC = 3.3V, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance 10MHz, VCC = 3.3V, VI = 0V or VCC 20 pF 2.7V An, Bn 1.5V 0V tPLH, tPHL VOH Bn, An 1.5V VOL WAVEFORM 1 – An to Bn PROPAGATION DELAYS tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns 2.7V OEBA 1.5V 1.5V 0V OEAB tPZH tPHZ VOH – 0.3V 1.5V An, Bn ≈ 0V tPZL An, Bn tPLZ ≈ 3.0V 1.5V VOL + 0.3V WAVEFORM 2 – OEBA/OEAB to An/Bn OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns Figure 4. AC Waveforms LCX DATA BR1339 — REV 3 7 MOTOROLA MC74LCX16501 2.7V An, Bn 1.5V 0V ts th 2.7V CAB, CBA tw 1.5V 1.5V 0V fmax tPLH, tPHL VOH Bn, An 1.5V VOL WAVEFORM 3 – CLOCK to Bn/An PROPAGATION DELAYS, CLOCK MINIMUM PULSE WIDTH, An/Bn to CLOCK SETUP AND HOLD TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted 2.7V An, Bn 1.5V 0V ts th 2.7V LEAB, LEBA tw 1.5V 1.5V 0V tPLH, tPHL VOH Bn, An 1.5V VOL WAVEFORM 4 – LExx to An, Bn PROPAGATION DELAYS, LExx MINIMUM PULSE WIDTH, An, Bn to LExx SETUP AND HOLD TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted tw NEGATIVE PULSE 1.5V 1.5V POSITIVE PULSE 1.5V 1.5V tw WAVEFORM 5 – INPUT PULSE DEFINITION tR = tF = 2.5ns, 10% to 90% of 0V to 2.7V Figure 5. AC Waveforms (continued) MOTOROLA 8 LCX DATA BR1339 — REV 3 MC74LCX16501 VCC PULSE GENERATOR R1 DUT CL RT TEST 6V OPEN GND RL SWITCH tPLH, tPHL Open tPZL, tPLZ 6V Open Collector/Drain tPLH and tPHL 6V tPZH, tPHZ GND CL = 50pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 6. Test Circuit LCX DATA BR1339 — REV 3 9 MOTOROLA MC74LCX16501 OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 1202–01 ISSUE A 56X K REF 0.12 (0.005) M T U S V K K1 S T U S J J1 29 0.254 (0.010) M 56 SECTION N–N B –U– L ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ 1 N 28 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. A –V– PIN 1 IDENT. N F DETAIL E D C 0.25 (0.010) –W– 0.076 (0.003) –T– SEATING PLANE M DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 13.90 14.10 6.00 6.20 ––– 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.12 ––– 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.547 0.555 0.236 0.244 ––– 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.005 ––– 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_ H G Motorola reserves the right to make changes without further notice to any products herein. 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