SEMICONDUCTOR TECHNICAL DATA
!'!$ %$ $ (" "!"
!' #!% !%$
$$ ! &#$ The MC74LVQ574 is a high performance, non–inverting octal D–type
flip–flop operating from a 2.7 to 3.6V supply. The MC74LVQ574 is
suitable for TTL level bus oriented applications where a memory element
is required.
Current drive capability is 12mA at the outputs. The MC74LVQ574
consists of 8 edge–triggered flip–flops with individual D–type inputs and
3–state true outputs. The buffered clock and buffered Output Enable (OE)
are common to all flip–flops. The eight flip–flops will store the state of
individual D inputs that meet the setup and hold time requirements on the
LOW–to–HIGH Clock (CP) transition. With the OE LOW, the contents of
the eight flip–flops are available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. The OE input level does not affect
the operation of the flip–flops.
LVQ
LOW–VOLTAGE CMOS
OCTAL D–TYPE FLIP–FLOP
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
20
• Designed for 2.7 to 3.6V VCC Operation – Ideal for Low Power/Low
Noise Applications
• Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
• Guaranteed Skew Specifications
1
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
20
• Guaranteed Incident Wave Switching into 75Ω
• Low Static Supply Current (10µA) Substantially Reduces System Power
1
Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V
20
1
20
Pinout: 20–Lead (Top View)
1
VCC
O0
O1
O2
O3
O4
O5
O6
O7
CP
20
19
18
17
16
15
14
13
12
11
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
PIN NAMES
1
2
3
4
5
6
7
8
9
10
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
Pins
Function
OE
CP
D0–D7
O0–O7
Output Enable Input
Clock Pulse Input
Data Inputs
3–State Outputs
11/95
Motorola, Inc. 1995
1
REV 0
MC74LVQ574
LOGIC DIAGRAM
OE
CP
1
11
2
D0
O0
Q
D
3
D1
18
nCP
O1
Q
D
4
D2
17
nCP
O2
Q
D
5
D3
16
nCP
O3
Q
D
6
D4
15
nCP
O4
Q
D
7
D5
14
nCP
O5
Q
D
8
D6
13
nCP
O6
Q
D
9
D7
INPUTS
19
nCP
12
nCP
Q
O7
D
INTERNAL
LATCHES
OUTPUTS
OE
CP
Dn
Q
On
OPERATING MODE
L
L
↑
↑
l
h
L
H
L
H
Load and Read Register
L
↑
X
NC
NC
Hold and Read Register
H
↑
X
NC
Z
Hold and Disable Outputs
H
H
↑
↑
l
h
L
H
Z
Z
Load Internal Register and Disable Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low Voltage Level; l = Low
Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; NC = No Change; X = High or Low Voltage Level and Transitions
are Acceptable; Z = High Impedance State; ↑ = Low–to–High Transition; ↑ = Not a Low–to–High Transition; For ICC Reasons DO NOT FLOAT
Inputs
MOTOROLA
2
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MC74LVQ574
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
VCC
DC Supply Voltage
VI
Value
Condition
Unit
–0.5 to +7.0
V
DC Input Voltage
–0.5 ≤ VI ≤ VCC + 0.5V
V
VO
DC Output Voltage
–0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State
V
IIK
DC Input Diode Current
–20
VI = –0.5V
mA
+20
VI = VCC + 0.5V
mA
–20
VO = –0.5V
mA
+20
VI = VCC + 0.5V
mA
IOK
DC Output Diode Current
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current
±400
mA
IGND
DC Ground Current
±400
mA
TSTG
Storage Temperature Range
–65 to +150
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
TA
Operating Free–Air Temperature
∆V/∆t
Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V, VCC = 3.0V
Min
Typ
Max
Unit
2.0
3.3
3.6
V
0
VCC
V
0
VCC
V
–40
+85
°C
0
125
mV/ns
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
Symbol
Characteristic
Condition
Min
2.0
VIH
HIGH Level Input Voltage (Note 1)
2.7V ≤ VCC ≤ 3.6V,
VO = 0.1V or VCC – 0.1V
VIL
LOW Level Input Voltage (Note 1)
2.7V ≤ VCC ≤ 3.6V,
VO = 0.1V or VCC – 0.1V
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
II
Input Leakage Current
IOZ
Maximum 3–State Leakage Current
IOLD
Minimum Dynamic Output Current (Note 2)
IOHD
ICC
Quiescent Supply Current
Max
V
0.8
2.7V ≤ VCC ≤ 3.6V; IOH = –50µA
VCC – 0.1
VCC = 2.7V; IOH = –12mA
2.2
VCC = 3.0V; IOH = –12mA
2.48
Unit
V
V
2.7V ≤ VCC ≤ 3.6V; IOL = 50µA
0.1
2.7V ≤ VCC ≤ 3.6V; IOL= 12mA
0.4
2.7V ≤ VCC ≤3.6V; VI= VCC, GND
±1.0
µA
VI(OE) = VIL, VIH; VI, VO= VCC, GND
±2.5
µA
VCC = 3.6V; VOLD = 0.8V Max
36
mA
VCC = 3.6V; VOHD = 2.0V Min
–25
mA
2.7V ≤ VCC ≤3.6V; VI = VCC, GND
10
µA
V
1. These values of VI are used to test DC electrical characteristics only. Functional test should use VIH ≥ 2.4V, VIL ≤ 0.5V.
2. Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed. Maximum test
duration is 2ms, one output loaded at a time.
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3
MOTOROLA
MC74LVQ574
DYNAMIC SWITCHING CHARACTERISTICS (VCC = 3.3V)
TA = +25°C
Symbol
Characteristic
Condition
VOLP
Dynamic LOW Peak Voltage (Note 1)
VOLV
Dynamic LOW Valley Voltage (Note 1)
VIHD
VILD
Min
Typ
Max
Unit
CL = 50pF, VIH = 3.3V, VIL = 0V
0.6
1.0
V
CL = 50pF, VIH = 3.3V, VIL = 0V
–0.5
–1.0
V
High Level Dynamic Input Voltage
(Note 2)
Input–Under–Test Switching 0V to Threshold,
f=1MHz
1.5
2.0
V
Low Level Dynamic Input Voltage
(Note 2)
Input–Under–Test Switching 3.3V to Threshold,
f=1MHz
1.5
0.8
V
1. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW. The remaining output is measured in the
LOW state.
2. Number of data inputs is defined as “n” switching, “n–1” inputs switching 0V to 3.3V.
AC CHARACTERISTICS (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω)
Limits
TA = +25°C
VCC = 3.0V to 3.6V
Symbol
Parameter
TA = –40°C to +85°C
VCC = 2.7V
VCC = 3.0V to 3.6V
VCC = 2.7V
Min
Typ
Max
Min
Typ
Max
Min
Max
Max
Unit
tPLH
tPHL
Propagation Delay
CP to On
2.5
2.5
10.5
10.0
13.0
13.0
2.5
2.5
11.5
11.0
14.0
13.5
2.5
2.5
14.0
13.5
16.0
14.0
ns
tPZH
tPZL
Output Enable Time
to High and Low Level
2.5
2.5
7.5
7.0
9.5
9.5
2.5
2.5
8.5
8.5
10.5
10.5
2.5
2.5
10.5
10.0
11.5
11.0
ns
tPHZ
tPLZ
Output Disable Time
From High and Low Level
1.0
1.0
9.5
6.0
12.0
9.0
1.0
1.0
10.0
7.0
13.0
9.5
1.0
1.0
12.5
10.0
13.5
10.5
ns
tOSHL
tOSLH
Output–to–Output Skew
(Note 1)
1.0
1.0
1.5
1.5
1.0
1.0
1.5
1.5
1.5
1.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
AC OPERATING REQUIREMENTS (tR = tF = 2.5ns; CL = 50pF; RL = 500Ω)
Limits
TA = +25°C
Symbol
Parameter
TA = –40°C to +85°C
VCC = 3.0V to 3.6V
VCC = 2.7V
VCC = 3.0V to 3.6V
VCC = 2.7V
Min
Min
Min
Min
Unit
ts
Setup TIme, HIGH or LOW Dn to CP
3.0
4.0
3.0
4.5
ns
th
Hold TIme, HIGH or LOW Dn to CP
1.5
1.5
1.5
1.5
ns
tw
CP Pulse Width, HIGH or LOW
4.0
5.0
4.0
6.0
ns
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CPD
Power Dissipation Capacitance
CIN
Input Capacitance
MOTOROLA
Condition
Typical
Unit
10MHz, VCC = 3.3V, VI = 0V or VCC
30
pF
VCC = Open, VI = 0V or VCC
4.5
pF
4
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MC74LVQ574
VCC
VCC
Dn
50% VCC
50% VCC
50% VCC
OE
50% VCC
0V
0V
tPZH
th
ts
tPHZ
VCC
VOH – 0.3V
VCC
CP
50% VCC
On
50% VCC
≈ 0V
0V
fmax
tPLH, tPHL
tPZL
VOH
On
tPLZ
≈ 3.0V
50% VCC
On
50% VCC
VOL + 0.3V
GND
VOL
WAVEFORM 2 – OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
WAVEFORM 1 – PROPAGATION DELAYS, SETUP AND HOLD TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
VCC
CP
50% VCC
50% VCC
tw
0V
VCC
tw
50% VCC
CP
50% VCC
0V
WAVEFORM 3 – PULSE WIDTH
tR = tF = 2.5ns (or fast as required) from 10% to 90%;
Output requirements: VOL ≤ 0.8V, VOH ≥ 2.0V
Figure 1. AC Waveforms
VCC
2 • VCC
PULSE
GENERATOR
R1
DUT
CL
RT
TEST
OPEN
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
2 • VCC
Open Collector/Drain tPLH and tPHL
2 • VCC
tPZH, tPHZ
Open
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 2. Test Circuit
ECLinPS and ECLinPS Lite
DL140 — Rev 3
5
MOTOROLA
MC74LVQ574
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–A
–
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
11
1
–B
–
P 10 PL
A
B
0.010 (0.25)
B
M
M
10
D
20 PL
J
0.010 (0.25)
M
T
S
S
DIM
A
B
C
D
F
G
J
K
M
P
R
F
R X 45°
C
–T
G
18 PL
M
SEATING
–
PLANE
K
MILLIMETERS
MIN
MAX
12.65 12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05 10.55
0.25
0.75
INCHES
MIN
MAX
0.499 0.510
0.292 0.299
0.093 0.104
0.014 0.019
0.020 0.035
0.050 BSC
0.010 0.012
0.004 0.009
0°
7°
0.395 0.415
0.010 0.029
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
20
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5 THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
M_
L
10
1
DETAIL P
Z
D
e
VIEW P
A
c
A1
b
0.13 (0.005)
MOTOROLA
M
0.10 (0.004)
6
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.032
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MC74LVQ574
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
ISSUE B
20X
K REF
0.12 (0.005)
T U
M
V
S
S
0.25 (0.010)
N
20
L/2
11
M
N
B
L
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
F
PIN 1
IDENT
1
10
DETAIL E
K
–U–
A
–V–
0.20 (0.008)
M
J
T U
S
NOTES:
13 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 CONTROLLING DIMENSION: MILLIMETER.
15 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
16 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
17 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR INTRUSION
SHALL NOT REDUCE DIMENSION K BY MORE
THAN 0.07 (0.002) AT LEAST MATERIAL
CONDITION.
18 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
19 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
K1
SECTION N–N
0.076 (0.003)
–T–
–W–
C
SEATING
PLANE
D
G
DETAIL E
H
20X
0.15 (0.006) T U
K REF
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
K
K1
2X
L/2
20
11
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
NOTES:
6 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
7 CONTROLLING DIMENSION: MILLIMETER.
8 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
9 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
10 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
11 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
12 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
M
A
–V–
N
F
DETAIL E
–W–
C
D
G
INCHES
MIN
MAX
0.278
0.288
0.205
0.212
0.068
0.078
0.002
0.008
0.024
0.037
0.026 BSC
0.023
0.030
0.003
0.008
0.003
0.006
0.010
0.015
0.010
0.013
0.301
0.311
0_
8_
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
0.10 (0.004)
S
MILLIMETERS
MIN
MAX
7.07
7.33
5.20
5.38
1.73
1.99
0.05
0.21
0.63
0.95
0.65 BSC
0.59
0.75
0.09
0.20
0.09
0.16
0.25
0.38
0.25
0.33
7.65
7.90
0_
8_
H
DETAIL E
0.100 (0.004)
–T– SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
1.20
–––
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
0.047
–––
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PLANE
ECLinPS and ECLinPS Lite
DL140 — Rev 3
7
MOTOROLA
MC74LVQ574
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: [email protected] –TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
◊
MOTOROLA
8
*MC74LVQ574/D*
MC74LVQ574/D
ECLinPS and ECLinPS Lite
DL140 — Rev 3