MCM28F256ACH MCM28F256ACH 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers Literature Number: SNOS764A July 1995 MCM28F256ACH 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers General Description Features The MCM28F256ACH is a 268,435,456-bit flash memory module, organized as 16 pages with 16,777,216 bytes (8,388,608 words) per page. Utilizing Intel’s FlashFile TM Memory and National’s SCANTM I/O buffers, the MCM28F256ACH offers several revolutionary features, including a user-configurable x8/x16 architecture, selective block locking, on-board write buffers, pipelined command execution and boundary scan test capability. Several power reduction features are also incorporated, including Automatic Power Savings (APS), which puts the module into a low current state when it is being accessed by a slowed or stopped CPU. The MCM28F256ACH includes sixteen 28F016SA flash memories, decoding logic and IEEE 1149.1 compliant I/O buffers. The module is offered in a 68-lead, hermetic package. Both through-hole and surface mount lead configurations are available. Y Y Y Y Y et Y e Y Read access time of 140 ns over the industrial temperature range (160 ns over the military temperature range) Utilizes Intel’s FlashFile architecture with 512 independently lockable blocks (16 pages with 32 blocks per page) Choice of x8 or x16 architecture (user-configurable) Pipelined command execution Automated write and erase capability can be executed simultaneously in all 16 pages, greatly improving average write/erase cycle times National’s lEEE 1149.1 compliant SCAN I/O buffers simplify the integration of design and test TTL compatible inputs Low noise, TRl-STATEÉ outputs drive 50X transmission line to TTL levels (75X transmission line over military temperature range) Hermetically sealed, integral substrate package DIP and surface mount packaging available Y Y Y O bs ol Connection Diagram Pin Names Description A0 A1 –A24 DQ0 –DQ7 DQ8 –DQ15 CE RP OE WE RY/BY WP BYTE VPP VCC GND NC Byte-Select Address Input Word-Select Address Inputs Low-Byte Data I/O Bus High-Byte Data I/O Bus Chip Enable Input (Active LOW) Reset/Power-Down Input (Active LOW) Output Enable Input (Active LOW) Write Enable Input (Active LOW) Ready/Busy Output Write Protect Input (Active LOW) Byte Enable Input (Active LOW) Erase/Write Power Supply Device Power Supply Ground No Connection TL/Z/12436 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. SCANTM is a trademark of National Semiconductor Corporation. FlashFileTM is a trademark of Intel Corporation C1995 National Semiconductor Corporation TL/Z/12436 RRD-B30M115/Printed in U. S. A. MCM28F256ACH 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers PRELIMINARY e Block Diagram Each page of memory has three types of status registers and a RY/BY output to provide information on the progress of the requested operation. The Compatible Status Register (CSR) is 100% compatible with status register used in previous FlashFile memory devices. The Global Status Register (GSR) informs the system of command queue status, sector buffer status and WSM status. Block Status Registers (BSR) provide block-specific status information such as the block lock bit status. A choice of four different RY/BY configurations can be selected via special CUI commands: levelmode (default), pulse-on-write, pulse-on-erase, or disabled. O bs ol The MCM28F256ACH is a 268,435,456-bit (256-Mbit) flash memory module, organized as 16 pages with 16,777,216 bytes (8,388,608 words) per page. The module is segmented into 512 independently lockable blocks (32 blocks per page). A Command User Interface (CUI) serves as the interface between the system controller and each page of internal memory. Automation of the byte/word write and block erase functions allow these commands to be executed using a two-write command sequence to the CUI. An internal Write State Machine (WSM) automatically executes the algorithms, timings and verifications necessary for the write and erase operations, thereby relieving the system controller of these tasks. et TL/Z/12436 – 2 Functional Description 2 Functional Description (Continued) The BYTE input allows either x8 or x16 read/writes to the MCM28F256ACH. With BYTE at logic low the device operates in the 8-bit mode. Address A0 selects either the low or high byte, and the high-byte data bus (DQ8 –DQ15) floats to TRI-STATE. With BYTE at logic high the device is in the 16bit mode of operation. In this case A1 becomes the lowest order address, A0 is not used (don’t care) and data is input and output on all 16 bits of the data bus (DQ0 –DQ15). The MCM28F256ACH offers several low power modes of operation. Standby mode is entered when the module is deselected (CE at logic high). The typical ICC current draw in this mode is 20 mA. If a WSM is processing a command when the module is deselected, the operation continues and power consumption remains at the non-standby level until the command has completed. With RP at logic low, enters deep power-down mode. The typical ICC current draw in this mode is 4 mA. Bringing RP low interrupts any current or pending commands and resets all status registers, CUI and WSM. The contents of any memory location being written or block being erased will no longer be valid. The Sleep command puts a page of memory in sleep mode, which reduces the power consumption for that page of memory to deep power-down levels. The sleep command allows any current or pending commands to execute before going into sleep mode. Automatic Power Savings (APS) is a feature which puts the module into a low current state when it is being accessed by a slowed or stopped CPU. After data is read from the memory array, power reduction control circuitry reduces the typical ICC current draw to 20 mA until a new memory location is accessed. To get the lowest possible power consumption in all modes, input pins should be held at VCC or GND (CMOS levels), rather than VIH or VIL (TTL levels). For detailed information regarding the operation of the 28F016SA FlashFile Memory, refer to the Intel data sheet (order number 290489) and user’s manual (order number 297372). O bs ol et e Memory data is written in byte/word increments typically within 6 ms. Each page of memory incorporates two sector buffers of 256 bytes (128-words) which allow sector data writes at SRAM speeds. Writes from sector buffers to the flash array can be initiated with a single command and will complete independently, freeing the system controller for other tasks. Any one of the 512 blocks can be erased typically within 0.6 seconds, without affecting the contents of the remaining blocks. Write and erase operations can be executed simultaneously in all 16 pages, greatly improving average write/ erase cycle times. A write protection scheme has been incorporated that provides maximum flexibility for selecting which blocks can be modified by the end user. A non-volatile lock bit is assigned to each block, and is used in conjunction with the master write protect input (WP). With WP at logic low, block locking capability is invoked and the WSM is notified if a requested write or erase operation is not allowed. With WP at logic high, the status of all lock bits is overridden, allowing write or erase operations in any block. The MCM28F256ACH reduces system overhead by allowing a subset of commands to be pipelined to the CUI on each page of memory. Ordinarily the command queue is 3commands deep. However, if only single block erase commands are queued, the queue becomes virtually 32-commands deep. Commands in the queue are prioritized. In order to capture data as it arrives in real time, write commands are executed before erase commands regardless of the command order. Also, multiple erase commands are queued in conjunction with write commands. If the CUI receives a write command affecting a block which is in queue to be erased, it will prioritize that block erase command ahead of other erase operations, allowing the complete block modification to occur as quickly as possible. 3 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Device Power Supply Voltage (VCC) 4.5V to 5.5V Erase/Write Power Supply Voltage (VPP) (Note 2) Read-Only Operations (VPPL) 0.0V to 6.5V Erase/Write Operations (VPPH) 11.4V to 12.6V Input Voltage (VIN) 0V to VCC Output Voltage (VOUT) 0V to VCC Case Operating Temperature (TC) b 45§ C to a 85§ C Industrial b 55§ C to a 125§ C Military Minimum Input Edge Rate (dV/dt) 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Maximum Static Output Current b 32 mA High Level (IOH) a 64 mA Low Level (IOL) b 0.2V to a 7.0V Device Power Supply Voltage (VCC) Erase/Write Power Supply Voltage (VPP) b0.2V to a 14.0V DC Input Diode Current (IIK) b 20 mA VIN e b0.5V a 20 mA VIN e VCC a 0.5V DC Output Diode Current (IOK) b 20 mA VOUT e b0.5V a 20 mA VOUT e VCC a 0.5V b 0.5V to VCC a 0.5V DC Output Voltage (VOUT) g 70 mA DC Output Source/Sink Current (IOUT) DC VCC or Ground Current g 70 mA Per Output Pin (ICC or IGND) 5§ C/W Thermal Resistance, Junction to Case (iJC) a 150§ C Junction Temperature (TJ) b 65§ C to a 150§ C Storage Temperature (TSTG) e Note 2: Erase and write operations are inhibited when VPP e VPPL and not guaranteed In the range betveeen VPPL and VPPH. DC Electrical Characteristics Symbol Parameter Minimum High Input Voltage VIL Maximum Low Input Voltage IIH Maximum High Input Current IIL Military Industrial TC e b55§ C to a 125§ C TC e b45§ C to a 85§ C Units VCC e 4.5V to 5.5V VCC e 4.5V to 5.5V 2.0 bs ol VIH Conditions et Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of this module outside the datasheet specifications. Maximum Low Input Current 0.8 0.8 V 1.0 1.0 mA VIN e VCC TCK, TDI, TMS Inputs 15.0 15.0 mA VIN e GND All inputs except TCK, TDI, TMS b 1.0 b 1.0 mA VIN e GND TCK, TDI, TMS Inputs b 1.2 b 1.2 mA g 15.0 g 10.0 mA VCC b 1.35 VCC b 1.35 Maximum I/O Leakage Current VI/O e VCC or GND VOH Minimum High Output Voltage IOUT e b50 mA IOUT e b32 mA Maximum Low Output Voltage IOUT e 50 mA 0.1 IOUT e 64 mA Minimum Dynamic Output Current ² V 0.55 VOLD e 0.8 VMax 63 94 VOHD e 2.0 VMin b 27 b 40 b 100 b 100 mA 2.0 2.0 mA 25 25 mA IOS Minimum Output Short Circuit Current ² VOUT e 0V ICCT Maximum VCC Current per Input at TTL HIGH VIN e VCC b 2.1V All inputs except TCK,TDI, TMS ICCS Maximum VCC Standby Current CE e RP e VCC ² Maximum V 0.1 0.55 IOUT e 48 mA IOHD 2.4 2.4 O IOUT e b24 mA IOLD V VIN e VCC All inputs except TCK, TDI, TMS IOZT VOL 2.0 test duration 2.0 ms, one output loaded at a time. 4 mA DC Electrical Characteristics (Continued) Symbol Parameter ICCD Maximum VCC Deep Power Down Current RP e GND, TDI e TMS e VCC ICCR Maximum VCC Read Current ICCW Maximum VCC Write Current ICCES 5 5 mA f e 5 MHz IOUT e 0 mA 120 120 mA Single Write Operation 70 70 mA 16 Simultaneous Write Operations 650 650 mA Maximum VCC Block Erase Current Single Erase Operation 60 60 16 Simultaneous Erase Operations 480 480 Maximum VCC Erase Suspend Current Single Erase Operation Suspended 45 45 16 Erase Operations Simultaneously Suspended 220 220 Maximum VPP Standby Current VPP t VCC IPPD Maximum VPP Deep Power Down Current RP e GND IPPR Maximum VPP Read Current VPP e VPPH 5 5 IPPW Maximum VPP Byte Write Current Single Write Operation 18 18 16 Simultaneous Write Operations 290 290 Maximum VPP Block Erase Current Single Erase Operation 15 15 16 Simultaneous Erase Operations 240 240 1 mA 1 1 mA bs ol IPPES 1 et IPPS IPPE Maximum VPP Erase Suspend Current ² Maximum mA mA e ICCE Military Industrial TC e b55§ C TC e b45§ C Units to a 125§ C to a 85§ C e e VCC 4.5V to 5.5V VCC 4.5V to 5.5V Conditions 1–16 Erase Operations Suspended 5 5 mA mA mA mA test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics Read Operations Symbol Parameter Military TC e b55§ C to a 125§ C VCC e 4.5V to 5.5V Min tAVAV tAVEL tAVQV Min Read Cycle Time (No Page Change) 160 140 Read Cycle Time (With Page Change) 180 160 Address Setup to CE Going Low 20 15 Address Setup to OE Going Low 0 O tAVGL Max Industrial TC e b45§ C to a 85§ C VCC e 4.5V to 5.5V Units Max ns ns 0 ns Address A0 – A20 to Output Delay 160 140 Address A21 – A24 to Output Delay 180 160 tELQV CE to Output Delay 200 180 tPHQV RP to Output Delay 800 700 ns tGLQV OE to Output Delay 80 70 ns tELQX CE to Output Low Z tEHQZ CE to Output High Z 40 ns tGLQX OE to Output Low Z tGHQZ OE to Output High Z 60 ns 0 0 50 0 5 ns ns 0 70 ns ns AC Electrical Characteristics Read Operations (Continued) Symbol Parameter Military TC e b55§ C to a 125§ C VCC e 4.5V to 5.5V Min tOH Output Hold from Address CE or RE Change, Whichever Occurs First tFLQV tFHQV BYTE to Output Delay tFLQZ tELFL tELFH Industrial TC e b45§ C to a 85§ C VCC e 4.5V to 5.5V Max Min 0 Units Max 0 ns 160 140 ns BYTE Low to Output High Z 35 30 ns CE Low to BYTE Low or High 0 0 ns AC Electrical Characteristics WE Controlled Command Write Operations Parameter Military TC e b55§ C to a 125§ C VCC e 4.5V to 5.5V Min Write Cycle Time 160 tVPWH VPP Setup to WE Going High 300 tPHEL RP Setup to CE Going Low tELWL tAVWL Max Units Min Max 140 ns 250 ns 700 600 ns CE Setup to WE Going Low 40 35 ns Address A20 – A24 Setup to WE Going Low ² 20 15 ns tAVWH Address A0 – A20 Setup to WE Going High 70 60 ns tDVWH Data Setup to WE Going High 70 60 ns tWLWH WE Pulse Width Low 70 60 ns tWHDX Data Hold from WE High 10 5 ns tWHAX Address Hold from WE High 20 15 ns tWHEH CE Hold from WE High 20 15 ns tWHWL WE Pulse Width High 70 60 ns tGHWL Read Recovery before Write 0 tWHRL WE High to RY/BY Going Low tRHPL RP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY High O bs ol et tAVAV Industrial TC e b45§ C to a 85§ C VCC e 4.5V to 5.5V e Symbol 0 150 ns 130 ns 0 0 ns tPHWL RP High Recovery to WE Going Low 1.5 1.25 ms tWHGL Write Recovery before Read 110 100 ns tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY High 0 0 ms tWHQV1 Duration of Word/Byte Write Operation (Measured to Valid Status Register Data) 3.0 3.6 ms tWHQV2 Duration of Block Erase Operation (Measured to Valid Status Register Data) 0.2 0.24 ms ² Address lines A20 –A24 must be valid during the entire WE Low pulse. 6 AC Electrical Characteristics CE Controlled Command Write Operations Symbol Military TC e b55§ C to a 125§ C VCC e 4.5V to 5.5V Parameter Min Industrial TC e b45§ C to a 85§ C VCC e 4.5V to 5.5V Max Min Units Max Write Cycle Time 160 140 ns tVPEH VPP Setup to CE Going High 300 250 ns tPHWL RP Setup to WE Going Low 700 600 ns tWLEL WE Setup to CE Going Low 0 0 ns tAVEL Address A20 – A24 Setup to CE Going Low ² 0 0 ns tAVEH Address A0 – A20 Setup to CE Going High 55 45 ns tDVEH Data Setup to CE Going High 55 45 ns tELEH CE Pulse Width Low 70 60 ns tEHDX Data Hold from CE High 40 35 ns tEHAX Address Hold from CE High 55 45 ns tENWH WE Hold from CE High 55 45 ns tEHEL CE Pulse Width High 70 tGHEL Read Recovery before Write 0 tEHRL CE High to RY/BY Going Low tRHPL RP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY High tPHEL RP High Recovery to CE Going Low tEHGL Write Recovery before Read tQVVL VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY High tEHQV1 Duration of Word/Byte Write Operation (Measured to Valid Status Register Data) ² Address 60 0 190 Duration of Block Erase Operation (Measured to Valid Status Register Data) ns ns ns 0 ns et 0 165 1.5 1.25 ms 110 100 ns 0 0 ms 3.0 3.6 ms 0.2 0.24 s bs ol tEHQV2 e tAVAV lines A20 –A24 must be valid during the entire WE Low pulse. AC Electrical Characteristics WE Controlled Page Buffer Write Operations Symbol Parameter Military TC e b55§ C to a 125§ C VCC e 4.5V to 5.5V Min tAVAV tELWL tAVWL Min Units Max Write Cycle Time 160 140 ns CE Setup to WE Going Low 40 35 ns Address Setup to WE Going Low ² 20 15 ns Data Setup to WE Going High 70 60 ns O tDVWH Max Industrial TC e b45§ C to a 85§ C VCC e 4.5V to 5.5V tWLWH WE Pulse Width Low 70 60 ns tWHDX Data Hold from WE High 10 5 ns tWHAX Address Hold from WE High 20 15 ns tWHEH CE Hold from WE High 20 15 ns tWHWL WE Pulse Width High 70 60 ns tGHWL Read Recovery before Write 0 0 ns tWHGL Write Recovery before Read 110 100 ns ² Address must be valid during the entire WE Low pulse. 7 AC Electrical Characteristics CE Controlled Page Buffer Write Operations Symbol Parameter Military TC e b55§ C to a 125§ C VCC e 4.5V to 5.5V Min Max Industrial TC e b45§ C to a 85§ C VCC e 4.5V to 5.5V Min Units Max Write Cycle Time 160 140 tWLEL WE Setup to CE Going Low 0 0 ns tAVEL Address Setup to CE Going Low ² 0 0 ns tDVEH Data Setup to CE Going High 55 45 ns tELEH CE Pulse Width Low 70 60 ns tEHDX Data Hold from CE High 40 35 ns tEHAX Address Hold from CE High 55 45 ns tEHWH WE Hold from CE High 55 45 ns tEHEL CE Pulse Width High 70 60 ns tGHEL Read Recovery before Write 0 0 ns tEHGL Write Recovery before Read 110 100 ns ² Address ns e tAVAV must be valid during the entire CE Low pulse. Symbol Parameter et AC Electrical Characteristics Write and Erase Performance (Excluding System Level Overhead) Military TC e b55§ C to a 125§ C VCC e 4.5V to 5.5V Typ ² Typ ² Units Max Word/Byte Write Time 6 tWHRH2 Block Write Time (Byte Write Mode) 0.4 3.0 0.4 2.5 tWHRH3 Block Write Time (Word Write Mode) 0.2 1.4 0.2 1.2 s Block Erase Time 0.6 1.4 0.6 12 s Full Page Erase Time 19.2 bs ol tWHRH1 19.2 VPP e 12.0V, VCC e 5.0V. O ² 25§ C, 6 Max Industrial TC e b45§ C to a 85§ C VCC e 4.5V to 5.5V 8 ms s s Capacitance Typ Units Conditions CIN Symbol Input Pin Capacitance Parameter 10 pF VCC e 5.0V CI/O Input/Output Pin Capacitance 25 pF VCC e 5.0 e AC Testing Load Circuit bs ol AC Reference Waveforms et TL/Z/12436 – 3 O Input rise and fall times (10%–90%) e 3 ns 9 TL/Z/12436 – 4 10 e et bs ol O et e Physical Dimensions (inches) O bs ol 68-Lead, Hermetic, Dual-In-Line, Custom, ISPMCM-DC Package NS Package Number IS68A 11 e et 68-Lead, Hermetic, Surface Mount, Custom, ISPMCM-DC Package NS Package Number IS68B bs ol MCM28F256ACH 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers Physical Dimensions (inches) (Continued) LIFE SUPPORT POLICY O NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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