MOTOROLA Order this document by MCM6205D/D SEMICONDUCTOR TECHNICAL DATA MCM6205D 32K x 9 Bit Fast Static RAM The MCM6205D is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in a plastic small–outline J–leaded package. • • • • • Single 5 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary Fast Access Times: 15, 20, and 25 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems • Low Power Operation: 130 – 140 mA Maximum AC • Fully TTL Compatible — Three State Output PIN ASSIGNMENT BLOCK DIAGRAM A1 VCC A3 VSS A4 A6 A7 MEMORY MATRIX 256 ROWS x 128 x 9 COLUMNS ROW DECODER A9 J PACKAGE 300 MIL SOJ CASE 857–02 NC 1 32 V CC NC 2 31 A14 A8 3 30 E2 A7 4 29 W A6 5 28 A13 A5 6 27 A9 A4 7 26 A10 A3 8 25 A11 A2 9 24 G A1 10 23 A12 A0 11 22 E1 DQ0 12 21 DQ8 DQ1 13 20 DQ7 DQ2 14 19 DQ6 DQ3 15 18 DQ5 VSS 16 17 DQ4 A10 A11 PIN NAMES DQ0 DQ8 COLUMN I/O INPUT DATA CONTROL E1 E2 COLUMN DECODER A0 A2 A5 A8 A12 A13 A14 A0 – A14 . . . . . . . . . . . . . Address Input DQ0 – DQ8 . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E1, E2 . . . . . . . . . . . . . . . . . Chip Enable NC . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground W G REV 1 5/95 Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM6205D 1 TRUTH TABLE (X = Don’t Care) E1 E2 G W Mode VCC Current Output Cycle H X L L L X L H H H X X H L X X X H H L Not Selected Not Selected Output Disabled Read Write ISB1, ISB2 ISB1, ISB2 ICCA ICCA ICCA High–Z High–Z High–Z Dout High–Z — — — Read Cycle Write Cycle ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 1.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Power Supply Voltage Voltage Relative to VSS For Any Pin Except VCC Storage Temperature — Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) Parameter VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ±1 µA Output Leakage Current (E1 = VIH or G = VIH or E2 = VIL, Vout = 0 to VCC) Ilkg(O) — ±1 µA Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Output Low Voltage (IOL = 8.0 mA) VOL — 0.4 V Symbol – 15 – 20 – 25 Unit AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) ICCA 140 135 130 mA AC Standby Current (E1 = VIH, or E2 = VIL, VCC = Max, f = fmax) ISB1 40 40 35 mA CMOS Standby Current (VCC = Max, f = 0 MHz, E1 ≥ VCC – 0.2 V or E2 ≤ VSS + 0.2 V, Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V) ISB2 20 20 20 mA * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter POWER SUPPLY CURRENTS Parameter MCM6205D 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested) Characteristic Symbol Max Unit Address Input Capacitance Cin 6 pF Control Pin Input Capacitance (E1, E2, G, W) Cin 8 pF I/O Capacitance CI/O 8 pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted READ CYCLE (See Notes 1 and 2) Parameter MCM6205D–15 MCM6205D–20 MCM6205D–25 Symbol Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 15 — 20 — 25 — ns 3 Address Access Time tAVQV — 15 — 20 — 25 ns Enable Access Time tELQV — 15 — 20 — 25 ns Output Enable Access Time tGLQV — 8 — 10 — 12 ns Output Hold from Address Change tAXQX 4 — 4 — 4 — ns Enable Low to Output Active tELQX 4 — 4 — 4 — ns 5, 6, 7 Enable High to Output High–Z tEHQZ 0 8 0 9 0 10 ns 5, 6, 7 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — ns 5, 6, 7 Output Enable High to Output High–Z tGHQZ 0 7 0 8 0 10 ns 5, 6, 7 tELICCH 0 — 0 — 0 — ns Power Up Time 4 Power Down Time tEHICCL — 15 — 20 — 25 ns NOTES: 1. W is high for read cycle. 2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E1 = VIL, E2 = VIH, G = VIL). TIMING LIMITS AC TEST LOADS +5V 480 Ω Z0 = 50 Ω OUTPUT OUTPUT 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MOTOROLA FAST SRAM Figure 1B The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. MCM6205D 3 READ CYCLE 1 (See Note 8) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note 4) tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX HIGH–Z Q (DATA OUT) ICC tELICCH HIGH Z DATA VALID tEHICCL VCC SUPPLY CURRENT ISB MCM6205D 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3) Parameter Write Cycle Time MCM6205D–15 MCM6205D–20 MCM6205D–25 Symbol Min Max Min Max Min Max Units Notes tAVAV 15 — 20 — 25 — ns 4 Address Setup Time tAVWL 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 12 — 15 — 20 — ns Write Pulse Width tWLWH, tWLEH 12 — 15 — 20 — ns Write Pulse Width, G High tWLWH, tWLEH 10 — 12 — 15 — ns Data Valid to End of Write tDVWH 7 — 8 — 10 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns Write Low to Output High–Z tWLQZ 0 7 0 8 0 10 ns 6, 7, 8 Write High to Output Active tWHQX 4 — 4 — 4 — ns 6, 7, 8 5 Write Recovery Time tWHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E. 3. If G goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. All timings are referenced from the last valid address to the first transitioning address. 5. If G ≥ VIH, the output will remain in a high impedance state. 6. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 7. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 8. This parameter is sampled and not 100% tested. WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3) tAVAV A (ADDRESS) tWHAX tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) MOTOROLA FAST SRAM tWHDX HIGH–Z tWHQX HIGH–Z MCM6205D 5 WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) MCM6205D–15 Parameter Write Cycle Time MCM6205D–20 MCM6205D–25 Symbol Min Max Min Max Min Max Unit Notes tAVAV 15 — 20 — 25 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 12 — 15 — 20 — ns Enable to End of Write tELEH, tELWH 10 — 12 — 15 — ns Data Valid to End of Write tDVEH 7 — 8 — 10 — ns Data Hold Time tEHDX 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — ns 4, 5 NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tELEH tELWH tAVEL tEHAX tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) tEHDX DATA VALID HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 6205D X XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns) Package (J = 300 mil SOJ) Full Part Numbers — MCM6205DJ15 MCM6205DJ20 MCM6205DJ25 MCM6205D 6 MCM6205DJ15R2 MCM6205DJ20R2 MCM6205DJ25R2 MOTOROLA FAST SRAM PACKAGE DIMENSIONS CASE 857–02 32 LEAD 300 MIL SOJ F 32 PL 0.17 (0.007) 32 17 1 M D 32 PL 0.17 (0.007) P 0.17 (0.007) S B 16 -AL G DETAIL Z A S A S NOTE 5 S S -B-X- K S NOTE 4 NOTE 3 E C 0.10 (0.004) -T- SEATING PLANE R 0.25 (0.010) S RADIUS S B S NOTE 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DATUM PLANE -X- LOCATED AT TOP OF MOLD PARTING LINE AND COINCIDENT WITH TOP OF LEAD, WHERE LEAD EXITS BODY. 4. TO BE DETERMINED AT PLANE -X-. 5. TO BE DETERMINED AT PLANE -T-. 6. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 7. 857-01 IS OBSOLETE, NEW STANDARD 857-02. DIM A B C D E F G K L N P R S MILLIMETERS MIN MAX 20.83 21.08 7.50 7.74 3.26 3.75 0.41 0.50 2.24 2.48 0.67 0.81 1.27 BSC 0.89 1.14 0.64 BSC 0.76 1.14 8.38 8.64 6.60 6.86 0.77 1.01 INCHES MIN MAX 0.820 0.830 0.295 0.305 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040 Motorola reserves the right to make changes without further notice to any products herein. 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Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM6205D 8 ◊ CODELINE TO BE PLACED HERE *MCM6205D/D* MCM6205D/D MOTOROLA FAST SRAM