MOTOROLA Order this document by MCM6206D/D SEMICONDUCTOR TECHNICAL DATA MCM6206D 32K x 8 Bit Fast Static RAM The MCM6206D is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in plastic dual–in–line and plastic small–outline J–leaded packages. P PACKAGE 300 MIL PLASTIC CASE 710B–01 • • • • • Single 5 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary Fast Access Times: 12, 15, 20, and 25 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems • Low Power Operation: 125 – 140 mA Maximum AC • Fully TTL Compatible — Three State Output J PACKAGE 300 MIL SOJ CASE 810B–03 PIN ASSIGNMENT A14 1 28 A12 2 27 W A7 3 26 A13 VCC A6 4 25 A8 VSS A5 5 24 A9 A4 6 23 A11 A3 7 22 G A2 8 21 A10 A1 9 20 E A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 BLOCK DIAGRAM A1 A3 A4 A6 A7 MEMORY MATRIX 256 ROWS x 128 x 8 COLUMNS ROW DECODER A8 A9 A11 DQ0 DQ7 INPUT DATA CONTROL .. . V CC COLUMN I/O COLUMN DECODER PIN NAMES E W G A0 A2 A5 A10 A12 A13 A14 A0 – A14 . . . . . . . . . . . . . Address Input DQ0 – DQ7 . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground REV 1 5/95 Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM6206D 1 TRUTH TABLE (X = Don’t Care) E G W Mode VCC Current Output Cycle ISB1, ISB2 ICCA High–Z – High–Z – ICCA ICCA Dout High–Z Read Cycle H X X Not Selected L H H Output Disabled L L H Read L X L Write Write Cycle ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 1.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Power Supply Voltage Voltage Relative to VSS For Any Pin Except VCC Storage Temperature—Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ±1 µA Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Ilkg(O) — ±1 µA Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Output Low Voltage (IOL = 8.0 mA) VOL — 0.4 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter POWER SUPPLY CURRENTS Parameter Symbol – 12 – 15 – 20 – 25 Unit AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) ICCA 140 135 130 125 mA AC Standby Current (E = VIH, VCC = Max, f = fmax) ISB1 40 35 35 30 mA CMOS Standby Current (VCC = Max, f = 0 MHz, E ≥ VCC – 0.2 V Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V) ISB2 20 20 20 20 mA CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested) Characteristic Symbol Max Unit Address Input Capacitance Cin 6 pF Control Pin Input Capacitance (E, G, W) Cin 8 pF I/O Capacitance CI/O 8 pF MCM6206D 2 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted READ CYCLE (See Note 1) – 12 Parameter – 15 – 20 – 25 Symbol Min Max Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 12 — 15 — 20 — 25 — ns 2 Address Access Time tAVQV — 12 — 15 — 20 — 25 ns Enable Access Time tELQV — 12 — 15 — 20 — 25 ns Output Enable Access Time tGLQV — 6 — 8 — 10 — 12 ns Output Hold from Address Change tAXQX 4 — 4 — 4 — 4 — ns 4,5,6 Enable Low to Output Active tELQX 4 — 4 — 4 — 4 — ns 4,5,6 Enable High to Output High–Z tEHQZ 0 7 0 8 0 9 0 10 ns 4,5,6 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — ns 4,5,6 Output Enable High to Output High–Z tGHQZ 0 6 0 7 0 8 0 10 ns 4,5,6 Power Up Time tELICCH 0 — 0 — 0 — 0 — ns Power Down Time tEHICCL — 12 — 15 — 20 — 25 ns 3 NOTES: 1. W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 5. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). TIMING LIMITS AC TEST LOADS +5 V 480 Ω Z0 = 50 Ω OUTPUT OUTPUT 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MOTOROLA FAST SRAM Figure 1B The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. MCM6206D 3 READ CYCLE 1 (See Note 7) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note 3) tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX Q (DATA OUT) ICC HIGH–Z tELICCH HIGH–Z DATA VALID tEHICCL VCC SUPPLY CURRENT ISB MCM6206D 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) – 12 Parameter Write Cycle Time – 15 – 20 – 25 Symbol Min Max Min Max Min Max Min Max Unit Notes tAVAV 12 — 15 — 20 — 25 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 10 — 12 — 15 — 20 — ns Write Pulse Width tWLWH, tWLEH 10 — 12 — 15 — 20 — ns Write Pulse Width, G High tWLWH, tWLEH 10 — 10 — 12 — 15 — ns Data Valid to End of Write tDVWH 6 — 7 — 8 — 10 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — ns Write Low to Output High–Z tWLQZ 0 6 0 7 0 8 0 10 ns 5,6,7 Write High to Output Active tWHQX 4 — 4 — 4 — 4 — ns 5,6,7 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns 4 NOTES: 1. A write occurs during the overlap of E low and W low. 2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If G ≥ VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) tAVAV A (ADDRESS) tWHAX tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) MOTOROLA FAST SRAM tWHDX HIGH–Z tWHQX HIGH–Z MCM6206D 5 WRITE CYCLE 2 (E Controlled, See Note 1) – 12 Parameter Write Cycle Time – 15 – 20 – 25 Symbol Min Max Min Max Min Max Min Max Unit tAVAV 12 — 15 — 20 — 25 — ns Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 10 — 12 — 15 — 20 — ns Enable to End of Write tELEH, tELWH 9 — 10 — 12 — 15 — ns Data Valid to End of Write tDVEH 6 — 7 — 8 — 10 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns Notes 3,4 NOTES: 1. A write occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Note 1) tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tELEH tELWH tAVEL tEHAX tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) tEHDX DATA VALID HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 6206D X XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns, 25 = 25 ns) Package (P = 300 mil Plastic DIP, J = 300 mil SOJ) Full Part Numbers — MCM6206DP12 MCM6206DP15 MCM6206DP20 MCM6206DP25 MCM6206D 6 MCM6206DJ12 MCM6206DJ15 MCM6206DJ20 MCM6206DJ25 MCM6206DJ12R2 MCM6206DJ15R2 MCM6206DJ20R2 MCM6206DJ25R2 MOTOROLA FAST SRAM PACKAGE DIMENSIONS CASE 710B–01 300 MIL PDIP 28 LEAD -A- 28 15 1 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION A AND B DOES NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). -B- DIM A B C D E F G J K L M N L C -T- K SEATING PLANE E F N G D 28 PL 0.25 (0.010) M J 28 PL M T A 0.25 (0.010) S M T B MILLIMETERS MIN MAX 34.55 34.79 7.12 7.62 3.81 4.57 0.39 0.53 1.27 BSC 1.15 1.39 2.54 BSC 0.21 0.30 3.18 3.42 7.62 BSC 0° 15° 0.51 1.01 INCHES MIN MAX 1.360 1.370 0.280 0.300 0.150 0.180 0.015 0.021 0.050 BSC 0.045 0.055 0.100 BSC 0.008 0.012 0.125 0.135 0.300 BSC 0° 15° 0.020 0.040 S CASE 810B–03 300 MIL SOJ 28 LEAD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. 5. 810B-01 AND -02 OBSOLETE, NEW STANDARD 810B-03. F DETAIL Z 28 15 N 1 D 24 PL 14 0.18 (0.007) -A- M T A 0.18 (0.007) H BRK S S T B S P -B- L G M M E C 0.10 (0.004) K DETAIL Z -T- SEATING PLANE S RAD R 0.25 (0.010) S T B S DIM A B C D E F G H K L M N P R S MILLIMETERS MIN MAX 18.29 18.54 7.74 7.50 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 — 1.14 0.89 0.64 BSC 0° 10° 1.14 0.76 8.64 8.38 6.86 6.60 1.01 0.77 INCHES MIN MAX 0.720 0.730 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.020 — 0.035 0.045 0.025 BSC 0° 10° 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040 Motorola reserves the right to make changes without further notice to any products herein. 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Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM6206D 8 ◊ CODELINE TO BE PLACED HERE *MCM6206D/D* MCM6206D/D MOTOROLA FAST SRAM