MOTOROLA Order this document by MCM67A518/D SEMICONDUCTOR TECHNICAL DATA 32K x 18 Bit Asynchronous/ Latched Address Fast Static RAM • • • • • • • • • Single 5 V ± 10% Power Supply Fast Access Times: 10/12/15 ns Max Byte Writeable via Dual Write Enables Separate Data Input Latch for Simplified Write Cycles Address and Chip Enable Input Latches Common Data Inputs and Data Outputs Output Enable Controlled Three–State Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package FN PACKAGE PLASTIC CASE 778–02 A6 A7 E UW LW VCC V SS DL AL G A8 A9 A10 PIN ASSIGNMENT DQ9 DQ10 VCC VSS DQ11 DQ12 DQ13 DQ14 VSS VCC DQ15 DQ16 DQ17 7 6 5 4 3 2 1 52 51 50 49 48 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0 A5 A4 A3 A2 A1 A0 V SS V CC NC A14 A13 A12 A11 The MCM67A518 is a 589,824 bit latched address static random access memory organized as 32,768 words of 18 bits, fabricated with Motorola’s high– performance silicon–gate BiCMOS technology. The device integrates a 32K x 18 SRAM core with advanced peripheral circuitry consisting of address and data input latches, active low chip enable, separate upper and lower byte write strobes, and a fast output enable. This device has increased output drive capability supported by multiple power pins. Address, data in, and chip enable latches are provided. When latch enables (AL for address and chip enables and DL for data in) are high, the address, data in, and chip enable latches are in the transparent state. If latch enables are tied high, the device can be used as an asynchronous SRAM. When latch enables are low, the address, data in, and chip enable latches are in the latched state. This input latch simplifies read and write cycles by guaranteeing address and data–in hold time in a simple fashion. Dual write enables (LW and UW) are provided to allow individually writeable bytes. LW controls DQ0 – DQ8 (the lower bits) while UW controls DQ9 – DQ17 (the upper bits). Additional power supply pins have been utilized and placed on the package for maximum performance. The MCM67A518 will be available in a 52–pin plastic leaded chip carrier (PLCC). This device is ideally suited for systems which require wide data bus widths, cache memory, and tag RAMs. MCM67A518 PIN NAMES A0 – A14 . . . . . . . . . . . . . . . . Address Inputs AL . . . . . . . . . . . . . . . . . . . . . . Address Latch DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch LW . . . . . . . . . . . . Lower Byte Write Enable UW . . . . . . . . . . . . Higher Byte Write Enable E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 – DQ17 . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . No Connection All power supply and ground pins must be connected for proper operation of the device. REV 2 5/95 Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM67A518 1 BLOCK DIAGRAM A0 – A14 LATCH 15 15 MEMORY ARRAY 32K x 18 OUTPUT BUFFER 18 DQ0 – DQ17 18 18 9 9 WRITE AMP E 18 LATCH CONTROL LATCH AL UW LW G DL TRUTH TABLE E LW UW AL* DL* G Mode Supply Current I/O Status H X X X X X Deselected Cycle ISB High–Z L X X L X X Read or Write Using Latched Addresses ICC — L X X H X X Read or Write Using Unlatched Addresses ICC — L H H X X L Read Cycle ICC Data Out L H H X X H Read Cycle ICC High–Z L L L X L X Write Both Bytes Using Latched Data In ICC High–Z L L L X H X Write Both Bytes Using Unlatched Data In ICC High–Z L L H X X X Write Cycle, Lower Byte ICC High–Z L H L X X X Write Cycle, Lower Byte ICC High–Z *E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data–in satisfies the specified setup and hold times for falling edge of DL. NOTE: This truth table shows the application of each function. Combinations of these functions are valid. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0) Rating Symbol Value Unit VCC – 0.5 to 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 30 mA Power Dissipation PD 1.6 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Storage Temperature MCM67A518 2 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.5 V Input High Voltage VIH 2.2 VCC + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ± 1.0 µA Output Leakage Current (G = VIH) Ilkg(O) — ± 1.0 µA AC Supply Current (G = VIH, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0, Cycle Time ≥ tAVAV min) ICCA10 ICCA12 ICCA15 — 290 275 260 mA AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH ≥ 3.0 V, f = fmax) ISB1 — 75 mA CMOS Standby Current (E ≥ VCC – 0.2, All Inputs ≥ VCC – 0.2 V or ≤ 0.2 V, f = fmax) ISB2 — 30 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 3.3 V Symbol Typ Max Unit Input Capacitance (All Pins Except DQ0 – DQ17) Cin 4 5 pF Input/Output Capacitance (DQ0 – DQ17) CI/O 6 8 pF ** VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS Parameter CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic MOTOROLA FAST SRAM MCM67A518 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted ASYNCHRONOUS READ CYCLE TIMING (See Notes 1 and 2) MCM67A518–10 Parameter MCM67A518–12 MCM67A518–15 Symbol Min Max Min Max Min Max Unit Notes tAVAV 10 — 12 — 15 — ns 3 ns 4 tAVQV tELQV tGLQV — — — 10 10 5 — — — 12 12 6 — — — 15 15 7 Output Hold from Address Change tAXQX 4 — 4 — 4 — Output Buffer Control: E Low to Output Active G Low to Output Active E High to Output High–Z G High to Output High–Z tELQX tGLQX tEHQZ tGHQZ 3 1 2 2 — — 5 5 3 1 2 2 — — 6 6 2 1 2 2 — — 9 7 tELICCA 0 — 0 — 0 — Read Cycle Times Access Times: Address Valid to Output Valid E Low to Output Valid Output Enable Low to Output Valid Power Up Time ns ns 5 ns NOTES: 1. AL and DL are equal to VIH for all asynchronous cycles. 2. Both Write Enable signals (LW, UW) are equal to VIH for all read cycles. 3. All read cycle timing is referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tEHQZ is less than tELQX and tGHQZ is less than tGLQX for a given device. AC TEST LOADS +5V 480 Ω OUTPUT OUTPUT Z0 = 50 Ω RL = 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MCM67A518 4 Figure 1B MOTOROLA FAST SRAM ASYNCHRONOUS READ CYCLES AL (ADDRESS LATCH) A1 A (ADDRESS) A2 A3 tAVAV E (CHIP ENABLE) tELQV tELQX Q (DATA OUT) tAVQV tAXQX tEHQZ Q (A1) Q (A2) tGHQZ Q (A3) tGLQX tGLQV G (OUTPUT ENABLE) LW, UW (WRITE ENABLE) DL (DATA LATCH) MOTOROLA FAST SRAM MCM67A518 5 ASYNCHRONOUS WRITE CYCLE TIMING (See Notes 1, 2, and 3) MCM67A518–10 Parameter MCM67A518–12 MCM67A518–15 Symbol Min Max Min Max Min Max Unit Notes tAVAV 10 — 12 — 15 — ns 4 Address Valid to End of Write Address Valid to E High Address Valid to W Low Address Valid to E Low Address Valid to W High Data Valid E High tAVWH tAVEH tAVWL tAVEL tDVWH tDVEH 9 9 0 0 5 5 — — — — — — 10 10 0 0 6 6 — — — — — — 13 13 0 0 7 7 — — — — — — W High to Address Invalid E High to Address Invalid W High to Data Invalid E High to Data Invalid tWHAX tEHAX tWHDX tEHDX 0 0 0 0 — — — — 0 0 0 0 — — — — 0 0 0 0 — — — — Write Pulse Width: Write Pulse Width (G Low) Write Pulse Width (G High) Write Pulse Width Enable to End of Write Enable to End of Write tWLWH tWLWH tWLEF tELWH tELEH 9 8 9 9 9 — — — — — 10 9 10 10 10 — — — — — 13 12 13 13 13 — — — — — tWHQV tWHQX tWLQZ 10 3 0 — — 5 12 3 0 — — 6 15 5 0 — — 9 Write Cycle Times Setup Times: ns Hold Times: ns ns Output Buffer Control: W High to Output Valid W High to Output Active W Low to Output High–Z 5 6 5, 6 ns 7 7, 8 NOTES: 1. W (write) refers to either one or both byte write enables LW and UW. 2. AL and DL are equal to VIH for all asynchronous cycles. 3. Both Write Enables must be equal to VIH for all address transitions. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes high coincident with or before W goes high the output will remain in a high impedance state. 6. If E goes low coincident with or after W goes low the output will remain in a high impedance state. 7. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tWLQZ is less than tWHQX for a given device. 8. If G goes low coincident with or after W goes low the output will remain in a high impedance state. MCM67A518 6 MOTOROLA FAST SRAM ASYNCHRONOUS WRITE CYCLE AL (ADDRESS LATCH) A1 A2 tAVAV tAVWH A (ADDRESS) A3 A4 tEHAX E (CHIP ENABLE) tELWH tAVEH tAVEL tELEH tAVWL tWHAX tWLWH tWLEH LW, UW (WRITE ENABLE) tWHDX tEHDX tDVWH DATA–IN tDVEH D (A1) D (A2) D (A3) D (A4) DL (DATA LATCH) tWHQX tWLQZ Q (DATA OUT) G (OUTPUT ENABLE) MOTOROLA FAST SRAM MCM67A518 7 LATCHED READ CYCLE TIMING (See Notes 1 and 2) MCM67A518–10 Parameter MCM67A518–12 MCM67A518–15 Symbol Min Max Min Max Min Max Unit Notes tAVAV 10 — 12 — 15 — ns 3 tAVQV tELQV tALHQV tGLQV — — — — 10 10 10 5 — — — — 12 12 12 6 — — — — 15 15 15 7 Address Valid to AL Low E Valid to AL Low Address Valid to AL High E Valid to AL High tAVALL tEVALL tAVALH tEVALH 2 2 0 0 — — — — 2 2 0 0 — — — — 2 2 0 0 — — — — AL Low to Address Invalid AL Low to E Invalid tALLAX tALLEX 2 2 — — 2 2 — — 3 3 — — Output Hold: Address Invalid to Output Invalid AL High to Output Invalid tAXQX tALHQX1 4 4 — — 4 4 — — 4 4 — — Address Latch Pulse Width tALHALL 5 — 5 — 5 — Output Buffer Control: E Low to Output Active G Low to Output Active AL High to Output Active E High to Output High–Z AL High to Output High–Z G High to Output High–Z tELQX tGLQZ tALHQX2 tEHQZ tALHQZ tGHQZ 3 1 3 2 2 2 — — — 5 5 5 3 1 3 2 2 2 — — — 6 6 6 2 1 2 2 2 2 — — — 9 9 7 Read Cycle Times Access Times: ns Address Valid to Output Valid E Low to Output Valid AL High to Output Valid Output Enable Low to Output Valid Setup Times: 3 4 ns Hold Times: 4 4 ns 4 ns ns ns 5 NOTES: 1. Both Write Enable Signals (LW, UW) are equal to VIH for all read cycles. 2. All read cycle timing is referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data latch (DL). 5. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tEHQZ is less than tELQX and tLEHQZ is less than tLEHQX2 and tGHQZ is less than tGLQX for a given device. MCM67A518 8 MOTOROLA FAST SRAM LATCHED READ CYCLES AL (ADDRESS LATCH) tALLAX A1 A (ADDRESS) tALHALL tAVALH tAVALL A2 tALLEX A3 tAVAV tEVALH tEVALL E (CHIP ENABLE) tALHQV tELQV tEHQZ tELQX Q (DATA OUT) tAXQX Q (A1) tLEHQX2 Q (A2) tALHQZ Q (A3) tGHQZ tGLQX G (OUTPUT ENABLE) tAVQV tALHQX1 tGLQV LW, UW (WRITE ENABLE) DL (DATA LATCH) MOTOROLA FAST SRAM MCM67A518 9 LATCHED WRITE CYCLE TIMING (See Notes 1, 2, and 3) MCM67A518–10 MCM67A518–12 MCM67A518–15 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Times: Address Valid to Address Valid tAVAV 10 — 12 — 15 — ns 4 Address Valid to End of Write Address Valid to End of Write E Valid to AL Low Address Valid to AL Low E Valid to AL High Address Valid to AL High AL High to W Low Address Valid to W Low Address Valid to E Low Data Valid to DL Low Data Valid to W High Data Valid to E High DL High to W High DL High to E High tAVWH tAVEH tEVALL tAVALL tEVALH tAVALH tALHWL tAVWL tAVEL tDVDLL tDVWH tDVEH tDLHWH tDLHEH 9 9 2 2 0 0 0 0 0 2 5 5 5 5 — — — — — — — — — — — — — — 10 10 2 2 0 0 0 0 0 2 6 6 6 6 — — — — — — — — — — — — — — 13 13 2 2 0 0 0 0 0 2 7 7 7 7 — — — — — — — — — — — — — — AL Low to E High AL Low to Address Invalid DL Low to Data Invalid W High to Address Invalid E High to Address Invalid W High to Data Invalid E High to Data Invalid W High to DL High E High to DL High W High to AL High tALLEH tALLAX tDLLDX tWHAX tEHAX tWHDX tEHDX tWHDLH tEFDLH tWHALH 2 2 2 0 0 0 0 0 0 0 — — — — — — — — — — 2 2 2 0 0 0 0 0 0 0 — — — — — — — — — — 3 3 3 0 0 0 0 0 0 0 — — — — — — — — — — AL High to W High Write Pulse Width (G Low) Write Pulse Width (G High) Write Pulse Width Enable to End of Write Enable to End of Write tALHWH tWLWH tWLWH tWLEH tELWH tELEH 9 9 8 9 9 9 — — — — — — 10 10 9 10 10 10 — — — — — — 13 13 12 13 13 13 — — — — — — tALHALL 5 — 12 — 15 — tWHQV tWHQX tWLQZ 10 3 0 — — 5 12 3 0 — — 6 15 5 0 — — 9 Setup Times: ns Hold Times: ns Write Pulse Width: 4 4 ns Address Latch Pulse Width Output Buffer Control: W High to Output Valid W High to Output Active W Low to Output High–Z 5 6 7 6, 7 ns 4 ns 8 8, 9 NOTES: 1. W (write) refers to either one or both byte write enables LW and UW. 2. A write occurs during the overlap of E low and W low. 3. Both Write Enables must be equal to VIH for all address transitions. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data latch (DL). 6. If E goes high coincident with or before W goes high the output will remain in a high impedance state. 7. If E goes low coincident with or after W goes low the output will remain in a high impedance state. 8. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tWLQZ is less than tWHQX for a given device. 9. If G goes low coincident with or after W goes low the output will remain in a high impedance state. MCM67A518 10 MOTOROLA FAST SRAM LATCHED WRITE CYCLES AL (ADDRESS LATCH) tAVALL tALHALL tELAX A (ADDRESS) A1 A2 tAVALH tWHAX tEVALH A3 A4 tAVAV tEVALL tALLEH tAVEH tEHAX tAVET tELEH E (CHIP ENABLE) tAVWL tALHWH tWLEH tWLWH tALHWL tELWH tWHALH tAVWH LW, UW (WRITE ENABLE) tDVWH tDLHEH tWHDX DATA–IN D (A1) tDLHWH tEHDX tDVEF D (A2) D (A3) tDVDLL D (A4) tWHDLH tEHDLH tDLLDX DL (DATA LATCH) tWHQX tWLQZ Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 67A518 X XX Motorola Memory Prefix Speed (10 = 10 ns, 12 = 12 ns, 15 = 15 ns) Part Number Package (FN = PLCC) Full Part Numbers — MCM67A518FN10 MCM67A518FN12 MCM67A518FN15 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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MOTOROLA FAST SRAM MCM67A518 11 PACKAGE DIMENSIONS FN PACKAGE 52–LEAD PLCC CASE 778–02 B Y BRK -N- 0.007 (0.180) M T L –M 0.007 (0.180) U M S N T L –M S N S 0.010 (0.250) S S D -L- -M- 52 LEADS ACTUAL (NOTE 1) 52 Z W D 1 G1 X VIEW D-D V A 0.007 (0.180) M T L –M S N S R 0.007 (0.180) M T L –M S N S T L –M N S S Z C H 0.004 (0.100) G -T- J F N S S 0.007 (0.180) M T L –M S N S VIEW S G1 S T L –M K SEATING PLANE VIEW S 0.010 (0.250) M K1 E (NOTE 1) 52 0.007 (0.180) T L –M S N S NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 — 0.020 — 0.025 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 0.020 — 10° 2° 0.710 0.730 0.040 — MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 18.04 18.54 1.02 — Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM67A518 12 ◊ CODELINE TO BE PLACED HERE *MCM67A518/D* MCM67A518/D MOTOROLA FAST SRAM