FEDL9213-01 1Semiconductor ML9213 This version: Oct. 2001 56-Bit Duplex/Triplex (1/2 duty/1/3 duty) VFD Controller/Driver with Anode Digital Dimming GENERAL DESCRIPTION The ML9213 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. It consists of a 56-segment driver multiplexed to drive up to 168 segments, and 10-bit digital dimming circuit. ML9213 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the VFD driver with keyscan and A/D converter function. ML9213 provides an interface with a microcontroller only by three signal lines: DATA IN, CLOCK and CS. FEATURES N Logic supply voltage (VDD) : 5.0 V H10% N Driver supply voltage (VDISP) : 8.0 to 18.0 V N Duplex/Triplex (1/2 duty / 1/3 duty) selectable DUP/TRI = 1/2 duty selectable at “H” level DUP/TRI = 1/3 duty selectable at “L” level N Number of display segments 112 segments max. (during 1/2 duty mode) 168 segments max. (during 1/3 duty mode) N Master/Slave selectable : Master mode M/S = “H” level M/S = “L” level : Slave mode N Interface with a microcontroller Three lines: CS, CLOCK, and DATA IN N 56-segment driver outputs : IOH = –5.0 mA at VOH = VDISP–0.8 V (SEG1 to 37) (can be directly connected to VFD tube : IOH = –10.0 mA at VOH = VDISP–0.8 V (SEG38 to 56) and requires no external resistors) : IOL = 500 2A at VOL = 2.0 V (SEG1 to 56) N 3-grid pre-driver outputs : IOH = –5.0 mA at VOH = VDISP–0.8 V (requires external drivers) IOL = 10.0 mA at VOL = 2.0 V N Logic outputs : IOH = –200 2A at VOH = VDD–0.8 V IOL = 200 2A at VOL = 0.8 V N Built-in anode digital dimming circuit (10-bit resolution) N Built-in oscillation circuit (external resistor and capacitor) N Built-in Power-On-Reset circuit N Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) Product name: ML9213GA 80-pin plastic QFP (QFP80-P-1414-0.65-K) Product name: ML9213GP 1/19 FEDL9213-01 1Semiconductor ML9213 BLOCK DIAGRAM SEG1 VDISP L-GND Power On Reset 0H POR Mode Select In1-3 Control DATA IN OSC0 3 Grid Pre Driver POR Out1-56 168 to 56 Segment Control In1-56 In1-56 4H CS CLOCK GRID1 GRID2GRID3 56 Segment Driver D-GND VDD SEG56 1H 0H POR Out1-56 Segment Latch1 In1-56 2H 0H POR Out1-56 Segment Latch2 In1-56 Out1-3 3 bit Shift Register Out1-56 32 bit Shift Register POR POR 3H 0H POR 4H POR In1-56 Out1-56 Segment Latch3 In1-56 In1-10 Dimming Latch Out1-10 10 bit Digital Dimming OSC POR DIM OUT DIM IN SYNC OUT1 SYNC IN1 SYNC IN2 Timing Generator SYNC OUT2 M/S DUP/TRI 2/19 FEDL9213-01 1Semiconductor ML9213 80 VDISP 79 SEG37 78 SEG36 77 SEG35 76 SEG34 75 SEG33 74 SEG32 73 SEG31 72 SEG30 71 SEG29 70 SEG28 69 SEG27 68 SEG26 67 SEG25 66 SEG24 65 VDISP PIN CONFIGURATION (TOP VIEW) GRID1 GRID2 GRID3 NC D-GND 64 63 62 61 60 59 58 57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 NC VDD 25 DIM IN 26 SYNC IN1 27 SYNC IN2 28 CS 29 CLOCK 30 DATA IN 31 NC 32 L-GND 33 OSC0 34 DUP/TRI 35 M/S 36 SYNC OUT2 37 SYNC OUT1 38 DIM OUT 39 D-GND 40 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 NC: No connection ML9213GA 80-Pin Plastic QFP (QFP80-P-1420-0.80-BK) 3/19 FEDL9213-01 1Semiconductor 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG39 SEG38 VDISP SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 VDISP SEG23 SEG22 ML9213 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC D-GND VDD DIM IN SYNC IN1 SYNC IN2 CS CLOCK DATA IN NC L-GND OSC0 DUP/TRI M/S SYNC OUT2 SYNC OUT1 DIM OUT D-GND NC SEG1 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 GRID1 GRID2 GRID3 NC: No connection ML9213GP 80-Pin Plastic QFP (QFP80-P-1414-0.65-K) 4/19 FEDL9213-01 1Semiconductor ML9213 PIN DESCRIPTIONS Symbol Pin ML9213GA ML9213GP Type VDISP 65, 80 63, 78 — VDD D-GND 25 24, 40 23 22, 38 — — L-GND 33 31 — SEG1 to 37 42 to 64, 66 to 79 40 to 62, 64 to 77 SEG38 to 56 1 to 19 79, 80, 1 to 17 GRID1 20 18 GRID2 GRID3 21 22 19 20 O CS 29 27 I CLOCK 30 28 I DATA IN 31 29 I DUP/TRI 35 33 I M/S 36 34 I DIM IN 26 24 I SYNC IN1 27 25 O O I SYNC IN2 28 26 DIM OUT 39 37 O Description Power supply pins for VFD driver circuit. These should be connected externally. Power supply pin for logic drive. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. These should be connected externally. Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH –5 mA Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH –10 mA Inverted Grid signal output pins. Since these pins are connected to the pre-driver, an external circuit is required. IOL 10 mA Chip select input pin. Data is not transferred when CS is set to a Low level. Shift clock input pin. Serial data shifts at the rising edge of the CLOCK. Serial data input pin (positive logic). Data is input to the shift register at the rising edge of the CLOCK signal. Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation is selected when this pin is set to VDD. Triplex (1/3 duty) operation is selected when this pin is set to LGND. Master/Slave mode select input pin. Master mode is selected when this pin is set to VDD. Slave mode is selected when this pin is set to L-GND. Dimming pulse input. When the slave mode is selected, connect this pin to the master side DIM OUT pin. The pulse width of all the segment outputs is controlled by an input pulse width of DIM IN. When the master mode is selected, input to this pin is ignored; therefore, connect this pin to VDD or L-GND. The pulse width of all the segment outputs is controlled by the built-in digital dimming circuit, and the pulse width of all the grid outputs is controlled by the internal timing generator. Synchronous signal input. When the slave mode is selected, connect these pins to the master side SYN COUT1 and 2 pins. When the master mode is selected, input to these pins is ignored; therefore, connect these pins to VDD or L-GND. Dimming pulse output. Connect this pin to the slave side DIM IN pin. 5/19 FEDL9213-01 1Semiconductor ML9213 Pin Symbol ML9213GA ML9213GP SYNC OUT1 38 36 SYNC OUT2 37 35 OSC0 34 Type 32 Description O Synchronous signal output. Connect these pins to the slave side SYNC IN1 and 2 pins. I/O RC oscillator connecting pins. Oscillation frequency depends on display tubes to be used. For details, refer to ELECTRICAL CHARACTERISTICS. VDD R OSC0 C ABSOLUTE MAXIMUM RATINGS Symbol Condition Rating Unit Driver Supply Voltage Parameter VDISP — –0.3 to +20 V Logic Supply Voltage VDD — –0.3 to +6.5 V Input Voltage VIN — –0.3 to VDD+0.3 V Power Dissipation PD Storage Temperature Output Current Ta25°C QFP80-P-1420-0.80-BK 342 QFP80-P-1414-0.65-K 343 mW TSTG — –55 to +150 °C IO1 SEG1 to 37 –10.0 to +2.0 mA IO2 SEG38 to 56 –20.0 to +2.0 mA IO3 GRID1 to 3 –10.0 to +20.0 mA IO4 DIM OUT, SYNC OUT1, SYNC OUT2 –2.0 to +2.0 mA RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Driver Supply Voltage VDISP — 8.0 13.0 18.0 V Logic Supply Voltage VDD — 4.5 5.0 5.5 V High Level Input Voltage VIH All inputs except OSC0 0.8VDD — — V Low Level Input Voltage VIL All inputs except OSC0 — — 0.2VDD V Clock Frequency fC — — — 2.0 MHz Oscillation Frequency fOSC R = 10 k 5%, C = 27 pF 5% 2.2 3.3 4.4 MHz Frame Frequency fFR R = 10 k 5%, C = 27 pF 5% 1/3 Duty 179 269 358 Hz 1/2 Duty 268 403 538 Hz Operating Temperature TOP — –40 — +105 °C 6/19 FEDL9213-01 1Semiconductor ML9213 ELECTRICAL CHARACTERISTICS DC Characteristics Ta = –40 to +105°C, VDISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Symbol Applied pin Condition Min. Max. Unit High Level Input Voltage Parameter VIH *1) — 0.8VDD — V Low Level Input Voltage VIL *1) — — 0.2VDD V High Level Input Current IIH *1) VIH = VDD –1.0 +1.0 A Low Level Input Current IIL *1) VIL = GND –1.0 +1.0 A VDISP–0.8 — V VDISP–0.8 — V IOH3 = –5 mA VDISP–0.8 — V IOH4 = –200 A VDD–0.8 — V — 2.0 V High Level Output Voltage Low Level Output Voltage Supply Current VOH1 SEG1-37 VOH2 SEG38-56 VOH3 GRID1-3 IOH1 = –5 mA VDISP = 9.5 V IOH2 = –10 mA VOH4 *2) VOL1 SEG1-37 IOL1 = 500 A VOL2 SEG38-56 VDISP = 9.5 V IOL2 = 500 A — 2.0 V VOL3 GRID1-3 IOL3 = 10 mA — 2.0 V VOL4 *2) IOL4 = 200 A — 0.8 V IDISP VDISP R=10 k ±5%,C=27 pF ±5%, — 100 A IDD VDD no load — 5.0 mA VDD = 4.5V VDD = 4.5 V *1) CS, CLOCK, DATA IN, DIM IN, SYNC IN1, SYNC IN2, M/S, DUP/TRI *2) DIM OUT, SYNC OUT1, SYNC OUT2 AC Characteristics Ta = –40 to +105°C, VDISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter Symbol Condition Min. Max. Unit Clock Frequency fC — — 2.0 MHz Clock Pulse Width tCW — 200 — ns Data Setup Time tDS — 200 — ns Data Hold Time tDH — 200 — ns CS Off Time tCSL — 20 — s CS Setup Time (CS–Clock) tCSS — 200 — ns CS Hold Time (Clock–CS) tCSH — 200 — ns CS Wait Time tRSOFF — 400 — s — 2.0 s Output Slew Rate Time tR CL = 100 pF tR = 20% to 80% — 2.0 s VDD Rise Time tPRZ Mounted in a unit — 100 s VDD Off Time tPOF Mounted in a unit, VDD = 0.0 V 5.0 — ms tF tF = 80% to 20% 7/19 FEDL9213-01 1Semiconductor ML9213 TIIMING DIAGRAM N Data Input Timing tCSL CS tCSS tCSH 1/fC tCW tCW –0.2VDD tDH VALID DATA IN –0.2VDD –0.8VDD CLOCK tDS –0.8VDD VALID VALID –0.8VDD VALID –0.2VDD N Reset Timing VDD tPRZ –0.8VDD tPOF –0.0 V tRSOFF –0.8VDD CS –0.0 V N Driver Output Timing SEG1-56, GRID1-3 tR tF tR –0.8VDISP –0.2VDISP 8/19 FEDL9213-01 1Semiconductor ML9213 N Output Timing (Duplex Operation) *1 bit time = 4/fOSC Solid line: Indicates that the anode dimming data is 1016/1024 in the master mode. Chain line: Indicates that the anode dimming data is 64/1024 in the master mode. N Output Timing (Triplex Operation) *1 bit time = 4/fOSC Solid line: Indicates that the anode dimming data is 1016/1024 in the master mode. Chain line: Indicates that the anode dimming data is 64/1024 in the master mode. 9/19 FEDL9213-01 1Semiconductor ML9213 FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, the ML9213 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: N The contents of the shift registers and latches are set to “0”. N The anode dimming duty cycle is set to “0”. N All segment outputs (SEG1 to 56) are set to Low level. N The GRID1 output is set to Low level. N The GRID2 and GRID3 outputs are set to High level. Data Transfer Method Data can be transferred between the rising edge and the next falling edge of chip select input. The mode data, segment data and anode dimming data are written by a serial transfer method. The serial data is input to the shift register at the rising edge of a shift clock pulse. The mode data (M0 to M2) must be transferred after the segment data and anode dimming data succeedingly. When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the latches. Set the shift clock to a High level except during data transfer. CS CLOCK M0 M1 M2 DATA IN Segment data or dimming data Mode data Function Mode Function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as follows: FUNCTION MODE OPERATING MODE MODE DATA M0 M1 M2 0 Segment Data for GRID1-3 Input 0 0 0 1 Segment Data for GRID1 Input 1 0 0 2 Segment Data for GRID2 Input 0 1 0 3 Segment Data for GRID3 Input 1 1 0 4 Digital Dimming Data Input 0 0 1 10/19 FEDL9213-01 1Semiconductor ML9213 Segment Data Input [Function Mode: 0 to 3] N ML9213 receives the segment data when function mode 0 to 3 are selected. N The same segment data is transferred to the 3 segment data latches corresponding to GRID1 to 3 at the same time when the function mode 0 is selected. N The segment data is transferred to only one segment data latch corresponding to the specified GRID when the function mode is 1, 2 or 3 is selected. N Segment output (SEG1 to 56) becomes High level (lighting) when the segment data (S1 to S56) is set to “1”. [Data Format] Input Data : 59 bits Segment Data: 56 bits Mode Data : 3 bits Bit 1 2 3 4 ………. 53 54 55 56 57 58 59 Input Data S1 S2 S3 S4 ………. S53 S54 S55 S56 M0 M1 M2 Segment Data (56 bits) Mode Data (3 bits) [Bit correspondence between segment output and segment data] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 Segment output 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 Segment output Segment data Segment output Segment data Segment output Segment data 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 49 50 51 52 53 54 55 56 --- --- --- --- --- --- --- --- S49 S50 S51 S52 S53 S54 S55 S56 --- --- --- --- --- --- --- --- 11/19 FEDL9213-01 1Semiconductor ML9213 Anode Dimming Data Input [Function Mode: 4] N ML9213 receives the anode dimming data when function mode 4 is selected. N The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. N The 10-bit anode dimming data is input from LSB. [Data Format] Input Data : 13 bits Anode Dimming Data : 10 bits Mode Data : 3 bits Bit Input Data 1 2 3 4 5 6 7 8 9 10 11 12 13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 M0 M1 M2 LSB MSB Digital Dimming Data (10bits) (LSB) Mode Data (3bits) Dimming Data (MSB) Duty Cycle D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 Master Mode Master Mode is selected when M/S pin is set at High level. The master mode operation is as follows: N Input to DIM IN, SYNC IN1 and SYNC IN2 is ignored, and these pins should be connected to L-GND or VDD. N The pulse width of SEG1 to SEG56 is controlled by the internal digital dimming circuit. N The segment data corresponding to GRID1 to 3 is selected by the internal timing generator. 12/19 FEDL9213-01 1Semiconductor ML9213 Slave Mode Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows: N Output from internal anode dimming circuit is ignored. Connect the DIM IN, SYNC IN1 and SYNC IN2 pins to the master side DIM OUT, SYNC OUT1 and SYNC OUT2 pins respectively. N The pulse width of SEG1 to 56 is controlled by the pulse width of DIM IN signal. N The segment data corresponding to GRID1 to 3 is selected by combinations of the SYNC IN1 and SYNC IN2 signals. N The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC OUT1 and SYNC OUT2 are set at Low level. [Correspondence between SYNC IN1, 2 and GRID1 to 3] [Correspondence between DIM IN and SEG1 to 56] SYNC IN 1 SYNC IN 2 Segment Latch GRID DIM IN SEG1 to 56 0 0 No No 0 Low 1 0 Latch1 GRID1 1 High 0 1 Latch2 GRID2 1 1 Latch3 GRID3 Note: Low: Lights OFF High: Lights ON 13/19 ML9213 (MASTER) SEG56 VDD VDISP VDD DUP/TRI GRID1 M/S GRID2 M/S GRID2 Microcontroller SYNC IN1 DIM IN CS DATA IN CLOCK SYNC IN2 VDD SYNC IN1 DIM IN CS DATA IN CLOCK SYNC OUT2 SYNC OUT1 DIM OUT L-GND S110 S111 S112 S1 S2 S3 G1 Duplex VFD Tube G2 Ef R OSC0 GND GRID3 GND SYNC OUT2 SYNC OUT1 DIM OUT R C SEG56 GRID1 GRID3 VDD VDD SEG1 DUP/TRI SYNC IN2 GND VDISP ML9213 (SLAVE) 1Semiconductor VDD SEG1 APPLICATION CIRCUITS VDISP 1. Circuit for the duplex VFD tube (2-Grid K 112-Anode) VDD OSC0 D-GND C L-GND D-GND GND GND FEDL9213-01 ML9213 14/19 VDD Microcontroller VDD SEG1 GND SEG1 SEG56 SEG56 GRID1 M/S GRID1 DUP/TRI GRID2 DUP/TRI GRID2 GRID3 SYNC OUT2 SYNC OUT1 DIM OUT GND VDD SYNC IN2 SYNC IN1 DIM IN CS DATA IN CLOCK GRID3 SYNC OUT2 SYNC OUT1 DIM OUT OSC0 L-GND S110 S111 S112 S1 S2 S3 G1 G2 Triplex VFD Tube G3 Ef R R C VDISP ML9213 (SLAVE) M/S SYNC IN2 SYNC IN1 DIM IN CS DATA IN CLOCK GND VDD 1Semiconductor VDD VDISP VDISP ML9213 (MASTER) 2. Circuit for the triplex VFD tube (3-Grid K 112-Anode) VDD OSC0 D-GND C L-GND D-GND GND GND FEDL9213-01 ML9213 15/19 FEDL9213-01 1Semiconductor ML9213 NOTES ON TURNING POWER ON/OFF N Connect L-GND and D-GND externally to be an equal potential voltage. N To avoid wrong operations, turn on the driver power supply after turning on the logic power supply. Conversely, turn off the logic power supply after turning off the driver power supply. [Voltage] VDISP VDD [Time] 16/19 FEDL9213-01 1Semiconductor ML9213 PACKAGE DIMENSIONS (Unit: mm) QFP80-P-1420-0.80-BK Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 1.27 TYP. 4/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/19 FEDL9213-01 1Semiconductor ML9213 (Unit: mm) QFP80-P-1414-0.65-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.85 TYP. 3/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 FEDL9213-01 1Semiconductor ML9213 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 19/19