E2C0020-29-53 ¡ Semiconductor MSC1209 ¡ Semiconductor This version: May 1999 MSC1209 Previous version: Nov. 1997 42-Bit Vacuum Fluorescent Display Tube Driver with Digital Dimming Function GENERAL DESCRIPTION The MSC1209 is a Bi-CMOS display driver for a 1/2-duty vacuum fluorescent display tube. The MSC1209 consists of an 84-bit shift register, an 84-bit latch circuit, a 10-bit digital dimming circuit, 42-bit segment drivers, a 2-bit grid circuit, and a cascade control circuit. The MSC1209 is interfaced with a microcontroller by using three signal lines of LOAD, CLOCK, and DATA. The cascaded MSC1209 ICs can share LOAD, CLOCK, and DATA. FEATURES • Power supply voltage: 8V to 18V (Built-in 5V regulator for logic) • Operating temperature range: –40 to +105°C • Driving 42 segments directly: VOH=VDD–0.5V at IOH=–3.0mA (VDD=15.0V) • Built-in digital dimming circuit 10-bit resolution Programmable in the duty range of 0/2048 (0%) to 1016.5/2048 (49.6%) • 3 interfaces with microcontroller: LOAD, CLOCK, DATA • Cascade connection available (The cascaded MSC1209 ICs can share LOAD, CLOCK, and DATA.) • Built-in oscillation circuit with an external capacitor (a single pin is used) • Built-in power-on reset circuit • Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSC1209GS-2K) 1/15 ¡ Semiconductor MSC1209 BLOCK DIAGRAM GRID1 GRID2 SEG1 2-bit Grid Driver SEG42 42-bit Segment Driver VDD Voltage Regulator VSS VDD=8 to 18V Level Shifter 5V POR 5V BLANK VCC=5.0V (Regulator) Timing Generator Multiplexer MODEA POR OSC SEL 10-bit Digital Dimming OSC POR 84-bit Latch L L 10-bit Latch 84 bits MODEB LOAD LOAD Timing Control 10-bits (Q1 to Q10) POR DATA CLOCK D 2-bit S/R D Q1-Q84 84-bit Shift Register 2/15 ¡ Semiconductor MSC1209 INPUT AND OUTPUT CONFIGURATION • Schematic Diagram of Logic Portion Input • Schematic Diagram of Logic Portion Input Circuit 1 Circuit 2 VDD VDD (5V Reg.) (5V Reg.) SEL INPUT VSS VSS VSS VSS • Schematic Diagram of Logic Portion Output • Schematic Diagram of Driver Output Circuit Circuit (5V Reg.) VDD OUTPUT OUTPUT VSS VSS VSS VSS 3/15 ¡ Semiconductor , MSC1209 56 55 54 53 52 51 50 49 48 47 46 45 44 43 SEG 3 SEG 2 SEG 1 SEL MODEB LOAD CLOCK NC DATA VSS MODEA OSC BLANK GRID2 PIN CONFIGURATION (TOP VIEW) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GRID1 VDD SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SEG 6 SEG 7 SEG 8 SEG 9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 NC SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG 4 SEG 5 NC: No connection 56-Pin Plastic QFP 4/15 ¡ Semiconductor MSC1209 PIN DESCRIPTION Pin Symbol 48 DATA I Microcontroller Serial data input. (Positive logic) Receives display data and dimming data. 50 CLOCK I Microcontroller Shift clock input. Serial data is shifted on the rising edge of this shift clock pulse. 51 LOAD I Microcontroller Load pulse input. The load signal is input when the transfer of serial data is completed. O Anode electrode of VFD tube Segment driver output. O Grid electrode of VFD tube Grid driver output. When this pin is set to "L", the display goes on. Connect an external PNP transistor to this pin. The segment data of the first bit (S1) to the 42nd bit (S42) is valid in the 84-bit segment data. Grid driver output. When this pin is set to "L", the display goes on. Connect an external PNP transistor to this pin. The segment data of the 43rd bit (S43) to the 84th bit (S84) is valid in the 84-bit segment data. 1 to 20, 22 to 40, SEG1 to SEG42 54 to 56 42 GRID1 Type Connected to Description 43 GRID2 O Grid electrode of VFD tube 44 BLANK I — Input with pull-up resistor for display blank. When this pin is set to "L", the display goes off. (SEGn="L") — Input and output for oscillation. Connect an external capacitor of 68pF. 45 68pF The typical value of oscillating frequency is 512kHz. 45 OSC I/O These pins specify the operating mode. 46 MODEA I 52 — MODEB MODEA 0 1 0 1 MODEB 0 0 1 1 Operating Mode Master Operation Test Mode Slave Operation Slave Operation SEL pin of the master IC outputs switching signals for the segment data that corresponds to the grid signals. The SEL pin of the master IC is connected to the MODEA pin of the slave IC. 53 SEL O MODEA pin at slave side 41 VDD — Power source Power supply pin (8V to 18V). 47 VSS — Power source GND pin. (Ground) 5/15 ¡ Semiconductor MSC1209 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD — –0.3 to +20 V Input Voltage VIN –0.3 to +6.0 Power Dissipation PD All input pins Ta≥25°C 257 V mW TSTG — –65 to +150 °C Storage Temperature RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage VDD "H" Input Voltage "L" Input Voltage VIH VIL "H" Driver Output Current IO–1 IO–2 CLOCK Frequency Condition Min. Typ. Max. Unit — 8.0 — 18.0 V All input pins other than OSC All input pins other than OSC 3.8 –0.3 — — 5.5 +0.8 V V VDD=10.8V, 1 driver at the ON state VDD=10.8V, all drivers at the ON state — — — — –2.2 –92.4 mA mA fC — — — 1.0 MHz Oscillation Frequency Grid Frequency fOSC fGRID C=68pF C=68pF 307.2 150 512 250 716.8 350 kHz Hz Operating Temperature TOP — –40 — +105 °C 6/15 ¡ Semiconductor MSC1209 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Unless otherwise specified: Ta=–40 to +105°C, VDD=8.0 to 18.0V Condition Min. Max. Unit Applied pin Symbol "H" Input Voltage "L" Input Voltage VIH VIL — — 3.8 –0.3 5.5 +0.8 V "H" Input Current IIH1 VDD=18.0V, VIH1=5.0V –1.0 +1.0 mA All input pins other than BLANK IIH2 VDD=18.0V, VIH2=5.0V –60 +60 mA IIL1 VDD=18.0V, VIL1=0.0V –1.0 +1.0 mA BLANK All input pins other than BLANK IIL2 VDD=18.0V, VIL2=0.0V –500 –100 mA BLANK VOH1 VOH2 VDD=9.5V, IOH1=–2.0mA VDD=12.0V, IOH2=–2.5mA VDD–0.5 VDD–0.5 — — V V SEG1 to 42 VOH3 VOH4 VDD=15.0V, IOH3=–3.0mA VDD=9.5V, IOH4=–0.8mA VDD–0.5 VDD–0.5 — — V V VOH5 VDD=12.0V, IOH5=–1.0mA 4.0 — V SEL VOL1 VOL2 VDD=9.5V, IOL1=500mA VDD=9.5V, IOL2=200mA — — 4.0 2.0 V V SEG1 to 42 VOL3 VOL4 VDD=9.5V, IOL3=1.0mA VDD=9.5V, IOL4=500mA — — 4.0 2.0 V V VOL5 VDD=9.5V, IOL5=200mA — 1.0 V VOL6 VDD=12.0V, IOL6=1.0mA — 1.0 V SEL IDD fOSC=512kHz, no load — 20 mA VDD–VSS "L" Input Current "H" Output Voltage "L" Output Voltage Supply Current All input pins V GRID1 to 2 AC Characteristics (Ta=–40 to +85°C, VDD=8 to 18V) Parameter CLOCK Frequency CLOCK Pulse Width Symbol Condition Min. Max. Unit fC(1/tCLOCK) — — 1.0 MHz tCW — 400 — ns tCR/tCF — — 300 ns DATA Setup Time tDS — 200 — ns DATA Hold Time tDH — 200 — ns CLOCKÆ LOAD Time tCL — 100 — ns LOADÆ CLOCK Time tLC — 100 — ns CLOCK Rise/Fall Time LOAD Pulse Width tLW — 1.0 — ms SEGn Rise/Fall Time tR/tF CL=50pF — 1.0 ms SEL Rise/Fall Time tR/tF CL=50pF — 1.0 ms VDD-DATA Input Time at VDD ON fPDA When mounted in a unit 300 — ms VDD-Hold Time at VDD OFF fPDF When mounted in a unit 5.0 — ms VDD Rise Time at VDD ON fPR2 — — 100 ms 7/15 ¡ Semiconductor MSC1209 TIMING DIAGRAM 1) Data Timing tCR 0.8V tCF tCLOCK tCL CLOCK tDS DATA 3.8V tLW SEL tLC tCW 3.8V tCW 0.8V tDH VALID VALID VALID 3.8V VALID 0.8V 2) Reset Timing VDD 80%VDD tPOF tPRZ 0.0V tPDA 3.8V DATA 0.8V 3) Output Timing SEGn, GRIDn tR tF 0.8VDD 0.2VDD SEL t R tF 4.0V 1.0V 8/15 ¡ Semiconductor MSC1209 FUNCTIONAL DESCRIPTION DATA Input This device uses 10-bit dimming data (D1 to D10) and 84-bit segment data (S1 to S84). To transfer these data, the mode bits (M0 and M1) must be sent after each of these data succeedingly. The data transfer timing diagram is shown below. DATA D1 D2 D10 M0 M1 S1 S2 S83 S84 M0 M1 CLOCK LOAD Figure 1 Data Transfer Timing M0 : Enable bit M0 = "0": Indicates the data from the master IC. M0 = "1": Indicates the data from the slave IC. M1 : Mode specification bit M1 = "1": Indicates that the data sent on ahead is dimming data. M1 = "0": Indicates that the data sent on ahead is segment data. D1 : LSB of dimming data S1 : data for GRID1 of SEG1 S2 : data for GRID1 of SEG2 : S42 : data for GRID1 of SEG42 S43 : data for GRID2 of SEG1 : S84 : data for GRID2 of SEG42 Notes: 1. When the number of input data bits are larger, the data bits are pushed out in the same order that they are input, and 86 bits of the data counted from the bit entered last are used as valid data. (In the case of segment data) 2. When the number of input data bits are smaller, the data remaining in the shift register before data transfer is shifted and used as valid data. CLOCK Input Data is shifted at the rising edge of the clock. LOAD Input The contents of the shift register are shifted in while the LOAD input is "H" level and latched at "H" to "L" transition. This LOAD signal is regenerated in the VFD tube driver for the latch pulse for dimming data and segment data. When 10-bit dimming data and 84-bit segment data have been transferred, input the LOAD signal prior to the next clock. 9/15 ¡ Semiconductor MSC1209 Blank Function Inputting a "L" level to the BLANK pin turns display off (segment output = "L"). At this time, grid outputs are output normally. Initial Setting When power is turned on (i.e., when segment data has never been transferred), the display is turned off (segment output = "L"). Display is turned on at the moment when transfer of the segment data is complete. The relationship between the data transfer and display is shown in Figure 2. VDD Dimming Data DATA Segment Data LOAD Display OFF SEGn Display ON Figure 2 Relationship Between Data Transfer and Display If, after power-on, the segment data is transferred before the dimming data is transferred, display is turned on at the moment when transfer of the segment data is complete, at which time the dimming value is undefined. The relationship between the data transfer and display is shown in Figure 3. VDD DATA Segment Data LOAD SEGn Dimming Data Undefined Dimming Value Display OFF Display ON Figure 3 Relationship Between Advanced Transfer of Segment Data and Display 10/15 ¡ Semiconductor MSC1209 Oscillator Connect an external capacitor (C), as shown in Figure 4. The oscillating frequency fOSC depends on the external capacitor used. The following equation is true between fOSC and grid frequency (fGRID): fGRID = fOSC/2048 OSC Pin fOSC C (68pF) Figure 4 Oscillator Equivalent Circuit Dimming Function The duty cycle of grid output can be changed in 1/2048 step with respect to 10-bit dimming data. Table 1 shows the relationship between dimming data and duty ratio. Table 1 Dimming Data and Duty Ratio 00 00 0000 0000 0000 0001 0/2048 1/2048 1015/2048 1016/2048 1016.5/2048 ~ 0111 1000 1001 ~ 1111 1111 1111 ~ 11 11 11 ~ ~ Duty Ratio ~ (LSB) ~ Dimming Data ~ (MSB) 11 1111 1110 1016.5/2048 Max Ø Max Note: Setting for address 3FFH is invalid. Duty ratios are programmable within the range of 0/2048 (0%) to 1016.5/2048 (49.6%). Figure 5 shows the grid output timing. Cascade Connection When two MSC1209 ICs are used in cascade connection, use the MODEA and MODEB pins to connect them, as shown below. MSC1209 (Master) MODEA MODEB OSC MSC1209 (Slave) SEL MODEA 5V SEL OPEN MODEB OSC 11/15 ¡ Semiconductor MSC1209 The IC where the MODEA and MODEB pins are set to "L" operates as the master, and the one where the MODEB pin is set to "H" as the slave. By connecting the master side SEL output pin to the slave side MODEA pin, the segments on the slave side operate in synchronization with the grid on the master side. 12/15 ¡ Semiconductor MSC1209 GRID Output Timing tFOSC tGRID (fOSC) SEGn S43 - S84 tBLANK1 tBLANK2 S1 - S42 S43 - S84 SEL * Dimming Data; 3FE[H] to 3F9[H] GRID1 GRID2 Display OFF Display ON Display ON Display OFF Display ON Display OFF * Dimming Data; 3F8[H] GRID1 GRID2 Display OFF Display ON Display ON Display OFF Display ON Display OFF * Dimming Data; 002[H] GRID1 GRID2 Display OFF ON Display OFF Display OFF ON ON * Dimming Data; 001[H] GRID1 GRID2 Display OFF ON ON Display OFF Display OFF ON * Dimming Data; 000[H] GRID1 Display OFF GRID2 Display OFF tFOSC = 2ms Typical tGRID = 2048tFOSC tBLANK1 = 2tFOSC, tBLANK2 = 5.5tFOSC Figure 5 Dimming Data and Duty Ratio 13/15 ¡ Semiconductor MSC1209 APPLICATION CIRCUIT * When one MSC1209 IC is used (SEG1 to 42) ¥ 1 SEG1 CPU LOAD CLOCK DATA MODEA MODEB OSC VSS SEG42 GRID1 GRID2 VF Display Tube SEL VDD * When two MSC1209 ICs are used (SEG1 to 42) ¥ 2 SEG1 CPU LOAD CLOCK DATA MODEA MODEB OSC VSS SEG42 GRID1 GRID2 SEG1 SEG42 LOAD CLOCK DATA GRID1 GRID2 VF Display Tube MODEA SEL 5V MODEB OSC VDD VSS VDD 14/15 ¡ Semiconductor MSC1209 PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/15 E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. 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