MP7611 Octal 14-Bit DAC ArrayTM D/A Converter with Output Amplifier and Parallel Data/Address mP Control Logic June 1998-3 FEATURES · Rugged Construction -- Latch-Up Free · Serial Version: MP7610 · Eight Independent Channel 14-Bit DACs with Output Amplifiers · Low Power 320 mW (typ.) · Parallel Digital Data and Address Port · Double Buffered Data Interface · Readback of DAC Latches · Zero Volt Output Preset (Data = 10 .. 00) · 14-Bit Resolution, 12-Bit Accuracy · Extremely Well Matched DACs · Extremely Low Analog Ground Current (<60mA/Channel) · +10 V Output Swing with +11.4 V Supplies APPLICATIONS · · · · · · · Data Acquisition Systems ATE Process Control Self-Diagnostic Systems Logic Analyzers Digital Storage Scopes PC Based Controller/DAS GENERAL DESCRIPTION The MP7611 provides eight independent 14-bit resolution Digital-to-Analog Converters with voltage output amplifiers and a parallel digital address and data port. Built using an advanced linear BiCMOS, these devices offer rugged solutions that are latch-up free, and take advantage of EXAR’s patented thin-film resistor process which exhibits excellent long term stability and reliability. A standard m-processor and TTL/CMOS compatible 14-bit input data port loads the data into the pre-selected DACS. This device can easily be interfaced to a data bus, and digital readback of each channel is available. Typical DAC matching for C grade versions is 1.5 LSB across all codes. The output amplifier is capable of sinking and sourcing 5mA, and the output voltage settles to 12-bits in less than 30ms (typ.). ORDERING INFORMATION Package Type Temperature Range Part No. Res. (Bits) INL (LSB) DNL (LSB) FSE (LSB) PQFP 0 to +70°C MP7611CE 14 ¦2 ¦2 ¦16 PQFP --40 to +85°C MP7611BE 14 ¦4 ¦3 ¦24 PQFP --40 to +85°C MP7611AE 14 ¦8 ¦4 ¦32 PLCC 0 to +70°C MP7611CP 14 ¦2 ¦2 ¦16 PLCC --40 to +85°C MP7611BP 14 ¦4 ¦3 ¦24 PLCC --40 to +85°C MP7611AP 14 ¦8 ¦4 ¦32 Rev. 3.01 E1998 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017 MP7611 SIMPLIFIED BLOCK DIAGRAM RB0 Bus I/O 14 D0 - D13 VRP D Q LAT0B XR XE D Q LAT0A XRXE 14 14 VRN XE0 A0 - A2 LD1 RD CS R1 3 Control Logic + -- VO0 + -- VO7 RB7 8 XE0 - XE7 8 VRP RB0 - RB7 D Q LAT7A XR XE D Q LAT7B XR XE 14 LD2 VRP VRP VEE VCC VCC AGND AGND VREF DAC7 VRN XE7 R2 VEE DAC0 -+ VRN DGND DVDD PIN CONFIGURATIONS 33 23 1 34 22 See the following page for pin numbers and descriptions See the following page for pin numbers and descriptions Index 44 12 1 11 44-Pin PQFP (14 mm x 14 mm) 44-Pin PLCC Rev. 3.01 2 VREFN MP7611 PIN OUT DEFINITIONS PLCC PIN NO. PQFP PIN NO. 29 1 NAME DESCRIPTION N/C No Connection 30 2 VO3 DAC 3 Output 31 3 VEE Analog Negative Power Supply (--12 V) 32 4 VCC Analog Positive Power Supply (+12 V) 33 5 N/C No Connection or DVDD 34 6 VREF Analog Voltage Reference Input (+5 V) 35 7 VREFN Analog Negative Voltage Reference Output (--2.5 V) 36 8 VCC Analog Positive Power Supply (+12 V) 37 9 VEE Analog Negative Power Supply (--12 V) DAC 4 Output 38 10 VO4 39 11 N/C No Connection 40 12 VO5 DAC 5 Output 41 13 VO6 DAC 6 Output 42 14 VO7 DAC 7 Output 43 15 AGND Analog Ground ( 0 V) 44 16 CS Chip Select Enable 1 17 RD Read Back Enable 2 18 R2 Second--Latch-Bank Reset Enable 3 19 R1 First--Latch-Bank Reset Enable 4 20 LD2 Second--Latch-Bank Load Enable 5 21 LD1 First--Latch-Bank Load Enable 6 22 A2 Digital Address Bit 2 7 23 A1 Digital Address Bit 1 8 24 A0 Digital Address Bit 0 9 25 DB0 Digital Input Data Bit 0 10 26 DB1 Digital Input Data Bit 1 11 27 DB2 Digital Input Data Bit 2 12 28 DB3 Digital Input Data Bit 3 13 29 DB4 Digital Input Data Bit 4 14 30 DB5 Digital Input Data Bit 5 15 31 DB6 Digital Input Data Bit 6 16 32 DB7 Digital Input Data Bit 7 17 33 DB8 Digital Input Data Bit 8 18 34 DB9 Digital Input Data Bit 9 19 35 DB10 Digital Input Data Bit 10 20 36 DB11 Digital Input Data Bit 11 21 37 DB12 Digital Input Data Bit 12 22 38 DB13 Digital Input Data Bit 13 (MSB) 23 39 DVDD Digital Positive Power Supply (+5 V) 24 40 DGND Digital Ground (0 V) 25 41 AGND Analog Ground (0 V) 26 42 VO0 DAC 0 Output 27 43 VO1 DAC 1 Output 28 44 VO2 DAC 2 Output Rev. 3.01 3 MP7611 ELECTRICAL CHARACTERISTICS VCC = +12 V, VEE = --12 V, VREF = 5 V, DVDD = 5.0 V, T = 25°C, Output Load = 5kW (unless otherwise noted) Parameter Symbol Min N 14 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) A B C INL Differential Non-Linearity A B C DNL Positive Full Scale Error A B C +FSE Positive Full Scale Error D+FSE/ DT Temperature Coefficient --FSE Negative Full Scale Error D--FSE/ DT ZOFS Bipolar Zero Offset DZOFS/ DT INL Matching A B C All Channels Maximum Error with DAC 0 adjusted to minimum error A B C Bipolar Zero Matching A B C Full Scale Error Matching A B C ¦8 ¦4 ¦2 ¦8 ¦4 ¦2.5 ¦4 ¦3 ¦2 ¦4 ¦3 ¦2.5 ¦32 ¦24 ¦16 ¦32 ¦24 ¦16 End Point Linearity Spec LSB LSB 4 ppm/°C 0°C to 85°C LSB 24 16 12 Bipolar Zero Offset A B C Temperature Coefficient LSB 24 16 12 Negative Full Scale Error A B C Temperature Coefficient Bits ¦32 ¦24 ¦16 ¦32 ¦24 ¦16 4 ppm/°C 0°C to 85°C LSB ¦16 ¦12 ¦12 ¦16 ¦12 ¦12 2 ppm/°C DINL LSB ¦8 ¦6 ¦6 ¦8 ¦6 ¦6 ME LSB ¦16 ¦8 ¦6 ¦16 ¦8 ¦6 ¦16 ¦12 ¦12 ¦16 ¦12 ¦12 ¦16 ¦12 ¦12 ¦16 ¦12 ¦12 DZOFS LSB DFSE LSB Rev. 3.01 4 0°C to 85°C MP7611 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter 25°C Typ Max Tmin to Tmax Min Max tsd 30 50 50 CT Q PSRR 0.04 --70 5 Symbol Min Units Test Conditions/Comments DYNAMIC PERFORMANCE Voltage Settling from LD to VDAC Out1 Channel-to-Channel Crosstalk6 Digital Feedthrough1, 6 Power Supply Rejection Ratio ms LSB dB ppm/% ZS to FS (20 V Step) 5k, 50pF load DC CLK and Data to VOUTi DVEE & DVCC = +5%, ppm of FS REFERENCE INPUTS Impedance of VREF REF 350 VREF Voltage1, 2 VREF 3.5 VIH VIL IL CL 2.4 700 1.05k 350 1.05k 6 W See Application Hints for driving the reference input V DIGITAL INPUTS3 Logic High Logic Low Input Current Input Capacitance1 V V mA pF 0.8 +10 8 ANALOG OUTPUTS Output Swing Output Drive Current VREFN Output Drive Current Output Impedance Output Short Circuit Current --VEE +1.4 --5 --10 VCC --1.4 RO ISC 1 25 30 40 55 V mA mA W mA mA mA mA VOH VOL 4.5 0.5 V V 5 +10 For test purposes only +FS to AGND +FS to VEE --FS to AGND --FS to VCC DIGITAL OUTPUTS Output High Voltage Output Low Voltage POWER SUPPLIES VCC Voltage5 VEE Voltage5 DVDD Voltage Positive Supply Current Negative Supply Current Digital Supply Current Power Dissipation VCC VREF+1.5 12 VEE --12.75 --12 DVDD 4.5 5 ICC 8 IEE 15 IDD PDISS 320 12.75 --5 5.5 10 20 2 420 VREF+1.5 12.75 --12.75 --5 4.5 5.5 10 20 2 450 V V V mA mA mA mW Bipolar zero Bipolar zero Bipolar zero Bipolar zero mA See Application Notes ANALOG GROUND CURRENT Per Channel1 IAGND ±60 DIGITAL TIMING SPECIFICATIONS1,4 Data Setup Time Data Hold Time Address Set-up Time Address Hold Time Chip Select to LD1 Set-up Time Chip Select to LD1 Hold Time LD1 Pulse Width LD1 Negative Edge to LD2 Positive Edge LD2 Pulse Width Chip Select to RD Set-Up Time Chip Select to RD Hold Time VIL = 0 V, VIH = 5 V, CL = 20 pF tDS tDH tAS tAH tLD1W tLD1LD2 20 20 100 0 6 0 50 60 ns ns ns ns ns ns ns ns tLD2W tCS2 tCH2 60 6 0 ns ns ns tCS1 tCH1 Rev. 3.01 5 MP7611 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min tRD tDA tDR 600 600 200 100 100 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments DIGITAL TIMING SPECIFICATIONS1, 4 (CONT’D) RD Pulse Width High Z to Data Valid for Readback Data Valid for Readback to High Z R1 Pulse Width R2 Pulse Width tR1W tR2W ns ns ns ns ns NOTES: 1 Guaranteed; not tested. 2 Specified values guarantee functionality. 3 Digital inputs should not go below digital GND or exceed DVDD supply voltage. 4 See Figures 1, 2 and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level. 5 For power supply values < ¦2£VREF, the output swing is limited as specified in Analog Outputs. 6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +.5 V DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --.5 V Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . . --40°C to +85°C Military . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to +125°C Maximum Junction Temperature . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . --65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . +300°C Package Power Dissipation Rating to 75°C PQFP, PGA, PLCC . . . . . . . . . . . . . . . . . . 800mW Derates above 75°C . . . . . . . . . . . . . . . . 11mW/°C VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +16.5 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . --16.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V Analog Outputs & Inputs Infinite Shorts to VCC, VEE, DVDD, AGND and DGND (provided that power dissipation of the package spec is not exceeded) AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality guaranteed for ¦0.5 V only) Digital Input & Digital Output Voltage to: NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. APPLICATION NOTES NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog ground connection. The difference between the DGND and AGND should be limited to ¦300 mV to assure normal operation. If there is any chance that the AGND to DGND can be greater than ¦1 V, we recommend two back-to-back diodes be used between DGND and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may help reduce noise induced from long lead or trace lengths. Rev. 3.01 6 MP7611 Data Input/Output Bus 1 Address A0-A2 1 0 0 Chip Select CS 1 Load Latch A LD1 1 Load Latch B LD2 1 Analog Output tDS tDH tAH tAS tCH1 don’t care 0 tCS1 don’t care tLD1W 0 tLD1LD2 0 tLD2W +FS --FS tSD Figure 1. Loading Latch A and Updating Latch B Notes: (1) Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable in the above diagram. (2) R1 = R2 = 1. (3) For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode). Address A0-A2 1 0 Chip Select CS 1 0 Data Readback RD 1 0 Digital Output Data D0 to D113 1 0 tAS tAH don’t care don’t care tCS2 HIGH-Z tRD tCH2 tDR tDA HIGH-Z Figure 2. Read Back First Latch Bank of One DAC Notes: (1) Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable in the above diagram. (2) R1 = R2 = 1. R1 R2 tR1W 1 0 Reset first latch bank to 1000 . . . . .0000 1 0 Reset second latch bank to 1000 . . . . .0000 and analog output to zero volt. Figure 3. Reset Operations Rev. 3.01 7 tR2W MP7611 all 8-channels simultaneously. The selected DAC becomes transparent (activity on the digital inputs appear at the analog output) when both LD1 = LD2 = 0. A standard m-processor and TTL/CMOS compatible input data port loads the data into the pre-selected DACS. If CS = 0, the chip accesses digital data on the bus. Then address bits A0 to A2 select the appropriate DAC and LD1 loads the data into the first-latch-bank. When all 8-channels first-latch-banks are loaded, then LD2 enables the second-latch-bank and updates Function R1 = 0 resets the first-latch-bank. R2 = 0 resets the secondlatch-bank which sets the analog output to zero volts (data = 100...00), regardless of digital inputs. A2 A1 A0 RD LD1 LD2 CS R1 R2 Load Latch 1 of DAC1 Load Latch 1 of DAC2 Load Latch 1 of DAC3 Load Latch 1 of DAC4 Load Latch 1 of DAC5 Load Latch 1 of DAC6 Load Latch 1 of DAC7 Load Latch 1 of DAC8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0®1 0®1 0®1 0®1 0®1 0®1 0®1 0®1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Load Latch 2 of DAC1®8 X X X 1 1 0®1 X 1 1 Read Latch 1 of DAC1 Read Latch 1 of DAC2 Read Latch 1 of DAC3 Read Latch 1 of DAC4 Read Latch 1 of DAC5 Read Latch 1 of DAC6 Read Latch 1 of DAC7 Read Latch 1 of DAC8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset Latch 1 of DAC1®8 Reset Latch 2 of DAC1®8 X X X X X X X X X X X X X X 0 1 1 0 Note: 1: High, 0: Low, X: Don’t Care Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table Note: For timing information see Electrical Characteristics Rev. 3.01 8 MP7611 3 A0 to A2 3-8 Decoder 8 8 To first latch bank enable LD1 8 8 CS To switches across the first latch bank for readback enable RD To second latch bank enable LD2 R1 To reset all first latch bank R2 To reset all second latch bank Figure 4. Simplified Parallel Logic Port Hex Code Binary Code Output Voltage = 2 · Vr (--1 + 2·D ) (Vr = +5 V) 16384 OOOO 00000000000000 10 · (--1 + 0) = --10 1FFF 01111111111111 2OOO 10000000000000 10 · (--1 +16384 ) = 0 2OO1 10000000000001 10 · (--1 +16386 ) = 1.22 mV 16384 3FFF 11111111111111 10 · (--1 +32766 ) = 9.99878 16382 ) = --1.22 mV 16384 10 · (--1 + 16384 16384 Table 2. MP7611 Ideal DAC Output vs. Input Code Note: See Electrical Characteristics for real system accuracy Rev. 3.01 9 MP7611 A0 to A15 16 3 AS mP Address Decoder A0 to A2 LD1 R DB0 to DB16 From System Reset R1 From System Reset R2 12 or 14 DB0 to DB11 or DB13 Figure 5. Parallel mP Interface Rev. 3.01 10 MP7611 PERFORMANCE CHARACTERISTICS 11 V 0V --11 V VOUT 2.5mV 0V --2.5mV VOUT Settling 50ms/Division Graph 1. Typical Output Settling Characteristic VREF = 5 V, RL = 5K, CL = 500pF Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the difference between the output and the ideal output. 14-BIT LSB 4 --4 0 CODE Graph 2. Linearity with VREF = 5 V, All DACs, All Codes Rev. 3.01 11 16384 MP7611 Graph 3. DAC 0 INL vs. VREF Graph 4. DAC 0 DNL vs. VREF 4 14-BIT LSB 14-BIT LSB 4 --4 0 CODE --4 16384 0 Graph 5. DAC 0 Linearity with VREF = 5 V, VOUT = ¦10 16384 Graph 6. DAC 0 Linearity with VREF = 4.5 V, VOUT = ¦9 14-BIT LSB 4 14-BIT LSB 4 --4 CODE 0 CODE --4 16384 Graph 7. DAC 0 Linearity with VREF = 4 V, VOUT = ¦8 0 CODE 16384 Graph 8. DAC 0 Linearity with VREF = 3.5 V, VOUT = ¦7 Rev. 3.01 12 MP7611 50 VOUT MP7610 Family 5k VO 500pF I CL 2mA CL = 500pF, 5nF, 50nF, 500nF Figure 6. Circuit for Determining Typical Analog Output Pulse Response 2.0mA I 0.0 400mV VO --400mV 200mV CL = 500pF CL = 5nF CL = 50nF CL = 500nF VOUT --200mV 0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms Graph 9. Typical Response of the MP7610 Family Analog Output to a Current Pulse with CL=500pF, 5nF, 50nF, 500nF (See Figure 9. above) Rev. 3.01 13 6.0ms MP7611 44 LEAD PLASTIC QUAD FLAT PACK (14 mm x 14 mm QFP) Rev. 1.00 D D1 33 23 34 22 D1 D 44 12 1 11 B A2 e C A Seating Plane a A1 L INCHES SYMBOL A MILLIMETERS MIN MAX MIN MAX 0.110 0.134 2.80 3.40 A1 0.010 0.014 0.25 0.35 A2 0.100 0.120 2.55 3.05 B 0.014 0.020 0.35 0.50 C 0.005 0.009 0.13 0.23 D 0.667 0.687 16.95 17.45 D1 0.547 0.555 13.90 14.10 e 0.039 BSC 1.00 BSC L 0.026 0.37 0.65 0.95 a 0° 7° 0° 7° Note: The control dimension is the millimeter column Rev. 3.01 14 MP7611 44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 C D D1 Seating Plane 45° x H1 45° x H2 A2 2 1 44 B1 D D1 B D 2 D3 e R D3 A1 A INCHES SYMBOL A MILLIMETERS MIN MAX MIN MAX 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 A2 0.020 ------. 0.51 ------ B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ. 12.70 typ. e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is the inch column Rev. 3.01 15 MP7611 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1998 EXAR Corporation Datasheet June 1998 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 3.01 16