MP7613 Octal 12-Bit DAC ArrayTM D/A Converter with Output Amplifier and Parallel Data/Address µP Control Logic FEATURES • Eight Independent Channel 12-Bit DACs with Output Amplifiers • Low Power 320 mW (typ.) • Parallel Digital Data and Address Port • Double Buffered Data Interface • Readback of DAC Latches • Zero Volt Output Preset (Data = 10 .. 00) • 12-Bit Resolution, 11-Bit Accuracy • Extremely Well Matched DACs • Extremely Low Analog Ground Current (<60µA/Channel) • +10 V Output Swing with +11.4 V Supplies • Rugged Construction – Latch-Up Proof • Serial Version: MP7612 APPLICATIONS • • • • • • • Data Acquisition Systems ATE Process Control Self-Diagnostic Systems Logic Analyzers Digital Storage Scopes PC Based Controller/DAS GENERAL DESCRIPTION The MP7613 provides eight independent 12-bit resolution Digital-to-Analog Converters with voltage output amplifiers and a parallel digital address and data port. put data port loads the data into the pre-selected DACS. Built on using an advanced linear BiCMOS, these devices offer rugged solutions that are latch-up free, and take advantage of EXAR’s patented thin-film resistor process which exhibits excellent long term stability and reliability. Typical DAC matching is 0.7 LSB across all codes. Accuracy of +0.75 LSB for DNL and +1 LSB for INL is achieved for B grade versions. The output amplifier is capable of sinking and sourcing 5mA, and the output voltage settles to 12-bits in less than 30µs (typ.). This device can easily be interfaced to a data bus, and digital readback of each channel is available. A standard µ-processor and TTL/CMOS compatible 12-bit in- SIMPLIFIED BLOCK DIAGRAM RB0 12 DB0 - DB11 Bus I/O VRP D Q LAT0B XR XE D Q LAT0A XR XE 12 12 DAC0 + – VO0 + – VO7 VRN XE0 A0 - A2 LD1 RD CS R1 3 8 Control Logic 8 RB7 XE0 - XE7 VRP RB0 - RB7 D Q LAT7B XR XE D Q LAT7A XR XE 12 DAC7 VRN XE7 R2 LD2 VRP VRP VEE VEE VCC VCC AGND AGND VREF Rev. 2.00 1 DGND DVDD – + VRN VREFN MP7613 ORDERING INFORMATION Package Type Temperature Range Part No. Res. (Bits) INL (LSB) DNL (LSB) FSE (LSB) PQFP –40 to +85°C MP7613BE 12 1 0.75 6 PQFP –40 to +85°C MP7613AE 12 –40 to +85°C 2 1 8 PGA MP7613BG 12 0.75 6 PGA –40 to +85°C 1 MP7613AG 12 –40 to +85°C 2 1 8 PLCC MP7613BP 12 0.75 6 PLCC –40 to +85°C 1 MP7613AP 12 2 1 8 PIN CONFIGURATIONS 33 See Packaging Section for Package Dimensions 23 34 22 See the following page for pin numbers and descriptions See the following page for pin numbers and descriptions Index 44 12 1 11 44-Pin PQFP (14 mm x 14 mm) Q44 44-Pin PGA G44 1 See the following page for pin numbers and descriptions 44-Pin PLCC P44 Rev. 2.00 2 MP7613 PIN OUT DEFINITIONS PLCC PIN NO. PQFP & PGA PIN NO. DESCRIPTION NAME 29 1 N/C No Connection 30 2 VO3 DAC 3 Output 31 3 VEE Analog Negative Power Supply (–12 V) 32 4 VCC Analog Positive Power Supply (+12 V) 33 5 DGND Digital Ground (0 V) 34 6 VREF Analog Positive Voltage Reference Input (+5 V) 35 7 VREFN Analog Negative Voltage Reference Output (–2.5 V) 36 8 VCC Analog Positive Power Supply (+12 V) 37 9 VEE Analog Negative Power Supply (–12 V) 38 10 VO4 DAC 4 Output 39 11 N/C No Connection 40 12 VO5 DAC 5 Output 41 13 VO6 DAC 6 Output 42 14 VO7 DAC 7 Output 43 15 AGND Analog Ground ( 0 V) 44 16 CS Chip Select Enable 1 17 RD Read Back Enable 2 18 R2 Second–Latch-Bank Reset Enable 3 19 R1 First–Latch-Bank Reset Enable 4 20 LD2 Second–Latch-Bank Load Enable 5 21 LD1 First–Latch-Bank Load Enable 6 22 A2 Digital Address Bit 2 7 23 A1 Digital Address Bit 1 8 24 A0 Digital Address Bit 0 9 25 N/C No Connection 10 26 N/C No Connection 11 27 DB0 Digital Input Data Bit 0 (LSB) 12 28 DB1 Digital Input Data Bit 1 13 29 DB2 Digital Input Data Bit 2 14 30 DB3 Digital Input Data Bit 3 15 31 DB4 Digital Input Data Bit 4 16 32 DB5 Digital Input Data Bit 5 17 33 DB6 Digital Input Data Bit 6 18 34 DB7 Digital Input Data Bit 7 19 35 DB8 Digital Input Data Bit 8 20 36 DB9 Digital Input Data Bit 9 21 37 DB10 Digital Input Data Bit 10 22 38 DB11 Digital Input Data Bit 11 (MSB) 23 39 DVDD Digital Positive Power Supply (+5 V) 24 40 DGND Digital Ground (0 V) 25 41 AGND Analog Ground (0 V) 26 42 VO0 DAC 0 Output 27 43 VO1 DAC 1 Output 28 44 VO2 DAC 2 Output Rev. 2.00 3 MP7613 ELECTRICAL CHARACTERISTICS VCC = +12 V, VEE = –12 V, VREF = 5 V, DVDD = 5.0 V, T = 25°C, Output Load = 5kΩ (unless otherwise noted) Parameter Symbol Min N 12 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) A B INL Differential Non-Linearity A B DNL Positive Full Scale Error A B +FSE Negative Full Scale Error A B –FSE Bipolar Zero Offset A B ZOFS INL Matching A B All Channels Maximum Error with DAC 0 adjusted to minimum error A B Bipolar Zero Matching A B Full Scale Error Matching A B Bits LSB 2 1 2 1 1 0.75 1 0.75 6 4 8 6 8 6 6 4 8 6 8 6 4 3 4 3 2 1.5 2 1.5 End Point Linearity Spec LSB LSB LSB LSB INL LSB ME LSB 4 2 4 2 4 3 4 3 4 3 4 3 50 50 ZUFS LSB ∆FSE LSB DYNAMIC PERFORMANCE Voltage Settling from LD to VDAC Out1 Channel-to-Channel Crosstalk1, 6 Digital Feedthrough1, 6 Power Supply Rejection Ratio tsd 30 CT Q PSRR 0.04 –70 5 µs ZS to FS (20 V Step) LSB dB ppm/% DC CLK and Data to VOUTi ∆VEE & ∆VCC = +5%, ppm of FS Ω See Application Hints for driving the reference input REFERENCE INPUTS Impedance of VREF REF 350 VREF Voltage1, 2 VREF 3.5 700 1.05k 6 Rev. 2.00 4 350 1.05k V MP7613 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min VIH VIL IL CL 2.4 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments DIGITAL INPUTS3 Logic High Logic Low Input Current Input Capacitance1 V V µA pF 0.8 +10 8 ANALOG OUTPUTS Output Swing Output Drive Current VREFN Output Drive Current Output Impedance Output Short Circuit Current –VEE +1.4 –5 –10 VCC –1.4 RO ISC 1 25 30 40 55 V mA µA Ω mA mA mA mA VOH VOL 4.5 0.5 V V VCC VEE DVDD ICC IEE IDD PDISS VREF+1.5 12 –12.75 –12 4.5 5 8 15 IAGND ±60 5 +10 For test purposes only +FS to AGND +FS to VEE –FS to AGND –FS to VCC DIGITAL OUTPUTS Output High Voltage Output Low Voltage POWER SUPPLIES VCC Voltage5 VEE Voltage5 DVDD Voltage Positive Supply Current Negative Supply Current Digital Supply Current Power Dissipation 320 12.75 –5 5.5 10 20 2 420 VREF+1.5 12.75 –12.75 –5 4.5 5.5 10 20 2 450 V V V mA mA mA mW Bipolar zero Bipolar zero Bipolar zero Bipolar zero µA See Application Notes ANALOG GROUND CURRENT Per Channel1 DIGITAL TIMING SPECIFICATIONS1,4 Data Setup Time Data Hold Time Address Set-up Time Address Hold Time Chip Select to LD1 Set-up Time Chip Select to LD1 Hold Time LD1 Pulse Width LD1 Negative Edge to LD2 Positive Edge LD2 Pulse Width Chip Select to RD Set-Up Time Chip Select to RD Hold Time RD Pulse Width High Z to Data Valid for Readback Data Valid for Readback to High Z R1 Pulse Width R2 Pulse Width VIL = 0 V, VIH = 5 V, CL = 20 pF tLD1W tLD1LD2 20 20 100 0 6 0 50 60 ns ns ns ns ns ns ns ns tLD2W tCS2 tCH2 tRD tDA tDR R1W R2W 60 6 0 600 600 200 100 100 ns ns ns ns ns ns ns ns tDS tDH tAS tAH tCS1 tCH1 Specifications are subject to change without notice Rev. 2.00 5 MP7613 ELECTRICAL CHARACTERISTICS (CONT’D) NOTES: 1 Guaranteed; not tested. 2 Specified values guarantee functionality. 3 Digital inputs should not go below digital GND or exceed DVDD supply voltage. 4 See Figures 1, 2, and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level. 5 For power supply values < 2VREF, the output swing is limited as specified in Analog Outputs. 6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –16.5 V Digital Input & Digital Output Voltage to: DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +.5 V DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V Operating Temperature Range . . . . . . . . . . –40°C to +85°C VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C Analog Outputs & Inputs Infinite Shorts to VCC, VEE, DVDD, AGND and DGND (provided that power dissipation of the package spec is not exceeded) Storage Temperature Range . . . . . . . . . . . –65°C to +150°C VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16.5 V Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C Package Power Dissipation Rating to 75°C PQFP, PGA, PLCC . . . . . . . . . . . . . . . . . . . . . . 800mW Derates above 75°C . . . . . . . . . . . . . . . . . . . 11mW/°C AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality guaranteed for 0.5 V only) NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. APPLICATION NOTES Refer to Section 8 for Applications Information NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog ground connection. The difference between the DGND and AGND should be limited to 300 mV to assure normal operation. If there is any chance that the AGND to DGND can be greater than 1 V, we recommend two back-to-back diodes be used between DGND and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may help reduce noise induced from long lead or trace lengths. Rev. 2.00 6 MP7613 Data Input/Output Bus 1 Address A0-A2 1 Chip Select CS 1 Load Latch A LD1 1 Load Latch B LD2 1 0 tDH tDS 0 tAH tAS tCH1 don’t care 0 tCS1 don’t care tLD1W 0 tLD1LD2 0 tLD2W Analog Output +FS –FS tSD Figure 1. Loading Latch A and Updating Latch B Notes (1) Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable in the above diagram. (2) R1 = R2 = 1. (3) For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode). Address A0-A2 1 0 Chip Select CS 1 0 Data Readback RD 1 0 Digital Output Data D0 to D13 1 0 tAS tAH don’t care don’t care tCS2 HIGH-Z tRD tCH2 tDR tDA HIGH-Z Figure 2. Read Back First Latch Bank of One DAC Notes (1) Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable in the above diagram. (2) R1 = R2 = 1. R1 1 0 R2 1 0 tR1W Reset first latch bank to 1000 . . . . .0000 tR2W Reset second latch bank to 1000 . . . . .0000 and analog output to zero volt. Figure 3. Reset Operations Rev. 2.00 7 MP7613 A standard µ-processor and TTL/CMOS compatible input data port loads the data into the pre-selected DACS. If CS = 0, the chip accesses digital data on the bus. Then address bits A0 to A2 select the appropriate DAC and LD1 loads the data into the first-latch-bank. When all 8-channels first-latch-banks are loaded, then LD2 enables the second-latch-bank and updates Function all 8-channels simultaneously. The selected DAC becomes transparent (activity on the digital inputs appear at the analog output) when both LD1 = LD2 = 0. R1 = 0 resets the first-latch-bank. R2 = 0 resets the secondlatch-bank which sets the analog output to zero volts (data = 100...00), regardless of digital inputs. A2 A1 A0 RD LD1 LD2 CS R1 R2 Load Latch 1 of DAC1 Load Latch 1 of DAC2 Load Latch 1 of DAC3 Load Latch 1 of DAC4 Load Latch 1 of DAC5 Load Latch 1 of DAC6 Load Latch 1 of DAC7 Load Latch 1 of DAC8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0→1 0→1 0→1 0→1 0→1 0→1 0→1 0→1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Load Latch 2 of DAC1→8 X X X 1 1 0→1 0 1 1 Read Latch 1 of DAC1 Read Latch 1 of DAC2 Read Latch 1 of DAC3 Read Latch 1 of DAC4 Read Latch 1 of DAC5 Read Latch 1 of DAC6 Read Latch 1 of DAC7 Read Latch 1 of DAC8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset Latch 1 of DAC1→8 Reset Latch 2 of DAC1→8 X X X X X X X X X X X X X X 0 1 1 0 Note: 1: High, 0: Low, X: Don’t Care Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table Note: For timing information see Electrical Characteristics A0 to A2 3 3-8 Decoder 8 8 To first latch bank enable LD1 8 8 CS To switches across the first latch bank for readback enable RD To second latch bank enable LD2 R1 To reset all first latch bank R2 To reset all second latch bank Figure 4. Simplified Parallel Logic Port Rev. 2.00 8 MP7613 Hex Code Binary Code Output Voltage = 2 • Vr (–1 + 2•D ) (Vr = +5 V) 4096 000 000000000000 10 • (–1 + 0) = –10 7FF 011111111111 800 100000000000 10 • (–1 + 4096 ) = 0 801 100000000001 10 • (–1 + 4098 ) = 4.88 mV FFF 111111111111 10 • (–1 + 8190 ) = 9.99512 10 • (–1 + 4094 ) = –4.88 mV 4096 4096 4096 4096 Table 2. MP7613 Ideal DAC Output vs. Input Code Note: See Electrical Characteristics on pages 28-30 for real system accuracy A0 to A15 16 3 AS Address Decoder A0 to A2 µP LD1 R DB0 to DB16 From System Reset R1 From System Reset R2 12 or 14 DB0 to DB11 or DB13 Figure 5. Parallel µP Interface Rev. 2.00 9 MP7613 PERFORMANCE CHARACTERISTICS 11 V 0V –11 V VOUT 2.5mV 0V –2.5mV VOUT Settling 50µs/Division Graph 1. Typical Output Settling Characteristic VREF = 5 V, RL = 5K, CL = 500pF Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the difference between the output and the ideal output. Graph 2. Linearity with VREF = 5 V, All DACs, All Codes Rev. 2.00 10 MP7613 Graph 3. DAC 0 INL vs. VREF Graph 4. DAC 0 DNL vs. VREF Graph 5. DAC 0 Linearity with VREF = 5 V, VOUT = 10 Graph 6. DAC 0 Linearity with VREF = 4.5 V, VOUT = 9 Graph 7. DAC 0 Linearity with VREF = 4 V, VOUT = 8 Graph 8. DAC 0 Linearity with VREF = 3.5 V, VOUT = 7 Rev. 2.00 11 MP7613 VOUT MP7610 Family 50W 5k VO 500pF I CL 2mA CL = 500pF, 5nF, 50nF, 500nF Figure 6. Circuit for Determining Typical Analog Output Pulse Response 2.0mA I 0.0 400mV VO –400mV 200mV CL = 500pF CL = 5nF CL = 50nF CL = 500nF VOUT –200mV 0s 1.0µs 2.0µs 3.0µs 4.0µs 5.0µs Graph 9. Typical Response of the MP7610 Family Analog Output to a Current Pulse with CL=500pF, 5nF, 50nF, 500nF (See NO TAG above) Rev. 2.00 12 6.0µs MP7613 44 LEAD PLASTIC QUAD FLAT PACK (14mm x 14mm PQFP, METRIC) Q44 D D1 33 23 34 22 D1 D 44 12 1 11 B A2 e C A α A1 L MILLIMETERS SYMBOL A INCHES MIN MAX MIN MAX –– 3.15 –– 0.124 A1 0.25 –– 0.01 –– A2 2.6 2.8 0.102 0.110 B 0.3 0.4 0.012 0.016 C 0.13 0.23 0.005 0.009 D 16.95 17.45 0.667 0.687 D1 13.9 14.1 0.547 0.555 e 1.00 BSC 0.039 BSC L 0.65 1.03 0.026 0.040 α 0° 7° 0° 7° Coplanarity = 4 mil max. Rev. 2.00 13 MP7613 44 LEAD PIN GRID ARRAY (PGA) G44 D D1 A e É É É É É É É D b 8 7 6 e 5 D1 4 3 2 1 H Q G F E D C B A Pin 1 L1 Seating Plane INCHES SYMBOL MILLIMETERS CONNECTION TABLE MIN MAX MIN MAX PAD PIN PAD PIN PAD PIN A 0.082 0.10 2.08 2.54 b 0.016 0.020 0.406 0.508 D 0.841 0.859 21.4 21.8 D1 0.688 0.712 17.5 18.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B2 B1 C2 C1 D2 D1 E1 E2 F1 F2 G1 G2 H2 G3 H3 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 G4 H4 H5 G5 H6 G6 H7 G7 G8 F7 F8 E7 E8 D8 D7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 C8 C7 B8 B7 A7 B6 A6 B5 A5 A4 B4 A3 B3 A2 e L1 Q 0.100 typ. 0.170 0.190 0.050 typ. 2.54 typ. 4.32 4.83 1.27 typ. Note: The letters A-H and numbers 1-8 are the coordinates of a grid. For example, pin 1 is at the intersections of the “B” vertical line and the “2” horizontal line. Rev. 2.00 14 MP7613 44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P44 D Seating Plane A2 D1 1 B D D1 D2 e1 C D3 A1 A INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.165 0.180 4.19 4.57 A1 0.100 0.110 2.54 2.79 A2 0.148 0.156 3.76 3.96 B 0.013 0.021 0.330 0.553 C 0.097 0.0103 0.246 0.261 D 0.685 0.695 17.40 17.65 D1 (1) 0.650 0.654 16.51 16.61 D2 0590 0.630 14.99 16.00 D3 0.500 Ref 12.70 Ref. e1 0.050 BSC 1.27 BSC Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. Rev. 2.00 15 MP7613 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 16