OKI MSM6588LGS-2K

E2D0025-27-42
¡ Semiconductor
MSM6588/6588L
¡ Semiconductor
This version:
Jan. 1998
MSM6588/6588L
Previous version: May. 1997
ADPCM Solid-State Recorder (for Serial Registers)
GENERAL DESCRIPTION
The MSM6588/6588L is a "solid-state recorder" IC developed using the ADPCM method. By
externally connecting a microphone, a speaker, a speaker amplifier and a serial register or other
Memory device to store ADPCM data, it can record and playback voice data similar to a tape
recorder.
The MSM6588/6588L has a stand-alone mode and a microcontroller interface mode. In standalone mode, record/playback can be selected from a pin and it is possible to control the MSM6588
by a simple drive timing. In microcontroller interface mode, record/playback can be controlled
by commands from the microcontroller in microcontroller mode, the MSM6588/6588L is much
more flexible than in stand-alone operation. In addition, recording and playback with fixed
message are easily implemented by connecting a serial voice ROM.
The MSM6588 and the MSM6588L support 5 V and 3 V operation respectively.
FEATURES
• 12bit A/D converter
• 12bit D/A converter
• Microphone amplifier
• Low-pass filter (LPF)
Filter characteristics –40 dB/oct
• Serial registers
MSM6588
Up to four 1Mbit serial registers (MSM6685) can be driven directly
One 512Kbit serial register (MSM6587) can be driven directly
One 256Kbit serial register (MSM6586) can be driven directly
MSM6588L
Up to four 1Mbit serial registers (MSM63V89C) can be driven directly
• Serial Voice ROMs
1Mbit serial voice ROM (MSM6595A-xxx)
2Mbit serial voice ROM (MSM6596A-xxx)
3Mbit serial voice ROM (MSM6597A-xxx)
• Maximum recording time
262 seconds (when using 3-bit ADPCM, 5.3 kHz sampling)
• Voice triggered starting
• Pause function
• Master clock frequency: 4.096 MHz to 8.192 MHz
• Power supply voltage
MSM6588: Single 5 V Power supply
MSM6588L: Single 3 V Power supply
• Package options:
44-pin plastic QFP (QFP44-P-910-0.80-2K)(Product name: MSM6588GS-2K)
44-pin plastic QFP (QFP44-P-910-0.80-2K)(Product name: MSM6588LGS-2K)
44-pin plastic TQFP (TQFP44-P-1010-0.80-K)(Product name: MSM6588LTS-K)
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¡ Semiconductor
MSM6588/6588L
• Differences between MSM6588 and MSM6588L
The major differences between the MSM6588 and the MSM6588L are shown below.
Parameter
Operating voltage
Full scale of A/D and D/A converters
Voice detection level for voice
triggered starting
MSM6588
MSM6588L
3.5 to 5.5V
2.7 to 3.6V
0 to VDD
3
1
VDD
VDD to
4
4
± VDD , ± VDD , ± VDD
64
32
16
± VDD , ± VDD , ± VDD
128
64
32
1Mbits (MSM6389C)
External only register
512Kbits (MSM6587)
1Mbits (MSM63V89C)
256Kbits (MSM6586)
1. Characteristics in stand-alone mode
• 3-bit ADPCM
•Sampling frequency:
5.3 kHz or 8.0 kHz (when the oscillator operates at 4.096 MHz)
10.6 kHz or 16.0 kHz (when the oscillator operates at 8.192 MHz)
• Number of phrases: 1, 2, 4 or 8
2. Characteristics in microcontroller interface mode
• 3-bit/4-bit ADPCM selectable
• Sampling frequency:
4.0 kHz, 5.3 kHz, 6.4 kHz or 8.0 kHz (when the oscillator operates at 4.096 MHz)
8.0 kHz, 10.6 kHz, 12.8 kHz or 16.0 kHz (when the oscillator operates at 8.192 MHz)
• Condition setting, start, and stop of record/playback controllable by 13 commands.
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¡ Semiconductor
MSM6588/6588L
CONTENTS
GENERAL DESCRIPTION ................................................................................................................................... 1
FEATURES .............................................................................................................................................................. 1
BLOCK DIAGRAM ................................................................................................................................................ 6
Stand-Alone Mode ....................................................................................................................................... 6
Microcontroller Interface Mode ................................................................................................................. 7
PIN CONFIGURATION (Top View) ................................................................................................................... 8
1. Stand-alone mode (MCUM pin=”L”) ............................................................................................... 8
2. Microcontroller interface (MCUM pin=”H”) .................................................................................. 9
PIN DESCRIPTIONS ............................................................................................................................................ 10
Common Functions in Stand-Alone Mode and Microcontroller Interface Mode ............................. 10
Stand-Alone Mode ..................................................................................................................................... 12
Microcontroller Interface Mode ............................................................................................................... 13
ABSOLUTE MAXIMUM RATINGS (for MSM6588 (5V Version)) ............................................................... 14
RECOMMENDED OPERATING CONDITIONS (for MSM6588 (5V Version)) ......................................... 14
ELECTRICAL CHARACTERISTICS (for MSM6588 (5V Version)) ............................................................... 14
DC Characteristics ...................................................................................................................................... 14
Analog Characteristics ............................................................................................................................... 15
AC Characteristics ...................................................................................................................................... 15
1. Common characteristics in stand-alone mode and
microcontroller interface mode ....................................................................................................... 15
2. Stand-alone mode .............................................................................................................................. 16
3. Microcontroller interface mode ....................................................................................................... 17
ABSOLUTE MAXIMUM RATINGS (for MSM6588L (3V Version)) ............................................................. 19
RECOMMENDED OPERATING CONDITIONS (for MSM6588L (3V Version)) ....................................... 19
ELECTRICAL CHARACTERISTICS (for MSM6588L (3V Version)) ............................................................ 19
DC Characteristics ...................................................................................................................................... 19
Analog Characteristics ............................................................................................................................... 20
AC Characteristics ...................................................................................................................................... 20
1. Common characteristics in stand-alone mode and
microcontroller interface mode ....................................................................................................... 20
2. Stand-alone mode .............................................................................................................................. 21
3. Microcontroller interface mode ....................................................................................................... 22
TIMING DIAGRAMS .......................................................................................................................................... 24
Reset Function and Power Down Function ............................................................................................ 24
1. Stand-alone mode when the PDMD pin is “L” ............................................................................. 24
2. Stand-alone mode when the PDMD pin is “H” and
in microcontroller interface mode ................................................................................................... 24
Stand-alone Mode ....................................................................................................................................... 25
1. Timing during recording (PDMD pin=”L”, VDS pin=”L”) ........................................................ 25
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¡ Semiconductor
MSM6588/6588L
2
Timing during recording by voice triggered starting
(PDMD pin=”L”, VDS pin=”H”) ..................................................................................................... 25
3. Timing during playback (PDMD pin=”L”) ................................................................................... 26
4. Timing during repeated playback (PDMD pin=”L”) ................................................................... 26
5. Timing during recording (PDMD pin=”H”, VDS pin=”L”) ....................................................... 27
6. Timing during recording by voice triggered starting
(PDMD pin=”H”, VDS=”H”) ........................................................................................................... 27
7. Timing during playback (PDMD pin=”H”) .................................................................................. 28
8. Timing during repeated playback (PDMD pin=”H”) .................................................................. 28
9. Timing of pause in record/playback .............................................................................................. 29
Microcontroller Interface ........................................................................................................................... 30
1. Data read (RD pulse) ......................................................................................................................... 30
2. Data write (WR pulse) ....................................................................................................................... 30
3. Input method of 1 nibble command
(NOP, PAUSE, PLAY, REC, START and STOP commands) ....................................................... 31
4. Input method of 2 nibble command
(SAMP, CHAN and VDS commands) ............................................................................................ 31
5. Input method of ADRWR command .............................................................................................. 32
6. Input method of ADRRD command ............................................................................................... 32
7. Recording method by START command ....................................................................................... 33
8. Timing of voice triggered starting ................................................................................................... 33
9. Playback method using START command .................................................................................... 34
10. Timing of pause in record/playback using PAUSE command .................................................. 34
11. Timing of data transfer by DTRW command ................................................................................ 35
12. Timing of recording by EXT command .......................................................................................... 35
13. Timing of playback by EXT command ........................................................................................... 36
FUNCTIONAL DESCRIPTION .......................................................................................................................... 37
Recording Time and Memory Capacity .................................................................................................. 37
Analog Input Amplifier Circuit ................................................................................................................ 37
Connection of LPF Circuit Peripherals .................................................................................................... 38
LPF Characteristics ..................................................................................................................................... 40
Full Scale of A/D and D/A Converters .................................................................................................. 40
Voice Triggered Starting ............................................................................................................................ 41
How to Connect an Oscillator .................................................................................................................. 42
How to Connect Power Supply ................................................................................................................ 44
Data Configuration of External Serial Registers .................................................................................... 44
1. Channel index area ............................................................................................................................ 45
2. Voice (ADPCM) data area ................................................................................................................ 46
Selection of Serial Registers ....................................................................................................................... 47
Recording Control Modes ......................................................................................................................... 47
1. Direct mode ........................................................................................................................................ 47
2. Fixed mode ......................................................................................................................................... 47
3. Flex mode ............................................................................................................................................ 48
Channel Usage ............................................................................................................................................ 49
1. Selection of a channel in direct mode and flex mode ................................................................... 49
2. Channel selection in fixed mode ..................................................................................................... 49
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¡ Semiconductor
MSM6588/6588L
Operation in Stand-alone Mode ............................................................................................................... 51
1. Power down function ........................................................................................................................ 51
2. Master clock frequency and sampling frequency ......................................................................... 51
3. Method of recording ......................................................................................................................... 52
4. Method of playback ........................................................................................................................... 53
5. Method of pause in record/playback ............................................................................................. 54
6. Operation in voice triggered starting ............................................................................................. 55
7. Method of re-recording ..................................................................................................................... 56
8. Pull-up resistor ................................................................................................................................... 57
Operation in Microcontroller Interface Mode ........................................................................................ 58
1. Command input method .................................................................................................................. 58
2. Explanation of commands ................................................................................................................ 61
3. Explanation of status register .......................................................................................................... 63
4. Selection of sampling frequency (SAMP command) .................................................................... 65
5. Recording control modes (SAMP and CHAN commands) ......................................................... 65
6. Selection of channel (CHAN command) ........................................................................................ 66
7. Input/output of start address and stop address
(ADRWR and ADRRD commands) ................................................................................................ 67
8. Specifying ADPCM bit length (VDS command) ........................................................................... 71
9. Specifying voice triggered starting mode (VDS command) ........................................................ 71
10. Recording method ............................................................................................................................. 71
11. Playback method ............................................................................................................................... 75
12. Pause method (temporary suspension) with the (PAUSE command) ....................................... 77
13. Operation in voice triggered starting (VDS command) ............................................................... 79
14. Address control operation ................................................................................................................ 80
15. Multi-channel record/playback method ........................................................................................ 84
16. Playback method by means of a serial voice ROM ....................................................................... 87
17. Data transfer method with external serial registers (DTRW command) ................................... 91
18. Method of record/playback by input/output of data from
the data bus (EXT command) ........................................................................................................... 93
19. Reset and power down function ..................................................................................................... 96
APPLICATION CIRCUITS ................................................................................................................................. 97
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¡ Semiconductor
20-bit
STOP ADDRESS REGISTER
BLOCK DIAGRAM
SAD
SAS
TAS
RWCK
WE
CS1
CS2
CS3 (STBY)
REGISTER
CONTROLLER
20-bit
ADDRESS REGISTER
TIMING
CONTROLLER
REC/PLAY
ST
SP
PAUSE
MCUM
PDMD
SAM
VDS
RESET
MON
Stand-Alone Mode
20 Stage
ADDRESS COUNTER
ADDRESS
CONTROLLER
RSEL1
RSEL2
CSEL1
CSEL2
CA1
CA2
CA3
CS4
I/O
20-bit
COMPARATOR
CS4(RSEL0)
RSEL0
XT
XT
OSC
DI/O
DVDD
DVDD’
AVDD
-
-
+
+
MOUT LIN LOUT AMON FIN
LPF
AOUT FOUT
12-bit
ADC
ADIN
12-bit
DAC
SG
CIRCUIT
SG
DGND
AGND
6/101
MSM6588/6588L
MIN
DATA
I/O
ADPCM
ANALYZER/SYTHESIZER
20-bit
STOP ADDRESS REGISTER
TIMING
CONTROLLER
MCUM
RESET
MON
XT
XT
CS4
I/O
20-bit
COMPARATOR
CS4(RSEL0)
RSEL0
DATA
I/O
ADPCM
ANALYZER/SYTHESIZER
OSC
-
-
+
+
MOUT LIN LOUT AMON FIN
LPF
AOUT FOUT
12-bit
ADC
ADIN
12-bit
DAC
SG
CIRCUIT
SG
DI/O
DVDD
DVDD’
AVDD
DGND
AGND
TEST
TEST
TEST
TEST
TEST
7/101
MSM6588/6588L
MIN
SAD
SAS
TAS
RWCK
WE
CS1
CS2
CS3(STBY)
REGISTER
CONTROLLER
20-bit
ADDRESS REGISTER
STATUS
REGISTER
MCU I/F
D3
D2
D1
D0
WR
RD
CE
¡ Semiconductor
20 Stage
ADDRESS COUNTER
ADDRESS
CONTROLLER
Microcontroller Interface Mode
RSEL1
RSEL2
¡ Semiconductor
MSM6588/6588L
PIN CONFIGURAITON (Top View)
XT
XT
DI/O
CS4(RSEL0)
CS3(STBY)
37
36
35
34
24 DGND
21
22
23 AGND
MIN
11
26 SAS
25 TAS
MOUT
ADIN
RESET
SAM
MON
RWCK
WE
DVDD
44
43
42
41
40
39
27 SAD
20
10
28 CS1
LIN
9
29 CS2
19
CA3
VDS
31 RSEL2
30 RSEL1
18
8
32 CSEL1
SG
CA2
33 CSEL2
LOUT
7
17
CA1
DVDD'
6
16
MCUM
15
5
AVDD
4
PDMD
AMON
PAUSE
14
3
FIN
REC/PLAY
13
2
AOUT
ST
12
1
FOUT
SP
38
1. Stand-alone mode (MCUM pin = "L")
44-Pin Plastic QFP
44-Pin Plastic TQFP
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¡ Semiconductor
MSM6588/6588L
34 CS3(STBY)
35 CS4(RSEL0)
21
22
MOUT
MIN
37 XT
38 XT
39 DVDD
40 WE
41 RWCK
42 MON
20
ADIN 11
24 DGND
23 AGND
LIN
D3 10
25 TAS
19
9
18
D2
26 SAS
SG
8
LOUT
D1
27 SAD
17
7
DVDD'
6
D0
16
MCUM
29 CS2
28 CS1
15
5
30 RSEL1
AVDD
TEST
31 RSEL2
AMON
4
32 TEST
14
TEST
33 TEST
FIN
3
13
CE
AOUT
2
43 TEST
44 RESET
RD
12
1
FOUT
WR
36 DI/O
2. Microcontroller interface mode (MCUM pin = "H")
44-Pin Plastic QFP
44-Pin Plastic TQFP
Selection of stand-alone mode or microcontroller interface mode is controlled by the level of the
MCUM pin.
MCUM="H": microcontroller interface mode
MCUM="L":
stand-alone mode
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¡ Semiconductor
MSM6588/6588L
PIN DESCRIPTIONS
Common Functions in Stand-Alone Mode and Microcontroller Interface Mode
Pin
Symbol
Type
39
DVDD
—
17
DVDD’
—
16
AVDD
—
24
DGND
—
Digital GND pin
23
AGND
—
Analog GND pin
18
SG
O
Output pin for analog circuit reference voltage (signal ground)
22
MIN
20
21
LIN
MOUT
19
LOUT
Description
Digital power supply pin. Insert a bypass capacitor of 0.1mF or more
between this pin and the DGND pin.
Digital power supply pin
Analog power supply pin. Insert a bypass capacitor of 0.1mF or more
between this pin and the AGND pin.
Inverting input pin for the built-in OP amplifier. Non-inverting input
I
pin is connected to SG internally.
MOUT and LOUT are output pins of the built-in OP amplifier for MIN
O
and LIN, respectively.
This pin is connected to the LOUT pin in recording mode and to the
15
AMON
O
DA converter output in playing mode. Connected to the built-in LPF
input (FIN pin).
Input pin for the built-in LPF.
14
FIN
I
12
FOUT
O
11
ADIN
I
13
AOUT
O
27
SAD
O
26
SAS
O
Clock pin to write the serial address.
25
TAS
O
Clock pin which tranfers the serial address data to the address counter
Output pin of the built-in LPF. Connected to the AD converter (ADIN
pin) input.
Input pin for the built-in 12-bit AD converter.
Output pin for the built-in LPF. Output pin for playback waveform.
Connected to the speaker drive amplifier.
(Serial Address Data) Connected to the SAD pin of serial register.
This pin outputs the Read/Write header address.
(Serial Address Strobe) Connected to the SAS pin of serial register.
(Transfer Address Strobe) Connecd to the TAS pin of serial register.
inside the serial register.
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¡ Semiconductor
Pin
Symbol
MSM6588/6588L
Type
41
RWCK
O
40
WE
O
36
DI/O
I/O
Description
(Read/Write Clock) Connected to the RWCK pin of the serial register.
Clock pin for reading and writing data to the serial registers.
(Write Enable) Connected to the WE pin of serial register. The pin
to select read or write mode.
(Data I/O) Connected to the DIN and DOUT pins of serial register.
Data input and output mode.
(Chip Select) Connected to the CS pin of the serial register.
CS3 pin and CS4 pin have different functions depending on the
number of serial registers to be connected. The number of serial
registers is selected by the RSEL1 and RSEL2 pins.
CS3 (STBY) pin becomes CS3 when four serial registers are used\,
28
CS1
O
29
CS2
O
34
CS3 (STBY)
O
35
CS4 (RSEL0)
I/O
otherwise it is the STBY pin which outputs a "H" level at power down.
CS4 (RSEL0) pin becomes CS4 when four serial registers are used,
otherwise it is the RSEL0-pin used to select the number of serial
registers used.
RSEL2
RSEL1
CS3 (STBY)
CS4 (RSEL0)
L
H
L
L
L
H
STBY STBY STBY
RSEL0 RSEL0 RSEL0
(I)
(I)
(I)
H
H
CS3
CS4
(O)
(Register Select) Those pins are to select the number of serial registers
to be connected.
35
CS4 (RSEL0)
I/O
30
RSEL1
I
31
RSEL2
I
RSEL2
RSEL1
RSEL0 (CS4)
Number of serial
voice registers
L
H
H
––
L
(I)
(I)
(I)
One
One
One
256Kbit 512Kbit 1Mbit
L
L
H
L
––
(I)
Two
1Mbit
H
H
CS4
(O)
Four
1Mbit
This pin is to select stand-alone mode or microcontroller interface
mode.
6
MCUM
I
44
RESET
I
37
XT
I
38
XT
O
"L" level.... stand-alone mode
"H" level.... microcontroller interface mode
The IC is initialized and goes into the power-down state by input of
a "L" level.
Connect to an oscillator. Use this input when providing an external
clock. When at power down input the GND level instead.
Connect to an oscillator. Leave open when using an external clock.
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¡ Semiconductor
MSM6588/6588L
Stand-Alone Mode
Pin
Symbol
Type
3
REC/PLAY
I
2
ST
I
1
SP
I
4
PAUSE
I
Description
This pin is to select recording or playback. When an "H" level is input,
the IC is in record mode.
When an "L" level pulse is input, record/playback is started. Internal
pull up connected.
When an "L" level pulse is input, record/playback is ended. Internal
pull up connected.
When an "L" level pulse is input, record/playback is suspended. Internal pull up connected.
These pins are to select the number of recorded words and control
mode. When the number of the recorded words is wished to be selected
in one word, select Flex mode.
32
CSEL1
33
CSEL2
I
CSEL2
CSEL1
L
L
L
H
H
L
H
H
Number of
recorded words
8
4
2
8
7
CA1
8
CA2
9
CA3
flex
fixed
Control mode
These pins are to specify the channel.
I
(Refer to Explanation of Functions.)
This pin is to select the sampling frequency.
The following is the relation between the master clock frequency
(fosc) and sampling frequency (fsam).
Numbers inside the parenthenses ( ) are for fosc=4.096MHz
43
SAM
I
SAM
L
H
fsamp
fOSC
768
fosc
512
(5.3kHz)
(8.0kHz)
This pin selects transition to the power down state.
"L" level.... The IC enters power down state automatically except during
5
PDMD
I
record/playback.
"H" level.... The IC enters standby state except during record/playback.
The power down state can be entered by the RESET pin. This mode
must be active when using the built-in LPF in an external circuit.
This pin is to select voice triggered starting that starts recording when
10
VDS
I
the voice input exceeds the preset amplitude. Input an "H" level and
the voice activation circuit is enabled.
Input an "L" level to disabel the voice activation circuit.
42
MON
O
Outputs a "H" level during record/playback.
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¡ Semiconductor
MSM6588/6588L
Microcontroller Interface Mode
Pin
Symbol
Type
Description
Bi-directional data bus. Performs input/output of commands and data
7
D0
8
D1
9
D2
10
D3
1
WR
I
2
RD
I
3
CE
I
with an external microcontroller.
I/O
This pin is to input WRITE pulses. Input is a "L" pulse when commands
or data to the D0~D3 pins are to be input.
This pin is to input READ pulses. Input is a "L" pulse when output
status or data from the D0~D3 pins is to read.
Chip enable. A "H" level on this pin disables WRITE (WR)/READ
(RD) input pulses. Input/output of data through the D0~D3 pins is disabled.
Outputs a "H" level during record/playback.
42
MON
O
When record/playback is in operation using the EXT command, clocks
for synchronization are output.
4, 32, 33, 43
TEST
5
TEST
I
These pins are for IC testing at the factory. Input a "L" level to the
TEST pin and an "H" level to the TEST pin.
13/101
¡ Semiconductor
MSM6588/6588L
ABSOLUTE MAXIMUM RATINGS (for MSM6588 (5 V Version))
Parameter
Power supply voltage
Symbol
VDD
Input voltage
VIN
Storage temperature
TSTG
Rating
Unit
–0.3 to +7.0
V
Condition
Ta = 25˚C
–0.3 to VDD +0.3
V
–55 to +150
˚C
—
RECOMMENDED OPERATING CONDITIONS (for MSM6588 (5 V Version))
Parameter
Power supply voltage
Range
Condition
Unit
Symbol
VDD
DGND = AGND = 0V
Operating temperature
TOP
––
–40 to +85
°C
Master clock frequency
fOSC
––
4.0 to 8.192
MHz
3.5 to 5.5 (Note 5)
V
ELECTRICAL CHARACTERISTICS (for MSM6588 (5 V Version))
DC Characteristics
DVDD=DVDD’=AVDD=4.5 to 5.5 V (Note 5), DGND=AGND=0 V, Ta= –40 to +85°C
Symbol
VIH
Condition
––
Min.
0.8¥VDD
Typ.
––
––
Unit
V
"L" input voltage
VIL
––
––
––
0.2¥VDD
V
"H" output voltage
VOH
IOH = –40mA
VDD–0.3
––
––
V
"L" output voltage
VOL
IOL = 2mA
––
––
0.45
V
"H" input current (Note 1)
IIH1
VIH = VDD
––
––
10
mA
"H" input current (Note 2)
IIH2
VIH = VDD
––
––
20
mA
"L" input current (Note 3)
IIL1
VIL = GND
–10
––
––
mA
"L" input current (Note 2)
IIL2
VIL = GND
–20
––
––
mA
"L" input current (Note 4)
IIL3
VIL = GND
–400
––
–20
mA
Operating current consumption
IDD
fOSC = 8MHz, no load
––
7
15
mA
––
––
10
mA
––
––
50
mA
Parameter
"H" input voltage
When power down,
Stand by current consumption
IDDS
no load Ta = –40 to +70°C
When power down,
no load Ta = –40 to +85°C
Note: 1.
2.
3.
4.
5.
Max.
Applicable to all input pins, excluding the XT pin.
Applicable to the XT pin.
Applicable to all input pins without pull-up resistors, excluding the XT pin.
Applicable to input pins (ST, SP, PAUSE) with pull-up resistors, excluding the XT pin.
Recording and playback should be performed at a power supply voltage of 4.5 to 5.5
V. For other operations such as backing up a serial register, the IC operates at 3.5 to
5.5 V.
14/101
¡ Semiconductor
MSM6588/6588L
Analog Characteristics
DVDD=DVDD’=AVDD=4.5 to 5.5 V, DGND=AGND=0 V Ta= –40 to +85°C
Symbol
VDAE
Condition
no load
Min.
––
Typ.
Max.
––
10
Unit
mV
VFIN
––
1
––
VDD–1
V
RFIN
––
1
––
––
MW
VADIN
––
0
—
VDD
V
RADIN
––
1
—
––
MW
Op-amp open loop gain
GOP
fIN = 0 to 4kHz
40
—
––
dB
Op-amp input impedance
RINA
––
1
—
––
MW
Op-amp load resistance
ROUTA
––
200
—
––
kW
AOUT load resistance
RAOUT
––
50
––
––
kW
FOUT load resistance
RFOUT
––
50
––
––
kW
Parameter
DA output relative error
FIN admissible input voltage
range
FIN input impedance
ADIN admissible input voltage
range
ADIN input impedance
AC Characteristics
1. Common characteristics in stand-alone mode and microcontroller interface mode
DVDD=DVDD’=AVDD=4.5 to 5.5 V, DGND=AGND=0 V, Ta= –40 to +85°C
When fsamp=8kHz
Parameter
RESET pulse width
RESET execution time (Note 1) *
Symbol
tRST
Min.
Typ.
Max.
Unit
1
––
––
ms
tREX
––
125
––
ms
Note: Item with * is proportional to the period of sampling frequency (fsamp).
1) The oscillation stable time is added to tREX.
The oscillation stable time is several tens of milliseconds for crystal oscillators and is
several hundreds of microseconds.
15/101
¡ Semiconductor
MSM6588/6588L
2. Stand-alone mode
The AC characteristics values of stand-alone mode are proportional to the period of the
sampling frequency (fsamp).
DVDD=DVDD’=AVDD=4.5 to 5.5 V, DGND=AGND=0 V, Ta= –40 to +85°C
When fsamp=8kHz
Symbol
tST
Min.
40
Typ.
––
Max.
––
Unit
ms
tSP
40
––
––
ms
PAUSE pulse width
tPSE
40
––
––
ms
Hold time of CA1, CA2, CA3, REC/PLAY for MON rise
tCAH
1
––
––
ms
Address control time at the start of record/playback
tAD1
––
1
––
ms
Address control time at the end of recording
tAD2
––
1
––
ms
tSPV
––
––
500
ms
Silence during repeated playback
tMID
––
1.5
––
ms
Time from input of PAUSE pulse until pause
tPP
––
––
250
ms
tPSP
––
––
500
ms
Oscillator stable time after input of ST pulse
tANA
––
32
––
ms
SP pulse (during recording) to the fall of MON
tSPM1
––
––
1
ms
SP pulse (during playback) to the fall of MON
tSPM2
––
––
260
ms
PDMD Standby transient time at start of playback
tAOR
––
64
––
ms
="L"
tAOF
––
256
––
ms
tMS
––
70
––
ms
SP pulse during pause to record end
tPSP1
––
––
1
ms
SP pulse during pause to playback end
tPSP2
––
––
260
ms
Parameter
ST pulse width (Note 1)
SP pulse width
Time until the release of recording standby
after input of SP pulse during voice standby
Time from input of ST pulse to the continuation of
record/playback during pause
Standby transient time at end of playback
Time from fall of MON to power down state at
the end of playback
ST pulse to MON rise
PDMD SP pulse to MON fall
="H"
ST pulse to voice standby state
SP pulse during pause to record/playback end
tSTM
––
––
1
ms
tSPM1
––
––
1
ms
tSTV
––
––
1
ms
tPSP1
––
––
1
ms
Note: 1. When the PDMD pin is "L", the oscillation stable time is added to tST. The oscillation
stable time is several tens of milliseconds for crystal oscillators and is several
hundreds of microseconds for ceramic oscillators.
16/101
¡ Semiconductor
MSM6588/6588L
3. Microcontroller interface mode
DVDD=DVDD’=AVDD=4.5 to 5.5 V, DGND=AGND=0 V, Ta= –40 to +85°C
When fsamp=8kHz
Symbol
tRR
Min.
200
Typ.
––
Max.
––
Unit
ns
Setup and hold time of CE for RD
tCR
30
Data valid from fall of RD
tDRE
––
––
––
ns
––
200
ns
tDRF
––
10
50
Data Hi-Z from rise of RD
ns
WR pulse width
tWW
200
––
––
ns
tCW
30
––
––
ns
Data setup time to rise of WR
tDWS
100
––
––
ns
Data Hold time from rise of WR
tDWH
30
––
––
ns
Paramenter
RD pulse width
Setup and hold time of CE from WR
Disable time for RD and WR
tDRW
250
––
––
ns
BUSY time after release of RESET (Note 1)
*
tBR
––
––
125
ms
BUSY time after input of 1 nibble command
*
tB1
––
––
16
ms
BUSY time after input of 2 nibble command
*
tB2
––
––
16
ms
BUSY time after input of 2 nibble command data
*
tBD
––
––
16
ms
BUSY time after input of ADRWR command
*
tBAW
––
––
270
ms
command
*
tBAD
—
—
50
ms
Data input time after input of ADRRD command
*
tWAR
270
––
––
ms
Time between output of address data nibbles during
*
ADRRD command
tWDR
50
—
—
ms
BUSY time after input address data of ADRWR
Note:
Items with * are proportional to the period of sampling frequency (fsamp).
1) The oscillation stable time is added to tBR.
The oscillation stable time is several tens of milliseconds for crystal oscillators and is
several hundred of microseconds for ceramic oscillators.
17/101
¡ Semiconductor
Parameter
Address control time at start of
MSM6588/6588L
*
record/playback
Symbol
Min.
Typ.
Max.
Unit
tAD1
––
1
––
ms
Address control time at end of recording
*
tAD2
––
1
––
ms
START command to rise of MON
*
tSTCM
––
––
1
ms
STOP command to fall of MON
*
tSPCM
––
––
1
ms
START command to RPM bit set ("H" level)
*
tSTCR
––
––
16
ms
START command (during voice triggered starting)
*
tSTCV
––
––
16
ms
tSPCV
––
––
500
ms
tPSCP
––
––
16
ms
tSTCP
––
––
500
ms
tSPCP
––
––
500
ms
tWRW
16
––
––
ms
tWXA1
16
––
––
ms
tWXA2
16
––
––
ms
tWXA3
270
––
––
ms
Delay time after input of REC command *
tWRC
16
––
––
ms
Delay time after input of write data
to VPM bit set ("H" level)
STOP command to release of voice standby
*
(during voice triggered starting)
PAUSE command to VPM bit set ("H" level)
*
START command (during pause) to
*
VPM bit reset ("L" level)
STOP command (during pause) to VPM bit reset
*
("L" level)
Delay time after input of
*
DTRW command
Delay time after input of
When
lower 4-bit of X vaddress
DTRW
Delay time after input of
*
*
command middle 4-bit of X address
is being
Delay time after input of
executed
upper 4-bit of X address
When
*
tWWD
50
––
––
ms
Delay time after input of PLAY command *
tWPL
50
––
––
ms
Delay time after input of STOP command *
tWSP
16
––
––
ms
EXT command to rise of MON
*
tEM
125
––
330
ms
"H" level time of MON
*
tMH
––
31
––
ms
"L" level time of MON
*
tML
––
94
––
ms
tERD
––
––
120
ms
tEWR
––
––
120
ms
tWE1
16
—
—
ms
*
tESP
––
––
100
ms
STOP command to record/playback end *
tWEX
––
––
250
ms
executimg MON rise to RD pulse rise
EXT
*
*
(during recording)
command MON rise to WR pulse rise
*
(during playback)
ADPCM data write pulse to input of
*
STOP command
STOP command until rise of MON
Note: Items with * are proportional to the period of sampling frequency (fsamp).
18/101
¡ Semiconductor
MSM6588/6588L
ABSOLUTE MAXIMUM RATINGS (for MSM6588L (3 V Version))
Parameter
Power supply voltage
Symbol
VDD
Input voltage
VIN
Storage temperature
TSTG
Condition
Ta = 25˚C
Rating
Unit
–0.3 to +7.0
V
–0.3 to VDD +0.3
V
–55 to +150
˚C
—
RECOMMENDED OPERATING CONDITIONS (for MSM6588L (3 V Version))
Symbol
VDD
Condition
Range
Unit
DGND = AGND = 0V
2.7 to 3.6
V
Operating temperature
TOP
––
–40 to +85
°C
Master clock frequency
fOSC
––
4.0 to 8.192
MHz
Parameter
Power supply voltage
ELECTRICAL CHARACTERISTICS (for MSM6588L (3 V Version))
DC Characteristics
DVDD=DVDD’=AVDD=2.7 to 3.6 V, DGND=AGND=0 V, Ta= –40 to +85°C
Parameter
"H" input voltage
Symbol
VIH
Condition
––
Typ.
Min.
0.85¥VDD ––
––
Unit
V
Max.
"L" input voltage
VIL
––
––
––
0.15¥VDD
V
"H" output voltage
VOH
IOH = –40mA
VDD–0.3
––
––
V
"L" output voltage
VOL
IOL = 2mA
––
––
0.45
V
"H" input current (Note 1)
IIH1
VIH = VDD
––
––
10
mA
"H" input current (Note 2)
IIH2
VIH = VDD
––
––
20
mA
"L" input current (Note 3)
IIL1
VIL = GND
–10
––
––
mA
"L" input current (Note 2)
IIL2
VIL = GND
–20
––
––
mA
"L" input current (Note 4)
IIL3
VIL = GND
–400
––
–10
mA
––
7
15
mA
––
––
15
mA
––
––
100
mA
Operating current
consumption
IDD
fOSC = 8MHz,
no load
When power down,
Stand by current
consumption
IDDS
no load Ta = –40 to +70°C
When power down,
no load Ta = –40 to +85°C
Note: 1.
2.
3.
4.
Applicable to all input pins, excluding the XT pin.
Applicable to the XT pin.
Applicable to all input pins without pull-up resistors, excluding the XT pin.
Applicable to input pins (ST, SP, PAUSE) with pull-up resistors, excluding the XT pin.
19/101
¡ Semiconductor
MSM6588/6588L
Analog Characteristics
DVDD=DVDD’=AVDD=2.7 to 3.6 V, DGND=AGND=0 V Ta= –40 to +85°C
Parameter
Symbol
VDAE
Condition
no load
Min.
––
Typ.
Max.
––
5
Unit
mV
VFIN
—
1/4¥VDD
––
3/4¥VDD
V
RFIN
––
1
—
––
MW
VADIN
––
1/4¥VDD
—
3/4¥VDD
V
RADIN
––
1
—
––
MW
Op-amp open loop gain
GOP
fIN = 0 to 4kHz
40
—
––
dB
Op-amp input impedance
RINA
––
1
—
––
MW
Op-amp load resistance
ROUTA
––
200
—
––
kW
AOUT load resistance
RAOUT
––
50
—
––
kW
FOUT load resistance
RFOUT
––
50
—
––
kW
DA output relative error
FIN admissible input voltage
range
FIN input impedance
ADIN admissible
input voltage range
ADIN input impedance
AC Characteristics
1. Common characteristics in stand-alone mode and microcontroller interface mode
DVDD=DVDD’=AVDD=2.7 to 3.6 V, DGND=AGND=0 V, Ta= –40 to +85°C
When fsamp=8 kHz
Parameter
RESET pulse width
RESET execution time (Note 1) *
Symbol
tRST
Min.
Typ.
Max.
Unit
1
––
––
ms
tREX
––
125
––
ms
Note: Item with * is proportional to the period of sampling frequency (fsamp).
1) The oscillation stable time is added to tREX.
The oscillation stable time is several tens of milliseconds for crystal oscillators and is
several hundreds of microseconds.
20/101
¡ Semiconductor
MSM6588/6588L
2. Stand-alone mode
The AC cjaracteristics values of stand-alone mode are proportional to the period of the
sampling frequency (fsamp).
DVDD=DVDD’=AVDD=2.7 to 3.6 V, DGND=AGND=0 V, Ta= –40 to +85°C
When fsamp=8 kHz
Symbol
tST
Min.
40
Typ.
––
Max.
––
Unit
ms
SP pulse width
tSP
40
––
––
ms
PAUSE pulse width
tPSE
40
––
––
ms
Hold time of CA1, CA2, CA3, REC/PLAY for MON rise
tCAH
1
––
––
ms
Address control time at the start of record/playback
tAD1
––
1
––
ms
Address control time at the end of recording
tAD2
––
1
––
ms
tSPV
––
––
500
ms
Silence during repeated playback
tMID
––
1.5
––
ms
Time from input of PAUSE pulse until pause
tPP
––
––
250
ms
tPSP
––
––
500
ms
Parameter
ST pulse width (Note 1)
Time until the release of recording standby
after input of SP pulse during voice standby
Time from input of ST pulse to the continuation of
record/playback during pause
Oscillator stable time after input of ST pulse
tANA
––
32
––
ms
SP pulse (during recording) to the fall of MON
tSPM1
––
––
1
ms
SP pulse (during playback) to the fall of MON
tSPM2
––
––
260
ms
PDMD Standby transient time at start of playback
tAOR
––
64
––
ms
="L"
tAOF
––
256
––
ms
tMS
––
70
––
ms
SP pulse during pause to record end
tPSP1
––
––
1
ms
SP pulse during pause to playback end
tPSP2
––
––
260
ms
ST pulse to MON rise
tSTM
––
––
1
ms
PDMD SP pulse to MON fall
="H"
ST pulse to voice standby state
tSPM1
––
––
1
ms
tSTV
––
––
1
ms
tPSP1
––
––
1
ms
Standby transient time at end of playback
Time from fall of MON to power down state at
the end of playback
SP pulse during pause to record/playback end
Note: 1. When the PDMD pin is "L", the oscillation stable time is added to tST. The oscillation
stable time is several tens of milliseconds for crystal oscillators and is several
hundreds of microseconds for ceramic oscillators.
21/101
¡ Semiconductor
MSM6588/6588L
3. Microcontroller interface mode
DVDD=DVDD’=AVDD=2.7 to 3.6 V, DGND=AGND=0 V, Ta= –40 to +85°C
When fsamp=8 kHz
Symbol
tRR
Min.
200
Typ.
––
Max.
––
Unit
ns
Setup and hold time of CE for RD
tCR
30
––
––
ns
Data valid from fall of RD
tDRE
––
––
200
ns
Data Hi-Z from rise of RD
tDRF
––
10
50
ns
WR pulse width
tWW
200
––
––
ns
Setup and hold time of CE from WR
tCW
30
––
––
ns
Data setup time to rise of WR
tDWS
100
––
––
ns
Data Hold time from rise of WR
tDWH
30
––
––
ns
Paramenter
RD pulse width
Disable time for RD and WR
tDRW
250
––
––
ns
BUSY time after release of RESET (Note 1)
*
tBR
––
––
125
ms
BUSY time after input of 1 nibble command
*
tB1
––
––
16
ms
BUSY time after input of 2 nibble command
*
tB2
––
––
16
ms
BUSY time after input of 2 nibble command data
*
tBD
––
––
16
ms
BUSY time after input of ADRWR command
*
tBAW
––
––
270
ms
command
*
tBAD
—
—
50
ms
Data input time after input of ADRRD command
*
tWAR
270
––
––
ms
Time between output of address data nibbles during
*
ADRRD command
tWDR
50
—
—
ms
BUSY time after input address data of ADRWR
Note:
Items with * are proportional to the period of sampling frequency (fsamp).
1) The oscillation stable time is added to tBR.
The oscillation stable time is several tens of milliseconds for crystal oscillators and is
several hundred of microseconds for ceramic oscillators.
22/101
¡ Semiconductor
Parameter
Address control time at start of
MSM6588/6588L
*
record/playback
Symbol
Min.
Typ.
Max.
Unit
tAD1
––
1
––
ms
Address control time at end of recording
*
tAD2
––
1
––
ms
START command to rise of MON
*
tSTCM
––
––
1
ms
STOP command to fall of MON
*
tSPCM
––
––
1
ms
START command to RPM bit set ("H" level)
*
tSTCR
––
––
16
ms
START command (during voice triggered starting)
*
tSTCV
––
––
16
ms
tSPCV
––
––
500
ms
tPSCP
––
––
16
ms
tSTCP
––
––
500
ms
tSPCP
––
––
500
ms
tWRW
16
––
––
ms
tWXA1
16
––
––
ms
tWXA2
16
––
––
ms
tWXA3
270
––
––
ms
Delay time after input of REC command *
tWRC
16
––
––
ms
Delay time after input of write data
*
tWWD
50
––
––
ms
Delay time after input of PLAY command *
tWPL
50
––
––
ms
Delay time after input of STOP command *
tWSP
16
––
––
ms
EXT command to rise of MON
*
tEM
125
––
330
ms
"H" level time of MON
*
tMH
––
31
––
ms
"L" level time of MON
*
tML
––
94
––
ms
tERD
––
––
120
ms
tEWR
––
––
120
ms
tWE1
16
—
—
ms
*
tESP
––
––
100
ms
STOP command to record/playback end *
tWEX
––
––
250
ms
to VPM bit set ("H" level)
STOP command to release of voice standby
*
(during voice triggered starting)
PAUSE command to VPM bit set ("H" level)
*
START command (during pause) to
*
VPM bit reset ("L" level)
STOP command (during pause) to VPM bit reset
*
("L" level)
Delay time after input of
*
DTRW command
Delay time after input of
When
lower 4-bit of X vaddress
DTRW
Delay time after input of
*
*
command middle 4-bit of X address
is being
Delay time after input of
executed
upper 4-bit of X address
When
executimg MON rise to RD pulse rise
EXT
*
*
(during recording)
command MON rise to WR pulse rise
*
(during playback)
ADPCM data write pulse to input of
*
STOP command
STOP command until rise of MON
Note: Items with * are proportional to the period of sampling frequency (fsamp).
23/101
¡ Semiconductor
MSM6588/6588L
TIMING DIAGRAMS
Reset Function and Power Down Function
,,
1. Stand-alone mode when the PDMD pin is "L".
VDD
tRST
RESET(I)
tREX
STBY(O)
Unstable
operation
Power dowm Reset
in progress
Power down
2. Stand-alone mode when the PDMD pin is "H" and in microcontroller interface mode.
VDD
tRST
RESET(I)
tREX
STBY(O)
Unstable
Power down
Reset operation
in progress
Standby for
record/playback
24/101
,,,,,,,
,, ,,,,,
¡ Semiconductor
MSM6588/6588L
Stand-alone Mode
1. Timing during recording (PDMD pin="L", VDS pin="L")
RSEL0 - RSEL2 (I)
CSEL1, CSEL2 (I)
CA1 - CA3
(I)
RESET
(I)
REC/PLAY
(I)
ST
(I)
SP
(I)
tST
tCAH
tSP
tSPM1
Oscillation stop
Oscillation start
XT
XT
(I)
(O)
Oscillation in progress
tANA
MON
(O)
STBY
(O)
tAD1
Power down
tAD2
Analog stable time
Recording
Address control
Power down
Address control
2. Timing during recording by voice triggered starting (PDMD pin="L", VDS pin="H")
RSEL0 - RSEL2 (I)
CSEL1, CSEL2 (I)
CA1 - CA3
(I)
RESET
(I)
REC/PLAY
(I)
ST
(I)
SP
(I)
tST
tCAH
tSP
tSP
tSPV
tSPM1
Oscillation start
XT
XT
(I)
(O)
Oscillation stop
Oscillation in progress
tANA
MON
(O)
STBY
(O)
tAD1
Power down Analog stable time
Standby for voice
Determined as voice
tAD2
Recording
Power down
Address control
Address control
When the STOP pulse is input during the standby for voice,
the IC goes into the power-down state.
25/101
¡ Semiconductor
MSM6588/6588L
3. Timing during playback (PDMD pin="L")
RESET
(I)
,,
,,
,,
,,
,
REC/PLAY ,(I)
,,
,,
,,
,,
,,
,
ST
(I)
SP
(I)
XT
XT
(I)
(O)
MON
(O)
STBY
(O)
AOUT
(O)
,
tST
,
tSP
Oscillating
tSPM2
tAOR
tANA
Power down
tAD1
tMS
tAOF
Analog
Standby
stable time transition time
Playback
Standby transition time
Power down
4. Timing during repeated playback (PDMD pin="L")
ST
(I)
SP
(I)
MON
(O)
STBY
(O)
AOUT
(O)
tSP
tSPM2
tMS
tANA
tAOR
Power down
First playback
Analog stable Standby
time
transition time
tMID
tAOF
Second playback
No voice
Power down
n-th playback
Standby
transition time
Note: Repeated playback is executed only when only one serial register is connected.
26/101
,,,,,,,,
, ,, ,,,,,
¡ Semiconductor
MSM6588/6588L
5. Timing during recording (PDMD pin="H", VDS pin="L")
RSEL0 - RSEL2 (I)
CSEL1, CSEL2 (I)
CA1 - CA3
(I)
RESET
(I)
REC/PLAY
(I)
tST
ST
(I)
SP
(I)
tCAH
tSP
Oscillation
stop
Oscillation start
XT
XT
(I)
(O)
Oscillating
tSPM1
tSTM
MON
(O)
STBY
(O)
tAD1
tAD2
Standby
Recording
Power down
Address control
Standby
Power down
Address control
6. Timing during recording by voice triggered starting (PDMD pin="H", VDS pin="H")
RSEL0 - RSEL2 (I)
CSEL1, CSEL2 (I)
CA1 - CA3
(I)
RESET
(I)
REC/PLAY
(I)
ST
(I)
SP
(I)
tST
tCAH
tSP
Oscillation
start
XT
XT
(I)
(O)
MON
(O)
STBY
(O)
tSP
tSPM1
tSPV
tSTV
Oscillation stop
Oscillating
tAD1
Power down
Standby
Standby for voice
Determined as voice
tAD2
Recording
Standby
Power down
Address control
Address control
When the STOP pulse is input during the standby for voice,
the IC goes into the power-down state.
27/101
¡ Semiconductor
MSM6588/6588L
7. Timing during playback (PDMD pin="H")
RESET
(I)
REC/PLAY (I)
,,
,,
,,
,,
ST
(I)
,,
,,
tST
,,
,,
,,
,,
,
,,
tSP
SP
(I)
XT
XT
(I)
(O)
tSTM
MON
(O)
STBY
(O)
AOUT
(O)
,,
,,
,,
,,
,,
,,
,,
,,
,,
tSPM1
GND level
tAD1
Standby
Power down
Playback
Standby
Power down
Address control
8. Timing during repeated playback (PDMD pin="H")
RESET
(I)
ST
(I)
SP
(I)
MON
(O)
STBY
(O)
AOUT
(O)
tSP
tSTM
tSPM1
1/2 VDD
level
1/2 VDD
level
GND level
GND level
tAD1
tAD1
Power down
Standby
First playback
Address control
2nd playback
n-th playback
Standby
Power down
No voice
Note: Repeated playback is executed only when only one serial register is connected.
28/101
¡ Semiconductor
MSM6588/6588L
9. Timing of pause in record/playback
tST
ST
tST
(I)
Start pulse
SP
tSP
Re-start pulse
(I)
tPSE
tPSE
PAUSE (I)
tPP
tPST
tPP
tPSP1
tPSP2
MON (O)
Standby
Record/Playback
Pause
Record/Playback
Pause
Standby
Note: tPSP1 ...... for recording or playback with the PDMD pin="H"
tPSP2 ...... for recording or playback with the PDMD pin="L"
29/101
,
,
¡ Semiconductor
Microcontroller Interface
1. Data read (RD pulse)
CE
(I)
RD
(I)
tCR
D0 - D3 (I/O)
2. Data write (WR pulse)
CE
(I)
WR
(I)
tCW
,
, ,
,
,
MSM6588/6588L
tCR
tRR
tDRE
tDRF
tCW
tWW
tDWS
tDWH
D0 - D3 (I/O)
30/101
¡ Semiconductor
MSM6588/6588L
3. Input method of 1 nibble command (NOP, PAUSE, PLAY, REC, START and STOP
commands)
WR
(I)
tDRW
RD
(I)
D0 - D3
(I/O)
Command input
Status output
tB1
Status register
BUSY bit
4. Input method of 2 nibble command (SAMP, CHAN and VDS commands)
WR
(I)
tDRW
RD
tDRW
(I)
Status output
D0 - D3
Status output
(I/O)
Command input (first nibble)
Status register
tB2
Data input (second nibble)
tBD
BUSY bit
31/101
¡ Semiconductor
MSM6588/6588L
5. Input method of ADRWR command
WR
(I)
RD
(I)
D0 - D3
(I/O)
Status
Status register
ADRWR command
input (first nibble)
tBAW
Address data
input (2nd nibble)
tBAD
Address data input
(3rd nibble)
tBAD
Address data input
(9th nibble)
WR pulse
input enabled
tBAD
BUSY bit
Note: 1. In the BUSY bit of the status register, input the command after checking that it is not
in the BUSY state.
2. Next, input the address data into 2nd through 9th nibble command, but after checking
that the status is not BUSY by either method as follows.
• Check on the Busy bit of the status register
• Input the next WR pulse after the waiting time of tBAW or tBAD
6. Input method of ADRRD command
WR
(I)
tWAR
RD
(I)
D0 - D3
(I/O)
tWDR
tWDR
WR, RD pulse
input enabled
Command input
Address data output
Address data output
(first nibble)
(2nd nibble) (3rd nibble) (4th nibble)....(8th nibble)
(9th nibble)
Note: 1. In the BUSY bit of the status register, input the command after checking that it is not
in the BUSY state.
2. Next, read out the address data into 2nd through 9th nibble command, but this can
not check the BUSY bit by the RD pulse input. Input the next RD pulse after waiting
time of tWAR or tWDR.
32/101
¡ Semiconductor
MSM6588/6588L
7. Recording method by START command
RESET
(I)
WR
(I)
RD
(I)
D0 - D3
(I/O)
,,
,,
,,
,,
,,
,,
START command
(O)
STBY
(O)
,,
,
tBR
Status register
,,
,
(STOP command)
tSTCM
MON
,,
,,
tSPCM
tB1
tB1
BUSY bit
RPM bit
tAD1
tAD2
tSTCR
Power down
Standby
Recording
Reset operation
in progress
Address control
Standby
Power down
Address control
8. Timing of voice triggered starting
WR
(I)
RD
(I)
D0 - D3
(I/O)
START command
MON
(STOP command)
(STOP command)
tSPCV
tSPCV
Status
(O)
tB1
Status register
tB1
tB1
BUSY bit
RPM bit
VPM bit
tAD1
tSTCR, tSTCV
Standby
Standby for voice
tAD2
Recording
Address control
Determined
as voice
Standby
Address control
When STOP command is input, the
IC enters standby for recording.
33/101
¡ Semiconductor
MSM6588/6588L
9. Playback method using START command
RESET
(I)
WR
(I)
RD
(I)
D0 - D3
(I/O)
,,
,,
,,
,,
,,
,,
,,
,
START command
Status
MON
(O)
STBY
(O)
,,
,,
,
(STOP command)
tSPCM
tSTCM
tBR
Status register
,,
tB1
tB1
BUSY bit
RPM bit
tSTCR
AOUT
1/2 VDD
level
1/2 VDD level
(O)
GND level
GND level
tAD1
Power down
Playback
Standby
Reset operation
in progress
Standby
Power down
Address control
10. Timing of pause in record/playback using PAUSE command
WR
(I)
RD
(I)
D0 - D3
(I/O)
START command
PAUSE command
START command
PAUSE command
STOP command
tSTCM
MON
(O)
tSPCM
Status register
tB1
tB1
tB1
tB1
tB1
BUSY bit
RPM bit
tSTCR
tPSCP
tSTCP
tPSCP
tSPCP
VPM bit
Standby
Record/Playback
Pause
Record/Playback
Pause
Standby
34/101
¡ Semiconductor
MSM6588/6588L
11. Timing of data transfer by DTRW command
tWRW tWXA1 tWXA2
WR
(I)
RD
(I)
D0 - D3
(I/O)
tWXA3
tWRC
tWWD
Next command
input enabled
tWSP
tWPL
STOP
command
DTRW
command
lower 4 bits
of X address
middle 4 bits
of X address
upper 4 bits
of X address
REC
Write-in
command data
Address input
PLAY
command
Write access
Read-out
data
Read access
12. Timing of recording by EXT command
RESET
(I)
,,
,,
,,
,,
WR
(I)
RD
(I)
,,
,,
,
,
D0 - D3 (I/O)
REC
command
EXT
command
tEM
MON
(O)
STBY
(O)
Power down
Standby
ADPCM data
ADPCM data
tMH
tML
tERD
Recording
tESP
STOP command
Next command
input enabled
tWEX
Standby Power down
35/101
¡ Semiconductor
MSM6588/6588L
13. Timing of playback by EXT command
RESET
(I)
,,
,,
,,
WR
(I)
RD
(I)
,,
,,
,,
,,
,
D0 - D3 (I/O)
Play
EXT
command command
Status
tEM
MON
(O)
STBY
(O)
AOUT
(O)
ADPCM data
ADPCM data
tMH
tML
tEWR
Standby
STOP command
Next command
input enabled
tWEX
1/2 VDD
level
1/2 VDD level
GND level
Power down
tESP
GND level
Playback
Standby Power down
36/101
¡ Semiconductor
MSM6588/6588L
FUNCTIONAL DESCRIPTION
Recording Time and Memory Capacity
Recording time depends on the memory capacity of the external serial registers, sampling
frequency, and the ADPCM bit length, and is expressed as
1.024 ¥ memory capacity(Kbit)
(sec)
sampling frequency (kHz) ¥ bit length
Recording time =
For example, if the sampling frequency is 5.3 kHz with a 3bit ADPCM and 4 serial registers, it
is possible to record up to 262 seconds because
Recording time=
1.024 ¥ 1024 (Kbit) ¥ 4 = 262 (sec)
5.3 (kHz) ¥ 3(bit)
Analog Input Amplifier Circuit
,,
This IC has two built-in operational amplifiers for amplifying the microphone output. Each OP
amplifier is provided with the inverting input pin and output pin. The analog circuit reference
voltage SG (signal ground) is connected internally to the non-inverting input of each OP amplifier.
For amplification, form an inverting amplifier circuit and adjust the amplification ratio by using
external resistors as shown below.
VIN
VLO
VMO
VDD
–
+
R1
R3
R2
MIN
MOUT
R4
LIN
–
+
VLO
LOUT
–
+
OP amp1
R4
R3
VMO=
R2 • R4
R1 • R3
1/2VDD
VFIN (min.)
OP amp2
SG
VLO=
VFIN (max.)
VIN (V)
GND
During recording, the output VLO of OP amp 2 is connected to the input FIN of the LPF. Adjust
the amplification ratio by using the external resistors so that the VLO amplitude is within the FIN
admissible input voltage (VFIN) range.
If VLO exceeds the VFIN range, the LPF output waveform will be distorted.
The table below shows an example of the FIN admissible input voltage range for the MSM6588
and the MSM6588L.
Parameter
Power Surpply
Voltage VDD
MSM6588
5V
3V
MSM6588L
FIN admissible input Voltage range VFIN
min
max
1V
0.75 V
4V
2.25 V
FIN admissible
input Voltage
3Vp-p
1.5Vp-p
The value of the OP amp load resistance ROUTA is 200kW minimum. Therefore the values of the
inverting amplifier circuit feedback resistors R2 and R4 should be 200 kW or more.
37/101
¡ Semiconductor
MSM6588/6588L
Connection of LPF Circuit Peripherals
Inside the IC, the AMON pin is connected to the output of the amplifying circuit in recording
mode (LOUT pin) and output of the DA converter in playback mode. This means that the AMON
pin is directly connected to the input pin (FIN pin) of the built-in LPF.
Both the FOUT pin and AOUT pin are output pins of the built-in LPF. The FOUT pin is connected
to the input pin (ADIN pin) of the AD converter and the AOUT pin is connected to a speaker
through the speaker amplifier.
The connection of the FOUT pin and the AOUT pin changes according to the output of LPF, SG
level or GND level inside the LSI depending on the operation state which is summarized by the
following:
• Microcontroller interface mode and stand-alone mode when the PDMD pin ="H"
Analog pin
During operation (RESET pin="H")
At power down
(RESET pin="L")
FOUT pin
GND level
AOUT pin
GND level
Recording mode
LPF output
(record wave form)
Playback mode
LPF output
LPF output
SG level
(playback wave form)
• Stand-alone mode when the PDMD pin ="L"
Analog pin
At power down
FOUT pin
GND level
AOUT pin
GND level
During operation
Recording mode
LPF output
(record wave form)
GND level
Playback mode
LPF output
LPF output
(playback wave form)
38/101
¡ Semiconductor
MSM6588/6588L
• Microcontroller interface mode and stand-alone mode when the PDMD pin ="H"
Speaker drive amplifier
LIN
–
+
LOUT AMON
FIN
Playback
mode
SG
AOUT
FOUT
ADIN
Record
mode
LPF
Playback
mode
–
+
ADC
Record
SG mode
DAC
GND
Power
down
–
+
GND
Power
down
Note: Switches in the figure denote the state during record operation.
• Stand-alone mode when the PDMD pin ="L"
Speaker drive amplifier
LIN
–
+
SG
LOUT AMON
FIN
AOUT
FOUT
ADIN
Record
mode
Playback
mode
LPF
Play
back
–
+
ADC
DAC
–
+
Power down
GND
Note: Switches in the figure denote the state during record operation.
39/101
¡ Semiconductor
MSM6588/6588L
LPF Characteristics
This IC has a built-in fourth order LPF using switched capacitor filter technology.
The filter characteristics are –40dB/oct. Both the cut-off frequency and frequency
characteristics change in proportion to the sampling frequency (fsamp).
The cut-off frequency is preset to 0.4 times the sampling frequency. The following graph depicts
the frequency characteristics of LPF when fsam = 8 kHz.
Gain
(dB)
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
100
1k
10k
f (Hz)
LPF Frequency Characteristics (fsam=8.0 kHz)
Full Scale of A/D and D/A Converters
Full scale of A/D and D/A converters
Parameter
min (V)
max (V)
amplitude (Vp-p)
MSM6588
0
VDD
VDD
MSM6588L
1 ¥V
DD
4
3 ¥V
DD
4
1 ¥V
DD
2
1. When the MSM6588 is used
VDD (5 V)
VDD-1 (4 V)
1 V (2.5 V)
2 DD
1 V (1 V)
0 V (0 V)
Full scale of A/D and D/A converters
Note: Values in perentheses are for VDD=5.0 V.
LPF admissible input Voltage range
40/101
¡ Semiconductor
MSM6588/6588L
2. When the MSM6588L is used
VDD (3 V)
3 V (2.25 V)
4 DD
1 V (1.5 V)
2 DD
1 V (0.75 V)
4 DD
0 V (0 V)
Full scale of A/D and D/A converters
Note: Values in parentheses are for VDD=3.0 V.
LPF admissible input Voltage range
Voice Triggered Starting
This IC has a voice triggered starting function that starts recording when the amplitude of voice
input exceeds a preset threshold.
The voice triggered starting function is controlled by the VDS pin in stand-alone mode and by
the VDS command in microcontroller interface mode. The voice standby state can be released
by a STOP pulse or the STOP command.
During recording/playback using the EXT command in microcontroller interface mode, voice
triggered starting cannot be used.
Stand-alone mode
Microcontroller interface mode
VDS pin
L
––
H
––
VD1
0
0
1
1
VD0
0
1
0
1
Voice triggered starting
disabled
±VDD/64
(±80mV)
±VDD/32
(±160mV)
±VDD/16
(±320mV)
Voice triggered starting
disabled
±VDD/128
(±24mV)
MSM6588 (5V version)
Values inside ( ) are for
VDD=5.12V
MSM6588L (3V version)
Values inside ( ) are for
VDD=3.072V
Vocie detection level
VVDS
±VDD/64
(±48mV)
±VDD/32
(±96mV)
Voice input level
(ADIN pin)
Upper threshold
+ VVDS
1/2 VDD
– VVDS
Lower threshold
Determined as voice, recording starts
Start signal input
41/101
¡ Semiconductor
MSM6588/6588L
How to Connect an Oscillator
Connect a ceramic oscillator or a crystal oscillator to XT and XT pins as shown below.
The optimal load capacities when connecting ceramic oscillators from MURATA MFG.,
KYOCERA CORPORATION, and TDK CORPORATION are shown below for reference.
MSM6588
MSM6588L
XT
XT
C1
C2
1. MSM6588
Ceramic oscillator
Type
Freq(MHz)
CSA4.00MG
C1(pF)
C2(pF)
30
30
33
33
—
—
4.0
CST4.00MGW
MURATA
MFG.
Optimal load capacity
CSA6.00MG
6.0
CST6.00MGW
CSA8.00MTZ
8.0
CST8.00MTW
KBR-4.0MSA
KBR-4.0MWS
KBR-4.0MKS
(with capacitor)
4.0
(with capacitor)
6.0
(with capacitor)
8.0
(with capacitor)
4.0
PBRC4.00A
KYOCERA
CORPORATION
KBR-6.0MSA
KBR-6.0MWS
KBR-6.0MKS
PBRC6.00A
KBR-8.0M
KBR-8.0MWS
PBRC8.00A
TDK CORPORATION
FCR4.0MC5
42/101
¡ Semiconductor
MSM6588/6588L
2. MSM6588L
Ceramic oscillator
Type
Freq(MHz)
CSA4.00MG
CST4.00MGW
MURATA
MFG.
(with 30pF capacitor)
CSA6.00MG
CST6.00MGW
(with 30pF capacitor)
CSA8.00MTZ
CST8.00MTW
Optimal load capacity
(with 30pF capacitor)
4.0
6.0
8.0
KBR-4.0MSB
KBR-4.0MKC
(with capacitor)
PBRC4.00A
PBRC4.00B
KYOCERA
CORPORATION
4.0
FCR8.0M2S
30
—
—
30
30
—
—
33
33
—
—
33
33
(with capacitor)
—
—
33
33
—
—
6.0
(with capacitor)
8.0
(with capacitor)
(with 30pF capacitor)
FCR6.0M5
FCR6.0MC5
30
—
FCR4.0M5
TDK CORPORATION
—
33
PBRC8.00A
FCR4.0MC5
30
—
—
KBR-8.0M
PBRC8.00B
30
33
PBRC6.00A
PBRC6.00B
C2(pF)
(with capacitor)
KBR-6.0MSB
KBR-6.0MKC
C1(pF)
(with 30pF capacitor)
4.0
6.0
8.0
33
33
33
33
—
—
33
33
—
—
33
33
—
—
33
33
43/101
¡ Semiconductor
MSM6588/6588L
How to Connect Power Supply
This IC uses a single power supply which is divided into two routes on the wiring, one is to the
analog section, and the other is to the logic section.
VDD
DVDD DVDD' AVDD
MSM6588
MSM6588L
DGND
AGND
The following connections are not permitted.
Power supply
for analog
Power supply
for digital
+5V
DVDD' DVDD
AVDD
DVDD' DVDD
AVDD
Data Configuration of External Serial Registers
The external serial registers are composed of (X address in the word direction) ¥ (depth of 1Kbit) and are divided into the channel index area and the voice (ADPCM) data area.
The maximum address of X address in the word direction can be summarized in the following
table depending on the memory capacity of connected serial registers:
Memory capacity of connected
serial registers (bit)
Maximun X address
256K
0FFh
512K
1FFh
1M
3FFh
2M
7FFh
3M
BFFh
4M
FFFh
44/101
¡ Semiconductor
MSM6588/6588L
1. Channel index area
Addresses 000h-007h, are header addresses for the serial registers and are known as the channel
index area which store the start and stop address of each channel.
The start address and stop address are expressed by 12-bit and by 20-bit, respectively.They store
the header and tail addresses of the voice data for each channel.
Depth of 1 K-bit in the Y direction
20-bit
12-bit
SP0
ST0
ch0
SP1
ST1
ch1
002h
SP2
ST2
ch2
003h
SP3
ST3
004h
SP4
ST4
ch4
005h
SP5
ST5
ch5
006h
SP6
ST6
ch6
007h
SP7
ST7
ch7
X address
000h
001h
992-bit
Unused
ch3
Start address
X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11
Header X address of channel
Stop address
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11
Tail Y address of channel
Lower
upper
Tail X address of channel
Lower
upper
45/101
¡ Semiconductor
MSM6588/6588L
2. Voice (ADPCM) data area
Addresses after 008h of the X address are the voice data area and store ADPCM data.
Depth of 1K-bit in the Y direction
X address
008h
ADPCM data
009h
X direction
Maximum
address
The storage method of ADPCM data per 1 address in the X-direction (1K-bit) is different for 3bit and 4-bit ADPCM. It is summarized as follows:
3-bit ADPCM
3-bit data ¥ 340 samples = 1020-bit stored in the 1K-bit memory area. The Y address is assigned
one address per two samples and is controlled by 00h-A9h.
1K-bit in the Y direction
Y
address
00h
01h
A9h
ADPCM ADPCM ADPCM ADPCM
1
2
3
4
ADPCM
339
Unused
4-bit
ADPCM
340
4-bit ADPCM
4-bit data ¥ 256 samples = 1024-bit are stored in the 1K-bit memory area. The Y address is
assigned one address per two samples and is controlled by 00h-7Fh.
1K-bit in the Y direction
00h
Y
address
ADPCM
1
01h
ADPCM
2
ADPCM
3
7Eh
ADPCM
254
7Fh
ADPCM
255
ADPCM
256
46/101
¡ Semiconductor
MSM6588/6588L
Selection of Serial Registers
RSEL1 and RSEL2 are used select the type and the number of serial registers connected
externally.
The CS4 (RSEL0) pin functions as a CS4 output pin when RSEL1=RSEL2=”H” and as an RSEL0
input pin otherwise to select either 512Kbit or 256Kbit.
RSEL2
L
L
H
H
RSEL1
L
H
L
H
L
H
––
––
CS4
(I)
(I)
(I)
(I)
(O)
One
One
One
Two
Four
512Kbit
1Mbit
1Mbit
1Mbit
RSEL (CS4)
Number of serial registers
256Kbit
Recording Control Modes
The recording control modes include fixed and flex mode during stand-alone operation and
fixed, flex and direct mode during microcontroller interface operation. The recording control
mode is specified by the CSEL1 and CSEL2 pin in stand-alone operation and by data input via
commands (RCON, CSEL1 AND CSEL2) during microcontroller interface operation.
Number of
RCON
CSEL2
CSEL1
L
––
––
8-word
L
L
8-word
Fixed mode
H
recording words
Control mode
Direct mode (only in microcontroller
interface mode)
L
H
4-word
(When the number of the recorded words is wished
H
L
2-word
to be selected in one word, select Flex mode.)
H
H
8-word
Flex mode
1. Direct mode
This mode can be used in microcontroller interface mode only.
The start and stop address of each channel are input to the channel index area directly from the
microcontroller. This means that the assignment of memory capacity of each channel is
controlled by the microcontroller.
2. Fixed mode
This mode can be used in both stand-alone mode and in microcontroller interface mode.
The start and stop address of each channel can be set indirectly by the channel selection (CA1CA3) and they are input to the channel index area.
The memory capacity of the external serial register equally divided by the number of recording
words is assigned to each channel by CSEL1 and CSEL2.
(Hereafter, this will be called the channel memory capacity).
47/101
¡ Semiconductor
MSM6588/6588L
,,,,,,,,
When recording, ADPCM data is written in from the header address of the selected channel
memory capacity. When stopping recording by the STOP signal, the memory capacity after that
is unused.
An example of selecting 4-word as the number of recording words
Memory capacity of serial register
ch0 header address
ch1 header address
Unused
ch3 header address
Unused
ch0
ch1
ch0 memory capacity
ch2 header address
Unused
ch2
ch1 memory capacity
ch3
ch2 memory capacity
ch3 memory capacity
Channel index area
3. Flex mode
This mode can be used in both stand-alone mode and microcontroller interface mode.
The start and stop addresses of each channel are indirectly set by channel selection (CA1 – CA3)
and are input to the channel index area.
When recording at the initial state (no recording has been performed in any channels), it is
necessary to record in the order of ch0 to ch7. When starting recording of ch0, ADPCM data is
stored from the header of the voice data area and the recording is stopped when the STOP signal
is input. When the STOP signal is not input, recording is stopped when the maximum address
of the serial register reached.
When ch1 is selected subsequently, the recordable memory area starts from the address
incremented by 1 from the stop address of ch0 through the maximum address. Similarly, the
recording continues to ch2, ch3.... The start address of chn is the one incremented by 1 from the
stop address of chn-1.
An example of recording 3 words onto 1Mbit serial register
Memory capacity of serial register
,,
,,
31Fh (22h)
ch1
282h
,,
008h
ch0
ch2
320h
Channel index area
SP2
3FFh (A9h)
SP1
281h (30h)
ch0 stop address = SP0
,
ch0 start address = ST0
ST1
ST2
48/101
¡ Semiconductor
MSM6588/6588L
Channel Usage
A channel can be specified by CA1, CA2 and CA3. In stand-alone mode, CA1–CA3 pins are used
while in microcontroller interface mode, command data is input with (CA1–CA3).
1. Selection of a channel in direct mode and flex mode
The number of recording words is 8 and is specified by CA1–CA3 as follows:
CA3
CA2
CA1
Channel
L
L
L
L
ch0
L
H
ch1
L
L
H
L
ch2
H
H
H
ch3
L
L
ch4
H
L
H
ch5
H
H
L
ch6
H
H
H
ch7
2. Channel selection in fixed mode
The relationship between the number of recorded words (CSEL1, CSEL2) and channels (CA1–
CA3) is shown in the following table.
CSEL2
L
L
H
CSEL1
L
H
L
Number of
recorded words
8-word
4-word
2-word
CA3
CA2
L
L
CA1
Channel
L
L
ch0
L
H
ch1
L
H
L
ch2
L
H
H
ch3
H
L
L
ch4
H
L
H
ch5
H
H
L
ch6
H
H
H
ch7
L
L
––
ch0
L
H
––
ch1
H
L
––
ch2
H
H
––
ch3
L
––
––
ch0
H
––
––
ch1
49/101
¡ Semiconductor
MSM6588/6588L
The relationship between the external serial registers, the number of recorded words and the
channel memory capacity is shown in the following table.
CSEL CSEL
Channel memory capacity
Number of
2
1
recorded words
L
L
8-word
L
H
H
4-word
L
2-word
2Mbit
serial
register
256Kbits
256Kbit
serial
register
32Kbits
512Kbit
serial
register
64Kbits
1Mbit
serial
register
128Kbits
(1 second)
(2 seconds)
(4 seconds)
64Kbits
128Kbits
256Kbits
(2 seconds)
(4 seconds)
128Kbits
256Kbits
4Mbit
serial
register
512Kbits
(8 seconds) (16 seconds)
512Kbits
1Mbits
(8 seconds) (16 seconds) (32 seconds)
1Mbits
512Kbits
2Mbits
(8 seconds) (16 seconds) (32 seconds) (64 seconds)
(4 seconds)
Note: Numbers in ( ) are recording time of each channel when the bit rate is 32 kbps.
Assignment to channel and channel memory capacity when connecting a 1 Mbit serial register
Channel index area
,,
ch2
3FFh
3FFh
380h
300h
ch7
2FFh
280h
37Fh
2FFh
27Fh
1FFh
200h
1FFh
ch6
ch3
3FFh
1FFh
200h
ch1
3FFh
007h 000h
008h
8-word
flex
,
000h
H
ch1
ch0
,,
,,
H
ch0
ch5
300h
,,
ch4
200h
,,
17Fh
2-word
,,
fix,
,
ch3
180h
L
,,
0FFh
H
,,
100h
4-word
fix
ch2
0FFh
H
ch1
080h
L
ch0
007h 000h
008h
8-word
fix
007h 000h
008h
L
008h
L
100h
CSEL2 CSEL1
07Fh
007h
X address of serial register
,,
By combining CSEL1, CSEL2, CA1, CA2 and CA3, it is possible to assign (the encircled channels)
ch0=16 seconds, ch2=8 seconds and ch3=8 seconds (fsam=8 kHz, 4 bit ADPCM).
50/101
¡ Semiconductor
MSM6588/6588L
Operation in Stand-alone Mode
1. Power down function
Transition to power down mode is selected by the PDMD pin and is summarized as follows:
PDMD pin
L
Power down operation
The IC automatically enters the power down state except during recording/playback.
The IC powers down by input of a "L" level to the RESET pin. When the RESET pin="H" level,
H
the IC is in stand-by mode and the analog circuit is active. When using the built-in LPF with
external circuit, select this mode.
During power down, the IC stops oscillating to minimize power consumption and the circuit
enters the initialized state.
When using an external clock, input the GND level to the XT pin to reduce power consumption.
2. Master clock frequency and sampling frequency
The relationship between the master clock frequency (fOSC) and the sampling frequency (fsamp)
is summarized in the following table by the SAM pin.
SAM
L
H
fsamp
fOSC
768
fOSC
512
(5.3kHz)
(8.0kHz)
Note: Numbers inside ( ) are for master clock frequency fOSC = 4.096 MHz.
51/101
¡ Semiconductor
MSM6588/6588L
3. Method of recording
(1) Select the sampling frequency by the SAM pin.
(2) Specify whether the voice triggered starting is used by the VDS pin.
(3) Select the number of words by the CSEL1 and CSEL2 pins and the channel by the CA1, CA2,
and CA3 pins.
(4) Input the "H" level to the REC/PLAY pin to set recording mode.
(5) Input a "L" pulse to the ST pin to start recording. To finish recording in the middle, input a
SP pulse. The time between these two pulses is recording time.
When recording is started by input of a "L" pulse to the ST pin and continues to the end of the
channel memory capacity, the recording is automatically finished at that point.
The MON pin outputs a "H" level during recording.
Start pulse
ST
(I)
SP
(I)
MON
(O)
Invalid
Stop pulse
Recording in progress (stopped in the middle)
Channel memory capacity
Start pulse
ST
(I)
MON
(O)
Recording in progress
Channel memory capacity
Recording automatically finished
52/101
¡ Semiconductor
MSM6588/6588L
4. Method of playback
(1) Select the sampling frequency by the SAM pin.
(2) Select the number of words by the CSEL1 and CSEL2 pins and the channel by the CA1, CA2
and CA3 pins.
(3) Input a “L” level to the REC/PLAY pin to set playback mode.
(4) Input a “L” level pulse to the ST pin to start playback. When played back for the duration of
recorded time, the playback ends automatically.
To stop the playback in the middle, input a “L” level pulse to the SP pin.
The MON pin outputs a “H” level during playback.
Do not start playback in channels not recorded because the playback data and time are
undefined. However, playback under these conditions can be halted by a SP pulse.
Start pulse
ST
(I)
MON
(O)
Playback in progress (same as recording time)
Playback automatically
finished
Start pulse
ST
(I)
SP
(I)
MON
(O)
Stop pulse
Playback in progress (stopped in the middle)
Recorded time
By maintaining the ST pin at "L" level, repeated playback is possible.
Repeated playback is executed only when only one serial register is connected.
ST
(I)
SP
(I)
MON
(O)
(stop pulse)
First playback
2nd playback
3rd playback
53/101
¡ Semiconductor
MSM6588/6588L
5. Method of pause in record/playback
By input of a “L” level pulse to the PAUSE pin during record/playback, input a “L” level pulse
to the ST pin. The recording/playback is finished when a “L” level pulse is input to the SP pin.
Start pulse
ST
(I)
PAUSE
(I)
Start pulse
Pause pulse
Pause
Resume
Start pulse
ST
(I)
SP
(I)
PAUSE
(I)
Stop pulse
Pause pulse
Pause
Record/Playback finished
After resuming record/playback, the voice triggered starting circuit does not operate and the
recording is resumed when a START pulse is input.
54/101
¡ Semiconductor
MSM6588/6588L
6. Operation in voice triggered starting
By input of a “H” level to the VDS pin, recording by voice triggered starting can be performed.
Using the voice triggered starting, the memory capacity can be utilized effectively by eliminating
any data prior to voice detection.
However, it does not remove silence data during recording.
Input of a ST pulse initiates standby for voice and recording is started when voice is detected. The
MON pin outputs a “H” level.
ST
(I)
SP
(I)
MON
(O)
Start pulse
Stop pulse
Standby for voice
Recording in progress
Determined as voice
When a STOP pulse is input during standby for voice, the standby for voice is finished and the
IC enters standby for recording.
ST
(I)
SP
(I)
Start pulse
Stop pulse
Standby for recording
Standby for voice
Standby for recording
55/101
¡ Semiconductor
MSM6588/6588L
7. Method of re-recording
7.1 Fixed mode
In this mode, because the memory area that each channel can use is already assigned, rerecording can by performed without interfering with the contents of other channels. Rerecording can be performed from the beginning similar to a new recording, regardless of the
previous recording time.
7.2 Flex mode
In this mode, recording for each channel is started from the address incremented by +1 from the
address of preceding channel, chn-1 (if ch0, the header address of the voice data area) and the
recording continues until the input of a SP pulse. If a SP pulse is not input, the recording is
continued until the maximum address of the external serial register. This indicates that if the
duration of recording is longer than the previously recorded time, it interferes with the contents
of proceeding channels.
The following shows an example in which the first recording is performed as in Figure (a) and
after that each channel is re-recorded.
If the duration of re-recording of ch0 is shorter than the initially recorded time, all the channels
function properly as shown in Figure (b).
If the duration of re-recording of ch1 is longer than the initially recorded time and reaches the
range of ch2, ch0, and ch1 function properly but the playback data of ch2 becomes undefined as
ch2 is played back from the middle of ch1 data.
By re-recording ch2 as shown if Figure (d), ch0-ch2 function properly.
56/101
¡ Semiconductor
MSM6588/6588L
Memory capacity of external serial register
ch0 stop address=SP0
SP1
SP2
Channel index area
,,
,,
ch0
(a)
ch1
ch0 start address=ST0
,,
,,
ch2
ST1
ST2
,,
,
Unused
SP0
,,
,,
,,
,,
(b)
,
ch0 new
,,
ST0
,,
,,
,,
,,
,,
,,
SP1
,,
,
ch1
,,
,,
,,
,,
,,
,,
SP1
ch1 new
ST0
ST1
ch0 new (normal)
,,
ST2
,,
ch0 new
,,
ch2
ST1
,,
SP0
(c)
SP2
SP2
ch2
ST2
ch1 new (normal)
,,
ch2 (undefined)
SP0
(d)
,,
SP1
,,
ch0 new
,,
,
ST0
ch1 new
ST1
SP2
ch2 new
ST2
8. Pull-up resistor
In stand-alone mode, a pull-up resistor is connected internally to the ST, SP and PAUSE pins.
However, the resistor is disconnected during a “L” level input to the RESET pin.
57/101
¡ Semiconductor
MSM6588/6588L
Operation in Microcontroller Interface Mode
There are 13 data bus commands, D0 to D3 and WR, RD and CE which control the MSM6588/
6588L in this mode. It has an internal status register so that the state of the LSI can be monitored.
1. Command input method
Input of commands and data can be performed by input of a “L” level (WR pulse) during
command data input on the D0 to D3-pin.
Input of a “L” level (RD pulse), outputs status or data to the D0 to D3-pin.
The CE pin controls enable/disable of the WR and RD pulses. Input of a “L” level enables WR
and RD pulses, while a “H” level disables WR and RD pulses and D0 to D3 become highimpedance. When using the D0 to D3-pin with the MSM6588/6588L alone, the CE pin can be
fixed at the “L” level.
1.1 Input method of 1 nibble command
(1) Input a RD pulse to fetch the contents of the status register and make sure that the BUSY bit
is 0. When it is 1, repeat input of RD pulses until it becomes 0.
(2) Send a command to the D0 to D3-pin to input a WR pulse.
(3) Confirm that it is not BUSY state as in (1) during input of the next command. Alternatively,
wait for the duration of the BUSY time.
CE
(I)
WR
(I)
,,
RD
,,
,,
(I) ,,,,,
,,
,,
,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,
D0 - D3 (I/O)
Status output
Command input
Status output
Busy time
Next command
input enabled
58/101
¡ Semiconductor
MSM6588/6588L
RD pulse input
No
Status output
BUSY=0?
BUSY bit confirmed
Yes
WR pulse input
Command input
1.2 Input method of 2 nibble command
(1) Input a RD pulse to confirm the BUSY bit.
(2) Send a command to the D0 to D3-pin to input an WR pulse.
(3) Input a RD pulse and wait until the BUSY bit becomes 0. Alternatively, wait for the duration
of the BUSY time.
(4) Set data to the D0 to D3-pin to input a WR pulse.
CE
WR
,(I)
RD
(I)
,,
,,
,,
(I)
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
D0 - D3 (I/O)
Status
1st nibble
Command
Status
2nd nibble
Command
Busy time
2nd nibble
Command
59/101
¡ Semiconductor
MSM6588/6588L
RD pulse input
No
BUSY=0?
Status output
BUSY bit confirmed
Yes
No
WR pulse input
1st nibble, command input
RD pulse input
Status output
BUSY=0?
BUSY bit confirmed (or wait for BUSY time)
Yes
WR pulse input
2nd nibble, data input
60/101
¡ Semiconductor
MSM6588/6588L
2. Explanation of commands
NOP
Code
D D D D
3 2 1 0
0 0 0 0
PAUSE
0
0
0
1
(PAUSE) Suspends record/playback temporarily.
PLAY
0
0
1
0
(PLAYBACK) Set playback mode.
REC
0
0
1
1
(RECORD) Sets recording mode.
START
0
1
0
0
(START) Starts record/playback.
STOP
0
1
0
1
(STOP) Stops record/playback. In record mode, the contents of the
SAMP
0
1
1
0
CHAN
0
1
1
1
ADRWR
1
0
0
0
Command
Function of commands
(NON OPERATION) no function
address counter are stored in the channel index area as the stop address.
(SAMPLING FREQUENCY) Specifies the sampling frequency and control
mode with the following (1) nibble.
(CHANNEL) Specifies the channel and control mode with the following
(1) nibble.
(ADDRESS WRITE) In direct mode, stores the start address and the
stop address to the channel index area with the following (8) nibbles.
ADRRD
1
0
0
1
(ADDRESS READ) Reads out the start address and the stop address
stored in the channel index area by reading of the following (8) nibbles.
During this operation, the contents of the status register cannot be read.
DTRW
1
0
1
0
EXT
1
0
1
1
(DATA READ WRITE) Transfers data to the external serial registers
through the data bus with preset timing.
(EXTERNAL) Performs record/playback by input and output of ADPCM
data through the data bus by preset timing. Use this command when
using SRAM or a hard disk as storage media of voice data. Does not
control the external serial registers nor addresses.
VDS
1
1
0
0
(VOICE DETECT SELECT) Selects the voice triggered starting condition
and the bit length of ADPCM with the following (1) nibble.
61/101
¡ Semiconductor
MSM6588/6588L
Command List
NOP
1st nibble
command
0 0 0 0
PAUSE
0
0
0
1
1 nibble command
PLAY
0
0
1
0
1 nibble command
REC
0
0
1
1
1 nibble command
START
0
1
0
0
1 nibble command
STOP
0
1
0
1
SAMP
0
1
1
0
Command
CHAN
0
1
1
1
D3
2nd nibble command
D2
D1
D0
Note
1 nibble command
1 nibble command
CSEL2
RCON
CSEL1
CA3
SA1
CA2
SA0
CA1
2 nibble command
CSELn
control mode
SAn
sampling freq
2 nibble command
RCON
control mode
CAn
channel
ADRWR
1
0
0
0
Inputs address data (2nd-9th nibble)
9 nibble command
ADRRD
1
0
0
1
Outputs address data (2nd-9th nibble)
9 nibble command
DTRW
1
0
1
0
EXT
1
0
1
1
VDS
1
1
0
0
Transfers data by preset timing
Records/plays back by
preset timing
––
BIT
VD1
VD0
2 nibble command
BIT
ADPCM bit length
VDn Voice triggered
starting condition
62/101
¡ Semiconductor
MSM6588/6588L
3. Explanation of status register
The status register is a 4-bit register and outputs the current state to the D0 to D3 pin by input
of a “L” level to the RD pin.
However, the contents of the status register cannot be read during the execution of ADRRD or
during record/playback by the EXT command.
D3
D2
D1
D0
FULL
VPM
RPM
BUSY
Status register
(1) BUSY
“H” level of this bit indicates that the RESET operation is in progress or a command is being
processed. Do not issue commands at this time.
(2) RPM
This bit becomes “H” level during recording or playback. Do not issue commands except the
STOP command, PAUSE command and START command after release of pause.
(3) VPM
This bit becomes “H” level when 1) standby for voice after voice triggered recording is started
and 2) suspending recording/playback by the PAUSE command.
(4) FULL
This status is used for recording in a flex mode. This bit is set to a “H” level when recording is
through to the end of the channel capacity which is maximum address of the serial register
connected to MSM6588/6588L. It is reset when either a REC command, PLAY command or
START command is input. After recording in flex mode, start recording of the next channel after
confirming the FULL bit.
63/101
¡ Semiconductor
MSM6588/6588L
BUSY Stauts
Bit
Enable
Duration of
BUSY
125ms (Note 3)
After input of 1 nibble command
Enable
16ms
After input of 2 nibble command
Enable
16ms
After input of data of 2 nibble command
Enable
16ms
After input of the ADRWR command
Enable
270ms
After input of address data of the ADRWR command
Enable
50ms
After input of the ADRRD command
Disable
270ms
After output address data of the ADRRD command
Disable
50ms
After input of the DTRW command
Enable
16ms
After input of lower 4-bit of ¥ address
Enable
16ms
execution of
After input of middle 4-bit of ¥ address
Enable
16ms
the DTRW
After input of upper 4-bit of ¥ address
Enable
270ms
command
After input of the REC command
Enable (Note 2)
16ms
After input of write-in data
BUSY Condition
After releasing RESET
During
Enable (Note 2)
50ms
After input of the PLAY command
Disable
50ms
After input of the STOP command
Enable (Note 2)
50ms
Note: 1. The duration of BUSY is proportional to the period of the sampling frequency
(fsamp).
2. When enabling only the data write access after input of the DTRW command, the
BUSY state can be confirmed by the BUSY bit.
3. The oscillation stable time is added to the duration of BUSY after releasing RESET.
The oscillation stable time is several tens of milliseconds for crystal oscillators and is
several hundreds of microseconds for ceramic oscillators.
64/101
¡ Semiconductor
MSM6588/6588L
4. Selection of sampling frequency (SAMP command)
Data that follows the SAMP command will select the sampling frequency.
The relationship between the master clock oscillation frequency (fOSC) and the sampling
frequency (fsamp) is shown in the following table using data bits SA1 and SA0.
Sampling frequency (fsam)
SA1
SA0
0
0
fosc / 1024
(4.0 kHz)
0
1
fosc / 768
(5.3 kHz)
1
0
fosc / 640
(6.4 kHz)
1
1
fosc / 512
(8.0 kHz)
Note: Numbers in ( ) are for master clock frequency fOSC=4.096 MHz.
5. Recording control modes (SAMP and CHAN commands)
In microcontroller interface mode, there are three record control modes. They are direct Fixed,
and flex mode. Control mode selection is performed by data bit RCON of the CHAN command
and data bits CSEL1 and CSEL2 of the SAMP command.
Number of
record words
8-word
RCON
CSEL2
CSEL1
0
––
––
0
0
8-word
0
1
4-word
1
0
2-word
1
1
8-word
1
Control mode
Direct mode
Fixed mode
Flex mode
(1) Direct mode
The start and stop address of each channel are input directly to the channel index area using the
ADRWR command from a microcontroller. This means that the assignment of memory capacity
for each channel is controlled by the microcontroller.
(2) Fixed mode
The start and stop address of each channel is input indirectly to the channel index area by channel
selection from a microcontroller. Memory capacity of each channel is assigned by equally
dividing the memory capacity of the external serial register by the number of recording words.
(3) Flex mode
The start and stop addresses of each channel are input indirectly to the channel index area by
channel selection from a micro-controller. There is no assignment of memory capacity of each
channel so that the recording time for each channel can be set arbitrarily.
Refer to the Recording Control Modes on each mode description. In the meantime, since the
method of re-recording for the fixed and flex modes is the same as that of the stand-alone mode,
refer to Item 7, Method of re-recording for the stand-alone mode.
65/101
¡ Semiconductor
MSM6588/6588L
6. Selection of channel (CHAN command)
6.1 Channel selection in direct mode and in flex mode
CA3
CA2
CA1
Channel
0
0
0
ch0
0
0
1
ch1
0
1
0
ch2
0
1
1
ch3
1
0
0
ch4
1
0
1
ch5
1
1
0
ch6
1
1
1
ch7
6.2 Channel selection in fixed mode
CSEL2
0
0
1
CSEL1
0
1
0
Number of
recorded words
8-word
4-word
2-word
CA3
CA2
CA1
Channel
0
0
0
ch0
0
0
1
ch1
0
1
0
ch2
0
1
1
ch3
1
0
0
ch4
1
0
1
ch5
1
1
0
ch6
1
1
1
ch7
0
0
––
ch0
0
1
––
ch1
1
0
––
ch2
1
1
––
ch3
0
––
––
ch0
1
––
––
ch1
66/101
¡ Semiconductor
MSM6588/6588L
7. Input/output of start and stop address (ADRWR and ADRRD commands)
When recording in direct mode, the start and stop address of each channel is directly input to the
channel index area by the ADRWR command.
The start address consists of 12bit and the stop address consists of 20bit. They denote the header
and tail addresses of the channel, respectively.
Start address STn
X0
X1
X2
X3
X4
X5
X6
X8
X9 X10 X11
Header address of channel
Lower
Upper
Stop address SPn
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X0
X1
Tail Y address of channel
Lower
X2
X3
X4
X5
X6
X8
X9 X10 X11
Tail X address of channel
Upper Lower
Upper
The X addresses of the voice data area are 008h-FFFh (when connecting the serial register for
4Mbit).
The tail Y address changes depending on the ADPCM bit length, the range that can be specified
is 00h-A9h (for 3bit ADPCM) and 00h-7Fh (for 4bit ADPCM). For ordinary recording, A9h or 7Fh
(tail address) should be input as the tail Y address.
The ADPCM and ADRRD commands input the start and stop address after issuing the
commands with the following 8 nibble data.
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D3
D2
D1
D0
1st nibble
1
0
0
0
Contents
ADRWR command
2nd nibble
Y3
Y2
Y1
Y0
Stop address
3rd nibble
Y7
Y6
Y5
Y4
(Y address)
4th nibble
X3
X2
X1
X0
5th nibble
X7
X6
X5
X4
6th nibble
X11
X10
X9
X8
7th nibble
X3
X2
X1
X0
8th nibble
X7
X6
X5
X4
9th nibble
X11
X10
X9
X8
Stop address
(X address)
Start address
(X address)
7.1 Input method of address data by the ADRWR command
(1) After confirming the BUSY bit, input the ADRWR command.
(2) After confirming the BUSY bit or waiting for the BUSY time period, input the low 4bit (Y3,
Y2, Y1, Y0) of the Y stop address. This operation is to be repeated for 8 times to input the stop
and start address.
7.2 Output method of address data by the ADRRD command
(1) After confirming the BUSY bit, input the ADRRD command.
(2) Wait for the BUSY time period and input a RD pulse to output the address data from the data
bus. This operation is to be repeated for 8 times to get the stop and start address to the
microcontroller.
(3) After input of the ninth nibble RD pulse, the next command is enabled after waiting for the
BUSY time period. During the execution of the ADRRD command, the contents of the status
register cannot be confirmed. It is necessary to wait for the BUSY time period between each
RD pulse.
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ADRWR Command Flow Chart
1st nibble
ADRWR command
2nd nibble
No
BUSY=0?
WR pulse input
3rd nibble
BUSY bit confirmed
(or wait for BUSY time)
Input of lower 4 address bits of
Y stop address
Input of upper 4 address bits of
Y stop address
4th nibble
Input of lower 4 address bits of
X stop address
5th nibble
Input of middle 4 address bits of
X stop address
6th nibble
Input of upper 4 address bits of
X stop address
7th nibble
Input of lower 4 address bits of
X start address
8th nibble
Input of middle 4 address bits of
X start address
9th nibble
No
BUSY=0?
WR pulse input
Input of upper 4 address bits of
X start address
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ADRRD Command Flow Chart
1st nibble
ADRRD command
2nd nibble
Wait for BUSY time
RD pulse input
3rd nibble
Output of lower 4 address bits of
Y stop address
Output of upper 4 address bits of
Y stop address
4th nibble
Output of lower 4 address bits of
X stope address
5th nibble
Output of middle 4 address bits of
X stop address
6th nibble
Output of upper 4 address bits of
X stop address
7th nibble
Output of lower 4 address bits of
X start address
8th nibble
Output of middle 4 address bits of
X start address
9th nibble
Wait for BUSY time
RD pulse input
Input of upper 4 address bits of
X start address
Wait for BUSY time
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8. Specifying ADPCM bit length (VDS command)
The ADPCM bit length is specified by the VDS command data (bit).
BIT
ADPCM bit length
0
3-bit
1
4-bit
9. Specifying voice triggered starting mode (VDS command)
Specify whether voice triggered starting is used and the voice detection level by the VDS
command data bits (VD0 and VD1).
Voice detection level VVDS
VD1
VD0
0
0
0
1
1
1
±VDD/32 (±96 mV)**
MSM6588 (5 V version)
Voice triggered starting
MSM6588L (3 V version)
Voice triggered starting
disabled
±VDD/64 (±80 mV)*
disabled
±VDD/128 (±24 mV)**
0
±VDD/32 (±160 mV)*
±VDD/64 (±48 mV)**
1
±VDD/16 (±320 mV)*
* Values in parentheses are for VDD=5.12 V.
** Values in parentheses are for VDD=3.072 V.
10. Recording method
10.1 Recording in direct mode
(1) Input the VDS command. Specify whether voice triggered starting is used and voice
detection level using VD1 and VD0, set the ADPCM bit length by use of the BIT data.
(2) Input the SAMP command. Specify the sampling frequency by SA0 and SA1 data. In direct
mode, CSEL1 and CSEL2 data are ignored.
(3) Input the CHAN command. Specify the channel by CA1, CA2 and CA3 data. By setting
RCON data to 0, the control mode is set to the direct mode.
(4) Input the start address and stop address with the ADRWR command to specify the memory
area to record into. The address data is stored in the channel index area.
(5) Input the REC command to set recording mode.
(6) Input the START command to begin recording. At this time, the IC fetches the start address
and the stop address of the specified channel from the channel index area and starts
recording after storing them to the address counter and the stop address register.
(7) When the contents of the address counter and the stop address register corresponds, the
recording is finished. The end of recording is confirmed by the RPM bit of the status
register.
(8) If the recording needs to be suspended temporarily, input the STOP command. The
contents of the address counter become the new stop address and are automatically stored
in the channel index area.
When finishing recording by the STOValues in parentheses are for VDD=5.12 V.P command,
input the next command after conValues in parentheses are for VDD=5.12 V.firming that the
recording operation is finished using the RPM bit.
(9) If recording is to be continued, specify the condition to be modified by (1)-(4).
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Flowchart of Recording in Direct Mode
Specification of voice triggered starting mode (VD0, VD1)
and ADPCM bit length (BIT)
VDS command
SAMP command
Sampling frequency (SA0, SA1)
CHAN command
Channel (CA1, CA2, CA3)
Control mode (RCON=0)
Input of start address and stop address
ADRWR command
Set to recording mode
REC command
Recording begins
START command
No
Check for start of recording
RPM=1?
Yes
Command input of
condition to be modified
RPM=0?
Yes
Check for end of recording
No
No
Stop recording?
Yes
STOP command
No
RPM=0?
Compulsory stop of recording
Check for end of recording
Yes
Yes
Continue to
record?
No
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10.2 Recording method in the fixed and flex modes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Input the VDS command. Specify whether voice triggered starting is used and voice
detection level with data bits VD0 and VD1. Specify the ADPCM bit length with the VDS
command data (BIT).
Input the SAMP command. Specify the sampling frequency with SA0 and SA1 data and
control mode with CSEL1 and CSEL2 data.
Input the CHAN command. Specify the channel with CA1, CA2 and CA3 data. The control
mode selection data (RCON) is set to 1.
Input the REC command to set the recording mode.
Start recording by input of the START command.
In fixed mode, recording is begun after storing the start and stop address generated inside
the IC to the address counter and the stop address register respectively, and to the channel
index area.
In flex mode, the start address is incremented by +1 from the address of preceding channel
(chn-1) fetched from the channel index area.
The stop address is the last address of external serial register. Recording is begun after
storing each address to the address counter, the stop address register and the channel index
area.
When the contents of the address counter and the stop address register corresponds,
recording is finished. The end of recording is confirmed by the RPM bit of the status
register.
If recording is to be suspended temporarily, input the STOP command. The contents of the
address counter become the new stop address and are automatically stored in the channel
index area.
After finishing recording using the STOP command, input the next command after
confirming that the recording operation is finished using the RPM bit.
In flex mode, make sure that the recording is finished to the end of the memory capacity by
checking the FULL bit of the status register. If recording is completed to the end of memory,
it is not possible to the next channel (chn+1).
If recording is to be continued, specify the condition to be modified by (1)-(3).
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Flowchart of Recording in Fixed and Flex Modes
Specification of voice triggered starting mode (VD0, VD1)
and ADPCM bit length (BIT)
VDS command
SAMP command
Sampling frequency (SA0, SA1)
Control mode (CSEL1,CSEL2)
CHAN command
Channel (CA1, CA2, CA3)
Control mode (RCON=0)
Set to recording mode
REC command
Recording begins
START command
No
Check for start of recording
RPM=1?
Yes
RPM=0?
Command input of
condition to be modified
Yes
Check for end of recording
No
No
Stop recording?
Continue to record?
Yes
STOP command
No
Compulsory halt of recording
RPM=0?
Yes
(FULL bit check)
Yes
In flex mode, check if recording is
through to the end of memory capacity.
Continue to
record?
No
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11. Playback method
(1) Input the VDS command. Specify the ADPCM bit length using the VDS command data (BIT).
VD0 and VD1 data for voice detection are invalid in playback mode.
(2) Input the SAMP command. Specify the sampling frequency using SA0 and SA1 data and the
control mode using CSEL1 and CSEL2 data.
(3) Input the CHAN command. Specify the channel using CA1, CA2 and CA3 and specify the
control mode during recording using the RCON data bit. Channel selection during playback
can be specified randomly in either control mode.
(4) Input the PLAY command to set playback mode.
(5) Start playback by input of the START command.
The IC fetches the start and stop addresses of the specified channel from the channel index
area and stores each to the address counter and the stop address register to begin playback.
(6) When the contents of the address counter and the stop address register corresponds,
playback is finished. The end of playback is confirmed by the RPM bit of the status register.
(7) If playback is to be suspended temporarily, input the STOP command. After finishing
playback using the STOP command, input the next command after confirming that the
recording operation is finished using the RPM bit.
(8) If recording is to be continued, specify the condition to be modified by (1)-(3).
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Flowchart of Playback
ADPCM bit length (BIT)
VDS command
No
SAMP command
Sampling frequency (SA0, SA1)
Control mode (CSEL1, CSEL2)
CHAN command
Channel (CA1, CA2, CA3)
Control mode (RCON)
PLAY command
Set to playback mode
START command
Playback begins
Check for start of playback
RPM=1?
Yes
RPM=0?
Command input of
condition to be modified
Yes
Check for end of playback
No
No
Stop playback?
Continue to playback?
Yes
STOP command
No
RPM=0?
Compulsory halt of playback
Check for end of playback
Yes
Yes
Continue to
playback?
No
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12. Pause method (temporary suspension) with the (PAUSE command)
Record/playback is suspended temporarily by input of the PAUSE command and is resumed by
input of the START command. During pause, the VPM bit of the status register is 1 and the RPM
bit is 1.
Even when recording is done with voice triggered starting activated, input of the START
command during pause resumes recording even in no-voice detected state.
During standby for record/playback, pause, and standby for voice, the PAUSE command is
invalid.
WR (I)
D0 - D3 (I/O)
START
command
PAUSE
command
START
command
STOP
command
Status register
RPM bit
VPM bit
Standby
Record/playback
Pause
Record/playback
Standby
Resumes even during recording by voice
triggered starting
Input of the STOP command during pause, record/playback is finished and the IC enters
standby mode.
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WR (I)
D0 - D3 (I/O)
START
command
PAUSE
command
STOP
command
Status register
RPM bit
VPM bit
Standby
Record/playback
Pause
Standby
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13. Operation in voice triggered starting (VDS command)
By setting the VD0 and VD1 data bits of the VDS command, recording through voice triggered
starting is enabled. Using voice triggered starting, it is possible to eliminate the silence data prior
to the detection of voice data thus utilizing the memory capacity efficiently. However,
elimination of silence data, once voice triggered recording has begun, does not occur. During
standby for voice, the VPM bit of the status register is held at a 1 and is reset back to 0 when
recording starts after voice is detected. The RPM bit becomes 1 after recording starts.
WR (I)
D0 - D3 (I/O)
STOP
command
START
command
Voice detected
Status register
RPM bit
VPM bit
Standby for recording Standby for voece
Recording
Standby for recording
Input of a STOP command during standby for voice causes the IC to first finish standby for voice
and then enter standby for recording.
WR (I)
D0 - D3 (I/O)
START
command
STOP
command
Status register
RPM bit
VPM bit
Standby for recording
Standby for voice
Standby for recording
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14. Address control operation
Address control operation during record/playback is performed via the channel index area.
Transfer of data with the channel index area differs depending on the control mode during
recording.
14.1 Address control operation during recording
14.1.1 Direct mode recording
(1)
Address data is directly written to the channel index area by the ADRWR command.
(2)
With the input of a START command, the start and stop addresses are read from the
channel index area. They are then set to the address counter and the stop address register
via the address register.
After this address control operation, recording is begun and the address counter counts
up.
(3)
When recording is stopped by the STOP command, the contents of the address counter at
that time are stored in the channel index area as the new stop address.
1)
ADRWR Command Input
MSM6588
Serial register
+1
Address
controller
Address counter
Channel index
area
Start address STn
Address register
Stop address SPn
Voice data
area
Stop address register
2)
START Command Input (recording begins)
MSM6588
Serial register
+1
Address
controller
Address counter
Channel index
area
Start address STn
Address register
Stop address SPn
Voice data
area
Stop address register
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3)
MSM6588/6588L
STOP Command (recording stops)
Serial register
MSM6588
Address
controller
Address counter
Channel index
area
Stop address SPn
Address register
Voice data
area
Stop address register
14.1.2 Fixed mode recording
(1)
With the input of a START command, the start and stop address generated in the address
controller is set to the address counter and the stop address register via the address
register, respectively. The address data is stored in the channel index area.
After this address control operation, recording is begun and the address counter counts
up.
(2)
When the recording is stopped by the STOP command, the contents of the start address
counter at that time are stored in the channel index area as the new stop address.
1)
START Command Input (recording begins)
MSM6588/6588L
Serial register
+1
Address
controller
Address counter
Channel index
area
Start address STn
Address register
Stop address SPn
Voice data
area
Stop address register
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14.1.3 Flex mode recording
(1)
With the input of a START command, the stop address of the preceding channel (SPn-1)
is read out from the channel index area.
(2)
Next, address data incremented by 1 from the contents of the stop address are stored in
the address counter and the channel index area as the start address (STn=SPn-1+1).
The stop address generated in the address controller (the maximum address of the serial
register) is set in the stop address register and is stored in the channel index area.
After this operation, recording is begun and the address counter counts up.
(3)
When recording is finished by the STOP command, the contents of the address counter at
that time are stored in the channel index area as the new stop address.
1)
START Command Input
Serial register
MSM6588/6588L
Address
controller
Address counter
Channel index
area
Address register
Stop address SPn-1
Voice data
area
Stop address register
2)
Start of Recording
Serial register
MSM6588/6588L
+1
Address
controller
Address counter
Start address STn
(SPn-1+1)
Address register
Channel index
area
Stop address SPn
Voice data
area
Stop address register
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14.2 Address control operation during playback
During play back, the IC performs playback using the address and stop addresses stored in the
channel index area regardless of the control mode.
(1)
(2)
1)
With the input of a START command, the IC first reads the start and stop address from the
channel index area. They are then set to the address counter and the stop address register,
respectively, through the address register.
After this address control operation, playback begins and the address counter counts up.
When a STOP command is input, playback is stopped. No address control operation is
performed at this time.
START Command Input (playback starts)
Serial register
MSM6588/6588L
+1
Address
controller
Address counter
Channel index
area
Start address STn
Address register
Stop address SPn
Voice data
area
Stop address register
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15. Multi-channel record/playback method
It is possible to record/playback on multiple channels by preparing memory corresponding to
the channel index area that stores the start and stop addresses of each channel inside a
microcontroller or equivalent external circuit.
Recording/playback of multiple channels is performed in the direct mode and the channel index
area can be used as temporary address data storage. In the case of playback for the fixed message
stored into the serial voice ROM, the address data of each word can be similarly stored into a
ROM in a microcontroller. The following shows the procedure.
15.1 Multi-channel recording method
(1)
(2)
(3)
(4)
(5)
Recording conditions are specified by a command input similar to the recording method in
direct method. Channels can be specific (e.g. ch0).
The stop and start addresses can be written into the channel index area by the ADRWR
command.
Recording is started.
After recording is performed, the stop address which is stored in the channel index area by
the ADRRD command is read out.
The stop address is stored in microcontroller memory.
15.2 Multi-channel playback method
(1)
(2)
(3)
Playback conditions are specified by a command input.
The stop and start addresses that are stored in microcontroller memory are written in the
channel index area by the ADRWR command.
Playback is started.
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Flowchart to Multi-channel Recording
Recording condition
specified by command
input
ADRWR command
REC command
START command
Control mode is direct mode
Input of start address and stop
address from microcontroller
Set to recording mode
Recording starts
(STOP command)
No
RPM=0?
Recording finished?
Yes
ADRRD command
Stop address is stored in
memory of microcontroller
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Flowchart to Multi-channel Playback
Playback condition
specified by command
input
ADRWR command
PLAY command
START command
Control mode is direct mode
Input of start address and stop
address from microcontroller
Set to playback mode
Playback starts
(STOP command)
No
RPM=0?
Playback finished?
Yes
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16. Playback method by means of a serial voice ROM
The following describes how to play a fixed message by connecting a serial voice ROM to the
MSM6588/6588L.
16. 1 Circuit and memory configurations
Be sure to assign here a serial register.
Assign here a serial register or serial voice ROM.
1Mbit
Internal ROM
Address data1
800
C00
1Mbit
400
1Mbit
000
1Mbit
MCU
MSM6588
MSM6588L
Address data2
Address data3
• • • • •
3FF
CS
7FF
CS
BFF
CS
FFF
CS
CS1
CS2
CS3
CS4
Address space (X address)
Serial register
000h-3FFh
400h-7FFh
Assignable
Assignable
CS3
800h-BFFh
Assignable
Assignable
CS4
C00h-FFFh
Assignable
Assignable
CS1
CS2
Serial voice ROM
Unassignable
Assignable
A serial register or serial voice ROM is assigned in the unit of 1 Mbit (CSn).
Note: Be sure to connect a serial register to CS1.
it is impossible to connect only a serial voice ROM and use it for playback only.
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The following circuit configuration shows the case where 256Kbit and 2Mbit are used for
playback and for a fixed playback, respectively.
For playback (variable message): 256Kbit serial register MSM6586
For fixed message: 2Mbit serial voice ROM MSM6596A-XXX
MSM6596A-XXX
MSM6588
MSM6586
000
400
800
C00
256Kbit
MCU
3FF
7FF
CS1
1Mbit
CS
1Mbit
0FF
100
BFF
CS2
FFF
CS1
CS2
CS3
CS4
CS1
000h-0FFh
Serial register for variable message
100h-3FFh
Unused (no addressing)
CS2
400h-7FFh
CS3
800h-BFFh
CS4
C00h-FFFh
Serial register
256Kbit
512Kbit
1Mbit
Serial voice ROM
1Mbit
2Mbit
3Mbit
Serial voice ROM for fixed message
Unused (no addressing)
MSM6586
MSM6587
MSM6389C
MSM6595A-XXX
MSM6596A-XXX
MSM6597A-XXX
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16. 2 How to contorol playback when a serial voice ROM is used.
(1)
ROM for saving address data
A start address and stop address for each word must be previously saved in the microcontroller’s
ROM when a serial voice ROM is used for playback.
The address data is 32bit per word.
Start address
Upper
X-address
12bit
Lower
Y-address
—
Stop address
12bit
8bit
32bit
per word
MCU’s ROM size = 32bit ¥ number of voice words
(2)
Address data
Address data described in the address correspondence table are saved in the microcontroller’s
ROM. The following offset addresses are added to CS2 through CS4, to which a serial voice ROM
is assigned.
Assigned to
Offset address
CS2
+400h
CS3
+800h
+C00h
CS4
For example, in the previous circuit, when MSM6596-600 is assigned to CS2 and CS3, and
“GOZEN” GOZEN that means “morning” is voiced, the address is shown below.
Start X
Stop X
No.1 00 GOZEN
Stop Y
0
Ø +400h
Address to be specifiedfi 400h
10
Ø +400H
410h
5D
Ø no addition
5Dh
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(3) Flowchart to Serial Voice ROM
The serial voice ROM playback differs in its playback method from the serial register playback
because after specifying the channel the serial voice ROM playback requires to enter the address
data that are saved in the microcontroller’s ROM, using the ADRWR command.
The channel index area is used temporarily.
Therefore, for example, ch0 is used only for serial voice ROM playback.
VDS command
ADPCM bit length (BIT)
Sampling frequency (SA0,SA1)
SAMP command
Fixed to channel (CA1,CA2,CA3) ch0
CHAN command
Specif the direct mode as
a control mode(RCON=0).
PLAY command
Set to playback mode
Enter address data
ADRWR command
START command
No
Checking of playback start
RPM=1?
Yes
RPM=0?
Yes
Checking of playback finished
No
No
Stop playback?
Yes
STOP command
No
RPM=0?
Checking of playback finished
Yes
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MSM6588/6588L
17. Data transfer method with external serial registers (DTRW command)
Data transfer can be performed with external serial registers using the DTRW command.
After input of the DTRW command, the X address of the serial register for read/write is specified.
Data in 4-bit nibbles are transferred from the header of the X address specified. Although the
serial registers are composed of the X address times 1K-bit (Y direction), the address can be
specified only in the X direction and no random address specification can be made that selects
the middle of the Y direction.
A single DTRW command input can do read/write operations continuously if they are in the
range of the same serial register. When the operation extends to other serial registers, it is
necessary to suspend the operation temporarily and re-specify the address by input of the DTRW
command.
The following is the DTRW command input procedure.
(1) The sampling frequency is specified by input of the SAMP command. Because the access time
of data transfer by the DTRW command is proportional to the period of the sampling
frequency, the highest frequency is usually selected.
(2) Input the DTRW command.
(3) Specify the header X address of the serial register with 3 WR pulses.
(4) Wait for BUSY time. Alternatively, the BUSY bit of the status register can be used to confirm
this.
(5) For writing data, input the data to be written with a WR pulse after input of the REC
command. It is necessary to wait for BUSY time between each WR pulse.
When performing data/write by a single DTRW command, the BUSY state can be checked
by the BUSY bit of the status register but if data read is also performed, confirmation by the
BUSY bit cannot be performed.
(6) For data read, 4-bit of data are output from the data bus by input of a RD pulse, after waiting
for the BUSY time, after the input of the PLAY command.
For data read, confirmation of BUSY state by the BUSY bit is invalid.
(7) If data read/write is to be continued, specify data transfer by read/write mode using the
PLAY/REC commands.
(8) If data read/write is to be terminated, input the STOP command. Wait for BUSY time and
start input of the next command. If data read is performed, confirmation by the BUSY bit is
invalid.
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Flowchart of data transfer by the DTRW command
SAMP command
Sampling frequency specified
(Usually, the highest sampling frequency is selected.)
DTRW command
Input of lower
X address
(X0, X1, X2, X3)
Input of middle
X address
(X4, X5, X6, X7)
Input of upper
X address
(X8, X9, X10, X11)
Wait for BUSY time
Data write?
No
Yes (Data write)
(Data read)
REC command
PLAY command
Wait for BUSY time
Wait for BUSY time
WR pulse input
Data input to
serial register
RD pulse input
Data output of
serial register
Wait for BUSY time
Yes
Data read/write
continue?
No
STOP command
Wait for BUSY time
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MSM6588/6588L
18. Method of record/playback by input/output of voice data from the data bus (EXT command)
When SRAM or a harddisk is used to store voice data instead of the serial registers, use the EXT
command to do record/playback.
During record/playback using the EXT command, voice data (ADPCM data) is directly input/
output from the data bus at the sampling frequency. There is no address control nor external
serial register control at this time, therefore, it is necessary to use the microcontroller to control
recording time and addresses.
Pause, voice triggered starting function and selection of channels cannot be made during record/
playback. Valid commands are PLAY, REC, STOP, SAMP, VDS and EXT only.
18.1 EXT command recording method
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
The sampling frequency is specified by SA0 and SA1 data of the SAMP command.
The ADPCM bit length is specified by BIT data of the VDS command.
Input the REC command to set the recording mode.
Input the EXT command to start recording. The sampling frequency clock is output from
the MON pin.
When the MON output pin becomes “H” level, input a RD pulse to fetch ADPCM data from
the data bus. The upper 3bit (D3 to D1 pin) are valid for 3bit ADPCM.
Store ADPCM data to external memory.
Repeat steps (5) and (6) to continue recording.
To stop recording input a STOP command. Recording can be continued for an indefinite
period of time until the STOP command is input.
As the status register cannot be checked during recording with the EXT command, it is
necessary to wait for BUSY time after input of the STOP command to start input of the next
command.
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MSM6588/6588L
Flowchart of recording with the EXT command
SAMP command
Sampling frequency specified (SA0, SA1)
VDS command
ADPCM bit length specified (BIT)
REC command
Set to recording mode
EXT command
EXT recording begins
Rise of MON
output pin detected
Yes
RD pulse input
Fetches ADPCM data
Stores ADPCM
data to memory
Stores ADPCM data
to external Memory
Continue
recording?
No
STOP command
EXT recording finished
Wait for BUSY time
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MSM6588/6588L
18.2 EXT command playback method
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Specify the sampling frequency by SA0 and SA1 data of the SAMP command.
Specify the ADPCM bit length of recording by BIT data of the VDS command.
Input the PLAY command to set playback mode.
Input the EXT command to start playback. The sampling frequency clock is output from
the MON pin.
When the MON pin becomes “H”, fetch ADPCM data from external memory.
Input a WR pulse to get ADPCM data from the data bus. In 3bit ADPCM, the upper 3bit
(D3 to D1 pin) are valid and data in the lower 1 bit (D0 pin) is invalid.
Repeat steps (5) and (6) to continue playback.
Input the STOP command to end playback.
Flowchart of playback by the EXT command
SAMP command
Sampling frequency specified (SA0, SA1)
VDS command
ADPCM bit length specified (BIT)
PLAY command
Set to playback mode
EXT command
EXT playback begins
Rise of MON
output pin detected
ADPCM data is
read from memory
WR pulse input
Yes
Write ADPCM data
Continue
Playback?
No
STOP command
EXT playback finished
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¡ Semiconductor
MSM6588/6588L
19. Reset and power down function
By input of a “L” level to the RESET pin, the IC stops oscillation to minimize power consumption
and is set to the power down state. The control circuit is simultaneously initialized. Data
specified by 2 nibble commands such as the sampling frequency, ADPCM bit length, and data
in the serial registers is not affected.
However, when a RESET pulse is input in the middle of record/playback, internal data and voice
data become undefined and operation stops.
The following shows the state of the IC at power down.
(1) Oscillation is stopped and all the operations in the internal circuit are halted, the control
circuit is initialized.
(2) Power consumption is minimized. When using an external clock, input the GND level to the
XT pin at power down so that no current is flowing to the oscillation circuit.
(3) The D0 to D3-pin on the data bus are in the high-impedance state regardless of the RD and
CE pins.
(4) Power consumption of the external serial registers is minimized by setting the CS1 to CS4 pin
to a “H” level output.
(5) The state of the output pins are as follows:
SAD, SAS, TAS, CS1~CS4, WE, RWCK, STBY pins ........... “H” level output
MON pin ................................................................................... “L” level output
DI/O pin ................................................................................... High-impedance
AOUT, FOUT pins................................................................... GND level output
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APPLICATION CIRCUITS
1Mbit Serial Register
CS VSS
AGND
AOUT
MON
XT
XT
CS1
CS2
CS3
CS4
SAD
SAS
TAS
RWCK
WE
DI/O
LOUT
AMON
FIN
FOUT
ADIN
SG
DGND
LIN
MOUT
CSEL2
CA1
CA2
CA3
MIN
CSEL1
RSEL1
RSEL2
SAM
PDMD
MCUM
VDS
RESET
PAUSE
+
AGND
AVDD
Switch array
+
+
DGND
SP
ST
DVDD'
DVDD
MSM6588/6588L
REC/PLAY
AVDD
DGND
SAD
SAS
TAS
RWCK
WE
DIN
DOUT
MSM6389C
TEST
TEST
FAM
RFSH
RS/A
CS VSS
VCC
MSM6389C
Speaker amplifier
CS VSS
VCC
MSM6389C
4.096MHz
VCC
MSM6389C
CS VSS
VCC
Figure 1 shows an application circuit when the MSM6588/6588L is used in stand-alone mode and
four 1Mbit serial registers are used.
Figure 2 shows an application circuit when the MSM6588/6588L is used in microcontroller
interface mode with two 1Mbit serial registers and one 2Mbit serial voice ROM.
Figure 3 shows an example of application circuit when record/playback is made using the EXT
command for MSM6588/6588L.
FIgure 1 Example of Application Circuit in Stand-alone Mode
with 1Mbit Serial Registers
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Microcontroller
AGND
AOUT
MON
XT
XT
AGND
MSM6588/6588L
+
+
LOUT
AMON
FIN
FOUT
ADIN
SG
DGND
LIN
MOUT
MIN
CS1
CS2
CS3
CS4
Speaker amplifier
DGND
4.096MHz
CS
VSS
VCC
VCC
MSM6389C
TEST
TEST
FAM
FRSH
RS/A
CS VSS
SAD
SAS
TAS
RWCK
WE
DIN
DOUT
1Mbit Serial Register
MSM6389C
RESET
MCUM
TEST
RSEL1
RSEL2
TEST
TEST
TEST
TEST
RD
WR
CE
SAD
SAS
TAS
RWCK
WE
DI/O
DVDD' AVDD
VCC
TEST
CS1 CS2 VSS
SADY
DOUT
SASY
SADX
SASX
TAS
RWCK
2Mbit Serial Voice ROM
MSM6596A-xxx
AVDD
+
DVDD
D3
D2
D1
D0
¡ Semiconductor
MSM6588/6588L
Figure 2 Example of Application Circuit in Microcontroller Interface Mode
with 1Mbit Serial Registers and 2Mbit Serial Voice ROM
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MSM6588/6588L
MCUM
TEST
RSEL1
RSEL2
TEST
TEST
TEST
TEST
RESET
+
MSM6588/6588L
DVDD DVDD' AVDD
SAD
D3
SAS
D2
TAS
D1
RWCK
D0
WE
RD
DI/O
WR
CE
MON
Microcontroller
External
Memory
Microcontroller
Control Circuit
¡ Semiconductor
Open
CS1
CS2
CS3
CS4
MIN
MOUT
XT
XT
LIN
AVDD
+
+
LOUT
AMON
FIN
FOUT
ADIN
SG
DGND
4.096MHz
DGND
AOUT
Speaker amplifier
AGND
AGND
Figure 3 Application Circuit When Record/Playback is Mode Using EXT Command
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PACKAGE DIMENSIONS
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
0.41 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
100/101
¡ Semiconductor
MSM6588/6588L
(Unit : mm)
TQFP44-P-1010-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.28 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
101/101