E2F0003-27-X1 ¡ Semiconductor MSM7650 ¡ Semiconductor This version: Jan. 1998 MSM7650 Previous version: Oct. 1997 NTSC/PAL Digital Encoder GENERAL DESCRIPTION The MSM7650 is a digital NTSC/PAL encoder. By inputting digital image data conforming to CCIR Rep624-4, it outputs analog composite video signals and analog S video signals. For the scanning system, interlaced or noninterlaced mode can be selected. Since the MSM7650 is provided with pins dedicated to overlay function, text and graphics can be superimposed on a video signal. In addition, this encoder has an internal 9-bit DAC. So, when compared with using a conventional analog encoder, the number of components, the board space, and points of adjustment can greatly be reduced, thereby realizing a low cost and high-accuracy system. The host interface provided conforms to Philips's I2 C specifications, which reduces interconnections between this encoder and mounting components. The internal synchronization signal generator (SSG) allows the MSM7650 to operate in master or slave mode. FEATURES • Video signal system: NTSC/PAL • Scanning system: interlaced/noninterlaced • Input digital level: conforms to ITU-601 (CCIR601) • Input-output timing: conforms to CCIR Rep 624-4 • Input signal (sampling ratio) Y:Cb:Cr (4:2:2/4:1:1) • Supported sampling rates • NTSC 4Fsc (14.32 MHz) • NTSC ITU-R601 (13.5 MHz) • NTSC Square Pixel (12.27 MHz) • PAL ITU-R601 (13.5 MHz) • PAL Square Pixel (14.75 MHz) • Internal SSG circuit (internally generates sync signals) • Operation by external synchronization possible • Internal 3ch 9-bit DAC (samples by double frequency) • 3-bit title graphics can be displayed • I2C-bus host interface function • Package 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM7650GS-BK) 1/34 ¡ Semiconductor MSM7650 APPLICATIONS • Video game equipment • Electronic still camera • Video printer • Video camera • Scanner • Image file system • CD-ROM • Video graphics board • Videophone • Video conference system • Multimedia equipment • Digital VTR 2/34 YD[7:0] Y Limitter Y Level Converter Black & Blank Pedestal CD[7:0] C Limitter U Level Converter Interpolator + LPF & UV Selector OLR OLG OLB V Level Converter Overlay Control IPF Interpolator + LPF YUV Color generator IPF Color Burst Generator DAC YA DAC CVBSO DAC CA Subcarrier Generator ¡ Semiconductor BLOCK DIAGRAM RESET_L CT [8:0] OLC CLKX2O VSYNC_L HSYNC_L BLANK_L CLKX1 Sync Generator & Timing Controller I2C Control Logic Test Control Logic CLKX2 X MS INTERLACE MODE[2:0] SCL SDA TOUT[2:1] TEST[4:1] MSM7650 3/34 ¡ Semiconductor MSM7650 66 YD1 65 YD0 68 YD3 67 YD2 70 YD5 69 YD4 72 YD7 71 YD6 74 CD1 73 CD0 76 CD3 75 CD2 78 CD5 77 CD4 80 CD7 79 CD6 PIN CONFIGURATION (TOP VIEW) VDD5 1 VDD3 2 64 VDD5 63 VDD3 GND 3 VSYNC_L 4 62 GND 61 OLR HSYNC_L 5 BLANK_L 6 60 OLG 59 OLB CLKX1 7 CLKX2 8 58 OLC 57 MODE[0] CLKX2O 9 X 10 56 MODE[1] 55 MODE[2] 54 INTERLACE 53 MS MSM7650 X_L 11 VDD3 12 GND 13 CT8 14 CT7 15 52 RESET_L 51 SCL 50 SDA 49 ADRS CT6 16 CT5 17 48 TOUT2 47 TOUT1 CT4 18 CT3 19 46 TEST4 45 TEST3 CT2 20 CT1 21 44 TEST2 43 TEST1 CT0 22 VDD5 23 GND 24 NC 40 AVDD 38 GND 39 AGND 36 CA 37 AVDD 33 AVDD 34 CVBSO 35 YA 31 AGND 32 COMP 29 AGND 30 VREF 27 FS 28 VDD3 25 NC 26 42 GND 41 VDD3 NC : No-connection pin 80-Pin Plastic QFP 4/34 ¡ Semiconductor MSM7650 PIN DESCRIPTIONS (1/2) Pin I/O Description Symbol 1 VDD5 5.0V power supply 2 VDD3 3.3V power supply 3 GND Digital GND 4 I/O VSYNC_L Vertical sync signal Polarity is negative. Output pin in master mode; input pin in slave mode. Horizontal sync signal 5 I/O HSYNC_L 6 I BLANK_L 7 I CLKX1 Pixel clock input pin 8 I CLKX2 Double pixel clock input pin Double pixel clock output pin Polarity is negative. Output pin in master mode; input pin in slave mode. 9 O CLKX2O 10 I X 11 O 12 I Test pin. Normally, fixed to "0". X_L Test pin VDD3 3.3V power supply GND 13 14 to 22 Composite blank signal. Polarity is negative. CT8 to CT0 Digital GND Input pin for testing. Normally, fixed to "0" or "1". 23 VDD5 5.0V power supply 24 GND Digital GND 25 VDD3 3.3V power supply NC 26 VREF Not connected Reference voltage for DAC 27 I/O 28 I FS DAC full scale adjustment pin 29 I COMP DAC phase compensation pin 30 I AGND Analog GND 31 O YA Analog luminance signal output pin 32 AGND Analog GND 33 AVDD Analog power supply AVDD Analog power supply 34 35 O 36 37 O CVBSO Analog composite video signal output pin AGND Analog GND CA Analog chrominance signal output pin 38 AVDD Analog power supply 39 GND Digital GND 40 NC 41 VDD3 3.3V power supply 42 GND Digital GND Not connected TEST1 Input pin 1 for testing. Normally, fixed to "0". 44 I TEST2 Input pin 2 for testing. Normally, fixed to "0". 45 I TEST3 Input pin 3 for testing. Normally, fixed to "0". 43 5/34 ¡ Semiconductor MSM7650 PIN DESCRIPTIONS (2/2) Pin I/O Symbol 46 I TEST4 Input pin 4 for testing. Normally, fixed to "0". 47 O TOUT1 Output pin for testing 48 O TOUT2 Output pin for testing 49 I ADRS I2C-bus subaddress setting pin. One of two addresses switchable can be Description selected as subaddress. 1: 1000110/0: 1000100 50 I/O SDA I2C-bus data pin 51 I SCL I2C-bus clock pin 52 I RESET_L 53 I MS 54 I INTERLACE System reset pin. "1" at an open state by an internal pull-up resistor Operation mode select signal pin for synchronization circuit. 1: master/0: slave. "1" at an open state by an internal pull-up resistor Interlace/noninterlace select signal pin. 1: interlaced/0: noninterlaced. "1" at an open state by an internal pull-up resistor 55 to 57 I MODE[2] to MODE[0] Video mode select pins These pins are valid when MR[7] is "1". 000: NTSC CCIR 001: NTSC Square Pixel 100: PAL CCIR 101: PAL Square Pixel 010: NTSC 4Fsc "000" at an open state by an internal pull-down resistor 58 I OLC Transparent control signal Overlay signal is displayed when this pin is "H". 59 I OLB Overlay text color (Blue component) 60 I OLG Overlay text color (Green component) 61 I 62 63 I 64 65 to 72 I OLR Overlay text color (Red component) GND Digital GND VDD3 3.3V power supply VDD5 5.0V power supply YD0 to YD7 Digital image luminance signal data input pin Level is based on ITU-601. YD7 is MSB. 73 to 80 CD0 to CD7 Digital image chrominance signal data input pin Level is based on ITU-601. CD7 is MSB. 6/34 ¡ Semiconductor MSM7650 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating VDD5 Ta=25°C –0.3 to +7 Unit V VDD3 Ta=25°C –0.3 to +4.5 AVDD Ta=25°C –0.3 to +4.5 Input Voltage VI Ta=25°C –0.3 to VDD5 +0.3 V Analog Output Current IO — 40 mA Power Consumption PW — 800 mW Storage Temperature TSTG — –55 to +150 °C Power Supply Voltage RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Power Supply Voltage Symbol Condition Min. Typ. Max. Unit VDD5 Ta=25˚C 4.5 5.0 5.5 VDD3 Ta=25˚C 3.0 3.3 3.6 AVDD Ta=25˚C 3.0 3.3 3.6 GND Ta=25˚C — 0.0 — AGND Ta=25˚C — 0.0 — VIH1 Except CLKX2, 2.2 — VDD5 V 0.8VDD5 — VDD5 V 2.4 — VDD5 V V V SDA, CLKX1, High Level Input Voltage Ta=25˚C VIH2 VIH3 SDA, Ta=25˚C CLKX1,CLKX2, Ta=25˚C Low Level Input Voltage VIL — 0.0 — 0.5 V Operating Temperature Range Ta — 0.0 — 70 ˚C External Reference Voltage (*1) Vrefex — — 1.25 — V DA Current Setting Resistance (*2) Riadj — — 330 — W RL — — 75 — W DA Output Load Resistance (*1) When external reference voltage is not supplied, internal reference voltage is as follows. Internal Reference Voltage (*2) Vrefin — 1.15 — 1.45 V A volume control resistor of approx. 500W is recommendable for adjusting the output current. 7/34 ¡ Semiconductor MSM7650 ELECTRICAL CHARACTERISTICS DC Characteristics (Ta=0 to +70°C, VDD3=3.3V±0.3V, VDD5=5V±10%) Parameter Symbol High Level Output Voltage VOH Low Level Output Voltage VOL Condition IOH=–4mA (*1) IOH=–8mA (*2) IOL=4mA (*1) IOL=8mA (*2) Min. Typ. Max. Unit 0.8VDD5 — VDD5 V 0 — 0.6 V Input Leak Current II VI=GND to VDD5 –10 — 10 mA Output Leak Current IO VI=GND to VDD5 (*3) –10 — 10 mA — 120 140 mA — 65 80 mA Power Supply Current (operating) IDDO Power Supply Current (standby) IDDS CLKX1=13.5MHz CLKX2=27.0MHz RESET_L="L" CLKX1=CLKX2=0Hz I2 C-bus SDA Output Voltage SDAVL Low level, IOL=3mA 0 — 0.4 V I2C-bus SDA Output Current SDAIO During Acknowledge 3 — — mA Internal Reference Voltage Vrefin — 1.15 — 1.45 DA Output Load Resistance RL — V 75 W Integral Linearity SINL ±2 LSB Differential Linearity SDNL ±1 LSB (*1) (*2) (*3) HSYNC_L, VSYNC_L, SDA, TO, CT[7:0] CLKX2O SDA 8/34 ¡ Semiconductor MSM7650 AC Characteristics (Ta=0 to +70°C, VDD3=3.3V±0.3V, VDD5=5V±0.5V) Parameter Symbol Condition Min. Typ. Max. Unit PAL Square Pixel — 67.8 — ns NTSC 4Fsc — 69.8 — ns NTSC Square Pixel — 81.5 — ns CLKX Cycle Time TS — 74.1 — ns Input Data Setup Time ts1 — 7.03 — — ns Input Data Hold Time th1 — 9.48 — — ns Output Delay Time td1 — 18.35 — 24.12 ns CLKX2O Delay Time td2 — 7.69 — 9.53 ns Rpull_up=4.7kW 200 50 — ITU-RS601 Clock Cycle Time tC_SCL Clock Duty Cycle tD_SCL Low Level Cycle tL_SCL — Rpull_up=4.7kW 100 ns % ns 9/34 ¡ Semiconductor CLKX1 Input timing Output timing MSM7650 RESET_L, HSYNC_L, VSYNC_L, YD[7:0], CD[7:0], MS, MODE[2:0], INTERLACE, OLR, OLG, OLB, OLC HSYNC_L, VSYNC_L ts1 valid th1 invalid td1 valid CLKX2 td2 CLKX2O tC_SCL tL_SCL SCL SDA The phase relations between CLKX1 and CLKX2 are shown below. 1. When the CLKX1 pulse rises later than the CLKX2 pulse. CLKX2 Tccd1 CLKX1 2. When the CLKX1 pulse rises earlier than the CLKX2 pulse. CLKX2 Tccd2 CLKX1 Tccd1: 20.14 [ns] Tccd2: 3.27 [ns] 10/34 ¡ Semiconductor MSM7650 BLOCK FUNCTIONAL DESCRIPTION Y Limitter This block limits the contents outside the specified range as follows for input luminance signal YD specified by the ITU-601 standard. • Signals are limited to YD = 235 when YD_IN > 235 • Signals are limited to YD = 16 when YD_IN < 16 • In other cases, signals are fed as is to next processing C Limitter This block limits the contents outside the specified range as follows for input chrominance signals specified by the ITU-601 standard. The input chrominance signal is output as a 2’s complement format. The processing procedure follows. 1) Format processing for input chrominance signals • If MR [6] = 0, CD is in offset binary format. CD is converted to 2’s complement format and is fed to next processing. • If MR [6] = 1, CD is in 2’s complement format. CD is fed as is to next processing. 2) • • • Clipping processing Signals are limited to CD = 112 when CD>112 Signals are limited to CD = -112 when CD < -112 In other cases, signals are fed to next processing In addition, this block separates U and V components from the input chrominance signal CD into which data of U and V components has been inserted using time sharing, and then passes signals to the next process. • Y Level Converter Converts ITU-601 standard luminance signal level to DAC digital input level. • U Level Converter Converts ITU-601 standard chrominance signal level to DAC digital input level. • V Level Converter Converts ITU-601 standard chrominance signal level to DAC digital input level. • YUV Color Generator This block generates luminance and chrominance signals from over lay color signals OLR, OLG and OLB. Control signals (CR [2:0] ) control the output content (overlay or color bar) and output level (100%, 75%, 50%, 25%). • Overlay Control This block selects input image data or YUV Color Generator output signals. It is determined by the level of the control signal (OLC, CR [2]), as shown below: CR [2] = 1, OLC = ?: Selects color bar signal (YUV Color Generator output signal). CR [2] = 0, OLC = 1: Selects overlay signal (YUV Color Generator output signal). CR [2] = 0, OLC = 0: Selects input image data. 11/34 ¡ Semiconductor MSM7650 • Black & Blank Pedestal This block adds sync signals at the luminance side to luminance signals. • Interpolator +LPF This block executes data interpolation and the elimination of high frequency components by LPF for input chrominance signals. Both 4:2:2 and 4:1:1 signals are processed. • I2C Control Logic This is the serial interface block based on I2C standard of Phillips Corporation. Internal registers MR and CR can be set from the master side. When writing to the internal registers other than MR [5] (black level control) and CR [1:0] (overlay level), written contents are immediately set to them. It is during the vertical blanking period that written contents are set to MR [5] and CR [1:0]. • Sync Generator & Timing Controller This block generates sync signals and control signals. This block is operated in slave mode, which performs external synchronization, and in master mode, which internally generates sync signals. • Color Burst Generator Outputs U and V components of amplitude of burst signals. • Subcarrier Generator Executes color subcarrier generation. • Interpolation Filter (IPF) This block performs upsampling at CLK X 2 (double speed CLKX1) for luminance signals and chrominance signals modulated with CLKX1. Interpolation processing is executed in this process. 12/34 ¡ Semiconductor MSM7650 INPUT DATA FORMAT Input Digital Level The content conforms to CCIR601 (ITU-601). For chrominance input Cb and Cr, 2’s complement and offset binary formats are available by setting of internal registers. Input values outside the specified range are limited by internal clipping processing. The valid input levels of luminance signal and chrominance signal are shown below. Digital Level Digital Level 100% White level 235 240(112) 128(0) Black Level 16 16(–112) Y data C data Note) Values are in offset binary format. (Values in parenthesis are in 2's complement format.) Input luminance signal level Input chrominance signal level Basic Pixel Sampling Ratio 4:2:2 and 4:1:1 sampling are supported. An internal register can control the sampling ratio. CLKX1 CLKX1 YD Y1 Y2 Y3 Y4 Y5 Y6 YD Y1 Y2 CD U1 V1 U3 V3 U5 V5 CD U1 V1 4:2:2 sampling Y3 Y4 Y5 Y6 U5 V5 4:1:1 sampling 13/34 ¡ Semiconductor MSM7650 OUTPUT FORMAT Output Level When the output level of the operation mode is NTSC, the content of the output level differs depending on setup level setting by internal registers. When the setup level is set, data is output with Black-White as 92.5 IRE. When the setup level is not set, data is output with Black-White as 100 IRE. However, the setup level setting above is valid only when NTSC is selected as operation mode, and setup level does not exist when PAL is selected as the operation mode. When the contents of 100% luminance order color bar are input to the encoder, the DAC input level is as follows. DAC data Lumi [IRE] Composite Wave Form (NTSC) Yellow White 480 133 389 100 359 89 307 70 276 59 227 41 197 169 144 135 114 30 20 11 7.5 0 59 –20 4 –40 Green Cyan Red Magenta Black Blue NTSC composite signal (setup: 7.5 IRE) 14/34 ¡ Semiconductor DAC data Lumi [IRE] MSM7650 Y Wave Form (NTSC) White 389 100 359 89 307 70 276 59 227 41 197 30 144 11 114 0 4 –40 Cyan Yellow Magenta Green Blue Red Black NTSC Y signal output (setup: 0) DAC data Lumi [IRE] 429 418 63 59 377 44 311 20 256 0 201 –20 135 –44 94 83 –59 –63 C Wave Form (NTSC) Yellow Cyan Green Red Magenta Blue Color Burst NTSC C signal output (setup: 0) 15/34 ¡ Semiconductor DAC data Lumi [IRE] MSM7650 Composite Wave Form (PAL) Yellow White 488 133 397 100 367 89 315 70 285 59 235 41 205 181 153 30 21.5 11 122 0 63 –21.5 4 –43 Green Cyan Red Magenta Black Blue PAL composite signal 16/34 ¡ Semiconductor DAC data Lumi [IRE] MSM7650 Y Wave Form (PAL) White 397 100 367 89 315 70 285 59 235 41 205 30 153 11 122 0 4 –43 Cyan Yellow Magenta Green Blue Red Black PAL Y signal output DAC data Lumi [IRE] 429 418 63 59 377 44 315 21.5 256 0 197 –21.5 135 –44 94 83 –59 –63 C Wave Form (PAL) Yellow Cyan Green Red Magenta Blue Color Burst PAL C signal output 17/34 ¡ Semiconductor MSM7650 CLOCK TIMING Input Data Timing Input data and sync signals are fed into the encoder at the rising edge of the clock. Input data is handled as valid pixel data when tSTART passes after the falling edge of HSYNC_L. Chrominance signal of input data at this time is regarded as Cb. ACTIVE VIDEO LINE tACT tSTART CLKX1 HSYNC_L YD, CD OLC, OLR OLG, OLB ts1 th1 don't care don't care VALID DATA BLANK_L Video data input timing Input data is recognized as valid pixel data when input signal BLANK_L is high in the tACT period. When BLANK_L is high during the blanking period, however, input data is not output as valid pixel data since processing to maintain blanking period is internally in-progress. The values of tSTART differ slightly in master mode and slave mode. The values of tSTART are as follows. In master mode In slave mode Operation mode tSTA(Ts) Operation mode tSTA(Ts) CCIR 601 NTSC 126 CCIR 601 NTSC 129 Square Pixel NTSC 141 Square Pixel NTSC 144 4Fsc NTSC 115 4Fsc NTSC 118 CCIR PAL 134 CCIR PAL 137 Square Pixel PAL 154 Square Pixel PAL 157 tSTA–tS1=tSTART 18/34 ¡ Semiconductor MSM7650 Internal Synchronization Output Timing Input and output timing of HSYNC_L and VSYNC_L in master mode is as follows. CLKX1 td1 td1 HSYNC_L VSYNC_L Output timing of internal synchronization CLK1, HSYNC_L and VSYNC_L VSYNC_L YA 523 524 525 1 2 3 4 5 6 7 17 18 Output timing of internal synchronization VSYNC_L 19/34 ¡ Semiconductor MSM7650 Output Timing Output timing conforms to CCIR Rep 624-4. When the operation method is NTSC/PAL and the scanning method is interlace/noninterlace, the output wave form content of composite signals are as follows. Field 1 259 Reference sub-carrier phase 260 261 262 263 1 A NEGATIVE HALF CYCLE Burst relative 180° to B-Y axis 2 3 4 B 5 POSITIVE HALF CYCLE Burst relative 180° to B-Y axis 6 7 8 17 18 19 6 7 8 17 18 19 6 7 8 17 18 19 6 7 8 17 18 19 C D E Field 2 259 Reference sub-carrier phase 260 261 262 263 1 A 2 3 4 B 5 C D E Field 3 259 Reference sub-carrier phase 260 261 262 263 1 A 2 3 4 B 5 C D E Field 4 259 Reference sub-carrier phase 260 261 262 263 A 1 2 3 4 B 5 C D E Output timing (interlaced NTSC) 20/34 ¡ Semiconductor Symbol MSM7650 Name Period Odd field (Even field) A First equalizing pulse period (3H) B Vertical synchronization period (3H) 259.5 to 262.5H 1 to 3H C Second equalizing pulse period (3H) D Burst pause period 1 to 6,259.5 to 262.5H E Vertical blanking period (20H) 1 to 17,259.5 to 262.5H 4 to 6H Output timing (interlaced NTSC) 21/34 ¡ Semiconductor MSM7650 NEGATIVE HALF CYCLE Burst relative 180° to B-Y axis Continuous Odd Field POSITIVE HALF CYCLE Burst relative 180° to B-Y axis Reference sub-carrier phase 260 261 262 1 A 2 3 4 5 B 6 7 8 17 18 19 6 7 8 17 18 19 6 7 8 17 18 19 6 7 8 17 18 19 C D E Reference sub-carrier phase 260 261 262 1 A 2 3 4 5 B C D E Continuous Even Field Reference sub-carrier phase 260 261 262 1 A 2 3 4 B 5 C D E Reference sub-carrier phase 260 261 262 1 A 2 3 B 4 5 C D E Output timing (noninterlaced NTSC) Symbol Period Name A First equalizing pulse period (2H) B Vertical synchronization period (3H) Continuous odd field Continuous even field 261 to 262H 261.5 to 262H 1 to 3H 1 to 3H C Second equalizing pulse period (2H) 4 to 6H 4 to 6H D Burst pause period 261 to 6H 261.5 to 6H E Vertical blanking period (19H) 261 to 17H 261.5 to 17.5H Output timing (noninterlaced NTSC) 22/34 ¡ Semiconductor MSM7650 burst phase +135° +V Field 1,5 309 310 311 312 313 1 2 A 3 burst phase -135° -V 4 B 5 6 7 8 23 24 25 5 6 7 8 23 24 25 5 6 7 8 23 24 25 5 6 7 8 23 24 25 C D E Field 2,6 309 310 311 312 313 1 2 A 3 4 B C D E Field 3,7 309 310 311 312 313 1 A 2 3 4 B C D E Field 4,8 309 310 311 312 313 1 A 2 3 4 B C D E Output timing (Interlaced PAL) Symbol Name Period Filed 1,5 Filed 2,6 Filed 3,7 Filed 4,8 A First equalizing pulse period (2.5H) 311 to 312.5H 311 to 312.5H 311 to 312.5H 311 to 312.5H B Vertical synchronization period (2.5H) 1 to 2.5H 1 to 2.5H 1 to 2.5H 1 to 2.5H C Second equalizing pulse period (2.5H) D Burst pause period E Vertical blanking period (25H) 2.5 to 5H 2.5 to 5H 2.5 to 5H 2.5 to 5H 1 to 6,310 to 312.5H 1 to 5.5,308.5 to 312.5H 1 to 5,311 to 312.5H 1 to 6.5,309.5 to 312.5H 1 to 22.5,311 to 312.5H 1 to 22.5,311 to 312.5H 1 to 22.5,311 to 312.5H 1 to 22.5,311 to 312.5H Output timing (Interlaced PAL) 23/34 ¡ Semiconductor MSM7650 burst phase +135° +V Continuous Odd Field 309 310 311 312 1 A 2 3 burst phase -135° -V 4 B 5 6 7 8 23 24 25 5 6 7 8 23 24 25 5 6 7 8 23 24 25 5 6 7 8 23 24 25 C D E 309 310 311 312 1 A 2 3 4 B C D E Continuous Even Field 309 310 311 312 1 A 2 3 4 B C D E 309 310 311 312 1 A 2 3 4 B C D E Output timing (Noninterlaced PAL) Symbol Period Name A First equalizing pulse period (2H) B Vertical synchronization period (2.5H) Continuous odd field Continuous even field 311 to 312H 311.5 to 312H 1 to 2.5H 1 to 2.5H C Second equalizing pulse period (2.5H) 2.5 to 5H 2.5 to 5H D Burst pause period 311 to 6H 311.5 to 6H E Vertical blanking period (24H) 311 to 22H 311.5 to 22.5H Output timing (Noninterlaced PAL) 24/34 ¡ Semiconductor MSM7650 <Equalizing pulse vertical synchronization period> Equalizing pulse vertical synchronization period q w e r q w 1/2H e 1/2H Setting content of equalizing pulse vertical synchronization period (Ts is sampling clock cycle in each mode) q w e 1/2H NTSC CCIR601 31Ts 398Ts 64Ts 429Ts PAL CCIR601 32Ts 369Ts 63Ts 432Ts NTSC Square Pixel qEqualizing pulse width qblanking level NTSC 4Fsc wVertical sync pulse width w(synchronizing+{blanking level) ¥ (2/3) e(synchronizing+{blanking level) ¥ (1/3) PAL Square Pixel eSerration rSynchronzing level Equalizing pulse vertical synchronization period 28Ts 332Ts 58Ts 390Ts 33Ts 387Ts 68Ts 455Ts 35Ts 403Ts 69Ts 472Ts Equalizing pulse vertical synchronization period <Horizontal blanking period> 1H r t e w q q w e r t qSynchronzing level w(synchronizing+{blanking level) ¥ (1/3) e(synchronizing+{blanking level) ¥ (2/3) rblanking level tpeak to peak value of burst qHorizontal sync pulse width wBurst signal output period eBurst signal start rHorizontal blanking period (excluding front porch) tFront porch start Horizontal blanking period Setting content of horizontal blanking period (Ts is sampling clock cycle in each mode) q w e r NTSC CCIR601 63Ts 31Ts 71Ts 127Ts 838Ts 858 PAL CCIR601 63Ts 31Ts 75Ts 142Ts 844Ts 864 NTSC Square Pixel 58Ts 31Ts 65Ts 116Ts 762Ts 780 NTSC 4Fsc 67Ts 36Ts 75Ts 135Ts 889Ts 910 PAL Square Pixel 69Ts 34Ts 82Ts 155Ts 922Ts 944 t Total dots/1H Setting content of horizontal blanking period 25/34 ¡ Semiconductor MSM7650 Internally Generated Color Bar Output Timing This function outputs a 100% and 75% luminance order color bar by setting internal registers. Output timing of each color of the color bar is as follows. White Yellow Cyan Green Magenta Red Blue Black q w e r t y u Each color of color bar output timing hblank q w e r t y u 1H NTSC CCIR601 127Ts 216Ts 305Ts 394Ts 483Ts 572Ts 661Ts 750Ts 858Ts NTSC Square Pixel 116Ts 197Ts 278Ts 359Ts 440Ts 521Ts 602Ts 682Ts 780Ts NTSC 4Fsc 135Ts 230Ts 325Ts 419Ts 513Ts 607Ts 701Ts 795Ts 910Ts PAL CCIR601 142Ts 230Ts 318Ts 406Ts 494Ts 582Ts 670Ts 757Ts 864Ts PAL Square Pixel 155Ts 251Ts 347Ts 443Ts 539Ts 635Ts 731Ts 827Ts 944Ts Operation mode (Ts is sampling clock cycle) Each color of color bar output timing 26/34 ¡ Semiconductor MSM7650 I2C-bus Interface Input/Output Timing Basic input/output timing of I2C-bus interface is shown below. SDA SCL MSB S 1 2 7 Start Condition Data Line Stable: Data Valid Change of Data Allowed 8 9 ACK tC.SCL 1 2 3-8 9 ACK P Stop Condition tL.SCL I2C-bus basic input/output timing 27/34 ¡ Semiconductor MSM7650 I2C BUS FORMAT Basic input format of I2C-bus interface is shown below. 1 cycle S Slave Address A Subaddress0 S A Data 0 Slave Address A A P Subaddress1 Symbol A Data 1 A P ..... Description S Start condition Slave Address Slave address 1000100 or 1000000, 8th bit is write signal. A Acknowledge. Generated by slave Subaddress Subaddress byte Data n Data byte and acknowledge continues until data byte stop condition is met. P Stop condition It is required to input the above-mentioned format from the start condition to the stop condition each time of writing a subaddress. For example, when writing the subaddresses 0 to 2, the format should be input three times. In case data of more than one byte are transferred, S Slave Address A Subaddress0 A Data 0 A P Data n A P The 4th byte data and following data each are written over the same subaddress. If one of the following matters occurs, the encoder will not return "A" (Acknowledge). • The slave address does not match. • A non-existent subaddress is specified. • The read/write attribute of a register does not match "X" (read/write control bit). The input timing is shown below. SDA 1 2 8 ACK 1 2 8 ACK 1 2 8 ACK SCL S Start Condition Slave Address Sub Address Data P Stop Condition 28/34 ¡ Semiconductor MSM7650 CONTENTS OF INTERNAL REGISTER SETTING All registers can be written by accessing 8 bits. "0" is read from an undefined bit. The contents of internal registers are shown below. (A value with "*" is the default.) Mode Register (MR) (Default value after system reset: 10H) MR[7] Override Selects setting of external terminal or internal register *0: setting of external terminal is valid 1: setting of internal registers is valid MR[6] Chroma format Chrominance signal input format *0: Offset binary 1: 2's Complement MR[5] Black level control Black level setting (setup) Note) Valid only for NTSC. *0: Black level 7.5 IRE 1: Black level 0 IRE MR[4] Synchronization mode Selects master/slave operation of sync signal generator. 0: slave mode *1: master mode MR[3] Pixel sampling ratio Sampling ratio *0: 4:2:2 1: 4:1:1 MR[2:0] Video mode select Selects operation mode *000: CCIR 601 NTSC 13.5 MHz 001: NTSC Square Pixel 12.27 MHz 010: NTSC 4Fsc 14.32 MHz 100: CCIR 601 PAL 13.5 MHz 101: PAL Square Pixel 14.75 MHz 29/34 ¡ Semiconductor MSM7650 Command Register (CR) (Default value after system reset: 1BH) CR[7:5] Undefined Undefined CR[4] Genlock Selects SCH phase management status 0: Genlock Off (subcarrier is self generated) *1: Genlock On (management of SCH phase is executed) CR[3] Non-Interlace Scanning method in master mode 0: Non-Interlace *1: Interlace CR[2] Color bar Output control of luminance order color bar for adjustment *0: input image data or overlay data 1: luminance order color bar CR[1:0] Overlay level Luminance signal output level control of overlay signals and luminance order color bar for adjustment 00: 25% 01: 50% 10: 75% *11: 100% Register function Subaddress Data byte D7 D6 D5 D4 D3 D2 D1 D0 Mode Register (MR) 0 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 Command Register (CR) 1 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 30/34 ¡ Semiconductor MSM7650 FILTER CHARACTERISTICS The characteristics of LPF used for color signal processing and interpolation filters used for upsampling processing are shown below. LPF for 411 color signals The following characteristics are when the clock frequency is 13.5 MHz. 0 Level [dB] –20 –40 –60 –80 –100 0 1 2 3 4 Frequency [MHz] 5 6 7 411 Interpolation+LPF Frequency Characteristic LPF for 422 color signals The following characteristics are when the clock frequency is 13.5 MHz. 0 Level [dB] –20 –40 –60 –80 –100 0 1 2 3 4 Frequency [MHz] 5 6 7 422 Interpolation + LPF Frequency Characteristic 31/34 ¡ Semiconductor MSM7650 Up Sampling Filter The following characteristics are when the clock frequency is 27 MHz. 0 Level [dB] –20 –40 –60 –80 –100 0 2 4 6 8 Frequency [MHz] 10 12 14 Up Sampling Filter Frequency Characteristic 32/34 ¡ Semiconductor MSM7650 APPLICATION CIRCUIT EXAMPLE 5V 5V RI RI I2C AVDD VDD3 SCL SDA DIP SW MODE[2:0] VDD5 5V 3.3V 3.3V Controller External reference Typ. 1.25V voltage VREF MS INTERLACE FS CC RC OLR OLG OLB OLC Overlay Controller COMP LPF AMP LPF AMP LPF AMP YA MSM7650 YD[7:0] YD[7:0] CD[7:0] CD[7:0] R1 CVBSO R2 CLKX1 CA VSYNC_L R2 HSYNC_L BLANK_L X GND AGND CLKX2 Recommended Analog Output Circuit +AVCC 0.1mF YA, CA, CVBSO 3.6mH 150W 150W 164pF 164pF + – 1000pF + OUTPUT 75W 560W 560W 0.1mF –AVCC 33/34 ¡ Semiconductor MSM7650 PACKAGE OUTLINES AND DIMENSIONS 25.0±0.2 20.0±0.2 ^4 $1 $0 1.0TYP. 14.0±0.2 19.0±0.2 ^5 *0 @5 @4 q 0.8TYP. 0.17±0.05 0.8 0.12 0.32 +0.08 –0.07 0.16 M SEATING PLANE 2.1±0.2 0 to 10° 0.25 2.5MAX. 2.5TYP. 0.05 to 0.35 INDEX MARK Mirror finished surface 1.3TYP. 1.38±0.15 34/34