MITEL MT88L70AT

ISO2-CMOS MT88L70
3 Volt Integrated DTMF Receiver

Features
ISSUE 2
•
2.7 - 3.6 volt operation
•
Complete DTMF receiver
•
Low power consumption
•
Internal gain setting amplifier
•
Adjustable guard time
•
Central office quality
•
Power-down mode
•
Inhibit mode
•
Functionally compatible with Mitel’s MT8870D
Ordering Information
MT88L70AC
18 Pin Ceramic DIP
MT88L70AE
18 Pin Plastic DIP
MT88L70AS
18 Pin SOIC
MT88L70AN
20 Pin SSOP
MT88L70AT
20 Pin TSSOP
-40 °C to + 85 °C
Description
The MT88L70 is a complete 3 Volt, DTMF receiver
integrating both the bandsplit filter and digital
decoder functions. The filter section uses switched
capacitor techniques for high and low group
filters;
the
decoder
uses digital counting
techniques to detect and decode all 16 DTMF tonepairs into a 4-bit code. External component count is
minimized by on chip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.
Applications
•
Paging systems
•
Repeater systems/mobile radio
•
Credit card systems
•
Remote control
•
Personal computers
•
Telephone answering machine
VDD
PWDN
May 1995
VSS
VRef
Bias
Circuit
INH
VRef
Buffer
Q1
Chip Chip
Power Bias
IN +
High Group
Filter
Dial
Tone
Filter
IN -
Digital
Detection
Algorithm
Code
Converter
and Latch
Q2
Zero Crossing
Detectors
Q3
Low Group
Filter
GS
Q4
to all
Chip
Clocks
OSC1
OSC2
St
GT
St/GT
Steering
Logic
ESt
STD
TOE
Figure 1 - Functional Block Diagram
4-23
MT88L70
IN+
INGS
VRef
INH
PWDN
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
IN+
INGS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
18 PIN CERDIP/PDIP/SOIC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
TOE
20 PIN SSOP/TSSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
18
20
1
1
IN+
Non-Inverting Op-Amp (Input).
2
2
IN-
Inverting Op-Amp (Input).
3
3
GS
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
4
VRef
Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Figure
5 and Figure 6).
5
5
INH
Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
6
6
PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
7
8
OSC1
Clock (Input).
8
9
OSC2
Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
9
10
VSS
Ground (Input). 0V typical.
10
11
TOE
Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
11- 1214 15
Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15
17
StD
Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below VTSt.
16
18
ESt
Early Steering (Output). Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
17
19
St/GT
18
20
VDD
Positive power supply (Input). +3V typical.
7,
16
NC
No Connection.
4-24
Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
MT88L70
Functional Description
The MT88L70 monolithic DTMF receiver offers small
size, low power consumption and high performance,
with 3 volt operation. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.
Filter Section
Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
Digit
TOE
INH
ESt
Q4
Q3
Q2
Q1
ANY
L
X
H
Z
Z
Z
Z
1
H
X
H
0
0
0
1
2
H
X
H
0
0
1
0
3
H
X
H
0
0
1
1
4
H
X
H
0
1
0
0
5
H
X
H
0
1
0
1
6
H
X
H
0
1
1
0
7
H
X
H
0
1
1
1
8
H
X
H
1
0
0
0
9
H
X
H
1
0
0
1
0
H
X
H
1
0
1
0
*
H
X
H
1
0
1
1
#
H
X
H
1
0
0
0
A
H
L
H
1
0
0
1
B
H
L
H
1
0
1
0
C
H
L
H
1
1
1
1
D
H
L
H
0
0
0
0
A
H
H
L
B
H
H
L
C
H
H
L
D
H
H
L
undetected, the output code
will remain the same as the
previous detected code
Table 1. Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
Decoder Section
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state (see “Steering Circuit”).
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes vc (see Figure 3) to
rise as the capacitor discharges. Provided signal
condition is maintained (ESt remains high) for the
validation period (tGTP), v c reaches the threshold
(VTSt) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives v c to V DD. GT continues to drive
high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three
state control input (TOE) to a logic high. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (dropout) too short to
be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
Guard Time Adjustment
In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 3 is applicable. Component
values are chosen according to the formula:
4-25
MT88L70
tREC=tDP+tGTP
tID=tDA+tGTA
tGTP=(RPC1) In [VDD / (VDD-VTSt)]
VDD
tGTA=(R1C1) In (VDD / VTSt)
C1
The value of t DP is a device parameter (see Figure 7)
and tREC is the minimum signal duration to be
recognized by the receiver. A value for C of 0.1 µF is
recommended for most applications, leaving R to be
selected by the designer.
RP = (R1R2) / (R1 + R2)
St/GT
R2
R1
ESt
a) decreasing tGTP; (tGTP < tGTA)
tGTP=(R1C1) In [VDD / (VDD-VTSt)]
VDD
VDD
tGTA=(RPC1) In (VDD / VTSt)
C1
C
VDD
St/GT
vc
St/GT
ESt
R1
R
R2
ESt
StD
MT88L70
RP = (R1R2) / (R1 + R2)
Figure 4 - Guard Time Adjustment
tGTA=(RC)In(VDD /VTSt)
tGTP=(RC)In[VDD/(VDD-VTSt)]
b) decreasing tGTA; (tGTP > tGTA)
Differential Input Configuration
Figure 3 - Basic Steering Circuit
Different steering arrangements may be used to
select independently the guard times for tone
present (tGTP) and tone absent (tGTA). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity. Increasing tREC
improves talk-off performance since it reduces the
probability that tones simulated by speech will
maintain signal condition long enough to be
registered. Alternatively, a relatively short tREC with a
long t DO would be appropriate for extremely noisy
environments where fast acquisition time and
immunity to tone drop-outs are required. Design
information for guard time adjustment is shown in
Figure 4.
The input arrangement of the MT88L70 provides a
differential-input operational amplifier as well as a
bias source (V Ref) which is used to bias the inputs at
mid-rail. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
C1
R1
MT88L70
IN+
+
IN-
C2
R4
GS
R3
R2
R5
VRef
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.
Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).
DIFFERNTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
All resistors are ± 1% tolerance.
R1 = R4 = R5 = 100 kΩ
All capacitors are ± 5% tolerance.
R2 = 60 kΩ, R3, = 37.5 kΩ
R2 R5
R3 =
R2 + R5
R5
VOLTAGE GAIN (AV diff) =
R1
INPUT IMPEDANCE
(ZINDIFF) = 2
R1 2 +
1
ωC
2
Figure 5 - Differential Input Configuration
4-26
MT88L70
VDD
C1
DTMF
Input
C2
R1
R2
X-tal
MT88L70
IN+
VDD
IN-
St/GT
GS
VRef
StD
INH
Q4
PDWN
Q3
OSC1
Q2
OSC2
VSS
TOE
ESt
Q1
R3
NOTES:
R1, R2 = 100 kΩ ±1%
R3 = 300 kΩ ±1%
C1,C2 = 100 nF ±5%
X-tal = 3.579545 MHz ±0.1%
VDD = 3.0V + 20% / -10%
Figure 6 - Single-Ended Input Configuration
the input pins are connected as shown in Figure 6
with the op-amp connected for unity gain and V Ref
biasing the input at 1/2V DD. Figure 5 shows the
differential configuration, which permits the
adjustment of gain with the feedback resistor R 5.
Applications
A single-ended input configuration is shown in Figure
6. For applications with differential signal inputs the
circuit shown in Figure 5 may be used.
Crystal Oscillator
The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
connected as shown in Figure 6 (Single-ended Input
Configuration).
4-27
MT88L70
Absolute Maximum Ratings†
Parameter
Symbol
1
DC Power Supply Voltage
2
Voltage on any pin
VI
3
Current at any pin (other than supply)
II
4
Storage temperature
5
Package power dissipation
Min
Max
Units
7
V
VDD+0.3
V
10
mA
+150
°C
500
mW
VDD
VSS-0.3
TSTG
-65
PD
† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Derate above 75 °C at 16 mW / °C. All leads soldered to board.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Sym
Min
Typ‡
Max
Units
3.0
3.6
V
+85
°C
1
DC Power Supply Voltage
VDD
2.7
2
Operating Temperature
TO
-40
3
Crystal/Clock Frequency
fc
3.579545
MHz
4
Crystal/Clock Freq.Tolerance
∆fc
±0.1
%
Test Conditions
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - VDD=3.0V+ 20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
Characteristics
1
Sym
Min
Typ‡
Max
Units
Standby supply current
IDDQ
1
10
µA
Operating supply current
IDD
2.0
5.5
mA
Power consumption
PO
6
4
High level input
VIH
5
Low level input voltage
VIL
Input leakage current
IIH/IIL
Pull up (source) current
2
3
S
U
P
P
L
Y
mW
PWDN=VDD
fc=3.579545 MHz
V
VDD=3.0V
0.9
V
VDD=3.0V
0.05
5
µA
VIN=VSS or VDD
ISO
4
15
µA
TOE (pin 10)=0,
VDD=3.0V
Pull down (sink) current
ISI
15
40
µA
INH=VDD, PWDN=VDD,
VDD=3.0V
9
Input impedance (IN+, IN-)
RIN
10
MΩ
@ 1 kHz
10
Steering threshold voltage
VTSt
0.465VDD
V
11
Low level output voltage
VOL
High level output voltage
VOH
VDD-0.03
Output low (sink) current
IOL
1.5
8
mA
VOUT=0.4 V
Output high (source) current
IOH
1.0
3.0
mA
VOUT=3.6 V, VDD=3.6V
VRef output voltage
VRef
0.512VDD
V
VRef output resistance
ROR
1
kΩ
6
7
8
12
13
14
15
16
I
N
P
U
T
S
O
U
T
P
U
T
S
2.1
Test Conditions
VSS+0.03
V
No load
V
No load
No load
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
4-28
MT88L70
Operating Characteristics - VDD=3.0V+20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
Gain Setting Amplifier
Characteristics
Sym
Min
Typ‡
Max
Units
100
nA
Test Conditions
VSS ≤ VIN ≤ VDD
1
Input leakage current
IIN
2
Input resistance
RIN
3
Input offset voltage
VOS
4
Power supply rejection
PSRR
50
dB
1 kHz
5
Common mode rejection
CMRR
40
dB
VSS + 0.75 V ≤ VIN ≤
VDD-0.75
biased at VRef =1.5 V
6
DC open loop voltage gain
AVOL
32
dB
7
Unity gain bandwidth
fC
0.30
MHz
8
Output voltage swing
VO
9
Maximum capacitive load (GS)
CL
100
pF
10
Resistive load (GS)
RL
50
kΩ
11
Common mode range
AC Electrical Characteristics Characteristics
10
MΩ
25
2.2
VCM
mV
Vpp
1.5
Vpp
Load ≥ 100 kΩ to VSS @ GS
No Load
VDD=3.0V +20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, using Test Circuit shown in Fig. 6.
Sym
Min
Typ‡
-34
15.4
Max
Units
-4.0
489
dBm
mVRMS
Notes*
1
Valid input signal levels
(each tone of composite
signal)
2
Negative twist accept
8
dB
2,3,6,9,12
3
Positive twist accept
8
dB
2,3,6,9,12
4
Frequency deviation accept
±1.5% ± 2 Hz
2,3,5,9
5
Frequency deviation reject
±3.5%
2,3,5,9
6
Third zone tolerance
-16
dB
2,3,4,5,9,10
7
Noise tolerance
-12
dB
2,3,4,5,7,9,10
8
Dial zone tolerance
+22
dB
2,3,4,5,8,9,11
1,2,3,5,6,9
Min @ VDD=3.6V
Max @ VDD=2.7V
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5%± 2 Hz.
7. Bandwidth limited (3 kHz ) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Guaranteed by design and characterization.
4-29
MT88L70
AC Electrical Characteristics - VDD=3.0V+20%/-10%, VSS=0V, -40°C ≤ To ≤ +85°C, using Test Circuit shown in Figure 6.
Sym
Min
Typ‡
Max
Units
Tone present detect time
tDP
5
11
14
ms
Note 1
Tone absent detect time
tDA
0.5
4
8.5
ms
Note 1
Tone duration accept
tREC
40
ms
Note 2
Tone duration reject
tREC
ms
Note 2
ms
Note 2
ms
Note 2
Characteristics
1
2
3
4
5
T
I
M
I
N
G
20
Conditions
Interdigit pause accept
tID
6
Interdigit pause reject
tDO
7
Propagation delay (St to Q)
tPQ
11
µs
TOE=VDD
Propagation delay (St to StD)
tPStD
20
µs
TOE=VDD
Output data set up (Q to StD)
tQStD
5.0
µs
TOE=VDD
Propagation delay (TOE to Q ENABLE)
tPTE
50
ns
load of 10 kΩ,
50 pF
Propagation delay (TOE to Q DISABLE)
tPTD
130
ns
load of 10 kΩ,
50 pF
Power-up time
tPU
30
ms
Note 3
Power-down time
tPD
20
ms
Crystal/clock frequency
fC
3.5759 3.5795 3.5831
MHz
8
9
10
11
12
13
O
U
T
P
U
T
S
P
D
W
N
14
15
16
17
18
C
L
O
C
K
40
20
Clock input rise time
tLHCL
110
ns
Ext. clock
Clock input fall time
tHLCL
110
ns
Ext. clock
Clock input duty cycle
DCCL
60
%
Ext. clock
Capacitive load (OSC2)
CLO
15
pF
40
50
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1.
Used for guard-time calculation purposes only and tested at -4dBm.
2.
These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3.
With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
4-30
MT88L70
D
A
EVENTS
B
C
tREC
tREC
E
TONE
#n + 1
AA
A
tDP
G
tDO
tID
TONE #n
Vin
F
TONE
#n + 1
tDA
ESt
tGTA
tGTP
VTSt
St/GT
tPQ
tQStD
Q1-Q4
DECODED TONE # (n-1)
HIGH IMPEDANCE
#n
# (n + 1)
tPSrD
StD
tPTE
tPTD
TOE
EXPLANATION OF EVENTS
A)
TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.
B)
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS.
C)
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID
TONE.
D)
OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
E)
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY
HIGH IMPEDANCE).
F)
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G)
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT
VALID TONE.
EXPLANATION OF SYMBOLS
Vin
DTMF COMPOSITE INPUT SIGNAL.
ESt
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
4-BIT DECODED TONE OUTPUT.
Q1 -Q 4
StD
DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE
tREC
tREC
tID
tDO
TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q 1 -Q 4 TO ITS HIGH IMPEDANCE STATE.
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
MINIMUM TIME BETWEEN VALID DTMF SIGNALS.
MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.
tDP
tDA
tGTP
tGTA
TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.
TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.
GUARD TIME, TONE PRESENT.
GUARD TIME, TONE ABSENT.
Figure 7 - Timing Diagram
4-31
MT88L70
NOTES:
4-32