NB7L14M 2.5V/3.3VDifferential 1:4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB7L14M is a differential 1−to−4 clock/data distribution chip with internal source terminated CML output structures, optimized for minimal skew and jitter. Device produces four identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively. As such, NB7L14M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs incorporate internal 50 W termination resistors and accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6). Differential 16 mA CML outputs provide matching internal 50 W terminations, and 400 mV output swings when externally terminated with 50 W to VCC (See Figure 14). The device is offered in a low profile 3x3 mm 16−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. 16 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB7L 14M ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Features • • • • • • • • • • • • Maximum Input Clock Frequency up to 8 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical < 0.5 ps of RMS Clock Jitter < 10 ps of Data Dependent Jitter 30 ps Typical Rise and Fall Times 110 ps Typical Propagation Delay 6 ps Typical Within Device Skew Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V CML Output Level (400 mV Peak−to−Peak Output) Differential Output Only 50 W Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP and SG Devices Pb−Free Packages are Available *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Q0 VTCLK Q0 50 W Q1 CLK Q1 CLK Q2 50 W Q2 Q3 VTCLK Figure 1. Logic Diagram © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 1 Q3 1 Publication Order Number: NB7L14M/D NB7L14M VTCLK 1 CLK 2 VEE Q0 Q0 VCC Exposed Pad (EP) 16 15 14 13 12 Q1 11 Q1 NB7L14M CLK 3 10 Q2 VTCLK 4 9 5 6 7 8 VEE Q3 Q3 VCC Q2 Figure 2. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O 1 VTCLK − 2 CLK LVPECL, CML, LVCMOS, LVTTL, LVDS Inverted Differential Clock/Data Input. (Note 1) 3 CLK LVPECL, CML, LVCMOS, LVTTL, LVDS Non−inverted Differential Clock/Data Input. (Note 1) 4 VTCLK − 5,16 VEE Power Supply 6 Q3 CML Output Inverted Differential Output 3 with Internal 50 W Source Termination Resistor. (Note 2) Non−inverted Differential Output 3 with Internal 50 W Source Termination Resistor. (Note 2) 7 Q3 CML Output 8,13 VCC Power Supply Description Internal 50 W Termination Pin for CLK. Internal 50 W Termination Pin for CLK. Negative Supply Voltage. All VEE pins must be externally connected to a Power Supply to guarantee proper operation. Positive Supply Voltage. All VCC pins must be externally connected to a Power Supply to guarantee proper operation. 9 Q2 CML Output Inverted Differential Output 2 with Internal 50 W Source Termination Resistor. (Note 2) 10 Q2 CML Output Non−inverted Differential Output 2 with Internal 50 W Source Termination Resistor. (Note 2) 11 Q1 CML Output Inverted Differential Output 1 with Internal 50 W Source Termination Resistor. (Note 2) 12 Q1 CML Output Non−inverted Differential Output 1 with Internal 50 W Source Termination Resistor. (Note 2) 14 Q0 CML Output Inverted Differential Output 0 with Internal 50 W Source Termination Resistor. (Note 2) 15 Q0 CML Output Non−inverted Differential Output 0 with Internal 50 W Source Termination Resistor. (Note 2) − EP − Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking conduit to improve heat transfer. It is recommended to connect the EP to the lower potential (VEE). 1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK and CLK, then the device will be susceptible to self−oscillation. 2. CML outputs require 50 W receiver termination resistors to VCC for proper operation. http://onsemi.com 2 NB7L14M Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Charged Device Model > 1500 V > 50 V > 500 V Moisture Sensitivity (Note 3) QFN−16 Flammability Rating Oxygen Index: 28 to 34 Pb Pkg Pb−Free Pkg Level 1 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 387 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Rating Units 3.6 V 3.6 V 2.8 |VCC − VEE| V V Static Surge 45 80 mA mA Output Current Continuous Surge 25 50 mA mA TA Operating Temperature Range QFN−16 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 4) 0 lfpm 500 lfpm QFN−16 QFN−16 42 36 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 4) QFN−16 3 to 4 °C/W Tsol Wave Solder 265 265 °C VCC Positive Power Supply VEE = 0 V VI Input Voltage VEE = 0 V VINPP Differential Input Voltage |CLK − CLK| VCC − VEE w 2.8 V VCC − VEE < 2.8 V IIN Input Current Through RT (50 W Resistor) Iout Pb Pb−Free Condition 2 VEE v VI v VCC Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 3 NB7L14M Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C) (Note 5) Symbol Characteristic Min Typ Max Unit 140 190 mA ICC Power Supply Current (Inputs and Outputs Open) VOH Output HIGH Voltage (Note 6) VCC − 60 VCC − 20 VCC mV VOL Output LOW Voltage (Note 6) VCC − 530 VCC − 420 VCC − 360 mV Differential Input Driven Single−Ended (see Figures 10 & 12) (Note 8) Vth Input Threshold Reference Voltage Range (Note 7) 1125 VCC − 75 mV VIH Single−ended Input HIGH Voltage (Note 8) Vth + 75 VCC mV VIL Single−ended Input LOW Voltage (Note 8) VEE Vth − 75 mV Differential Inputs Driven Differentially (see Figures 11 & 13) (Note 8) VIHCLK Differential Input HIGH Voltage 1200 VCC mV VILCLK Differential Input LOW Voltage VEE VCC − 75 mV VCMR Input Common Mode Range (Differential Configuration) 1163 VCC – 38 mV VID Differential Input Voltage (VIHCLK − VILCLK) 75 2500 mV IIH Input HIGH Current CLK / CLK (VTCLK/VTCLK Open) 0 25 100 mA IIL Input LOW Current CLK / CLK (VTCLK/VTCLK Open) −10 0 10 mA RTIN Internal Input Termination Resistor 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 W RTemp Coef Internal I/O Termination Resistor Temperature Coefficient 6.38 mW/°C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. CML outputs require 50 W receiver termination resistors to VCC for proper operation. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC. http://onsemi.com 4 NB7L14M Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; Note 9) −40°C Characteristic VOUTPP Output Voltage Amplitude (@VINPPmin) fin ≤ 6 GHz (See Figure 4) fin ≤ 8 GHz 280 125 400 300 280 125 400 300 280 125 400 300 mV fdata Maximum Operating Data Rate 10 12 10 12 10 12 Gb/s tPLH, tPHL Propagation Delay to Output Differential 70 110 150 70 110 150 70 110 150 ps tSKEW Duty Cycle Skew (Note 10) Within−Device Skew Device−to−Device Skew (Note 11) 2.0 6.0 20 5.0 15 50 2.0 6.0 20 5.0 15 50 2.0 6.0 20 5.0 15 50 ps tJITTER RMS Random Clock Jitter (Note 12) fin = 6 GHz fin = 8 GHz Peak/Peak Data Dependent Jitter fin = 2.488 Gb/s (Note 13) fdata = 5 Gb/s fdata = 10 Gb/s 0.2 0.2 2.0 5.0 6.0 0.5 0.5 5.0 8.0 10 0.2 0.2 2.0 5.0 6.0 0.5 0.5 5.0 8.0 10 0.2 0.2 2.0 5.0 6.0 0.5 0.5 5.0 8.0 10 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 14) 400 2500 400 2500 400 2500 mV tr tf Output Rise/Fall Times @ 1 GHz (20% − 80%) 30 60 30 60 30 60 ps Q, Q Max Min Typ 85°C Symbol 75 Typ 25°C Min 75 Max Min Typ 75 Max Unit NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). 10. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @1 GHz. 11. Device to device skew is measured between outputs under identical transition @ 1 GHz. 12. Additive RMS jitter with 50% duty cycle clock signal at 10 GHz. 13. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2^23−1. 14. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 450 VCC = 3.3 V 400 350 VCC = 2.5 V 300 250 200 150 100 50 0 1 2 3 4 5 6 7 8 9 10 11 12 INPUT FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) at Ambient Temperature (Typical) (VINPP = 400 mV) http://onsemi.com 5 Voltage (50 mV/div) Voltage (50 mV/div) NB7L14M DDJ = 1.6 ps* Time (80 ps/div) Time (40 ps/div) Figure 4. Typical Output Waveform at 2.488 Gb/s with PRBS 2^23−1 (Vinpp = 75 mV) Figure 5. Typical Output Waveform at 5 Gb/s with PRBS 2^23−1 (Vinpp = 75 mV) **Input signal DDJ = 7.2 ps Voltage (50 mV/div) *Input signal DDJ = 6.4 ps Voltage (50 mV/div) DDJ = 2.8 ps** DDJ = 2 ps*** DDJ = 6 ps*** Time (18 ps/div) Time (18.2 ps/div) Figure 6. Typical Output Waveform at 10.7 Gb/s with PRBS 2^23−1 (Vinpp = 75 mV) Figure 7. Typical Output Waveform at 12 Gb/s with PRBS 2^23−1 (Vinpp = 75 mV) ***Input signal DDJ = 11 ps ***Input signal DDJ = 13 ps http://onsemi.com 6 NB7L14M CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 8. AC Reference Measurement NB7L14M VCC 50 W Receiver Device VCC 50 W 50 W 50 W Q CLK Z = 50 W Q CLK Z = 50 W Figure 9. Typical Termination for 16 mA Output Driver and Device Evaluation (Refer to Application Notes AND8020/D and AND8173/D) CLK CLK CLK CLK Vth Vth Figure 10. Differential Input Driven Single−Ended VCC Vthmax Vth VCC VIHmax VILmax CLK Vthmin GND Figure 11. Differential Inputs Driven Differentially VIHCLKmax VCMmax VIH Vth VIL VCMR VIHmin VILmin VCMmax GND Figure 12. Vth Diagram CLK VILCLKmax V(CLK) = VIHCLK − VILCLK VIHCLKtyp CLK VILCLKtyp VIHCLKmin VILCLKmin Figure 13. VCMR Diagram http://onsemi.com 7 NB7L14M VCC 50 W 50 W Q Q 16 mA VEE Figure 14. CML Output Structure Table 6. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTCLK0, VTCLK0, VTCLK1, VTCLK1, VTSEL to VCC LVDS Connect VTCLK0, VTCLK0 together for CLK input AC−COUPLED Bias VTCLK0, VTCLK0 inputs within (VCMR) Common Mode Range RSECL, LVPECL Standard ECL Termination Techniques. See AND8020/D. LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. http://onsemi.com 8 NB7L14M Application Information minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). All NB7L14M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are VCC VCC 50 W 50 W Q CLK Z CML Driver VCC VCC VTCLK 50 W VTCLK 50 W NB7L14M Z Q CLK VEE VEE Figure 15. CML to CML Interface VCC VCC 50 W VBias PECL Driver VBias Recommended RT Values VCC 50 W RT RT 5.0 V 290 W CLK Z VTCLK 50 W NB7L14M VTCLK 50 W Z CLK RT 3.3 V 150 W 2.5 V 80 W VEE VEE VEE Figure 16. PECL to CML Receiver Interface http://onsemi.com 9 NB7L14M VCC VCC CLK Z 50 W VTCLK LVDS Driver NB7L14M VTCLK 50 W Z CLK VEE VEE Figure 17. LVDS to CML Receiver Interface VCC VCC CLK Z LVTTL/ LVCMOS Driver VTCLK No Connect* No Connect NB7L14M VTCLK VREF VEE 50 W *or 60 pF to GND 50 W CLK VCC Recommended VREF Values VREF LVCMOS VCC − VEE 2 LVTTL 1.5 V Figure 18. LVCMOS/LVTTL to CML Receiver Interface ORDERING INFORMATION Package Shipping † QFN−16 123 Units/Rail NB7L14MMNG QFN−16 (Pb−Free) 123 Units/Rail NB7L14MMNR2 QFN−16 3000 Tape & Reel QFN−16 (Pb−Free) 3000 Tape & Reel Device NB7L14MMN NB7L14MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NB7L14M PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G−01 ISSUE B D A B ÇÇÇ ÇÇÇ ÇÇÇ PIN 1 LOCATION 0.15 C E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW SEATING PLANE A1 16X L 5 e 4 16X 3.25 0.128 0.30 0.012 EXPOSED PAD 9 E2 K 12 1 16 16X e 1.50 0.059 3.25 0.128 13 b 0.10 C A B 0.05 C 0.575 0.022 EXPOSED PAD 8 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 −−− 0.30 0.50 SOLDERING FOOTPRINT* C D2 NOTE 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG BOTTOM VIEW NOTE 3 0.50 0.02 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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