NM93C13/C14 256-/1024-Bit Serial EEPROM General Description Features The NM93C13/C14 is 256/1024, respectively, bits of CMOS electrically erasable memory divided into 16/64 16bit registers. They are fabricated using National Semiconductor’s floating-gate CMOS process for high speed, high reliability and low power. The NM93C13/C14 is available in an 8-pin SO package to save board space. The serial interface of the NM93C13/C14 is MICROWIRETM compatible for simple interface to standard microcontrollers and microprocessors. There are 7 instructions: Read, Erase/Write Enable, Erase, Erase All, Write, Write All, and Erase/Write Disable. All programming cycles are completely self-timed for simplified operation. The ready/busy status is available on the DO pin to indicate the completion of a programming cycle. Y Y Y Y Y Y Y Y Y Typical active current 400 mA; Typical standby current 25 mA Reliable CMOS floating gate technology 4.5V to 5.5V operation in all modes MICROWIRE compatible serial I/O Self-timed programming cycle Device status indication during programming mode 15 years data retention Endurance: 100,000 read/write cycles minimum Packages available: 8-pin DIP, 8-pin SO Block Diagram TL/D/11291 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/D/11291 RRD-B30M65/Printed in U. S. A. NM93C13/C14 256-/1024-Bit Serial EEPROM September 1994 Connection Diagrams Alternate SO Pinout (TM8) NM93C14 Only Dual-In-Line Package (N) and 8-Pin SO (M8) TL/D/11291–2 TL/D/11291 – 3 Top View See NS Package M08A See NS Package Number N08E and M08A Ordering Information Commercial Temp. Range (0§ C to a 70§ C) Pin Names Order Number* CS Chip Select NM93C13N/NM93C14N NM93C13M8/NM93C14M8 NM93C14TM8 SK Serial Data Clock DI Serial Data Input DO Serial Data Output 2 GND Ground VCC Power Supply Absolute Maximum Ratings (Note 1) Operating Conditions b 65§ C to a 150§ C Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temp. (Soldering, 10 sec.) Ambient Operating Temperature NM93C13 – NM93C14 a 6.5V to b 0.3V 0§ C to a 70§ C Power Supply 4.5V to 5.5V a 300§ C ESD Rating 2000V DC and AC Electrical Characteristics VCC e 5.0V g 10% (unless otherwise specified) (Note 2) Symbol ICC1 Parameter Conditions Min Max Units 4 mA Operating Current CS e VIH, SK e 1 MHz ICC3 Standby Current CS e 0V IIL Input Leakage VIN e 0V to VCC IOL Output Leakage VIN e 0V to VCC VIL VIH Input Low Voltage Input High Voltage VOL1 Output Low Voltage IOL e 2.1 mA VOH1 Output High Voltage IOH e b400 mA VOL2 VOH2 Output Low Voltage Output High Voltage IOL e 10 mA IOH e b10 mA fSK SK Clock Frequency tSKH SK High Time (Note 3) 300 ns tSKL SK Low Time (Note 3) 250 ns tSKS SK Setup Time 50 ns tCS Minimum CS Low Time 250 ns tCSS CS Setup Time 50 ns tDH D0 Hold Time 70 ns tDIS DI Setup Time 100 ns tCSH CS Hold Time 0 ns tDIH DI Hold Time 20 tPD1 Output Delay to ‘‘1’’ tPD0 Output Delay to ‘‘0’’ 500 ns tSV CS to Status Valid 500 ns tDF CS to DO in TRI-STATEÉ tWP Write Cycle Time b 10 200 mA 10 mA mA b 10 10 b 0.1 0.8 2 VCC a 1 0.4 2.4 V V 0.2 VCC b 0.2 1 V MHz ns 500 CS e VIL V ns 100 ns 10 ms Capacitance (Note 4) AC Test Conditions TA e 25§ C f e 1 MHz Output Load 1 TTL Gate and CL e 100 pF Input Pulse Levels 0.4V to 2.4V Timing Measurement Reference Level Input 1V and 2V Output 0.8V and 2V Max Units COUT Symbol Output Capacitance Test Typ 5 pF CIN Input Capacitance 5 pF Note 1: Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: 100% functional test; AC/DC parameters sample tested to 0.4% AQL. Note 3: The SK frequency specification specifies a minimum SK clock period of 1 ms, therefore in an SK clock cycle tSKH a tSKL must be greater than or equal to 1 ms. For example, if the tSKL e 500 ns then the minimum tSKH e 500 ns in order to meet the SK frequency specification. Note 4: This parameter is periodically sampled and not 100% tested. 3 Functional Description The NM93C13/C14 have 7 instructions as described below. Note that the MSB of any instruction is a ‘‘1’’ and is viewed as a start bit in the interface sequence. For the C13 and C14 the next 8 bits carry the op code and the 6-bit address for register selection. Read (READ): The READ instruction outputs serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output string. Output data changes are initiated by a low to high transition of the SK clock. Erase/Write Enable (EWEN): When VCC is applied to the part, it powers up in the Erase/ Write Disable (EWDS) state. Therefore, all programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once an Erase/Write Enable instruction is executed, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC is removed from the part. Erase (ERASE): The ERASE instruction will program all bits in the specified register to the logical ‘1’ state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS). DO e logical ‘0’ indicates that programming is still in progress. DO e logical ‘1’ indicates that the register, at the address specified in the instruction, has been erased, and the part is ready for another instruction. Write (WRITE): The WRITE instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data is put on the data-in (DI) pin, CS must be brought low before the next rising edge of the SK clock. This falling edge of CS initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS). DO e logical 0 indicates that programming is still in progress. DO e logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. Erase All (ERAL): The ERAL instruction will simultaneously program all registers in the memory array and set each bit to the logical ‘1’ state. The Erase All cycle is identical to the ERASE cycle except for the different op-code. As in the ERASE mode, the DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS). The ERASE ALL instruction is not required, see note below. Write All (WRAL): The WRAL instruction will simultaneously program all registers with the data pattern specified in the instruction. As in the WRITE mode, the DO pin indicates the READY/BUSY status of the chip if CS is brought high after a minimum of 500 ns (tCS). Erase/Write Disable (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. Note: The NM93C13/C14 devices do not require an ‘ERASE’ or ‘ERASE ALL’ prior to the ‘WRITE’ and ‘WRITE ALL’ instructions. The ‘ERASE’ and ‘ERASE ALL’ instructions are included to maintain compatibility with the NMOS NMC9346. Instruction Set for the NM93C13 and NM93C14 SB Op Code Address READ Instruction 1 10 A5–A0 Data Reads data stored in memory at specified address. Comments EWEN 1 00 11XXXX Write enable must precede all programming modes. ERASE 1 11 A5–A0 WRITE 1 01 A5–A0 ERAL 1 00 10XXXX WRAL 1 00 01XXXX EWDS 1 00 00XXXX Erase selected register. D15 – D0 Writes selected register. Erases all registers. D15 – D0 Writes all registers. Disables all programming instructions. 4 Timing Diagrams Synchronous Data Timing TL/D/11291 – 4 READ: *Address bits A5 and A4 become ‘‘don’t care’’ for NM93C13. TL/D/11291 – 5 EWEN: *The NM93C13 and NM93C14 require a minimum of 9 clock cycles. TL/D/11291 – 6 5 Timing Diagrams (Continued) EWDS: *The NM93C13 and NM93C14 require a minimum of 9 clock cycles. TL/D/11291 – 7 WRITE: *Address bit A5 and A4 become ‘‘don’t care’’ for NM93C13. TL/D/11291 – 8 WRAL: *The NM93C13 and NM93C14 require a minimum of 9 clock cycles. TL/D/11291 – 9 6 Timing Diagrams (Continued) ERASE: *Address bits A5 and A4 are ‘‘don’t care’’ for NM93C13. TL/D/11291 – 10 ERAL: TL/D/11291 – 11 Physical Dimensions inches (millimeters) Molded Small Out-Line Package (M8) Order Number NM93C13M8 or NM93C14M8 NS Package Number M08A 7 NM93C13/C14 256-/1024-Bit Serial EEPROM Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number NM93C13N or NM93C14N NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. 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