NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Features • • • • • • • • • • • • • High Performance: -7K 3 CL=2 -75B, CL=3 -8B, CL=2 Units fCK Clock Frequency 133 133 100 MHz tCK Clock Cycle 7.5 7.5 10 ns — — — ns 5.4 5.4 6 ns Time 1 tAC Clock Access tAC Clock Access Time 2 1. Terminated load. See AC Characteristics on page 37. 2. Unterminated load. See AC Characteristics on page 37. 3. tRP = tRCD = 2 CKs • • • • • • Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge Four Banks controlled by BA0/BA1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8 Programmable Wrap: Sequential or Interleave Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Data Mask for Read/Write control (x4, x8) Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 8192 refresh cycles/64ms Random Column Address every CK (1-N Rule) Single 3.3V ± 0.3V Power Supply LVTTL compatible Package: 54-pin 400 mil TSOP-Type II • -7K parts for PC133 2-2-2 operation -75B parts for PC133 3-3-3 operation -8B parts for PC100 2-2-2 operation Description The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC’s advanced 256Mbit single transistor CMOS DRAM process technology. cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Thirteen row addresses (A0-A12) and two bank select addresses (BA0, BA1) are strobed with RAS. Eleven column addresses (A0-A9, A11) plus bank select addresses and A10 are strobed with CAS. Column address A11 is dropped on the x8 device, and column addresses A11 and A9 are dropped on the x16 device. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A12, BA0, BA1 during a mode register set REV 1.0 May, 2001 1 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Pin Assignments for Planar Components (Top View) VD D V DD V DD 1 54 V SS V SS V SS DQ0 V DDQ NC V DDQ 2 3 53 52 NC V SSQ DQ7 V SSQ DQ15 V SSQ DQ1 DQ0 V DDQ NC NC 4 51 NC NC DQ14 DQ2 DQ1 DQ0 5 50 DQ3 DQ6 DQ13 V SSQ DQ3 V SSQ NC V SSQ NC 6 7 49 48 V DDQ NC V DDQ NC V DDQ DQ12 DQ4 DQ2 V DDQ NC V DDQ DQ5 8 47 NC DQ5 DQ11 V DDQ NC 9 10 46 45 V SSQ NC V SSQ NC V SSQ DQ10 DQ1 11 44 DQ2 DQ4 DQ9 DQ6 NC DQ3 V SSQ V SSQ V SSQ 12 43 V DDQ V DDQ V DDQ DQ7 VD D NC V DD NC V DD LDQM WE NC WE NC WE 13 14 15 42 41 40 NC V SS NC NC V SS NC DQ8 V SS NC 16 39 DQM DQM UDQM CAS RAS CS CAS RAS CS CAS RAS CS 17 18 19 38 37 36 CK CKE A12 CK CKE A12 CK CKE A12 BA0 BA0 BA0 20 35 A11 A11 A11 BA1 A10/AP A0 BA1 A10/AP A0 BA1 A10/AP A0 21 22 23 34 33 32 A9 A8 A7 A9 A8 A7 A9 A8 A7 A1 A2 A1 A2 A1 A2 24 25 31 30 A6 A5 A6 A5 A6 A5 A3 V DD A3 V DD A3 V DD 26 27 29 28 A4 V SS A4 V SS A4 V SS 54-pin Plastic TSOP(II) 400 mil 16Mbit x 4 I/O x 4 Bank NT5SV64M4AT 8Mbit x 8 I/O x 4 Bank NT5SV32M8AT 4Mbit x 16 I/O x 4 Bank NT5SV16M16AT REV 1.0 May, 2001 2 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Pin Description CK Clock Input DQ0-DQ15 Data Input/Output CKE (CKE0, CKE1) Clock Enable DQM, LDQM, UDQM Data Mask CS Chip Select V DD Power (+3.3V) RAS Row Address Strobe V SS Ground CAS Column Address Strobe V DDQ Power for DQs (+3.3V) WE Write Enable V SSQ Ground for DQs BA1, BA0 Bank Select NC No Connection A0 - A12 Address Inputs — — Input/Output Functional Description Symbol Type Polarity Function CK Input Positive Edge CKE, CKE0, CKE1 Input Active High Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA1, BA0 Input The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. — Selects which bank is to be active. A0 - A12 Input — During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9, CA11), when sampled at the rising clock edge. Assume the x4 organization. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. DQ0 - DQ15 InputOutput — Data Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output Active High enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. DQM LDQM UDQM Input V DD , VSS Supply — Power and ground for the input buffers and the core logic. V DDQ V SSQ Supply — Isolated power supply and ground for the output buffers to provide improved noise immunity. REV 1.0 May, 2001 3 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Ordering Information Speed Grade Organization Part Number Clock Frequency@CAS Latency 64M x 4 32M x 8 16M x 16 16M x 16 Package Self Refresh 400mil 54PIN TSOP II SP Note NT5SV64M4AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100 NT5SV64M4AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100 NT5SV64M4AT-8B 125MHz@CL3 100MHz@CL2 PC100 NT5SV32M8AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100 NT5SV32M8AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100 NT5SV32M8AT-8B 125MHz@CL3 100MHz@CL2 PC100 NT5SV16M16AT-7K 143MHz@CL3 133MHz@CL2 PC133 , PC100 NT5SV16M16AT-75B 133MHz@CL3 100MHz@CL2 PC133 , PC100 NT5SV16M16AT-8B 125MHz@CL3 100MHz@CL2 PC100 NT5SV16M16AT-7KL 143MHz@CL3 133MHz@CL2 PC133 , PC100 NT5SV16M16AT-75BL 133MHz@CL3 100MHz@CL2 PC133 , PC100 NT5SV16M16AT-8BL 125MHz@CL3 100MHz@CL2 PC100 LP SP : Standard Power ; LP : Low power REV 1.0 May, 2001 4 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Block Diagram Cell Array Memory Bank 0 Cell Array Memory Bank 1 CK Buffer Sense Amplifiers Data Control Circu itry Mode Re gister Column Address Counter Refresh Counter Sense Amplifiers Control Signa l G enerator A ddress Buffers (15 ) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 BA1 BA0 A10 WE DQ X Column Decoder Row Decode r Ro w Decoder CAS Command Decoder CS DQ0 DQM Column Decoder RAS Da ta Input/O utpu t Buffe rs CK Column Decoder Ro w Decoder Column Decoder CKE Buffer Row Decoder CKE Cell Array Memory Bank 2 Sense Amplifiers Cell Array Memory Bank 3 Sense Amplifiers Cell Array, per bank, for 16Mb x 4 DQ: 8192 Row x 2048 Col x 4 DQ (DQ0-DQ3). Cell Array, per bank, for 8Mb x 8 DQ: 8192 Row x 1024 Col x 8 DQ (DQ0-DQ7). Cell Array, per bank, for 4Mb x 16 DQ: 8192 Row x 512 Col x 16 DQ (DQ0-DQ15). REV 1.0 May, 2001 5 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD +0.3V on any of the input pins or VDD supplies. The CK signal must be started at the same time. After power on, an initial pause of 200µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command is issued. After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. CAS Latency The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section. REV 1.0 May, 2001 6 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Mode Register Operation (Address Input For Mode Set) BA1 BA0 A12 A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 CAS Latency A3 A2 BT A1 Address Bus (Ax) A0 Burst Length Mode Register(Mx) Burst Type M3 Type 0 Sequential 1 Interleave Operation Mode M1 4 M13 M12 M11 M10 M9 M8 M7 Mode Burst Length 0 0 0 0 0 0 0 0 Normal 0 0 0 0 0 1 0 0 Multiple Burst with Single Write Length M2 May, 2001 M0 Sequential Interleave CAS Latency REV 1.0 M1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 M6 M5 M4 Latency 1 0 0 Reserved Reserved 0 0 0 Reserved 1 0 1 Reserved Reserved 0 0 1 Reserved 1 1 0 Reserved Reserved 0 1 0 2 1 1 1 Reserved Reserved 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 7 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A12, BA0, and BA1. The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 (actual page length is dependent on organization: x4, x8, or x16). Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected. Burst Length and Sequence Burst Length 2 4 8 Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) xx0 0, 1 0, 1 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 Note: Page length is a function of I/O organization and column addressing. x4 organization (CA0-CA9, CA11); Page Length = 2048 bits x8 organization (CA0-CA9); Page Length = 1024 bits x16 organization (CA0-CA8); Page Length = 512 bits REV 1.0 May, 2001 8 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Bank Activate Command In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select address BA0 - BA1 is used to select the desired bank. The row address A0 - A12 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS delay time (t RCD). Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC ). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD). The maximum time that each bank can be held active is specified as tRAS(max). Bank Activate Command Cycle (CAS Latency = 3, t RCD = 3) T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CK .......... Bank A Row Addr. ADDRESS Bank A Col. Addr. .......... R A S-CAS delay ( tRCD) COMMAND Bank A Activate NOP Bank B Row Addr. Bank A Row Addr. R A S - R A S delay time ( tRRD) Write A with Auto Precharge NOP .......... Bank B Activate Bank A Activate NOP NOP : “H” or “L” RAS Cycle time ( tRC ) Bank Select The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation. Bank Selection Bits REV 1.0 May, 2001 BA0 BA1 Bank 0 0 Bank 0 1 0 Bank 1 0 1 Bank 2 1 1 Bank 3 9 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (t RCD). WE must also be defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles up to 133MHz. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (tREF ) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address. Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle. REV 1.0 May, 2001 10 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A NOP C A S latency = 2 t CK2, DQs NOP NOP NOP NOP DOUT A 0 DOUT A 1 DOUT A2 DOUT A 3 DOUT A 0 DOUT A 1 DOUT A 2 C A S latency = 3 t CK3, DQs NOP NOP NOP DOUT A 3 Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 READ A READ B T2 T3 T4 T5 T6 T7 T8 CK COMMAND C A S latency = 2 t CK2, DQs C A S latency = 3 t CK3, DQs REV 1.0 May, 2001 NOP NOP NOP NOP NOP DOUT A 0 DOUT B 0 DOUT B1 DOUT B 2 DOUT B3 DOUT A 0 DOUT B 0 DOUT B1 DOUT B 2 NOP NOP DOUT B 3 11 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus. Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK DQM high for CAS latency = 2 only. Required to mask first bit of READ data. DQM COMMAND C A S latency = 2 t CK2, DQs NOP READ A WRITE A NOP NOP NOP DIN A 0 DIN A 1 DIN A 2 DIN A 3 DIN A 0 DIN A 1 DIN A 2 DIN A 3 NOP NOP NOP C A S latency = 3 t CK3, DQs : “H” or “L” REV 1.0 May, 2001 12 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK DQM COMMAND READ A NOP WRITE A NOP NOP NOP NOP NOP NOP CL = 2: DQM needed to mask first, second bit of READ data. C A S latency = 2 t CK2, DQs DIN A 0 DIN A 1 DIN A 2 DIN A 3 CL = 3: DQM needed to mask first bit of READ data. C A S latency = 3 t CK3, DQs DIN A 0 DIN A 1 DIN A 2 DIN A 3 : DQM high for CAS latency = 2 : DQM high for CAS latency = 3 REV 1.0 May, 2001 13 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Burst Write Command The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK NOP COMMAND DQs WRITE A DIN A 0 NOP NOP NOP DIN A 1 DIN A 2 DIN A 3 NOP NOP NOP NOP : “H” or “L” The first data element and the Write are registered on the same clock edge. Extra data is masked. Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 WRITE A WRITE B T3 T4 T5 T6 T7 T8 CK COMMAND NOP NOP NOP NOP DIN B 1 DIN B 2 DIN B 3 NOP NOP NOP 1 CK Interval DQs REV 1.0 May, 2001 DIN A 0 DIN B 0 14 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory. Minimum Write to Read Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND CAS latency = 2 t CK2, DQs CAS latency = 3 tCK3 , DQs : “H” or “L” REV 1.0 May, 2001 WRITE A DIN A 0 READ B NOP NOP NOP NOP NOP DOUT B 0 DOUT B 1 DOUT B 2 DOUT B 3 DOUT B 0 DOUT B 1 DOUT B 2 DIN A 0 Input data for the Write is masked. NOP NOP DOUT B 3 Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. 15 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Non-Minimum Write to Read Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND WRITE A NOP DIN A 0 DIN A 1 DIN A 0 DIN A 1 C A S latency = 2 tCK2, DQs READ B NOP NOP DOUT B0 NOP NOP NOP DOUT B 1 DOUT B2 DOUT B 3 DOUT B 0 DOUT B 1 DOUT B2 NOP CAS latency = 3 tCK3, DQs : “H” or “L” REV 1.0 May, 2001 Input data for the Write is masked. DOUT B 3 Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. 16 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands. A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP ) has been satisfied. When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t RAS(min). If this interval does not satisfy t RAS(min) then t RCD must be extended. Burst Read with Auto-Precharge (Burst Length = 1, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A Auto-Precharge CAS latency = 2 t CK2, DQs CAS latency = 3 t CK3, DQs NOP NOP NOP NOP NOP NOP NOP NOP * tRP‡ DOUT A 0 * tRP‡ DOUT A 0 can be reactivated at completion of t . *Bank t is a function of clock cycle time and speed sort. RP ‡ Begin Auto-precharge RP See the Clock Frequency and Latency table. REV 1.0 May, 2001 17 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Burst Read with Auto-Precharge (Burst Length = 2, CAS Latency = 2, 3) CK COMMAND T0 T1 READ A Auto-Precharge NOP T2 NOP T3 T4 NOP tCK2, DQs DOUT A 0 NOP NOP NOP T7 NOP T8 NOP DOUT A 1 * tRP‡ CAS latency = 3 tCK3, DQs T6 * tRP‡ CAS latency = 2 T5 DOUT A0 DOUT A 1 Begin Auto-precharge *‡ Bank can be reactivated at completion of t R P. tR P is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. * Burst Read with Auto-Precharge (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A Auto-Precharge NOP NOP NOP NOP DOUT A 0 DOUT A1 DOUT A 2 NOP * * tRP‡ DOUT A0 NOP DOUT A 3 CAS latency = 3 t CK3, DQs NOP tRP‡ CAS latency = 2 t CK2, DQs NOP DOUT A 1 DOUT A 2 DOUT A3 can be reactivated at completion of t . *Bank t is a function of clock cycle time and speed sort. RP ‡ Begin Auto-precharge RP See the Clock Frequency and Latency table. * REV 1.0 May, 2001 18 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay t RP . Burst Read with Auto-Precharge Interrupted by Read (Burst Length = 4, CAS Latency = 2, 3) CK COMMAND T0 READ A Auto-Precharge T1 NOP T2 READ B T3 T4 NOP NOP t CK2, DQs DOUT A 0 DOUT A1 t CK3, DQs T7 NOP NOP NOP DOUT B 0 DOUT B 1 DOUT B2 DOUT B 3 DOUT B 1 DOUT B2 T8 NOP * tRP‡ CAS latency = 3 T6 * tRP ‡ CAS latency = 2 T5 DOUT A0 DOUT A 1 DOUT B 0 DOUT B 3 can be reactivated at completion of t . *‡ Bank t is a function of clock cycle time and speed sort. RP RP See the Clock Frequency and Latency table. If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention. Burst Read with Auto-Precharge Interrupted by Write (Burst Length = 8, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A Auto-Precharge NOP NOP NOP WRITE B tRP ‡ CAS latency = 2 t CK2, DQs NOP DOUT A 0 D IN B0 DIN B 1 NOP NOP NOP D IN B 3 D IN B4 * D IN B2 DQM can be reactivated at completion of t . *‡ Bank t is a function of clock cycle time and speed sort. RP RP . See the Clock Frequency and Latency table . REV 1.0 May, 2001 19 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing autoprecharge cannot be reactivated until tDAL , Data-in to Active delay, is satisfied. Burst Write with Auto-Precharge T0 T1 T2 T3 T4 T5 (Burst Length = 2, CAS Latency = 2, 3) T6 T7 T8 CK COMMAND WRITE A Auto-Precharge NOP NOP DIN A 0 NOP NOP NOP * tDAL‡ DIN A 0 NOP DIN A 1 CAS latency = 3 t CK3, DQs NOP * tDAL ‡ CAS latency = 2 t CK2, DQs NOP DIN A 1 can be reactivated at completion of t . *‡ Bank t is a function of clock cycle time and speed sort. DAL DAL See the Clock Frequency and Latency table. Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the write. The bank undergoing auto-precharge can not be reactivated until t DAL is satisfied. Burst Write with Auto-Precharge Interrupted by Write T0 T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 3) T6 T7 T8 CK COMMAND WRITE A Auto-Precharge NOP WRITE B NOP DIN A 0 DIN A 1 DIN B 0 NOP NOP NOP NOP * tDAL‡ CAS latency = 3 t CK3, DQs NOP DIN B 1 DIN B2 DIN B3 can be reactivated at completion of t . *‡ Bank t is a function of clock cycle time and speed sort. DAL DAL See the Clock Frequency and Latency table. REV 1.0 May, 2001 20 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Burst Write with Auto-Precharge Interrupted by Read (Burst Length = 4, CAS Latency = 3) T0 CK COMMAND T1 WRITE A Auto-Precharge NOP T2 T3 NOP T4 READ B NOP NOP T6 T7 NOP DIN A 0 DIN A1 DIN A 2 T8 NOP NOP * tDAL ‡ CAS latency = 3 tCK3, DQs T5 DOUT B 0 DOUT B 1 DOUT B 2 * Bank A can be reactivated at completion of tDAL . ‡ tDAL is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which bank(s) is to be precharged when the command is issued. Bank Selection for Precharge by Address Bits A10 Bank Select Precharged Bank(s) LOW BA0, BA1 Single bank defined by BA0, BA1 HIGH DON’T CARE All Banks For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL , Data-in to Precharge delay. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP ). REV 1.0 May, 2001 21 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Burst Read Followed by the Precharge Command (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ Ax 0 NOP NOP NOP NOP Precharge A NOP tRP NOP NOP ‡ * C A S latency = 3 DOUT Ax 0 tCK2, DQs DOUT Ax1 DOUT Ax 2 * D O U T A x3 Bank A can be reactivated at completion of t RP . ‡ tR P is a function of clock cycle and speed sort. Burst Write Followed by the Precharge Command (Burst Length = 2, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND NOP Activate Bank Ax NOP NOP WRITE Ax 0 NOP Precharge A tDPL‡ NOP tRP‡ NOP * CAS latency = 2 t CK2, DQs DIN Ax 0 DIN Ax 1 can be reactivated at completion of t . *‡ tBankand t are functions of clock cycle and speed sort. RP DPL RP See the Clock Frequency and Latency table. REV 1.0 May, 2001 22 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Precharge Termination The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of CAS Latency. Burst Read Interrupted by Precharge (Burst Length = 8, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ Ax0 NOP NOP NOP NOP Precharge A NOP t CK2, DQs DOUT Ax 0 DOUT Ax1 DOUT Ax 2 NOP * tRP ‡ C A S latency = 2 NOP DOUT Ax 3 * tRP ‡ C A S latency = 3 t CK3, DQs DOUT Ax 0 DOUT Ax1 * ‡ REV 1.0 May, 2001 DOUT Ax 2 D O U T A x3 Bank A can be reactivated at completion of tRP . tR P is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. 23 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, t DPL. Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND NOP NOP WRITE Ax0 NOP NOP NOP Precharge A NOP NOP DQM tDPL ‡ CAS latency = 2 tCK2, DQs DIN Ax 0 DIN Ax 1 DIN Ax 2 tDPL‡ CAS latency = 3 tCK3, DQs DIN Ax 0 DIN Ax 1 ‡ REV 1.0 May, 2001 DIN Ax 2 tDPL is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time. 24 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Automatic Refresh Command (CAS before RAS Refresh) When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP ) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the RAS cycle time (tRC ). Self Refresh Command The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the devic e exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC ) plus the Self Refresh exit time (t SREX ). REV 1.0 May, 2001 25 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Power Down Mode In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (t RP ) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (t REF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect Command) is required on the next rising clock edge. Power Down Mode Exit Timing Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+ 8 COMMAND NOP NOP NOP NOP NOP CK tCK CKE tCES(min) COMMAND NOP : “H” or “L” REV 1.0 May, 2001 26 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Data Mask The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of CAS latency. Data Mask Activated during a Read Cycle (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK DQM COMMAND NOP READ A DQs NOP NOP DOUT A0 NOP DOUT A 1 NOP NOP NOP NOP A two-clock delay before the DQs become Hi-Z : “H” or “L” No Operation Command The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares. REV 1.0 May, 2001 27 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Clock Suspend Mode During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited. Clock Suspend during a Read Cycle T0 T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 2) T6 T7 T8 CK CKE A one clock delay to exit the Suspend command A one clock delay before suspend operation starts COMMAND NOP READ A NOP DQs NOP NOP DOUT A 0 DOUT A2 DOUT A 1 : “H” or “L” NOP DOUT element at the DQs when the suspend operation starts is held valid If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Suspend mode is exited. Clock Suspend during a Write Cycle (Burst Length = 4, CAS Latency = 2) CK T0 T1 T2 T3 T4 T5 CKE T6 T7 T8 A one clock delay to exit the Suspend command A one clock delay before suspend operation starts COMMAND DQs : “H” or “L” REV 1.0 May, 2001 NOP WRITE A DIN A 0 NOP NOP NOP DIN A 1 DIN A 2 DIN A 3 NOP DIN is masked during the Clock Suspend Period 28 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Command Truth Table (See note 1) CKE Function Device State Previous Cycle Current Cycle CS RAS CAS WE DQM BA0, BA1 A12, A11, A9-A0 A10 Notes Mode Register Set Idle H X L L L L X Auto (CBR) Refresh Idle H H L L L H X X X X Entry Self Refresh Idle H L L L L H X X X X Idle (SelfRefresh) H X X X Exit Self Refresh L H L H H H X X X X Single Bank Precharge See Current State Table H X L L H L X BS L X Precharge all Banks See Current State Table H X L L H L X X H X Bank Activate Idle H X L L H H X BS Write Active H X L H L L X BS L Column 2 Write with Auto-Precharge Active H X L H L L X BS H Column 2 Read Active H X L H L H X BS L Column 2 Read with Auto-Precharge Active H X L H L H X BS H Column 2 Reserved OP Code Row Address 2 2 H X L H H L X X X X No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Clock Suspend Mode Entry Active H L X X X X X X X X Clock Suspend Mode Exit Active L H X X X X X X X X Data Write/Output Enable Active H X X X X X L X X X Data Mask/Output Disable Active H X X X X X H X X X Power Down Mode Entry Idle/Active H L H X X X X X X X 6, 7 L H H H H X X X L H H H X X X X 6, 7 Power Down Mode Exit Any (Power Down) L H 4 5 1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the Current State Truth Table. 2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1 selects bank 3. 3. Not applicable. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cy cles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the devic e state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remai n in this mode longer than the Refresh period (t REF ) of the device. One clock delay is required for mode entry and exit. 7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high. REV 1.0 May, 2001 29 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Clock Enable (CKE) Truth Table CKE Current State Self Refresh Command Action Notes Previous Cycle Current Cycle CS RAS CAS WE BA0, BA1 A 12 - A0 H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh H X X X X X X X INVALID 1 L H H X X X X X Power Down mode exit, all banks idle 2 L H L X X X X X ILLEGAL 2 L L X X X X X X Maintain Power Down Mode H H H X X X H H L H X X H H L L H X H H L L L H H H L L L L H L H X X X Power Down All Banks Idle Any State other than listed above 3 Refer to the Idle State section of the Current State Truth Table 3 3 X X OP Code CBR Refresh Mode Register Set 4 3 Refer to the Idle State section of the Current State Truth Table H L L H X X H L L L H X H L L L L H H L L L L L L X X X X X X X Power Down H H X X X X X X Refer to operations in the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend 3 3 X X OP Code Entry Self Refresh 4 Mode Register Set 4 5 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (t CES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high (see page 26). 3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle stat e. 5. Must be a legal command as defined in the Current State Truth Table. REV 1.0 May, 2001 30 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Current State Truth Table Current State Idle Row Active Read Write (Part 1 of 3)(See note 1) Command CS RAS CAS WE BA0,BA1 A12 - A0 OP Code Action Description Mode Register Set Set the Mode Register X Auto or Self Refresh Start Auto or Self Refresh X Precharge No Operation Notes L L L L L L L H X L L H L BS L L H H BS L H L L BS Column Write w/o Precharge ILLEGAL 4 L H L H BS Column Read w/o Precharge ILLEGAL 4 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation or Power Down L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Precharge L L H H BS L H L L BS Column Write Start Write; Determine if Auto Precharge 7, 8 L H L H BS Column Read Start Read; Determine if Auto Precharge 7, 8 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Terminate Burst; Start the Precharge L L H H BS L H L L BS Column Write Terminate Burst; Start the Write cycle 8, 9 L H L H BS Column Read Terminate Burst; Start a new Read cycle 8, 9 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Terminate Burst; Start the Precharge L L H H BS L H L L BS Column Write Terminate Burst; Start a new Write cycle 8, 9 L H L H BS Column Read Terminate Burst; Start the Read cycle 8, 9 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst Row Address Bank Activate OP Code Row Address Bank Activate OP Code Row Address Bank Activate OP Code Row Address Bank Activate 2 2, 3 Activate the specified bank and row ILLEGAL ILLEGAL ILLEGAL 5 6 4 4 4 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (t RAS ) must be satisfied. 7. The RAS to CAS Delay (t RCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD ) is not satisfied. REV 1.0 May, 2001 31 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Current State Truth Table Current State Read with Auto Precharge Write with Auto Precharge Precharging Row Activating (Part 2 of 3)(See note 1) Command CS RAS CAS WE BA0,BA1 A12 - A0 OP Code Action Description Notes L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge No Operation; Bank(s) idle after tRP L L H H BS ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation No Operation; Bank(s) idle after tRP H X X X X X Device Deselect No Operation; Bank(s) idle after tRP L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS ILLEGAL 4, 10 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation No Operation; Row Active after tRCD H X X X X X Device Deselect No Operation; Row Active after tRCD Row Address Bank Activate OP Code Row Address Bank Activate OP Code Row Address Bank Activate OP Code Row Address Bank Activate 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (t RAS ) must be satisfied. 7. The RAS to CAS Delay (t RCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD ) is not satisfied. REV 1.0 May, 2001 32 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Current State Truth Table Current State Write Recovering Write Recovering with Auto Precharge Refreshing Mode Register Accessing (Part 3 of 3)(See note 1) Command CS RAS CAS WE BA0,BA1 A12 - A0 OP Code Action Description Notes L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS ILLEGAL 4 L H L L BS Column Write Start Write; Determine if Auto Precharge 9 L H L H BS Column Read Start Read; Determine if Auto Precharge 9 L H H H X X No Operation No Operation; Row Active after tDPL H X X X X X Device Deselect No Operation; Row Active after tDPL L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL L L H H BS L H L L BS Column L H L H BS Column L H H H X X H X X X X X L L L L L L L H X L L H L BS L L H H BS L H L L BS Column Write ILLEGAL L H L H BS Column Read ILLEGAL L H H H X X No Operation No Operation; Idle after tRC H X X X X X Device Deselect No Operation; Idle after tRC L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL L L H H BS L H L L BS Column Write ILLEGAL L H L H BS Column Read ILLEGAL L H H H X X No Operation No Operation; Idle after two clock cycles H X X X X X Device Deselect No Operation; Idle after two clock cycles Row Address Bank Activate OP Code Row Address Bank Activate 4 ILLEGAL 4 Write ILLEGAL 4, 9 Read ILLEGAL 4, 9 No Operation No Operation; Precharge after tDPL Device Deselect No Operation; Precharge after tDPL Mode Register Set ILLEGAL X Auto or Self Refresh ILLEGAL X Precharge ILLEGAL OP Code Row Address Bank Activate OP Code Row Address Bank Activate ILLEGAL ILLEGAL 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (t RAS ) must be satisfied. 7. The RAS to CAS Delay (t RCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD ) is not satisfied. REV 1.0 May, 2001 33 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Absolute Maximum Ratings Symbol VD D V DDQ V IN V OUT TA TSTG PD IOUT Parameter Rating Units Notes Power Supply Voltage -0.3 to +4.6 V 1 Power Supply Voltage for Output -0.3 to +4.6 V 1 Input Voltage -0.3 to V DD+0.3 V 1 Output Voltage -0.3 to V DD+0.3 V 1 0 to +70 °C 1 -55 to +125 °C 1 Power Dissipation 1.0 W 1 Short Circuit Output Current 50 mA 1 Operating Temperature (ambient) Storage Temperature 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (TA = 0°C to 70°C) Rating Symbol Parameter Min. Typ. Max. Units Notes V DD Supply Voltage 3.0 3.3 3.6 V 1 V DDQ Supply Voltage for Output 3.0 3.3 3.6 V 1 VI H Input High Voltage 2.0 — V DD + 0.3 V 1, 2 V IL Input Low Voltage -0.3 — 0.8 V 1, 3 1. All voltages referenced to VSS and V SSQ. 2. V IH (max) = V DD + 1.2V for pulse width ≤ 5ns. 3. V IL (min) = V SS - 1.2V for pulse width ≤ 5ns. Capacitance (TA = 25°C, f = 1MHz, V DD = 3.3V ± 0.3V) Symbol CI CO REV 1.0 May, 2001 Parameter Min. Typ Max. Units Input Capacitance (A0-A12, BA0, BA1, CS, RAS, CAS , WE, CKE, DQM) 2.5 3.0 3.8 pF Input Capacitance (CK) 2.5 2.8 3.5 pF Output Capacitance (DQ0 - DQ15) 4.0 4.5 6.5 pF Notes 34 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM DC Electrical Characteristics (T A = 0 to +70°C, VDD Symbol = 3.3V ±0.3V) Parameter Min. Max. Units Notes 1 II(L) Input Leakage Current, any input (0.0V ≤ V I N ≤ V DD), All Other Pins Not Under Test = 0V -1 +1 µA IO(L) Output Leakage Current (D OUT is disabled, 0.0V ≤ V OUT ≤ V DDQ ) -1 +1 µA V OH Output Level (LVTTL) Output “H” Level Voltage (IOUT = -2.0mA) 2.4 — V V OL Output Level (LVTTL) Output “L” Level Voltage (IOUT = +2.0mA) — 0.4 V DC Output Load Circuit 3.3 V 1200Ω V O H (DC) = 2.4V, I O H = -2mA Output V OL (DC) = 0.4V, I OL = 2mA 50pF REV 1.0 May, 2001 870Ω 35 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V ±0.3V) Speed Parameter Symbol Test Condition Units Notes 115 mA 1, 2, 3 -7K -75 B -8B 130 120 IC C 1 1 bank operation tR C = tRC(min), t CK = min Active-Precharge command cycling without burst operation ICC2P CKE ≤ V IL (max), tC K = min, CS = V I H(min) 2 2 2 mA 1 ICC2PS CKE ≤ V IL (max), tC K = Infinity, CS = V I H(min) 2 2 2 mA 1 ICC2N CKE ≥ V I H(min), tCK = min, CS = V IH (min) 30 30 20 mA 1, 5 ICC2NS CKE ≥ V I H(min), tCK = Infinity, 8 8 8 mA 1, 7 ICC3N CKE ≥ V I H(min), tCK = min, CS = V IH (min) 60 60 45 mA 1, 5 ICC3P CKE ≤ V IL (max), tC K = min, 6 6 6 mA 1, 6 Operating Current (Burst Mode) IC C 4 tCK = min, Read/ Write command cycling, Multiple banks active, gapless data, BL = 4 120 120 90 mA 1, 3, 4 Auto (CBR) Refresh Current IC C 5 tCK = min, t R C = tRC(min) CBR command cycling 175 175 155 mA 1 3 3 3 mA 1,8 IC C 6 CKE ≤ 0.2V SP Self Refresh Current LP 1.2 1.2 1.2 mA 8 Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode No Operating Current (Active state: 4 bank) 1. Currents given are valid for a single device. . 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tC K and t R C . Input signals are changed up to three times during tR C (min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during tC K (min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 7. Input signals are stable. 8. SP : Standard power ; LP : Lower power REV 1.0 May, 2001 36 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V) 1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and V IL (or between VIL and VIH ) 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and V IH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and V IH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A: AC measurements assume tT = 1.0ns. 6. Load Circuit B: AC timing tests have VIL = 0.8 V and V IH = 2.0 V with the timing referenced to the 1.40V crossover point 7. Load Circuit B: AC measurements assume tT = 1.2ns. . AC Characteristics Diagrams tT tCKL Clock tSETUP tCKH Vtt = 1.4V V IH 1.4V V IL 50Ω Output Zo = 50Ω 50pF AC Output Load Circuit (A) tHOLD Input 1.4V Output tAC Zo = 50Ω tO H 50pF tLZ Output REV 1.0 May, 2001 AC Output Load Circuit (B) 1.4V 37 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Clock and Clock Enable Parameters Symbol Parameter -7 K -75B -8B Min. Max. Min. Max. Min. Max. Units Notes tCK3 Clock Cycle Time, CAS Latency = 3 7 1000 7.5 1000 8 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 7.5 1000 10 — 10 1000 ns tAC3 (A) Clock Access Time, CAS Latency = 3 — — — — — — ns 1 tAC2 (A) Clock Access Time, CAS Latency = 2 — — — — — — ns 1 tAC3 (B) Clock Access Time, CAS Latency = 3 — 5.4 — 5.4 — 6 ns 2 tAC2 (B) Clock Access Time, CAS Latency = 2 — 5.4 — 6 — 6 ns 2 tCKH Clock High Pulse Width 2.5 — 2.5 — 3 — ns tCKL Clock Low Pulse Width 2.5 — 2.5 — 3 — ns tCES Clock Enable Set-up Time 1.5 — 1.5 — 2 — ns tCEH Clock Enable Hold Time 0.8 — 0.8 — 1 — ns tSB Power down mode Entry Time 0 7.5 0 7.5 0 10 ns tT Transition Time (Rise and Fall) 0.5 10 0.5 10 0.5 10 ns 1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A. 2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B. Common Parameters -7K Symbol -75B -8B Parameter Units Min. Max. Min. Max. Min. Max. Notes tCS Command Setup Time 1.5 — 1.5 — 2 — ns tC H Command Hold Time 0.8 — 0.8 — 1 — ns tAS Address and Bank Select Set-up Time 1.5 — 1.5 — 2 — ns tAH Address and Bank Select Hold Time 0.8 — 0.8 — 1 — ns tR C D RAS to CAS Delay 15 — 20 — 20 — ns 1 tR C Bank Cycle Time 60 — 67.5 — 70 — ns 1 tRAS Active Command Period 45 100K 45 100K 50 100K ns 1 tRP Precharge Time 15 — 20 — 20 — ns 1 tR R D Bank to Bank Delay Time 15 — 15 — 20 — ns 1 tC C D CAS to CAS Delay Time 1 — 1 — 1 — CK 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Mode Register Set Cycle -7K Symbol tRSC REV 1.0 May, 2001 -75B -8B Parameter Mode Register Set Cycle Time Units Min. Max. Min. Max. Min. Max. 15 — 15 — 20 — ns 38 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Read Cycle -7K Symbol -75B -8B Parameter Min. Max. Min. Max. Min. Units Notes Max. — — — — 2.5 — ns 1 2.7 — 2.7 — 3 — ns 2, 4 Data Out to Low Impedance Time 0 — 0 — 0 — ns tHZ3 Data Out to High Impedance Time 3 5.4 3 5.4 3 6 ns 3 tHZ2 Data Out to High Impedance Time 3 5.4 3 6 3 6 ns 3 tDQZ DQM Data Out Disable Latency 2 — 2 — 2 — CK 1. 2. 3. 4. tOH Data Out Hold Time tLZ AC Output Load Circuit A. AC Output Load Circuit B. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A). Refresh Cycle -7K Symbol tREF tSREX -75B -8B Parameter Units Notes 64 ms 1 — ns Min. Max. Min. Max. Min. Max. Refresh Period — 64 — 64 — Self Refresh Exit Time 10 — 10 — 10 1. 8192 a uto refresh cycles. Write Cycle -7K Symbol -75B -8B Parameter Units Min. Max. Min. Max. Min. Max. tDS Data In Set-up Time 1.5 — 1.5 — 2 — ns tD H Data In Hold Time 0.8 — 0.8 — 1 — ns tDPL Data input to Precharge 15 — 15 — 20 — ns tDAL3 Data In to Active Delay CAS Latency = 3 5 — 5 — 5 — CK tDAL2 Data In to Active Delay CAS Latency = 2 5 — 5 — 5 — CK tDQW DQM Write Mask Latency 0 — 0 — 0 — CK REV 1.0 May, 2001 39 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Clock Frequency and Latency Symbol Parameter -7K -75B -8B Units fCK Clock Frequency 143 133 133 100 125 100 MHz tCK Clock Cycle Time 7 7.5 7.5 10 8 10 ns tAA CAS Latency 3 2 3 2 3 2 CK tRP Precharge Time 3 2 3 2 3 2 CK tRCD RAS to CAS Delay 3 2 3 2 3 2 CK tRC Bank Cycle Time 9 8 9 7 9 7 CK tRAS Minimum Bank Active Time 6 6 6 5 6 5 CK tDPL Data In to Precharge 2 2 2 2 2 2 CK tDAL Data In to Active/Refresh 5 5 5 5 5 5 CK tRRD Bank to Bank Delay Time 2 2 2 2 2 2 CK tCCD CAS to CAS Delay Time 1 1 1 1 1 1 CK tWL Write Latency 0 0 0 0 0 0 CK tDQW DQM Write Mask Latency 0 0 0 0 0 0 CK tDQZ DQM Data Disable Latency 2 2 2 2 2 2 CK tCSL Clock Suspend Latency 1 1 1 1 1 1 CK REV 1.0 May, 2001 40 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Timing Diagrams Page AC Parameters for Write Timing..................................................................................................................................42 AC Parameters for Read Timing (3/3/3), BL=4 ...........................................................................................................43 AC Parameters for Read Timing (2/2/2), BL=2 ...........................................................................................................44 AC Parameters for Read Timing (3/2/2), BL=2 ...........................................................................................................45 AC Parameters for Read Timing (3/3/3), BL=2 ...........................................................................................................46 Mode Register Set.......................................................................................................................................................47 Power on Sequence and Auto Refresh (CBR) ............................................................................................................48 Clock Suspension / DQM During Burst Read .............................................................................................................49 Clock Suspension / DQM During Burst Write ............................................................................................................50 Power Down Mode and Clock Suspend......................................................................................................................51 Auto Refresh (CBR).....................................................................................................................................................52 Self Refresh (Entry and Exit) .......................................................................................................................................53 Random Row Read (Interleaving Banks) with Precharge, BL=8.................................................................................54 Random Row Read (Interleaving Banks) with Auto-precharge, BL=8 ........................................................................55 Random Row Write (Interleaving Banks) with Auto-Precharge, BL=8 ........................................................................56 Random Row Write (Interleaving Banks) with Precharge, BL=8.................................................................................57 Read/Write Cycle ...............................................................................................................................................58 Interleaved Column Read Cycle..................................................................................................................................59 Auto Precharge after a Read Burst, BL=4...................................................................................................................60 Auto Precharge after a Write Burst, BL=4...................................................................................................................61 Burst Read and Single Write Operation ......................................................................................................................62 CS Function (Only CS signal needs to be asserted at minimum rate) ........................................................................63 REV 1.0 May, 2001 41 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.0 May, 2001 Bank2,3 = Idle * BA0 = ”L” DQ DQM Hi-Z t CKH A0-A9, A11,A12 A10 * BA1 WE CAS RAS CS CKE CK tAS tCES T0 T3 tR CD tAH Ax0 CAx tCK2 tC H tCS T2 T4 Ax1 T5 Ax2 tR C RBx RBx T6 Ax3 T7 Bx0 CBx T9 Bx1 Bx2 tDS T11 Ac tivate Command Bank 0 Bx3 R Ay RAy T10 Ay0 CAy T14 tDH Ay1 T13 Write Command Bank 0 T 12 Ay2 T15 Ay3 T17 T18 Prec harge Command Bank 0 tD PL ‡ T16 ‡ tDPL and tDAL depend on clock cycle time and speed sort. S ee the Clock Frequency and Latency Table. tDAL ‡ T8 Activate Write with Activate Write with Command Auto Precharge Command Auto Precharge Bank 0 Command Bank 1 Command Bank 0 Bank 1 RAx RAx tC KL T1 RAz RAz tC EH T21 R By RBy T22 Ac tivate Command Bank 1 tRR D T20 Ac tivate Command Bank 0 tRP T 19 (Burst length = 4, CAS latency = 2) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM AC Parameters for Write Timing \ 42 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Hi-Z Bank2,3 = Idle * BA0 = ”L” DQ DQM A0-A9, A11, A12 A10 * BA1 WE CAS RAS CS CKE CK R Ax R Ax T1 Ac tivate C omm and Bank 0 T0 t RCD tCK 3 T2 C Ax tRAS T4 R ead w ith Auto Precharge Com mand Bank 0 tRRD T3 T6 Ac tiv ate Comm and Bank 1 tAC3 RBx RBx tRC T5 A x0 t OH Ax1 Begin Auto Prec harge Bank 0 T7 tRP Ax2 CBx T9 R ead with Auto Precharge C omm and Bank 1 T8 Ax3 T 10 Bx0 R Ay R Ay Bx1 Begin Auto Precharge Bank 1 T12 Ac tiv ate Com mand Bank 0 T 11 T13 Bx2 (Burst length = 4, CAS latency = 3; tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM AC Parameters for Read Timing (3/3/3) \ 43 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 tAS tCES tCKH tCKL T1 Hi-Z Bank2,3 = Idle R Ax R Ax T2 tRCD tAH tCH tCS tCK2 Ac tivate C omm and Bank 0 Note: Must satisfy t RAS(min) For -260 : extend t RC D1 clo ck * BA0 = ”L” DQ DQM A0-A9, A11, A12 A10 * BA1 WE CAS RAS CS CKE CK T0 tRRD T5 tLZ Ax0 t OH T6 Ac tiv ate C omm and Bank 1 tA C2 tRC RBx RBx Begin Auto Precharge Bank 0 t RAS(mi n) CAx T4 Read w ith Auto Prec harge Com mand Bank 0 T3 CB x T8 R ead with Auto Precharge C omm and Bank 1 Ax1 tHZ tRP T7 Begin Auto Precharge Bank 1 T9 Bx0 T10 tHZ Bx1 tRP R Ay R Ay T12 Ac tivate C omm and Bank 0 tCEH T 11 T 13 (Burst length = 2, CAS latency = 2; tRCD , tRP = 2) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM AC Parameters for Read Timing (2/2/2) \ 44 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 tAS tCES Hi-Z Bank2,3=Idle * BA0=” L” DQ tA H t CH tCS T1 Activate C ommand Bank 0 R Ax R Ax tCKH tCKL No te: Must satisfy t RAS(min). Exten ded tR CD 1 clo ck. No t requir ed for BL ≥ 4. DQM A0-A9, A11, A12 A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD t CK3 T2 tRAS CAx T4 R ead w ith Auto Precharge Com mand Bank 0 tRRD T3 tRC Ac tiv ate Com mand Bank 1 RBx RBx Begin Auto Precharge Bank 0 T5 tL Z tAC3 T6 Ax0 Ax 1 tHZ C Bx T8 R ead with Auto Precharge C omm and Bank 1 tO H t RP T7 Begin Auto Precharge Bank 1 T9 T 10 Bx0 tRP Bx 1 tHZ RAy RAy t CEH T 12 Ac tiv ate Comm and Bank 0 T11 T13 (Burst length = 2, CAS latency = 3; tRCD , tRP = 2) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM AC Parameters for Read Timing (3/2/2) \ 45 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 H i-Z *BA0=” L” Bank 2,3= Idle DQ Ac tiv ate Com mand Bank 0 R Ax A0-A9, A11, A12 DQM R Ax A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD tCK3 T2 CAx t RRD tRA S (mIn ) T3 tRC T4 Bank 0 Note: Must satisfy tRAS (min). R ead w ith E xtende d tRC D not r equired Auto Precharge for BL≥ 4. C omm and T1 T6 Ac tiv ate Com mand Bank 1 tAC3 RB x RB x Begin Auto Precharge Bank 0 T5 Ax0 tOH tRP T7 Ax1 T8 CB x T 10 Read w ith Auto Prec harge Com mand Bank 1 T9 T12 Activate Com mand Bank 0 RAy RAy Begin Auto Precharge Bank 1 T 11 Bx0 tRP tCEH T13 Bx1 T14 (Burst length = 2, CAS latency = 3; tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM AC Parameters for Read Timing (3/3/3) \ 46 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Mode Register Set T22 T 21 T20 T19 Mode Register Set Com mand tRP REV 1.0 May, 2001 DQ DQM A0-A9 A10,A11, A12 BA0,BA1 WE CAS RAS CS CKE CK Hi-Z T0 T1 tCK2 Precharge Command All Banks T2 T3 T4 Address Key tRSC T5 T6 Any Command T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T 17 T18 (CAS latency = 2) \ 47 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.0 May, 2001 DQ DQM A0-A9, A11,A12 A10 BS WE CAS RAS CS CKE CK tCK T2 T3 T4 Precharge 1st Auto Refresh Command Command All Banks tRP High level is required T1 Inputs must be stable for 200µs Hi-Z T0 T5 T7 T8 T9 T10 T11 T12 8th Auto Refresh Command T14 tRC T13 Minimum of 8 Refresh Cycles are required T6 T15 T18 Mode Register Set Command T19 Any Command 2 Clock min. T17 Address Key T16 T20 T21 T22 NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Power-On Sequence and Auto Refresh (CBR) \ 48 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Hi-Z Bank2,3=Idle * BA0=” L” DQ DQM A0-A9, A11,A12 A10 * BA1 WE CAS RAS CS CKE CK R Ax R Ax t CK 3 T1 Activate Command Bank 0 T0 T2 CA x T4 Read Command Bank 0 T3 T6 tCES T5 Ax0 Ax1 tCEH T8 T9 Clock Suspend 1 Cycle T7 T11 Clock Suspend 2 Cycles Ax2 T10 T12 Ax3 T14 T15 Clock Suspend 3 Cycles T13 T16 Ax4 T17 T18 T19 Ax6 tHZ T20 Ax7 T21 T22 (Burst length = 8, CAS latency = 3; tRCD = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Clock Suspension / DQM During Burst Read \ 49 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Hi-Z Bank2,3=Idle * BA0=” L” DQ DQM A0-A9, A11, A12 A10 * BA1 WE CAS RAS CS CKE CK R Ax R Ax tCK3 T1 Activate Comma nd Ba nk 0 T0 T2 CA x T4 DAx1 T5 Write Co mman d Bank 0 Clock S usp end 1 Cycle DAx0 T3 T7 T8 DAx2 Clock Suspen d 2 Cycles T6 T9 T11 DAx3 T12 Clock S usp end 3 Cycles T10 T13 T 14 T 16 D Ax5 T15 D Ax7 T 18 D Ax6 T 17 T19 T20 T21 T 22 (Burst length = 8, CAS latency = 3; tRCD = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Clock Suspension / DQM During Burst Write \ 50 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Hi-Z Bank2,3=Idle * BA0=” L” DQ DQM A0 -A9, A11,A12 A10 * BA1 WE CAS RAS CS CKE CK T1 Activate C omm and Bank 0 RAx RAx tCES T0 tSB T2 T4 ACT IVE STAN DBY tCES T3 NOP CAx T6 R ead Com mand Bank 0 T5 T8 Ax1 T9 T10 Cloc k Suspension Start A x0 tCK2 T7 T12 tHZ T 13 Cloc k Suspension End Ax2 T 11 T 15 Prec harge C omm and Bank 0 Ax3 VALID T14 T 16 T17 t SB T 18 T 20 T 22 Any Com mand T 21 NOP PR ECH ARGE STAND BY tCES T19 (Burst length = 4, CAS latency = 2) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Power Down Mode and Clock Suspend \ 51 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Auto Refresh (CBR) T21 T20 T19 REV 1.0 May, 2001 Precharge Command All Banks DQ DQM A0-A9, A11,A12 A10 BS WE CAS RAS CS CKE CK Hi-Z T0 T1 tCK2 tRP T2 T3 Au to Refresh Command T4 T5 T6 tRC T7 T8 T9 T10 Auto Refresh Command T11 T12 T13 tRC T14 T15 T16 T17 T18 (CAS latency = 2) T22 \ 52 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.0 May, 2001 DQ DQM A0-A9, A11,A12 A10 BS WE CAS RAS CS CKE CK All Banks must be idle Hi-Z T0 T2 t SB T3 T4 Power Down Entry Self Refresh Entry t CES T1 tCES Tm Power Down Exit Self Refresh Exit tS RE X tRC Any Command Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Tm+9 T m+10 Tm+11 T m+12 Tm +13 Tm +14 Tm+15 (Note: The CK signal must be reestablished prior to CKE returning high.) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Self Refresh (Entry and Exit) \ 53 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 BA0=” L” Bank2,3=Idle * DQ Ac tiv ate Comm and Bank 1 RBx A0-A9, A11,A12 DQM RBx Hi-Z H igh A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD tCK3 T1 CBx T3 Read Comm and Bank 1 T2 T4 tAC3 T5 Bx0 Bx1 R Ax R Ax T7 Activate Com mand Bank 0 T6 Bx2 T8 Bx3 Bx4 C Ax Bx5 T10 R ead C ommand Bank 0 T9 T 12 Precharge Com mand Bank 1 Bx6 T11 A x0 T 13 Ax1 R By R By T 15 Activate C om mand Bank 1 T14 T16 Ax4 Ax6 T18 Read C ommand Bank 1 Ax5 C By T17 Ax7 T 19 By0 T 21 Prec harge C ommand Bank 0 T20 T22 (Burst length = 8, CAS latency = 3; tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Random Row Read (Interleaving Banks) with Precharge \ 54 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Ac tivate Comm and Bank 1 H i-Z RB x RB x H igh * BA0=” L” B ank2,3 =Idle DQ DQM A0-A9, A11,A12 A10 * BA1 WE CAS RAS CS CKE CK T0 T2 CB x T3 Read w ith Auto Precharge Comm and Bank 1 tRCD tCK3 T1 T4 tAC3 T5 Bx0 T6 Bx1 Bx2 RAAx x R RA x R Ax T8 Activate Com mand Bank 0 T7 Bx3 T9 Bx5 Bx6 R ead with Auto Prec harge C ommand Bank 0 Bx4 T11 T 12 T 13 Bx7 A x0 Start Auto Prec harge Bank 1 CAx T10 T14 Ax1 T17 T18 RB y RB y Ax5 Ax6 Read w ith Auto Precharge Com mand Bank 1 Ax4 T 19 CB y Start Auto Precharge Bank 0 T16 Activ ate Com mand Bank 1 T15 Ax7 T20 T 21 By0 T22 (Burst length = 8,CAS latency = 3; tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Random Row Read (Interleaving Banks) with Auto-Precharge \ 55 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 * BA 0=” L” Bank2,3=Idle DQ Activ ate Com mand Bank 0 R Ax A0-A9, A11,A12 DQM R Ax Hi-Z High A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD tCK3 T1 C AX DAx1 T3 Write with Auto Precharge Com mand Bank 0 D Ax0 T2 T4 T5 D Ax4 T6 R Bx R Bx D Ax6 T8 Activate Com mand Bank 1 DAx5 T7 D Bx0 CBx T10 DBx1 T 11 ‡ W rite with Auto Precharge C omm and Bank 1 DAx7 T9 D Bx4 T 14 RAy RAy T16 Activate C ommand Bank 0 DBx5 T15 T17 DBx6 T18 Bank ma y be reactivated at the comp leti on of tD AL. D Ay1 DAy2 T22 tDAL‡ T 21 CAy D Ay0 T20 W rite with Auto Precharge C ommand Bank 0 D Bx7 T 19 Number of clocks depen ds on clock cycle time and speed sort. See the Clock Freque ncy and Latency table. D Bx2 D Bx3 T 13 tDAL‡ T12 (Burst length = 8, CAS latency = 3; tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Random Row Write (Interleaving Banks) with Auto-Precharge \ 56 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Hi -Z RAx RAx High Activate Command * BA0=” L” Bank 0 Bank2,3=Idle DQ DQM A0-A9, A11,A12 A10 * BA1 WE CAS RAS CS CKE CK T0 tRCD tCK3 T1 CAX D Ax1 T3 Write Command Bank 0 D Ax0 T2 T4 T5 DA x4 T6 R Bx R Bx DAx6 T8 Activate Comma nd Bank 1 DAx5 T7 DAx7 T9 DB x1 T11 Write Command Bank 1 D Bx0 C Bx T10 DB x3 T13 Precharge Command Bank 0 DB x2 T12 D Bx4 tRP T14 T16 Activate Command Bank 0 D Bx5 RAy RAy T15 T17 D Bx6 T18 D Bx7 T19 DAy2 Write Command Bank 0 P recharge Command Bank 1 DAy0 tDPL T22 D Ay1 T21 CAy T20 (Burst length = 8,CAS latency = 3; tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Random Row Write (Interleaving Banks) with Precharge \ 57 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 H i-Z * BA0 =” L” Bank2,3=Idle DQ DQM A0-A9, A11,A12 A10 * BA1 WE CAS RAS CS CKE CK RA x RA x tCK3 T1 Ac tiv ate Comm and Bank0 T0 T2 CAx T4 Read Com mand Bank 0 T3 T5 T6 Ax0 T7 Ax1 T8 Ax3 T10 D Ay0 T 13 D Ay1 T12 C Ay T11 DAy3 T 14 The Read D ata Write T he Write D ata is Mask ed w ith a Comm and is M asked with a T wo C lock Bank 0 Zero C lock Latenc y Latency Ax2 T9 DA y4 T15 T16 T18 Precharge Com mand Bank 0 T17 T19 T 20 T21 T22 (Burst length = 8, CAS latency = 3; tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Read / Write Cycle \ 58 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 DQ Activate BA0=” L” Command Bank 0 Bank2,3=Idle * R Ax A0-A9, A11,A12 Hi-Z R Ax DQM T1 tCK3 A10 * BA1 WE CAS RAS CS CKE CK T0 t RCD T2 C Ax T4 R Bx R Bx T5 Activate Command Bank 1 Read Comman d Bank 0 T3 Ax0 t AC3 T6 Ax1 CB x T8 Read Command Bank 1 T7 A x2 Ax3 C By Bx0 T10 Read Command Ban k 1 T9 T12 By0 By1 C Ay T13 T1 4 Bz0 T15 Bz1 T16 Read with Read Prechar ge Command A uto Prech arge Comma nd Command Bank 1 Bank 1 B ank 0 B x1 CB z T11 A y0 T17 T19 T20 Ay1 Ay2 Ay3 Start Auto Precharge Bank 0 T18 T21 T22 (Burst length = 4, CAS latency = 3; tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Interleaved Column Read Cycle \ 59 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Activate Command * BA 0=” L” Bank 0 Bank2,3=Idle DQ Hi-Z R Ax A0-A9, A11,A12 DQM R Ax A10 * BA1 WE CAS RAS CS CKE High CK T0 tCK3 T1 CA x R Bx RBx T4 A ctivate Comma nd Bank 1 T3 Read Command Bank 0 T2 T5 Ax1 C Bx T7 Ax2 Read with Auto Precharge Command Bank 1 A x0 T6 T8 Ax3 T9 Bx1 T12 Bx2 Read with Auto Precharge Command Bank 0 B x0 T11 T13 Bx3 T14 RB y R By Activa te Co mmand Bank 1 Ay0 Start Auto Pre charge Ban k 1 C Ay T10 T16 CBy T17 Ay1 Ay3 Read with Auto Precharg e Command Ban k 1 Ay2 Start Auto Precharge Bank 0 T15 T18 T20 T2 1 By0 By1 Star t Auto Precharge Bank 1 T19 (Burst length = 4, CAS latency = 3; tRCD , tRP = 3) T22 NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Auto Precharge after Read Burst \ 60 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Activ ate C ommand Bank 0 H i-Z R Ax R Ax High BA0=” L” Bank2,3=Idle * DQ DQM A0-A9, A11,A12 A10 * BA1 WE CAS RAS CS CKE CK T0 DAx1 T2 Write Command Bank 0 D Ax0 CAx tCK2 T1 R Bx R Bx T4 DAx3 CBx DBx0 T5 T6 DBx1 Write with Activate C ommand Auto Precharge Comm and Bank 1 Bank 1 DAx2 T3 T7 DBx2 T8 DAy0 DAy1 tDAL ‡ CAy T10 RAz RAz D Az0 CAz T17 DAz1 T 18 Write with Activate Command Auto Precharge Comm and Bank 0 Bank 0 D By3 T 16 D By2 T 15 DBy1 tDAL ‡ CBy T14 DBy0 T13 Write with Activate Command Auto Precharge Comm and Bank 1 Bank 1 DAy2 RBy D Ay3 T 12 RBy T 11 ‡ Num ber of cloc ks depends on clock c ycle and speed sort. See the Clock F requenc y and Latency table. Bank may be reac tiv ated at the com pletion of tD AL. Write with Auto Precharge Comm and Bank 0 D Bx3 T9 DAz2 T19 DAz3 T20 T22 tD AL ‡ T21 (Burst length = 4, CAS latency = 2) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Auto Precharge after Write Burst \ 61 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 Activate C ommand Bank 0 H i-Z H i-Z R Av R Av High Bank2,3=Idle * BA0=” L” DQ 8 - DQ 15 DQ 0 - DQ 7 UDQM LDQM A0-A9, A11, A12 A10 * BA1 WE CAS RAS CS CKE CK T0 T2 R ead C ommand Bank 0 CAv tCK2 T1 T3 Av0 Av0 T4 Av1 Av1 T5 Av2 Av2 T6 Av3 Av3 T7 T9 DAw 0 CAw Single Write C omm and Bank 0 DAw0 T8 T 11 Single Write C ommand Bank 0 DAx0 CAx T 10 CAy T13 T 14 Ay0 Ay0 T15 Ay1 T 16 Low er Byte R ead is m ask ed C ommand Upper By te Bank 0 is mas ked T12 A y2 T 17 Ay3 Ay3 T 18 T 20 Single Write Comm and Bank 0 DAz0 DAz0 CAz T19 T22 Low er Byte is mask ed T21 (Burst length = 4, CAS latency = 2) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Burst Read and Single Write Operation \ 62 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. REV 1.0 May, 2001 DQ Hi-Z DQM Low A0-A9, A11 A10, A12 BA0,BA1 WE CAS RAS CS CKE CK T0 T2 Activate Command Bank A RA x RA x tCK3 T1 tRCD T3 T5 Read Command Ba nk A T4 C Ax T6 T7 Ax0 T8 Ax1 T9 Ax2 Ax3 T10 T11 Write Command Bank A DA y2 T14 D Ay1 T13 D Ay0 C Ay T12 T17 T18 Prechar ge Comma nd Bank A tDPL T16 D Ay3 T15 T19 T20 T21 T22 (at 100MHz Burst Length = 4, CAS Latency = 3, tRCD , tRP = 3) NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM CS Function (Only CS signal needs to be asserted at minimum rate) \ 63 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. © NANYA TECHNOLOGY CORP. All rights reserved. NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Package Dimensions (400mil; 54 lead; Thin Small Outline Package) ± 0.13 11.76 ± 0.20 Detail A 10.1 6 ± 0 .13 22.22 Lead #1 Seating Plane 0.10 0.80 Basic 0.35 + 0.10 - 0.05 0.71REF 1.20 Ma x Detail A 0.25 Basic 0.5 Gage Plane ± 0.1 0.05 Min REV 1.0 May, 2001 64 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. ® © Nanya Technology Corporation. All rights reserved. Printed in Taiwan, R.O.C. May 2001 The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C , or other countries, or both. NANYA NANYA logo Other company, product and service names may be trademarks or services maeks of others. NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’s standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should be directed to NTC through a local sales office. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards. NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C. The NANYA TECHNOLOGY CORPORATION home page can be found at http:\\www.nanya.com