AD OP221GP

a
Dual Low Power Operational Amplifier,
Single or Dual Supply
OP221
FEATURES
Excellent TCVos Match, 2 ␮V/ⴗC Max
Low Input Offset Voltage, 150 ␮V Max
Low Supply Current, 550 ␮A Max
Single Supply Operation, 5 V to 30 V
Low Input Offset Voltage Drift, 0.75 ␮V/ⴗC
High Open-Loop Gain, 1500 V/mV Min
High PSRR, 3 ␮V/V
Wide Common-Mode Voltage
Range, V– to within 1.5 V of V+
Pin Compatible with 1458, LM158, LM2904
Available in Die Form
PIN CONNECTIONS
8-Lead SO
(S-Suffix)
8-Lead
HERMETIC DIP
(Z-Suffix)
+IN A 1
8
–IN A
V– 2
7
OUT A
OUT A 1
8
V+
7
OUT B
+IN B 3
6
V+
–IN A 2
–IN B 4
5
OUT B
+IN A 3
6
–IN B
V– 4
5
+IN B
NC = NO CONNECT
NC = NO CONNECT
GENERAL DESCRIPTION
The OP221 is a monolithic dual operational amplifier that can
be used either in single or dual supply operation. The wide
supply voltage range, wide input voltage range, and low supply
current drain of the OP221 make it well-suited for operation
from batteries or unregulated power supplies.
provide high performance in instrumentation amplifier designs.
The individual amplifiers feature very low input offset voltage,
low offset voltage drift, low noise voltage, and low bias current.
They are fully compensated and protected.
Matching between channels is provided on all critical parameters
including input offset voltage, tracking of offset voltage vs. temperature, non-inverting bias currents, and common-mode rejection.
The excellent specifications of the individual amplifiers combined
with the tight matching and temperature tracking between channels
SIMPLIFIED SCHEMATIC
V+
Q11
Q28
Q12
Q3
–IN
Q26
Q4
Q1
OUTPUT
Q2
Q9
+IN
Q27
Q10
Q7
Q4
Q29
Q6
Q5
Q13
NULL*
Q33
V–
*ACCESSIBLE IN CHIP FORM ONLY
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP221–SPECIFICATIONS (Electrical Characteristics at V = ⴞ2.5 V to ⴞ15 V, T = 25ⴗC, unless otherwise noted.)
s
A
.
OP221A/E
Parameter
Symbol
Conditions
Min
Input Offset Voltage VOS
OP221G
Typ
Max
75
Min
Typ
Max
Unit
150
250
500
µV
Input Offset Current Ios
VCM = 0
0.5
3
1.5
7
nA
Input Bias Current
VCM = 0
55
100
70
120
nA
IB
Input Voltage Range IVR
V+ = 5 V, V– = 0 V (Note 2)
VS = ± 15 V
Common-Mode
Rejection Ratio
V+ = –5 V, V– = 0 V
0 V ≤ VCM ≤ 3.5 V
VS = ± 15 V
–15 V ≤ VCM ≤ 13.5 V
CMRR
0/3.5
–15/13.5
100
75
85
95
100
80
90
dB
PSRR
VS = ± 2.5 V to ± 15 V
V– = 0 V, V+ = 5 V to 30 V
Large-Signal
Voltage Gain
Avo
VS = ± 15 V, RL = 10 kΩ
VO = ± 10 V
Output Voltage
Swing
VO
V+ = 5 V, V– = 0 V
RL = 10 kΩ
VS = 15 V, RL = 10 kΩ
RL = 10 kΩ (Note 1)
0.2
SR
Bandwidth
BW
Supply Current
(Both Amplifiers)
ISY
V
90
Power Supply
Rejection Ratio
Slew Rate
0/3.5
–15/13.5
3
6
10
18
32
57
100
180
µV/V
1500
800
V/mV
0.7/4.1
0.8/4
V
± 13.8
± 13.5
03
0.2
600
VS = ± 2.5 V, No Load
VS = ± 15 V, No Load
450
600
550
800
0.3
V/µS
600
kHz
550
850
650
900
µA
NOTES
1
Sample tested.
2
Guaranteed by CMRR test limits.
–2–
REV. A
OP221
(Electrical Characteristics at VS = ⴞ2.5 V to ⴞ15 V, –55ⴗC ≤ TA +125ⴗC for OP221A,
SPECIFICATIONS –25ⴗC ≤ T ≤ +85ⴗC for OP221E, –40ⴗC ≤ T ≤ +85ⴗC for OP221G, unless otherwise noted.)
A
A
.
OP221A/E
Parameter
Symbol
Average Input
Offset Voltage
Input Offset Voltage
Conditions
Min
OP221G
Typ
Max
TCVOS
0.75
VOS
Min
Typ
Max
Unit
1.5
2
3
µV/°C
150
300
400
700
µV
Input Offset Current IOS
VCM = 0
1
5
2
10
nA
Input Bias Current
IB
VCM = 0
55
100
80
140
nA
Input Voltage Range
IVR
V+ = 5 V, V– = 0 V (Note 2)
VS = ± 15 V
Common-Mode
Rejection Ratio
CMRR
V+ = –5 V, V– = 0 V
0 V ≤ VCM ≤ 3.5 V
VS = ± 15 V
–15 V ≤ VCM ≤ 13.5 V
Power Supply
Rejection Ratio
PSRR
VS = ± 2.5 V to ± 15 V
V– = 0 V, V+ = 5 V to 30 V
Large-Signal
Voltage Gain
AVO
VS = ± 15 V, RL = 10 kΩ
VO = ± 10 V
Output Voltage
Swing
VO
Supply Current
(Both Amplifiers)
ISY
V+ = 5 V, V– = 0 V
RL = 10 kΩ
VS = 15 V, RL = 10 kΩ
0/3.2
–15/13.2
0/3.2
–15/13.2
V
85
90
70
80
90
95
75
85
dB
6
10
18
32
57
100
180
320
µV/V
V/mV
1000
600
0.8/3.8
0.9/3.7
± 13.5
13.2
V
VS = ± 2.5 V, No Load
VS = ± 15 V, No Load
500
700
650
900
750
1000
µA
Typ
Max
Unit
250
600
µV
120
nA
10
nA
600
950
NOTES
1
Sample tested.
2
Guaranteed by CMRR test limits.
Matching Characteristics at Vs = ⴞ15 V, TA = 25ⴗC, unless otherwise noted.
.
OP221A/E
Parameter
Symbol
Input Offset
Voltage Match
∆VOS
Conditions
Min
Max
50
200
Average Noninverting
Bias Current
IB +
Noninverting Input
Offset Current
Min
80
IOS+
2
Common-Mode
Rejection Ratio
Match (Note 1)
∆CMRR VCM = –15 V to 13.5 V
Power Supply
Rejection Ratio
Match (Note 1)
∆PSRR
REV. A
OP221G
Typ
5
92
VS = ± 2.5 V to ± 15 V
72
14
–3–
4
dB
140
µV/V
Characteristics at V = ⴞ15 V, –55ⴗC ≤ T ≤ +125ⴗC for OP221A,
OP221–SPECIFICATIONS (Matching
–25ⴗC ≤ T ≤ +85ⴗC for OP221E, –40ⴗC ≤ T ≤ +85ⴗC for OP221G, unless otherwise noted.
s
A
A
A
Grades E and G are sample tested.)
.
OP221A/E
Parameter
Symbol
Input Offset
Voltage Match
∆VOS
Average Noninverting IB+
Bias Current
Conditions
Min
Max
100
400
VCM = 0
Input Offset
Voltage Tracking
IC∆VOS
Noninverting Input
Offset Current
IOS+
OP221G
Typ
Min
Typ
Max
Unit
400
800
µV
140
nA
100
VCM = 0
Common-Mode
Rejection Ratio
Match (Note 1)
∆CMRR VCM = –15 V to 13.2 V
Power Supply
Rejection Ratio
Match (Note 1)
∆PSRR
87
1
2
3
5
µV°C
3
7
6
12
nA
90
72
26
80
140
dB
µV/V
NOTES
1
∆CMRR is 20 log10 VCM/∆CME, where VCM is the voltage applied to both noninverting inputs and ∆CME is the difference in common-mode input-referred error.
2
∆PSRR is: Input-Referred Differential Error
∆VS
Wafer Test Limits at Vs = ⴞ2.5 V to ⴞ15 V, TA = 25ⴗC, unless otherwise noted.
.
OP221N
Limit
Unit
200
µV Max
VCM = 0
3.5
nA Max
IB
VCM = 0
85
nA Max
Input Voltage Range
IVR
V+ = 5 V, V– = 0 V
VS= ± 15 V
0/3.5
–15/13.5
V Min/Max
V Min
Common-Mode
Rejection Ratio
CMRR
V– = 0 V, V+ = 5 V,
0 V ≤ VCM ≤ 3.5 V
VS = ± 15 V
–15 V ≤ VCM ≤ 13.5 V
88
93
Parameter
Symbol
Input Offset Voltage
VOS
Input Offset Current
IOS
Input Bias Current
Conditions
dB Min
Power Supply
Rejection Ratio
PSRR
VS = ± 2.5 V to ± 15 V
V– = 0 V, V+ = 5 V to 30 V
12.5
22.5
V/mV Min
Large-Signal
Voltage Gain
Avo
VS = ± 15 V
RL = 10 kΩ
1500
V/mV Max
Output Voltage Swing
VO
V+ = 5 V, V– = 0 V, RL= 10 kΩ
VS = 15 V, RL = 10 kΩ
0.7/4.1
± 13.8
V Min/Max
V Min
Supply Current
(Both Amplifiers)
ISY
VS = ± 2.5 V, No Load
VS = ± 15 V, No Load
560
810
µA Max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
–4–
REV. A
OP221
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage . . . . . . . . . . 30 V or Supply Voltage
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP221A . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP221E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
OP221G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . . 300°C
Junction Temperature (TJ) . . . . . . . . . . . . . –65°C to +150°C
Package Type
␪JA (Note 2)
␪JC
Unit
8-Lead Hermetic DIP (Z)
148
16
°C/W
8-Lead Plastic DIP (P)
103
43
°C/W
8-Lead SO (S)
158
43
°C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
␪JA is specified for worst case mounting conditions, i.e., ␪JA is specified for device
in socket for TO, Cerdip, and PDIP packages; elA is specified for device soldered
to printed circuit board for SO package.
ORDERING INFORMATION 1,2
TA = +25ⴗC
VOS MAX
(␮V)
150
150
300
500
500
500
Cerdip
8-Lead
Packages
Plastic
8-Lead
OP221AZ3
OP221 EZ3
OP221GP3
OP221GS
Operating
Temperature
Range
Package
Options
MIL
IND
Q-8
XIND
XIND
R-8
1
Burn-in is available on commercial and industrial temperature range parts in CerDIP, plastic DIP, and
TO-can packages.
2
For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory
for 883 data sheet.
3
Not for new design, obsolete April 2002.
Figure 1. Dice Characteristics
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP221 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–5–
WARNING!
ESD SENSITIVE DEVICE
Typical Perfomance Characteristics – OP221
140
140
140
dc
dc
120
100Hz
80
1kHz
60
40
VS = ⴞ15V
100Hz
80
1kHz
60
40
VS = ⴞ15V
–25
0
25
50
75
100
80
60
40
20
0
–50
125
TA = 25ⴗC
RL = 15k⍀
100
20
20
0
–50
10Hz
100
–25
0
25
50
75
100
0
125
ⴞ5
0
TEMPERATURE – ⴗC
TEMPERATURE – ⴗC
TPC 1. Open-Loop Gain at ± 15 V vs.
Temperature
ⴞ10
ⴞ15
SUPPLY VOLTAGE – V
TPC 2. Open-Loop Gain at ± 5 V vs.
Temperature
TPC 3. Open-Loop Gain at vs.
Supply Voltage
70
25
60
20
80
CLOSED-LOOP GAIN – dB
100
80
VS = ⴞ15V
60
VS = ⴞ5V
40
20
50
VOLTAGE GAIN – dB
OPEN-LOOP GAIN – dB
120
40
30
20
10
0
TA = 25ⴗC
VS = ⴞ15V
100
120
15
⵰m = 42ⴗ
140
10
160
5
GAIN
PHASE
0
180
–5
200
PHASE SHIFT – Degrees
10Hz
100
120
OPEN-LOOP GAIN – dB
OPEN-LOOP GAIN – dB
OPEN-LOOP GAIN – dB
120
0
–10
1
10
1k
10k
100k
220
–10
100k
1M 10M
TPC 5. Closed-Loop Gain vs.
Frequency
1M
FREQUENCY – Hz
120
850k
40
GAIN BANDWIDTH
800k
750k
650k
100
TA = 25ⴗC
VS = ⴞ15V
100
+PSRR
80
80
CMRR – Hz
PHASE MARGIN
45
10M
TPC 6. Gain and Phase Shift vs.
Frequency
VS = ⴞ15V
50
700k
SLEW RATE –
V/␮sec
100
120
55
60
–PSRR
60
40
40
SLEW RATE
0.30
20
0.25
0.20
–50
10
FREQUENCY – Hz
PSRR – dB
PHASE MARGIN –
Degrees
TPC 4. Open-Loop Gain at ± 15 V vs.
Frequency
0.35
1
100 1k 10k 100k 1M 10M
FREQUENCY – Hz
GAIN BANDWIDTH – Hz
0.1
–25
0
25
50
75
100
125
TEMPERATURE – ⴗC
TPC 7. Phase Margin, Gain Bandwidth,
and Slew Rate vs. Temperature
0
10
TA = 25ⴗC
VS = ⴞ15V
20
0
100
1k
10k
FREQUENCY – Hz
TPC 8. PSRR vs. Frequency
–6–
100k
1
10
100
1k
10k
100k
FREQUENCY – Hz
TPC 9. CMRR vs. Frequency
REV. A
OP221
16
28
24
20
16
12
8
2.0
12
POSITIVE
10
NEGATIVE
8
6
4
TA = 25ⴗC
VS = ⴞ2.5V
NEGATIVE
POSITIVE
1.0
2
4
0
100
0
1K
10k
100k
FREQUENCY – Hz
1M
TPC 10. Maximum Output Swing
vs. Frequency
1k
10k
LOAD RESISTANCE – ⍀
100k
10
CURRENT NOISE – pA Hz
80
70
60
50
40
30
20
10
1.0
0.1
1
10
100
1k
FREQUENCY – Hz
TPC 13. Voltage Noise Density vs.
Frequency
REV. A
1
10
100
1k
FREQUENCY – Hz
TPC 13. Current Noise Density vs.
Frequency
–7–
0
100
1k
10k
100k
LOAD RESISTANCE – ⍀
TPC 11. Maximum Output Voltage
vs. Load Resistance
100
VOLTAGE NOISE – nV/ Hz
TA = 25ⴗC
VS = ⴞ15V
14
MAXIMUM OUTPUT – V
TA = 25ⴗC
VS = ⴞ15V
RL = 10k⍀
MAXIMUM OUTPUT – V
PEAK-TO-PEAK AMPLITUTDE – V
30
TPC 12. Maximum Output Voltage
vs. Load Resistance
OP221
Figure 2a. Noninverting Step Response
Figure 3a. Inverting Step Response
Figure 2b. Noninverting Step Response
Figure 3b. Inverting Step Response
INPUT
10k⍀
OUTPUT
INPUT
10k⍀
10k⍀
OUTPUT
Figure 4. TBD.
Figure 5. TBD.
–8–
REV. A
OP221
SPECIAL NOTES ON THE APPLICATION OF DUAL
MATCHED OPERATIONAL AMPLIFIERS
Advantages of Dual Monolithic Operational Amplifiers
Dual matched operational amplifiers provide the engineer with a
powerful tool for designing instrumentation amplifiers and many
other differential-input circuits. These designs are based on the
principle that careful matching between two operational amplifiers
can minimize the effect of dc errors in the individual amplifiers.
Reference to the circuit shown in Figure 6, a differential-in,
differential-out amplifier, shows how the reductions in error can
be accomplished. Assuming the resistors used are ideally matched,
the gain of each side will be identical. If the offset voltages of
each amplifier are perfectly matched, then the net differential
voltage at the amplifier’s output will be zero. Note that the output
offset error of this amplifier is not a function of the offset voltage
of the individual amplifiers, but only a function of the difference
(degree of matching) between the amplifiers’ offset voltages. This
error-cancellation principle holds for a considerable number of
input referred error parameters—offset voltage, offset voltage
drift, inverting and noninverting bias currents, common mode
and power supply rejection ratios. Note also that the impedances
of each input, both common-mode and differential-mode, are
high and tightly matched, an important feature not practical with
single operation amplifier circuits.
INSTRUMENTATION AMPLIFIER APPLICATIONS
Two-Op Amp Configuration
The two-op amp circuit (Figure 7) is recommended where the
common-mode input voltage range is relatively limited; the
common-mode and differential voltage both appear at V1. The
high open-loop gain of the OP221 is very important in achieving
good CMRR in this configuration. Finite open-loop gain of A1
(Ao1) causes undesired feedthrough of the common-mode input.
For Ad/Ao, << 1, the common-mode error (CME) at the output due to this effect is approximately (2 Ad/Ao1) x VCM. This
circuit features independent adjustment of CMRR and differential gain.
Three-Op Amp Configuration
The three-op amp circuit (Figure 8) has increased commonmode voltage range because the common-mode voltage is not
amplified as it is in Figure 7. The CMR of this amplifier is directly
proportional to the match of the CMR of the input op amps. CMRR
can be raised even further by trimming the output stage resistors.
R0
GAIN
ADJ
R2
R1
AD = 2 1+ R1
R0
1/2
OP221
R3
R4
V1
A1
VCM – 1/2VD
–
1/2
R3
OP221
Vd
R1
+
OP221
INPUT
VCM + 1/2VD
+
R4
VO = R3
OUTPUT
1+1
2
R2 + R3
R1 R4
–
R2
SIDE
‘R’
VO – ADVD
A2
+
SIDE
‘A’
+
R2 + R3
R0
Vd + R4
R3
R3 – R2
R4 R1
IF R1 = R2 = R3 = R4, THEN VO = 2 1 + R1 VD
R0
–
Figure 7. Two-Op Amp Circuit
R4
R1
Figure 6. Differential-In, Differential-Out Amplifier
VO = 2 1 +
A1
1/2
–
R0
V1
VD
V+
OP221
OP221
A3
R1
Vd
2R1
R0
R2
R2
VCM – 1/2VD
V+
R2
–
VCM + 1/2VD
A2
1/2
V–
V2
OP221
R2
V–
Figure 8. Three-Op Amp Circuit
REV. A
VCM
–9–
VO
OP221
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead CERDIP Package
(Q-8)
0.005 (0.13)
MIN
0.055 (1.4)
MAX
8
5
0.310 (7.87)
0.220 (5.59)
PIN 1
1
4
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
SEATING
0.023 (0.58) 0.070 (1.78) PLANE
0.014 (0.36) 0.030 (0.76)
15
0
0.015 (0.38)
0.008 (0.20)
8-Lead SOIC Package
(R-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.102 (2.59)
0.094 (2.39)
8ⴗ
0.0098 (0.25) 0ⴗ 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
–10–
REV. A
OP221
Revision History
Location
Page
09/01—Data Sheet changed from REV. 0 to REV. A.
Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Global deletion of references to OP221B and OP221C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 4
Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. A
–11–
–12–
PRINTED IN U.S.A.
C00324–0–1/02(A)