PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 FEATURES • • • • • • • • • Expandable Five-Channel Bidirectional Buffer 400-kHz Fast I2C Bus Operating VCC Range of 3 V to 3.6 V 5-V Tolerant I2C and Enable Input Pins to Support Mixed-Mode Signal Operation Active-High Individual Repeater Enable Inputs Open-Drain Input/Outputs Lockup-Free Operation Supports Arbitration and Clock Stretching Across the Repeater Supports Multiple Masters • • • • Powered-Off High-Impedance I2C Pins I2C Bus and SMBus Compatible Latchup Performance Exceeds 100 mA Per JESD 78 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DB, DBQ, DW, OR PW PACKAGE (TOP VIEW) EXPSCL1 EXPSCL2 SCL0 SDA0 SCL1 SDA1 EN1 SCL2 SDA2 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC EXPSDA2 EXPSDA1 EN4 SDA4 SCL4 EN3 SDA3 SCL3 EN2 DESCRIPTION/ORDERING INFORMATION The PCA9518 is an expandable five-channel bidirectional buffer for I2C and SMBus applications. The I2C protocol requires a maximum bus capacitance of 400 pF, which is derived from the number of devices on the I2C bus and the bus length. The PCA9518 overcomes this restriction by separating and buffering the I2C data (SDA) and clock (SCL) lines into multiple groups of 400-pF segments. Any segment-to-segment transition sees only one repeater delay. Each PCA9518 can communicate with other PCA9518 hubs through a 4-wire inter-hub expansion bus. Using multiple PCA9518 parts, any width hub (in multiples of five) can be implemented using the expansion pins, with only one repeater delay and no functional degradation of the system performance. ORDERING INFORMATION PACKAGE (1) (2) TA –40°C to 85°C (2) TOP-SIDE MARKING Reel of 2000 PCA9518DBR PD518 QSOP – DBQ Reel of 2500 PCA9518DBQR PCA9518 Tube of 25 PCA9518DW Reel of 2000 PCA9518DWR Tube of 70 PCA9518PW Reel of 2000 PCA9518PWR SOIC – DW TSSOP – PW (1) ORDERABLE PART NUMBER SSOP – DB PCA9518 PD518 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 DESCRIPTION (CONTINUED) The device is designed for 3-V to 3.6-V VCC operation, but it has 5-V tolerant I2C and enable (EN) input pins. This feature allows for translation from 3 V to 5 V between a master and slave. The enable pin also can be used to electrically isolate a repeater segment from the I2C bus. This is useful in cases where one segment needs to run at 100 kHz while the rest of the system is at 400 kHz. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz, because of the delays added by the repeater. The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lockup condition from occurring when the input low condition is released. A PCA9518 cluster cannot be put in series with a repeater such as the PCA9515 or another PCA9518 cluster, as the design does not allow this configuration. Multiple PCA9518 devices can be grouped with other PCA9518 devices into any size cluster using the EXPxxxx pins that allow the I2C signals to be sent or received from one PCA9518 to another PCA9518 within the cluster. Because there is no direction pin, slightly different valid low voltage levels are used to avoid lockup conditions between the input and the output of individual repeaters in the cluster. A valid low applied at the input of any of the PCA9518 devices is propagated as a buffered low, with a slightly higher value, to all enabled outputs in the PCA9518 cluster. When this buffered low is applied to another repeater or separate PCA9518 cluster (not connected via the EXPxxxx pins) in series, the second repeater or PCA9518 cluster does not recognize it as a regular low and does not propagate it as a buffered low again. For this reason, the PCA9518 should not be put in series with other repeater or PCA9518 clusters. The PCA9518 has five multidirectional open-drain buffers designed to support the standard low-level-contention arbitration of the I2C bus. Except during arbitration or clock stretching, the PCA9518 acts like a pair of noninverting open-drain buffers, one for SDA and one for SCL. There is an internal power-on-reset circuit (VPOR) that allows for an initial condition and the ramping of VCC to set the internal logic. As with the standard I2C system, pullup resistors are required on each SDAn and SCLn to provide the logic high levels on the buffered bus. The size of these pullup resistors depends on the system, but it is essential that each side of the repeater have a pullup resistor. The device is designed to work with standard-mode and fast-mode I2C devices in addition to SMBus devices. Standard-mode I2C devices only specify 3 mA in a generic I2C system where standard-mode devices and multiple masters are possible. 2 Submit Documentation Feedback PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 TERMINAL FUNCTIONS SOIC, SSOP, TSSOP, OR QSOP PIN NO. NAME 1 EXPSCL1 Expandable serial clock pin 1. Connect to VCC through a pullup resistor. 2 EXPSCL2 Expandable serial clock pin 2. Connect to VCC through a pullup resistor. DESCRIPTION 3 SCL0 Serial clock bus 0. Connect to VCC through a pullup resistor. 4 SDA0 Serial data bus 0. Connect to VCC through a pullup resistor. 5 SCL1 Serial clock bus 1. Connect to VCC through a pullup resistor. 6 SDA1 Serial data bus 1. Connect to VCC through a pullup resistor. 7 EN1 Active-high bus enable 1 8 SCL2 Serial clock bus 2. Connect to VCC through a pullup resistor. 9 SDA2 Serial data bus 2. Connect to VCC through a pullup resistor. 10 GND Ground 11 EN2 Active-high bus enable 2 12 SCL3 Serial clock bus 3. Connect to VCC through a pullup resistor. 13 SDA3 Serial data bus 3. Connect to VCC through a pullup resistor. 14 EN3 Active-high bus enable 3 15 SCL4 Serial clock bus 4. Connect to VCC through a pullup resistor. 16 SDA4 Serial data bus 4. Connect to VCC through a pullup resistor. 17 EN4 18 EXPSDA1 Expandable serial data pin 1. Connect to VCC through a pullup resistor. 19 EXPSDA2 Expandable serial data pin 2. Connect to VCC through a pullup resistor. 20 VCC Active-high bus enable 4 Supply voltage FUNCTION TABLE (1) (2) (3) INPUTS EN1 EN2 EN3 L L L L L FUNCTION EN4 SCL1 SCL2 SCL3 SCL4 SDA1 SDA2 SDA3 SDA4 L L Disconnect Disconnect Disconnect Disconnect Disconnect Disconnect Disconnect Disconnect L H Disconnect Disconnect Disconnect SCL0 Disconnect Disconnect Disconnect SDA0 L H L Disconnect Disconnect SCL0 Disconnect Disconnect Disconnect SDA0 Disconnect L L H H Disconnect Disconnect SCL0 SCL0 Disconnect Disconnect SDA0 SDA0 L H L L Disconnect SCL0 Disconnect Disconnect Disconnect SDA0 Disconnect Disconnect L H L H Disconnect SCL0 Disconnect SCL0 Disconnect SDA0 Disconnect SDA0 L H H L Disconnect SCL0 SCL0 Disconnect Disconnect SDA0 SDA0 Disconnect L H H H Disconnect SCL0 SCL0 SCL0 Disconnect SDA0 SDA0 SDA0 H L L L SCL0 Disconnect Disconnect Disconnect SDA0 Disconnect Disconnect Disconnect H L L H SCL0 Disconnect Disconnect SCL0 SDA0 Disconnect Disconnect SDA0 H L H L SCL0 Disconnect SCL0 Disconnect SDA0 Disconnect SDA0 Disconnect H L H H SCL0 Disconnect SCL0 SCL0 SDA0 Disconnect SDA0 SDA0 H H L L SCL0 SCL0 Disconnect Disconnect SDA0 SDA0 Disconnect Disconnect H H L H SCL0 SCL0 Disconnect SCL0 SDA0 SDA0 Disconnect SDA0 H H H L SCL0 SCL0 SCL0 Disconnect SDA0 SDA0 SDA0 Disconnect H H H H SCL0 SCL0 SCL0 SCL0 SDA0 SDA0 SDA0 SDA0 (1) (2) (3) SCL from master = SCL0 SDA from master = SDA0 See Description and Application Information for information on EXPxxx1 and EXPxxx2 behavior. Submit Documentation Feedback 3 PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 FUNCTIONAL BLOCK DIAGRAM VCC PCA9518 EXPSCL1 EXPSCL2 SCL0 Buffer SCL1 Buffer SCL2 Buffer Buffer SCL4 Buffer SCL3 Buffer SDA4 Buffer SDA3 Hub Logic EXPSDA1 EXPSDA2 SDA0 SDA1 SDA2 Buffer Hub Logic Buffer Buffer EN1 EN4 EN2 EN3 GND A more detailed view of each buffer in the functional block diagram is shown in Figure 1. To Output Data z In Inc Enable Figure 1. Buffer Details 4 Submit Documentation Feedback www.ti.com PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB SCPS132A – JUNE 2006 – REVISED JULY 2007 Enable EN1–EN4 are active-high enable pins and have internal pullup resistors. Each enable pin, ENn, controls its associated SDAn and SCLn ports. When ENn is low, it isolates its corresponding SDAn and SCLn from the system by blocking the inputs from SDAn and SCLn and disabling the output drivers on the SDAn and SCLn pins. It is essential that the ENn change state only when both the global bus and the local port are in an idle state to prevent system failures. EN1–EN4 also allow the use of open-drain drivers that can be wire-ORed to create a distributed enable where either centralized control signal (master) or spoke signal (submaster) can enable the channel when it is idle. Expansion The PCA9518 has four open-drain I/O pins used for expansion. The internal state of the serial data within each hub is communicated to other hubs through two expansion pins, EXPSDA1 and EXPSDA2. The EXPSDA1 pins of all hubs are connected together to form an open-drain bus. Similarly, all EXPSDA2 pins, EXPSCL1 pins, and EXPSCL2 pins are connected together, forming a 4-wire bus between hubs. When it is necessary to be able to deselect every port, each expansion device contributes only four ports that can be enabled or disabled; the fifth port does not have an enable pin. Pullup resistors are required on the EXPxxxx pins, even if only one PCA9518 is used. Submit Documentation Feedback 5 PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Enable input voltage range (2) –0.5 7 V 2 –0.5 VI/O I C bus voltage range IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) Tstg Storage temperature range DB package 63 DBQ package 61 DW package 46 PW package (1) (2) (3) 7 UNIT V °C/W 88 –55 125 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions VCC Supply voltage SCL, SDA VIH High-level input voltage EN VILc (1) Low-level input voltage contention TA Operating free-air temperature (1) 6 Low-level input voltage NOM MAX 3 3.3 3.6 0.7 × VCC 5.5 UNIT V 2 5.5 0.55 × VCC 5.5 SCL, SDA –0.5 0.3 × VCC EN –0.5 0.8 EXPSDA, EXPSCL –0.5 0.45 × VCC SCL, SDA –0.5 0.4 V –40 85 °C EXPSDA, EXPSCL VIL (1) MIN VIL specification is for the first low level seen by SDA/SCL. VILc is for the second and subsequent low levels seen by SDA/SCL. VILc must be at least 70 mV below VOL. Submit Documentation Feedback V V PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 Electrical Characteristics over recommended operating free-air temperature range, VCC = 3 V to 3.6 V, GND = 0 V (unless otherwise noted) PARAMETER VIK VOL VOL – VILc MAX UNIT –1.2 V SCLn, SDAn IOL = 0 (2) or 6 mA 3 V to 3.6 V EXPSCL, EXPSDA IOL = 12 mA 3 V to 3.6 V 0.5 Low-level input voltage below low-level output voltage SCL, SDA 3 V to 3.6 V 70 0.52 ±1 3 V to 3.6 V VI = 0.2 V (input current LOW) SDAn = SCLn = VCC, EXPSCLn = EXPSDAn = VCC Quiescent supply current, Both channels low One SDA and one SCL are at GND, while other SDA and SCL are open. Quiescent supply current, In contention SDAn = SCLn = GND, EXPSCLn = EXPSDAn = VCC Ioff SDAx, SCLx power-off condition with static VCC VI = 3.6 V II(ramp) SDAx, SCLx power-off condition with VCC ramping up or down VI = 3.6 V, V mV 1 VI = VCC VI = GND 0.7 ±1 VI = 0.2 V VI = 0.2 V 10 μA 20 2 3.6 V EN = L or H 0V EN = L or H 0 V to 3 V SCLn, SDAn EN1, EN2, EN3, EN4 0.45 VI = 3.6 V Quiescent supply current, Both channels high VI = 3 V or GND EXPSCL, EXPSDA (1) (2) TYP (1) 3 V to 3.6 V EXPSCL, EXPSDA CI MIN II = –18 mA EN1, EN2, EN3, EN4 ICC VCC Input diode clamp voltage SCLn, SDAn II TEST CONDITIONS 3 V to 3.6 V 1.75 6 2.5 9 9 11 1 1 1 8 9.5 3 7 6 8 mA μA μA pF All typical values are at 3.3-V supply voltage and TA = 25°C. Test performed with IOL = 10 μA Submit Documentation Feedback 7 PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 Switching Characteristics over operating free-air temperature range (unless otherwise noted) (see Figure 2) (1) PARAMETER tPHLs (2) tPLHs (3) tPHLE1s Propagation delay tPLHE1s tPLHE2s tTHLs tTLHs (1) (2) (3) Output transition time, SDAn, SCLn FROM (INPUT) TO (OUTPUT) SDA or SCL SDAn or SCLn MIN TYP MAX UNIT 105 202 389 ns 105 259 265 ns 109 193 327 ns 120 153 200 ns EXPSDA1 or EXPSCL1 SDA or SCL EXPSDA2 or EXPSCL2 SDA or SCL 120 234 279 ns 70% 30% 48 110 187 ns 30% 70% 0.85RC ns The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times mostly are internally controlled and are sensitive only to load capacitance. The rise times are RC time-constant controlled and, therefore, a specific numerical value can be given only for fixed RC time constants. The SDA high-to-low propagation delay, tPHLs, includes the fall time from VCC to 0.5 VCC of EXPSDA1 or EXPSCL1 and the SDA or SCL fall time from the quiescent high (usually VCC) to below 0.3 VCC. The SDA and SCL outputs have edge-rate-control circuits included that make the fall time almost independent of load capacitance. The SDA or SCL low-to-high propagation delay, tPLHs, includes the rise-time constant from the quiescent low to 0.5 VCC for EXPSDA1 or EXPSCL2, the rise-time constant for the quiescent low to 0.5 VCC for EXPSDA1 or EXPSCL1, and the rise time constant from the quiescent externally driven low to 0.7 VCC for SDA or SCL. Timing Requirements over operating free-air temperature range (unless otherwise noted) PARAMETER 8 MIN MAX UNIT tsu Setup time, EN↑ before Start condition 300 ns th Hold time, EN↓ after Stop condition 300 ns Submit Documentation Feedback PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION VCC VIN RL (see Note B) VOUT PULSE GENERATOR VCC S1 DUT GND CL (see Note C) RT (see Note A) TEST CIRCUIT FOR OPEN-DRAIN OUTPUT tTHLs S1 VCC tTLHs 0.7 VCC Input SDA 0.7 V CC or SCL 0.3 V CC 0.4 V 0.3 VCC 0.4 V tPHLs EXPSDA1 or EXPSCL1 TEST tPLH/tPHL Effective Stretch 0.5 V CC 0.5 VCC tPLHs EXPSDA2 or EXPSCL2 0.5 V CC tPHLE1s Output SDA or SCL 0.5 VCC tPLHE1s tPLHE2s tTHLs tTLHs 0.7 VCC 0.52 V 0.7 VCC 0.3 VCC 0.3 VCC VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES A. Termination resistance, RT, should be equal to the ZOUT of the pulse generators. B. Load resistor, RL = 1.1 kΩ for I2C and 500 Ω for EXP C. Load capacitance, CL, includes jig and probe capacitance; 100 pF for I2C and EXP. D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. E. The outputs are measured one at a time, with one transition per measurement. Figure 2. Test Circuit and Voltage Waveforms Submit Documentation Feedback 9 PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 APPLICATION INFORMATION Figure 3 shows an application in which the PCA9518 can be used. 3.3 V 5V 5V VCC SDA SCL SUBSYSTEM 5 3.3 V 100 kHz VCC EXPSCL1 SDA2 SCL2 SCL SUBSYSTEM 6 SDA0 3.3 V or 5 V 400 kHz SCL0 SDA SDA0 SCL SCL0 BUS MASTER 400 kHz 3.3 V or 5 V Disabled Not Connected SCL4 SDA2 SDA SCL2 SCL 5V SUBSYSTEM 2 400 kHz SDA3 SDA SCL3 SCL 3.3 V EN1 EN2 EN3 EN4 EN1 SDA4 3.3 V SUBSYSTEM 1 400 kHz PCA9518 DEVICE 1 PCA9518 DEVICE 2 SDA3 SCL3 SCL EXPSCL2 EXPSCL2 SDA SDA SDA1 EXPSCL1 SCL1 EXPSDA2 EXPSCL1 SDA1 EXPSDA2 SCL1 EXPSCL1 EN2 EN3 EN4 GND GND SUBSYSTEM 3 100 kHz SDA4 SDA SCL4 SCL SUBSYSTEM 4 100 kHz A. Only two of the five channels of the PCA9518 device 2 are being used. EN3 and EN4 are connected to GND to disable channels 3 and 4, or SDA3/SCL3 and SDA4/SCL4 are pulled up to VCC. SDA0 and SCL0 can be used as a normal I2C port, but they must be pulled up to VCC if unused, because there is no enable pin. Figure 3. Multiple Expandable Five-Channel I2C Hubs Here, the system master is running on a 3.3-V I2C bus, while the slaves are connected to a 3.3-V or 5-V bus. The PCA9518 is 5-V tolerant, so it does not require any additional circuitry to translate between the different bus voltages. All buses run at 100 kHz, unless slaves 3, 4, and 5 are isolated from the bus. If the master bus and slaves 1, 2, and 6 need to run at 400 kHz, slaves 3, 4, and 5 can be isolated through the bus master. In this case, the bus master will change the state on the corresponding EN pin (for slaves 3, 4, and 5) to low. Any segment of the hub can talk to any other segment of the hub. Bus masters and slaves can be located on any segment with 400-pF load allowed on each segment. When one port of the PCA9518 is pulled low by a device on the I2C bus, a CMOS hysteresis-type input detects the falling edge and drives the EXPxxx1 line low; when the EXPxxx1 voltage is less than 0.5-V VCC, the other ports are pulled down to the VOL of the PCA9518, which is typically 0.5 V. 10 Submit Documentation Feedback PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 APPLICATION INFORMATION (continued) If the bus master in Figure 3 were to write to the slave through the PCA9518, the waveform shown in Figure 4 would be created. 9th Clock Cycle 9th Clock Cycle VOL of PCA9518 VOL of Master SCL of Master BUS 0 tst SDA of Master EXPSDA1 tf1 tr1 tER1 EXPSDA2 EXPANSION BUS tf2 tr2 EXPSCL1 EXPSCL2 SCL of Slave BUS 1 SDA of Slave tPLH tPLH of Slave VOL VOL OF PCA9518 BUS n with n > 1 Figure 4. Bus Waveforms Note that any arbitration or clock-stretching events on bus 1 require that the VOL of the devices on bus 1 be 70 mV below the VOL of the PCA9518 (see VOL – VILc in electrical characteristics) to be recognized by the PCA9518 and transmitted to bus 0. This looks like a normal I2C transmission, except for the small step preceding each clock low-to-high transition and proceeding each data low-to-high transition for the master. The step height is the difference between the low level driven by the master and the higher-voltage low level driven by the PCA9518 repeater. Its width corresponds to an effective clock stretching coming from the PCA9518, which delays the rising edge of the clock. That same magnitude of delay is seen on the rising edge of the data. The step on the rising edge of the data is extended through the ninth clock pulse as the PCA9518 repeats the acknowledge from the slave to the master. The clock of the slave looks normal, except that the VOL is the 0.5-V level generated by the PCA9518. The SDA at the slave has a particularly interesting shape during the ninth clock cycle, when the slave pulls the line below the value driven by the PCA9518 during the ACK and then returns to the PCA9518 level, creating a foot before it completes the low-to-high transition. SDA lines, other than the one with the master and the one with the slave, have a uniform low level driven by the PCA9518 repeater. Submit Documentation Feedback 11 PCA9518 EXPANDABLE FIVE-CHANNEL I2C HUB www.ti.com SCPS132A – JUNE 2006 – REVISED JULY 2007 APPLICATION INFORMATION (continued) The expansion bus signals shown in Figure 4 are included primarily for timing reference points. All timing on the expansion bus is with respect to 0.5 VCC. EXPSDA1 is driven low whenever any SDA pin falls below 0.3-V VCC and EXPSDA2 is driven low when any pin is ≤0.4 V. EXPSCL1 is driven LOW whenever any SCL pin falls below 0.3-V VCC and EXPSCL2 is driven LOW when any SCL pin is ≤0.4 V. EXPSDA2 returns high after the SDA pin that was the last one being held below 0.4 V by an external driver starts to rise. The last SDA to rise above 0.4 V is held down by the PCA9518 to 0.5 V until after the delay of the circuit that determines that it was the last to rise; then, it is allowed to rise above the 0.5-V level driven by the PCA9518. Considering the bus 0 SDA to be the last one to go above 0.4 V, then EXPSDA1 returns to high after EXPSDA2 is high and either bus 0 SDA rise time is 1 μs or bus 0 SDA reaches 0.7-V VCC, whichever occurs first. After both EXPSDA2 and EXPSDA1 are high, the rest of the SDA lines are allowed to rise. The same description applies to the EXPSCL1, EXPSCL2, and SCL pins. Any arbitration or clock stretching events on bus 1 requires that the VOL of the devices on bus 1 be 70 mV below the VOL of the PCA9518 (see VOL – VILc in electrical characteristics) to be recognized by the PCA9518 and then transmitted to bus 0. 12 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCA9518DBQR ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PCA9518DBQRG4 ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PCA9518DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DBT ACTIVE SSOP DB 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DBTG4 ACTIVE SSOP DB 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DWT ACTIVE SOIC DW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518DWTG4 ACTIVE SOIC DW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9518PWT ACTIVE TSSOP PW 20 250 CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2007 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing PCA9518DBQR SSOP/ QSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) DBQ 20 2500 330.0 16.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.5 9.0 2.1 8.0 16.0 Q1 PCA9518DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 PCA9518DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PCA9518PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCA9518PWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9518DBQR SSOP/QSOP DBQ 20 2500 346.0 346.0 33.0 PCA9518DBR SSOP DB 20 2000 346.0 346.0 33.0 PCA9518DWR SOIC DW 20 2000 346.0 346.0 41.0 PCA9518PWR TSSOP PW 20 2000 346.0 346.0 33.0 PCA9518PWT TSSOP PW 20 250 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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