PCA9525 Simple 2-wire bus buffer Rev. 1 — 25 February 2011 Product data sheet 1. General description The PCA9525 is a monolithic CMOS integrated circuit for bus buffering in applications including I2C-bus, SMBus, DDC, PMBus, and other systems based on similar principles. The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing the maximum permissible bus capacitance on both sides of the buffer. The PCA9525 includes a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. Slave devices which employ clock stretching are therefore not supported. In its most basic implementation, the buffer will allow an extended number of slave devices to be attached to one (or more) master devices. In this case, all master devices would be positioned on the Sxx_IN side of the PCA9525. The direction pin (DIR) further enhances this function by allowing the unidirectional clock signal to be reversed, thus allowing master devices on both sides of the buffer. The enable (EN) function allows sections of the bus to be isolated. Individual parts of the system can be brought on-line successively. This means a controlled start-up using a diverse range of components, operating speeds and loads is easily achieved. 2. Features and benefits Simple impedance isolating buffer for 2-wire buses 4 mA maximum static open-drain pull-down capability supports a wide range of bus standards Works with I2C-bus (Standard-mode, Fast-mode), SMBus (standard and high power mode), and PMBus Fast switching times allow operation in excess of 1 MHz Enable allows bus segments to be disconnected Hysteresis on inputs provides noise immunity Operating voltages from 2.7 V to 5.5 V Very low supply current Uncomplicated characteristics suitable for quick implementation in most common 2-wire bus applications PCA9525 NXP Semiconductors Simple 2-wire bus buffer 3. Applications Electronic signs and displays Game consoles/boxes Gaming machine networks TV/projector/monitor interconnection (DDC) Power management systems Desktop and portable computers Security systems 4. Ordering information Table 1. Ordering information Type number Topside mark Package Name Description Version PCA9525D PCA9525 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCA9525DP 9525 TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 5. Block diagram 2.7 V to 5.5 V VDD R1 enable SDA SCL direction R2 R3 8 EN 1 R4 PCA9525 SDA_IN 6 7 SDA_OUT SCL_IN 3 2 SCL_OUT SDA SCL DIR 5 4 VSS 002aaf329 Fig 1. PCA9525 Product data sheet Block diagram of PCA9525 All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 2 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 6. Pinning information 6.1 Pinning EN 1 8 VDD SCL_OUT 2 7 SDA_OUT SCL_IN 3 6 SDA_IN VSS 4 5 DIR PCA9525D EN 1 8 VDD SCL_OUT 2 7 SDA_OUT SCL_IN 3 VSS 4 PCA9525DP SDA_IN 5 DIR 002aaf331 002aaf330 Fig 2. 6 Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8 6.2 Pin description Table 2. Pin description Symbol Pin Description EN 1 enable SCL_OUT 2 clock buffer, slave side SCL_IN 3 clock buffer, master side VSS 4 supply ground DIR 5 clock direction SDA_IN 6 data buffer, master side SDA_OUT 7 data buffer, slave side VDD 8 positive supply 7. Functional description Refer to Figure 1 “Block diagram of PCA9525”. 7.1 VDD, VSS — supply pins The power supply voltage for the PCA9525 may be any voltage in the range 2.7 V to 5.5 V. The IC supply must be common with the supply for the bus. Hysteresis on the ports is a percentage of the IC’s power supply, hence noise margin considerations should be taken into account when selecting an operating voltage. 7.2 SCL_IN, SCL_OUT — clock signal inputs/outputs The clock signal buffer is unidirectional, although the direction may be reversed under control of the direction pin (DIR). In normal bus operations, for example the I2C-bus, the master device generates a unidirectional clock signal to the slave. For lowest cost, the PCA9525 combines unidirectional buffering of the clock signal with a bidirectional buffer for the data signal. Clock stretching is therefore not supported and slave devices that may require clock stretching must be accommodated by the master adopting an appropriate PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 3 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer clocking when communicating with them. The buffer includes hysteresis to ensure clean switching signals are output, especially with slow rise times on high capacitively loaded buses. Output ports are open-drain type and require external pull-up resistors. 7.3 SDA_IN, SDA_OUT — data signal inputs/outputs The data signal buffer is bidirectional. The port (SDA_IN, SDA_OUT) which first falls below the ‘lock voltage’ Vlock, will take control of the buffer direction and ‘lock out’ signals coming from the opposite side. As the ‘input’ signal continues to fall, it will then drive the ‘output’ side LOW. Again, hysteresis is applied to the buffer to minimize the effects of noise. At some points during the communication, the data direction will reverse, e.g., when the slave transmits an acknowledge (ACK), or responds with its register contents. During these times, the controlling ‘input’ side will have to rise back above the unlock voltage (Vunlock) before it releases the ‘lock’, which then allows the ‘output’ side to gain control, and pull (what was) the ‘input’ side LOW again. This will cause a ‘pulse’ on the ‘input’ side, which can be quite a long duration in high capacitance buses. However, this pulse will not interfere with the actual data transmission, as it should not occur during times of clock line transition (during normal I2C-bus and SMBus protocols), and thus data signal set-up time requirements are still met. Ports are open-drain type and require external pull-up resistors. 7.4 Enable (EN) — activate buffer operations The active HIGH enable input (EN) can be used to disable the buffer, for the purpose of isolating sections of the bus. The IC should only be disabled when the bus is idle. This prevents truncation of commands which may confuse other devices on the bus. Enable (EN) may also be used to progressively activate sections of the bus during system start-up. Bus sections slow to respond on power-up can be kept isolated from the main system to avoid interference and collisions. The pin must be externally driven to a valid state. 7.5 Direction (DIR) — clock buffer direction control The direction input (DIR) is used to change the signal direction of the SCL ports. When the DIR pin is logic LOW, the clock signal input is SCL_IN and the buffered output is SCL_OUT. When the DIR pin is logic HIGH, the clock signal input is SCL_OUT and the buffered output is SCL_IN. The pin must be externally driven to a valid state. PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 4 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit supply voltage [1] −0.3 +7 V Vn voltage on any other pin [1] VSS − 0.5 VDD + 0.5 V II/O input/output current Ptot VDD Parameter Conditions - 20 mA total power dissipation - 300 mW Tstg storage temperature −55 +125 °C Tamb ambient temperature −40 +85 °C [1] any pin operating Voltages are specified with respect to pin 4 (VSS). 9. Characteristics Table 4. Characteristics Tamb = −40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.7 - 5.5 V - - 1 μA - 170 - μA Power supply VDD supply voltage operating IDD supply current quiescent; VDD = VI(EN) = 5.5 V SCL_IN, SDA_IN = 800 kHz; VDD = 5.5 V [1] Buffer ports (SDA_IN, SCL_IN, SDA_OUT, SCL_OUT) VI2C-bus VIL VIH VI(hys) I2C-bus voltage LOW-level input voltage HIGH-level input voltage hysteresis of input voltage - - VDD + 0.3 V VDD = 2.7 V [2] - - 0.4 V VDD = 5.5 V [2] - - 0.5 V VDD = 2.7 V [2] 1.2 - - V VDD = 5.5 V [2] 2.0 - - V VDD = 2.7 V [2] 80 - - mV VDD = 5.5 V [2] 200 - - mV ILI input leakage current VI2C-bus = VDD or GND −1 - +1 μA IO(sink) output sink current LOW-level; VI2C-bus < VIL 4 - - mA VOL LOW-level output voltage IOL = 4 mA - 80 300 mV IOL = 100 μA - 3 - mV Pins SDA_IN, SDA_OUT Vlock Vunlock direction lock voltage direction unlock voltage PCA9525 Product data sheet VDD = 2.7 V [2] - - 1.3 V VDD = 5.5 V [2] - - 3.0 V VDD = 2.7 V [2] 2.0 - - V VDD = 5.5 V [2] 4.8 - - V All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 5 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer Table 4. Characteristics …continued Tamb = −40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit EN active; VDD = 2.7 V 2.0 - - V EN active; VDD = 5.5 V 4.8 - - V EN standby; VDD = 2.7 V - - 0.9 V EN standby; VDD = 5.5 V - - 2.1 V VDD = 2.7 V 100 - - mV VDD = 5.5 V 200 - - mV VI = VDD - - ±0.1 μA VDD = 2.7 V 2.0 - - V VDD = 5.5 V 4.8 - - V VDD = 2.7 V - - 0.9 V VDD = 5.5 V Enable (EN) Vth(en) enable threshold voltage Vth(dis) disable threshold voltage Vhys hysteresis voltage ILI input leakage current Direction (DIR) VI(dir) direction input voltage direction SCL_OUT to SCL_IN direction SCL_IN to SCL_OUT Vhys hysteresis voltage input leakage current ILI - - 2.1 V VDD = 2.7 V 100 - - mV VDD = 5.5 V 200 - - mV VI = VDD - - ±0.1 μA Timing characteristics (Figure 4) td tf delay time RPU = 620 Ω [1] - 17 - ns fall time RPU = 620 Ω [1] - 3.5 - ns [1] Guaranteed by design, not subject to test. [2] Supply voltage dependent; refer to graphs (Figure 5 through Figure 8) for typical trend. VI2C-bus 70 % VDD 30 % VDD 30 % VDD Sxx_IN Sxx_OUT td tf time 002aaf332 Fig 4. PCA9525 Product data sheet Timing diagram All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 6 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 002aaf333 5 4 1000 VI(hys) (V) 800 3 600 VI (V) 002aaf334 Tamb = +85 °C +25 °C −40 °C Vlock 2 400 VIH 1 200 VIL 0 0 2 3 4 5 6 2 3 4 5 6 VDD (V) VDD (V) Tamb = 25 °C Fig 5. Typical input levels versus supply voltage 002aaf335 100 VOL (mV) 80 Typical VIH − VIL hysteresis versus supply voltage Fig 6. 002aaf336 300 VOL (mV) VDD = 5.5 V 2.7 V 200 60 40 100 20 VDD = 5.5 V 2.7 V 0 0 2 4 6 0 −50 8 10 RPU (kΩ) Tamb = 25 °C Fig 7. 0 50 100 150 Tamb (C) IOL = 4 mA Typical LOW-level output voltage versus pull-up resistance Fig 8. Typical LOW-level output voltage versus ambient temperature 9.1 Bidirectional data buffer The bidirectional data buffer will determine which side has first fallen below Vlock and give that side of the buffer control over the direction of the buffer. For the purpose of this one LOW-going pulse, that side now becomes the ‘input’ (be it SDA_IN or SDA_OUT). When the ‘input’ side falls to near VIL, it will begin to drive the ‘output’ side of the buffer LOW. It will continue to hold the ‘output’ low until the ‘input’ exceeds VIH at which point the ‘output’ is released and will rise as fast as it is permitted by the load and pull-up to which it is attached. (Assuming, of course, that the ‘output’ is not otherwise held LOW by some other device on the bus on that side of the buffer.) When the ‘input’ side again exceeds Vunlock, it will release its control of the buffer direction. At this point, if the ‘output’ side was being held LOW (< Vlock) by another device, it will immediately gain control and now become the ‘input’. What was the ‘input’ will now become the ‘output’, and the process will repeat as above, but in the opposite direction. PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 7 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer This means that as direction control is handed from one side of the buffer to the other, a voltage ‘spike’ of about Vunlock volts will appear on the side that was the ‘input’ and became the ‘output’. Figure 9 shows clock and data being buffered through the PCA9525. Channel 3 shows the SDA_IN port, with direction ‘hand over’ spike (upper left corner). The level of the SDA_OUT port (channel 4) can be seen to increase as it goes from being held LOW by the buffer, to being held LOW by another device on the bus. Of course, the information on the SDA line is only latched into an I2C-bus device on a clock edge. The spike on the data line does not occur at a time when data is being latched, and thus the set-up and hold conditions are still met for a valid I2C-bus transaction. Figure 9 also shows a glitch occurring on the SDA_OUT port (upper right corner). A more drastic example is shown in Figure 10. In this case, the side acting as the ‘input’ (SDA_OUT) is more lightly loaded than the side acting as the ‘output’ (SDA_IN). It therefore rises quickly to Vunlock level, before the SDA_IN has been able to exceed VIL. Direction control briefly reverses, and SDA_OUT gets pulled back LOW again until SDA_IN has exceeded VIH. 002aaf337 Fig 9. ‘Hand over’ spikes on the data bus PCA9525 Product data sheet 002aaf338 Fig 10. Fast rising SDA_xx ‘input’ side All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 8 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer Figure 11 shows that by choosing an appropriate value of pull-up resistance (or adding additional load capacitance if that is preferred), the rate of rise of both input and output can be matched, and the glitch on the rising edge eliminated. 002aaf339 Fig 11. Matched ‘input’ and ‘output’ rise times 9.2 Operating conditions A full byte transaction is shown in Figure 12. SDA_IN and SDA_OUT are shown at the top of the image, and SCL_IN and SCL_OUT are shown at the bottom. The START condition, address bits, read/write bit, acknowledge bit and STOP condition can all be clearly seen. 002aaf340 Fig 12. Full 400 kHz I2C-bus address byte transaction PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 9 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 10. Application information 10.1 Design considerations Figure 13 shows a typical data transfer through the PCA9525. The PCA9525 has excellent application to extending loads and providing interfaces to connectors on high speed microprocessor cards. PCA9525 can operate well in excess of the Fast-mode 400 kHz I2C-bus specification (Ref. 1). Rise times are determined simply by the side of the buffer with the slowest RC time constant. SCL (clock) SDA (data) A0 (master) S A1 (master) A2 (master) A3 (master) A4 (master) A5 (master) purpose of bit (address bit 5) START sequence device asserting data line (master/slave) A6 (master) W (master) ACK (slave) P SDA direction 'hand over' pulses upon change of device asserting the data line STOP sequence master side of PCA9525/PCA9605 slave side of PCA9525/PCA9605 002aaf341 Remark: Input to output delay exaggerated for clarity. Fig 13. Typical communication sequence through the PCA9525 Figure 14 shows a typical application for the PCA9525. In most applications there will be a single master on the Sxx_IN side of the buffer. One or more PCA9525s can be connected to this master, giving multiple isolated bus sections on which the slaves are located. Each bus section can have the maximum permissible load capacitance, and this capacitance will not influence any other bus section. The master can control the enable (EN) signals such that each bus section can be independently activated. This allows for slaves sharing the same address to be placed on different bus sections and thus uniquely addressed. The enable pin (EN) can similarly be used to interface buses of different operating frequencies. When certain bus sections are enabled, the system frequency may be limited by a bus section having a slave device specified only to 400 kHz (Fast-mode). When that bus section is disabled, the slow slave is isolated and the remaining bus can be run at 1 MHz (Fast-mode Plus). PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 10 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 3.3 V SCL_IN VDD SCL_OUT SCL SDA SDA_IN SDA_OUT SDA U5 U4 VDD SCL SLAVE SDA U1 MASTER/ SLAVE VDD PCA9525 SCL SLAVE U6 up to 400 pF load (PCA9525) up to 400 pF load (PCA9525) or 4 nF load if only PCA9605's used (R1 and R2 = 110 Ω) R5 110 Ω R4 110 Ω SCL_IN VDD SCL_OUT SCL SDA_IN SDA_OUT SDA SLAVE U7 VDD U2 SCL PCA9605 VDD DIR SCL EN SDA VDD SCL SDA DIR SDA EN BUS MASTER U3 R4 1.1 kΩ SCL SDA VDD R3 1.1 kΩ R2 1.1 kΩ R1 1.1 kΩ SLAVE U8 up to 4 nF load (PCA9605) 002aaf342 Fig 14. PCA9525 typical buffer application Figure 15 shows the PCA9525 used with masters on both sides of the buffer. More than one master may be used on the Sxx_IN side of the IC. However, to locate a master on the Sxx_OUT side and have that master be able to communicate with devices on the Sxx_IN side, it must either have direct control over the direction pin (DIR) of the PCA9525, or it must request another controlling master to change the direction. In Figure 15, U4 uses an IRQ to signal to U2 that is requests a direction change. Once in control, it could alternatively use the bus to signal ‘release of control’. PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 11 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 5V R1 R3 R4 SCL SCL_IN VDD SCL_OUT SCL SDA SDA_IN SDA_OUT SDA VDD U1 SCL IRQ PCA9525 SDA DIR VDD BUS MASTER SCL EN SDA VDD R2 VDD SCL SDA U2 MASTER/ SLAVE MASTER master U4 requests SCL direction change from master U2 using IRQ U4 SLAVE U5 U3 002aaf343 Fig 15. PCA9525 with masters on both sides of buffer Multiplexers such as the PCA9544A are simple analog switches which provide no capacitive load isolation between connected branches. Figure 16 shows the PCA9525 enhancing an I2C-bus multiplexer application by isolating the load capacitance of each branch. Figure 17 and Figure 18 show alternate forms of bus multiplexing, with the latter being an excellent way to eliminate the requirement for a master to dedicate pins to enabling multiple PCA9525 devices. 3.3 V R1 1.5 kΩ VCC SCL SDA BUS MASTER R3 1.1 kΩ R2 1.5 kΩ SCL_IN SDA_IN EN R4 1.1 kΩ VDD SCL_OUT SCL SDA_OUT SDA U2 SC0 SD0 SC1 PCA9525 DIR U1 VDD INT[3:0] SD1 SC2 A0 SD2 A1 SC3 A2 SD3 Using the PCA9525, up to 400 pF may be connected to each and every bus 0 through bus 3. PCA9544A U3 002aaf344 Alternately, using the PCA9546A, (which allows multiple outputs to be selected) you would simply place a PCA9525 on each output on the right hand side, rather than a single PCA9525 on the left hand side. Fig 16. PCA9525 multiplexer isolation application PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 12 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 5V R1 1.8 kΩ R2 1.8 kΩ SCL SCL_IN VDD SCL_OUT SDA SDA_IN SDA_OUT EN A B C VCC 74LS137 3-to-8 demultiplexer PCA9525 DIR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U1 VDD SCL_OUT SDA_IN SDA_OUT PCA9605 DIR U3 SDA isolated bus with 400 pF load capacitance 5V SCL_IN EN SCL SCL SDA isolated bus with 4 nF load capacitance U2 002aaf345 Fig 17. PCA9525 bus multiplexer application driven from a simple logic device 3.3 V R1 1.1 kΩ R2 1.1 kΩ SCL SCL_IN VDD SCL_OUT SCL SDA SDA_IN SDA_OUT SDA EN VDD SCL SDA I2C-bus I/O expander IO0 IO1 IO2 IO3 PCA9536 U3 PCA9525 DIR U1 3.3 V SCL_IN VDD SCL_OUT SDA_IN SDA_OUT EN DIR isolated bus with 400 pF load capacitance PCA9605 SCL SDA isolated bus with 4 nF load capacitance U2 002aaf346 Fig 18. PCA9525 bus multiplexer application driven from an I2C-bus I/O expander PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 13 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 11. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp L 4 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 19. Package outline SOT96-1 (SO8) PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 14 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 20. Package outline SOT505-1 (TSSOP8) PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 15 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 12. Handling information CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • PCA9525 Product data sheet Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 16 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 21) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 5 and 6 Table 5. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 6. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 21. PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 17 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 7. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DDC Data Display Channel I2C-bus Inter-Integrated Circuit bus I/O Input/Output IC Integrated Circuit PMBus Power Management Bus RC Resistor-Capacitor network SMBus System Management Bus 15. References PCA9525 Product data sheet [1] UM10204, I2C-bus specification and user manual — , Rev 03, 19 June 2007; NXP B.V. www.nxp.com/documents/user_manual/UM10204.pdf [2] System Management Bus (SMBus) Specification — Version 2.0, August 3, 2000; SBS Implementers Forum. All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 18 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 16. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9525 v.1 20110225 Product data sheet - - PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 19 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 20 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9525 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 25 February 2011 © NXP B.V. 2011. All rights reserved. 21 of 22 PCA9525 NXP Semiconductors Simple 2-wire bus buffer 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 8 9 9.1 9.2 10 10.1 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 VDD, VSS — supply pins . . . . . . . . . . . . . . . . . . 3 SCL_IN, SCL_OUT — clock signal inputs/ outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 SDA_IN, SDA_OUT — data signal inputs/ outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Enable (EN) — activate buffer operations . . . . 4 Direction (DIR) — clock buffer direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Bidirectional data buffer . . . . . . . . . . . . . . . . . . 7 Operating conditions. . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 10 Design considerations . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Handling information. . . . . . . . . . . . . . . . . . . . 16 Soldering of SMD packages . . . . . . . . . . . . . . 16 Introduction to soldering . . . . . . . . . . . . . . . . . 16 Wave and reflow soldering . . . . . . . . . . . . . . . 16 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 February 2011 Document identifier: PCA9525