PHILIPS PCF5001T

INTEGRATED CIRCUITS
DATA SHEET
PCF5001
POCSAG Paging Decoder
Product specification
Supersedes data of 1995 Apr 27
File under Integrated Circuits, IC17
1997 Mar 04
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
CONTENTS
BLOCK DIAGRAMS
7.22
7.23
7.23.1
7.23.2
EEPROM Write operation
EEPROM Read operation
Read-back operation via Microcontroller
Interface
Voltage converter
Test modes of the decoder
Board test mode
Pager Test Mode (Type Approval Mode)
6
PINNING
8
LIMITING VALUES
7
FUNCTIONAL DESCRIPTION
9
DC CHARACTERISTICS
7.1
The PCF5001 supports two basic modes of
operation
The POCSAG paging code
Modes and states of the decoder
Decoding of the POCSAG data stream
Generation of output signals
Alerter
Silent call storage and Repeat mode
Duplicate Call Suppression
LED indicator
Vibrator output
Start-up alert
Serial communication interface
Message data transfer
Call Data output on LED
Serial communication call data format
Data conversion
Memory Organization
Description of the Special Programmed
Function (SPF) bits
10
DC CHARACTERISTICS (WITH VOLTAGE
CONVERTER)
11
AC CHARACTERISTICS
12
TIMING CHARACTERISTICS
13
PROGRAMMING CHARACTERISTICS
14
APPLICATION INFORMATION
15
PACKAGE OUTLINES
16
SOLDERING
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.4
Introduction
Reflow soldering
Wave soldering
LQFP
SO
Method (LQFP and SO)
Repairing soldered joints
17
DEFINITIONS
18
LIFE SUPPORT APPLICATIONS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
1997 Mar 04
7.19
7.20
7.21
2
Philips Semiconductors
Product specification
POCSAG Paging Decoder
1
PCF5001
• Serial microcontroller interface for display pager
applications
FEATURES
• Wide operating supply voltage range (1.5 to 6.0 V)
• Optional visual indication of received call data using a
modified RS232 format
• Extended temperature range: −40 to +85 °C (between
−40 to −10 °C, minimum supply voltage restricted
to 1.8 V)
• Level shifted microcontroller interface signals
• Alert on low battery
• Very low supply current (60 µA typ. with
76.8 kHz crystal)
• Optional out-of-range indication.
• “CCIR radio paging Code No 1” (POCSAG) compatible
• Programmable call termination conditions
2
• 512 and 1200 bits/s data rates (2400 bits/s with some
restrictions), see Section 7.4
• Alert-only pagers, display pagers
APPLICATIONS
• Telepoint
• Improved ACCESS synchronization algorithm
• Telemetry/data receivers.
• Supports 4 user addresses (RICs) in two independent
frames
• Eight different alert cadences
3
• Directly drives magnetic or piezo ceramic beeper
The PCF5001 is a fully integrated low-power decoder and
pager controller. It decodes the CCIR radio paging Code
No.1 (POCSAG-Code) at 512 and 1200 bits/s data rates.
The PCF5001 is fabricated in SACMOS technology to
ensure low power consumption at low supply voltages.
• High level alert requires only a single external transistor
• Optional vibrator type alerting
• Silent call storage, up to eight different calls
GENERAL DESCRIPTION
• Repeat alarm facility
• Programmable duplicate call suppression
• Interfaces directly to UAA2050T, UAA2080 and
UAA2082 digital paging receivers
• Programmable receiver power control for battery
economy
• On-chip non-volatile EEPROM storage
• On-chip voltage converter with improved drive capability
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF5001T
SO28
PCF5001H
LQFP32(1)
DESCRIPTION
VERSION
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
SOT358-1
Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Handbook”
(order number 9397 750 00192) are followed.
1997 Mar 04
3
Philips Semiconductors
Product specification
POCSAG Paging Decoder
5
PCF5001
BLOCK DIAGRAMS
VSS
handbook, full pagewidth
VDD
17
DI
5
DO
4
DIGITAL INPUT
FILTER
CLOCK
RECOVERY
DS
26
27
DATA OUTPUT
CONTROL
SERIAL DATA PROCESSOR
EEPROM
MEMORY
DECODER AND
ERROR CORRECTION
CONTROL
7
EEPROM
CONTROL
RE
X1
X2
14
RECEIVER
ENABLE
CONTROL
SYNC
CONTROL
TIMING
CONTROL
10
ALERT
GENERATION
CONTROL
PCF5001T
9
OSCILLATOR
CLOCK
GENERATION
VOLTAGE
CONVERTER
POWER-ON
RESET
3
2
1
TEST
CONTROL
28
11
18
STATUS
CONTROL
21 20 22 19
8
12
15
25
16
13
23
PD
PS
AH
AL
OR
OM
OL
AI
BATTERY LOW
CONTROL
24
6
MCD454
CP
CN
V ref
FL
TS
TT
SR SK ON IE
Fig.1 Block diagram (SO28; SOT136-1).
1997 Mar 04
4
BL
BS
Philips Semiconductors
Product specification
POCSAG Paging Decoder
VSS
handbook, full pagewidth
VDD
31
DI
17
PCF5001
n.c.
n.c.
2
7
16
DIGITAL INPUT
FILTER
CLOCK
RECOVERY
n.c.
n.c.
20
DO
21
DS
10
11
DATA OUTPUT
CONTROL
SERIAL DATA PROCESSOR
EEPROM
MEMORY
DECODER AND
ERROR CORRECTION
CONTROL
19
EEPROM
CONTROL
RE
X1
X2
28
RECEIVER
ENABLE
CONTROL
SYNC
CONTROL
TIMING
CONTROL
24
ALERT
GENERATION
CONTROL
PCF5001H
23
OSCILLATOR
CLOCK
GENERATION
VOLTAGE
CONVERTER
POWER-ON
RESET
15
CP
14
CN
13
V ref
TEST
CONTROL
12
FL
25
32
TS
TT
STATUS
CONTROL
4
3
5
5
26
29
9
30
27
6
PD
PS
AH
AL
OR
OM
OL
AI
BATTERY LOW
CONTROL
1
SR SK ON IE
Fig.2 Block diagram (LQFP32; SOT358-1).
1997 Mar 04
22
8
BL
18
BS
MLB045
Philips Semiconductors
Product specification
POCSAG Paging Decoder
6
PCF5001
PINNING
PIN
SYMBOL
PCF5001T
(SOT136-1)
PCF5001H
(SOT358-1)
DESCRIPTION
Vref
1
13
Microcontroller interface reference voltage input/output. The LOW level of
pins FL, DS, DO, OR, BL, AI, ON, SK, SR and IE is related to the voltage
on Vref. May be driven from an external negative voltage source or must
be connected to VSS, if pins CN and CP are left open-circuit. When the
on-chip voltage converter is used, this pin provides a doubled negative
output voltage.
CN
2
14
Voltage converter external shunt capacitance, negative side. Connect the
negative side of the shunt capacitor to this pin, if the on-chip voltage
converter function is used.
CP
3
15
Voltage converter external shunt capacitor, positive side. Connect the
positive side of the shunt capacitor to this pin, if the on-chip voltage
converter function is used.
VDD
4
16
Main positive power supply. This pin is common to all supply voltages and
is referred to as 0 V (common).
DI
5
17
Serial data input (POCSAG code). The serial data signal train applied to
this pin is processed by the decoder. Pulled LOW by an on-chip pull-down
when the receiver is disabled (RE = LOW).
BS
6
18
Battery-low indication input. The decoder samples this input during
synchronization scan, when it is in ON or SILENT status and the receiver
is enabled (RE = HIGH). A battery-low condition is assumed, if the
decoder detects four consecutive samples HIGH. An audible battery-low
indication is made by the decoder, when operating in ON status. Normally
LOW by the operation of an on-chip pull-down.
PD
7
19
EEPROM programming data input and output. Normally HIGH by the
operation of an on-chip pull-up. During programming of the on-chip
EEPROM, PD is a bidirectional data and control signal.
PS
8
22
EEPROM programming strobe input. Normally LOW by the operation of
an on-chip pull-down. During programming of the on-chip EEPROM, PS is
a unidirectional control input.
X1
9
23
Crystal oscillator input. Connect a 32768 Hz or 76800 Hz crystal and a
biasing resistor between this pin and X2. In addition, provide a load
capacitance to VDD, which may also be used for frequency tuning.
X2
10
24
Crystal oscillator output. Return connection for the external crystal and
resistor at X1.
TS
11
25
Scan test mode enable input. Always LOW by operation of an on-chip
pull-down.
AH
12
26
Alert HIGH-level output. This output can directly drive an external bipolar
transistor to control HIGH-level alerting in conjunction with AL, by means
of an alerter or beeper.
OL
13
27
LED indication output. This output can directly drive an external bipolar
transistor to control the visual alert function by means of an LED. It may
also be used for visual indication of received call data during call
reception.
1997 Mar 04
6
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
PIN
SYMBOL
PCF5001T
(SOT136-1)
PCF5001H
(SOT358-1)
DESCRIPTION
RE
14
28
Receiver enable output. May be used to control the paging receiver power
control input, to minimize power consumption. The decoder provides a
HIGH-level at this pin, when receiver operation is requested. Each time
the decoder does not require any input data at DI the receiver enable
output is LOW.
AL
15
29
Alert LOW-level output. Open drain alert output in anti-phase to AH, to
provide LOW-level alerting. HIGH-level alerting is generated in conjunction
with AH.
OM
16
30
Vibrator output. This output can directly drive an external bipolar transistor
to control a vibrator type alerter.
VSS
17
31
Main negative supply voltage.
TT
18
32
Test mode enable input. Always LOW by operation of an on-chip
pull-down.
IE
19
1
Interface enable input. While the interface enable input is active HIGH,
operation of the ON, SK, SR, AI, BL and OR inputs and outputs is
possible. When IE is LOW the inputs do not respond to applied signals
and the outputs are made high-impedance. In alert-only pager mode the
interface enable input does not have any effect on the operation of inputs
ON, SK and SR, but IE must be referenced to LOW or HIGH.
SK
20
3
SILENT state control input. The SILENT control input selects the decoder
ON status (LOW-level) or SILENT status (HIGH-level), if the ON input is
active HIGH. An on-chip pull-up is provided, if the decoder has been
programmed for ‘alert-only pager’ mode, whereby the pull-up is disabled
for display pager mode. In ‘display pager’ mode status change is
possible if the interface enable input (IE) is HIGH and the status is latched
on the falling edge of IE.
SR
21
4
Status request and reset input. A HIGH-going pulse on this input causes
(a) status indication cadence to be generated, if the decoder is not alerting
or (b) resetting of a call alert, repeated call alert or battery-low alert, if
active or (c) triggers the call store re-alert facility, if repeat mode is active.
In ‘display pager’ mode operation of SR is possible only if the interface
control input is active. Normally LOW by the operation of an on-chip
pull-down.
ON
22
5
On/off control input. The on/off control input selects the decoder ON status
(HIGH-level) or OFF status (LOW-level). An on-chip pull-up resistor is
provided, if the decoder has been programmed for ‘alert-only pager’ mode,
but the pull-up resistor is disabled for ‘display pager’ mode. In
‘display pager’ mode, status change is possible if the interface enable
input (IE) is HIGH and the status is latched on the falling edge of IE.
AI
23
6
Alarm input. A HIGH-level on this input causes generation of a continuous
HIGH-level alert via AH and AL outputs, if the decoder operates in ON
status or OFF status. In addition, the LED output is active independent
from the decoder status, but in accordance with AI. Pulsing the input may
be used to modulate the alert and LED indication. Normally LOW in
‘alert-only pager’ mode by operation of an on-chip pull-down.
1997 Mar 04
7
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
PIN
SYMBOL
DESCRIPTION
PCF5001T
(SOT136-1)
PCF5001H
(SOT358-1)
BL
24
8
Battery-low indication output. If the decoder encounters a battery-low
condition a battery-low output latch is set HIGH. The battery-low output
latch may be tested for a battery-low condition, whenever the interface
enable input (IE) is active (HIGH), otherwise the battery-low output is
made high-impedance. The battery-low output latch is reset only, by
switching the decoder to OFF status.
OR
25
9
Out-of-range indication output. Whenever the decoder detects an
out-of-range condition an out-of-range output latch is set HIGH after expiry
of the programmed out-of-range hold-off time selected by means of
special programming (SPF06 and SPF07) of the EEPROM. The
out-of-range latch may be tested for an out-of-range condition, whenever
the interface enable input (IE) is active (HIGH), otherwise the out-of-range
output is made high-impedance. The out-of- range output is reset by
detection of a valid data transmission or by switching the decoder to OFF
status.
DO
26
10
Serial interface data output. During normal decoder operation, accepted
calls and possibly subsequent message data are serially output via this pin
in conjunction with the data strobe output (DS). This pin is also used to
output the EEPROM contents upon special command, if the decoder is
programmed for display pager.
DS
27
11
Serial interface data strobe output. Provides a clock signal for the received
call data and EEPROM data appearing at the data output (DO). Each time
this output is LOW the data at DO is valid. Additional start and stop
conditions allow easy identification of data sequence start and end.
FL
28
12
Frequency reference output. When programmed for ‘display pager’ mode,
this output provides a clock reference with 16384 or 32768 Hz per
second, selected by SPF32. See Chapter 7.
n.c.
−
2, 7, 20, 21
1997 Mar 04
Not connected.
8
Philips Semiconductors
Product specification
POCSAG Paging Decoder
Vref
1
28
CN
2
27 DS
CP
3
26 DO
VDD
4
25 OR
DI
5
24
BL
BS
6
23 AI
PD
7
22 ON
PCF5001T
handbook, halfpage
TT
VSS
OM
AL
RE
OL
AH
TS
index
corner
32
31
30
29
28
27
26
25
FL
IE
1
24 X2
n.c.
2
23 X1
SK
3
22 PS
SR
4
21 n.c.
PCF5001H
n.c.
7
18 BS
BL
8
17 DI
18
TT
AH 12
17
VSS
OL 13
16
OM
15
AL
RE 14
OR
9
TS 11
16
IE
19
X2 10
15
19 PD
CP
6
VDD
AI
14
20 SK
CN
9
13
X1
V ref
20 n.c.
12
5
11
ON
FL
21 SR
DS
8
10
PS
DO
handbook, halfpage
PCF5001
MLB048
MCD455 - 1
Fig.3 Pin configuration PCF5001T (SOT136-1).
7
Fig.4 Pin configuration PCF5001H (SOT358-1).
In display pager mode the state input logic is switched to
a bus interface structure. Received calls and messages
are transferred to an external microcontroller via the serial
microcontroller interface. A built-in voltage converter with
increased drive capabilities can supply doubled supply
voltage output, and appropriate logic level shifting on
microcontroller interface signals is provided.
FUNCTIONAL DESCRIPTION
The PCF5001 is a very low power Decoder and Pager
Controller specifically designed for use in new generation
radio pagers. The architecture of the PCF5001 allows for
flexible application in a wide variety of radio pager designs.
The PCF5001 is fully compatible with “CCIR radio paging
Code Number 1” (also known as the POCSAG code)
operating at the originally specified 512 bits/s data rate,
and also at the newly specified 1200 bits/s data rate
(2400 bits/s operation is also possible). The PCF5001 also
offers features which extend the basic flexibility and
efficiency of this code standard.
7.1
Upon reception of valid calls one of eight different call
cadences is generated; upon status interrogation status
indication tones make the current status of the decoder
available to the user.
On-chip non-volatile 114-bit EEPROM storage is provided
to hold up to four user addresses, two frame numbers and
the programmed decoder configuration.
The PCF5001 supports two basic modes of
operation
Synchronization to the input data stream is achieved using
the improved ACCESS algorithm, which allows for data
synchronization and re-synchronization without preamble
detection while minimizing battery power consumption by
receiver power control. One of four error correction
algorithms is applied to the received data to optimize the
call success rate.
In alert-only pager mode only a minimum number of
external components are required to build a complete
tone-only pager. Selection of operating states ON, OFF or
SILENT is achieved using a slider switch interface.
1997 Mar 04
9
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.2
PCF5001
Four different call types (‘numeric’, ‘alphanumeric’ and two
‘alert only’ types) can be distinguished. The call type is
determined by two function bits in the address codeword
(bits 20 and 21).
The POCSAG paging code
A transmission using the “CCIR Radio paging Code No. 1”
(POCSAG code) is constructed in accordance with the
following rules (see Fig.5).
Alert-only calls consist only of a single address codeword.
Numeric and alphanumeric calls have message
codewords following the address. A message causes the
frame structure to be temporarily suspended. Message
codewords are sent until the message is completed, with
only the sync words being transmitted in their expected
positions.
The transmission is started by sending a preamble,
consisting of at least 576 continuously alternating bits
(10101010...). The preamble is followed by an arbitrary
number of batch blocks. Only complete batches are
transmitted.
Each batch comprises 17 codewords of 32 bits each.
The first codeword is a synchronization codeword with a
fixed pattern. The sync word is followed by 8 frames
(0 to 7) of 2 codewords each, containing message
information. A codeword in a frame can either be an
address, message or idle codeword.
Message codewords are identified by an MSB at logic 1
and are coded as shown in Fig.5. The message
information is stored in a 20-bit field (bits 2 to 21).
The standard data format is determined by the call type: 4
bits per digit for numeric messages and 7 bits per (ASCII)
character for alphanumeric messages.
Idle codewords also have a fixed pattern and are used to
fill empty frames or to separate messages.
Each codeword is protected against transmission errors by
10 CRC check bits (bits 22 to 31) and an even-parity bit
(bit 32). This permits correction of a maximum of 2 random
errors or up to 3 errors in a burst of 4 bits (a 4-bit burst
error) per codeword.
Address codewords are identified by an MSB at logic 0
and are coded as shown in Fig.5. A user address or RIC
consists of 21 bits. Only the upper 18 bits are encoded in
the address codeword (bits 2 to 19). The lower 3 bits
designate the frame number (0 to 7) in which the address
is transmitted.
handbook, full pagewidth
PREAMBLE
BATCH 1
BATCH 2
BATCH 3
LAST BATCH
10101 . . . 10101010
SYNC | CW CW | CW CW | . . . . . | CW CW
FRAME 0
FRAME 1
Address code-word
0
18-bit address
Message code-word
1
20-bit message
FRAME 7
2 function bits
10 CRC bits
P
10 CRC bits
P
MCD456
Fig.5 POCSAG code structure.
1997 Mar 04
10
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.3
PCF5001
and the decoder. Upon detection of a valid call, address
and message information are transferred to the external
microcontroller using the serial microcontroller interface.
In addition, appropriate call alert cadences are generated.
Modes and states of the decoder
The PCF5001 supports two basic operating modes:
• ‘Alert-only pager’ mode
• ‘Display pager’ mode.
If the decoder is in one of the two operating modes, it is
always in one of the following three internal states:
Two further modes, the programming mode and the test
mode, are implemented to program and verify the
EEPROM contents and to support pager production and
approval tests, respectively.
• OFF status. This is the power saving, inactive status of
the PCF5001. The paging receiver is disabled, no
decoding of input data takes place. However, the crystal
oscillator is kept running to ensure that scanning of the
status inputs/status switch is maintained to allow
changing into one of the following two active states.
In ‘alert-only pager’ mode no external microcontroller is
required, see Fig.22. A three position slider switch
interface is provided to select the internal state of the
decoder. The decoder performs regular scanning of the
switch inputs to detect a status change. A push-button
interface is provided on the SR input, which is used as
input for user acknowledgment actions and status
interrogation. Upon reception of valid calls, tone alert
cadences are generated. A call storage is provided to store
calls received while operating in SILENT status and to
recall cadences upon ‘repeat’ mode operation.
The voltage doubler and the frequency reference output
are disabled in this mode.
• ON status. This is the normal active status of the
decoder. Incoming calls are compared with the user
addresses stored in the internal EEPROM. Upon
detection of valid calls, alert cadences and LED
indication are generated and data is shifted out at the
serial microcontroller interface.
• SILENT status. The SILENT status is the same as the
ON status with the exception that valid calls no longer
cause generation of call alert cadences. Instead, if
programmed as ‘alert-only pager’, the decoder stores up
to eight different calls and generates appropriate alert
cadences after the decoder has been put back into the
ON status. However, special SILENT override calls will
cause generation of alert cadences, if enabled.
In ‘display pager’ mode the PCF5001 operates as decoder
and pager controller in combination with an external
microcontroller (see Fig.23). The internal states of the
decoder are determined by appropriate logic levels on the
status inputs. A bus type interface structure is used to
interface the decoder to the microcontroller. The decoder's
on-chip voltage converter provides doubled supply voltage
output to provide a higher supply voltage to the
microcontroller and any additional hardware. The logic
levels of the interface's input and output signals are level
shifted to allow for direct coupling between microcontroller
Table 1
The decoder operating status is selected as indicated in
Table 1.
When programmed for ‘alert-only pager’ a switch
debounce period is applied to the status inputs. For status
change and status interrogation in ‘display pager’ mode,
see Figs 6 and 7.
Truth table for decoder operating status
ON INPUT
SK INPUT
OPERATING STATUS
0
0
OFF
0
1
OFF (EEPROM transfer mode; note 1)
1
0
ON
1
1
SILENT
Note
1. The EEPROM transfer mode applies to ‘display pager’ mode only.
1997 Mar 04
11
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
IE
ON
SK
INTERNAL
STATUS
t STP
t STD
t STD
t STH
t IEH
MCD457 - 1
Fig.6 Status change in display pager mode.
IE
SR
t
STP
t
STH
t
SPD
t
IEH
t
STH
MCD458
Fig.7 Status interrogation in display pager mode.
7.4
A data rate of 2400 bits/s is possible if an external clock
generator of 153.6 kHz is connected to X1. The minimum
supply voltage is then −1.8 V.
Decoding of the POCSAG data stream
The POCSAG coded input data stream is first noise filtered
by a digital filter. From the filtered data a sampling clock
synchronous to the data rate is derived. The PCF5001
supports 512 bits/s and 1200 bits/s data rates. This results
in a 512 Hz or 1200 Hz sampling clock frequency,
respectively. Synchronization on the POCSAG code
structure is performed using the improved Philips
ACCESS algorithm, which employs a state machine with
six internal states.
1997 Mar 04
The receiver enable output is activated a period equal to
tRXON before the input data is actually needed. The
decoder has first to achieve bit and word synchronization
before it can receive calls. The algorithm searches first for
the preamble and then for synchronization codeword
patterns.
12
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
This is carried out for the duration of 3 batches in
power-on mode or 1 batch (=preamble duration) in
preamble receive mode. Error correction algorithms are
applied to the data before it is compared with preamble
and synchronization codeword patterns.
The synchronization process is terminated and thus
data receive mode is entered as soon as synchronization
codewords are seen at the beginning of each batch.
In ‘data receive’ mode, the input data stream is sampled at
the synchronization codeword position and the
programmed frame positions. The received codewords are
error corrected and then, if address codewords, compared
with the stored user addresses related to that frame.
On detection of a valid call, the decoder performs the
following three operations:
1. Set a store for call alert cadence generation according
to the combination of the function bits in the accepted
address codeword. The call alert cadence will not be
generated before the call has been terminated.
The decoder handles loss of synchronization in three
steps:
1. If the decoder fails to detect the synchronization
pattern at the beginning of the current batch it
continues data reception as normal. This data fail
mode is signalled in the message output when an
address codeword was received, as shown in Table 4.
2. Keep the receiver enable output (RE) active and
receive subsequent message codewords, until any of
the call termination criteria are fulfilled.
3. Trigger the serial message transfer by sending a start
condition and transfer deformatted message
codewords as attached to the address codeword via
the serial microcontroller interface to an external
microcontroller, followed by a stop condition.
2. If also at the beginning of the next batch no
synchronization codeword can be detected, the
algorithm assumes a small bit shift in the
fade recovery mode and performs more
synchronization codeword checks around the
expected position for the following 15 batches. Call
reception is suspended.
Normally call termination is assumed, when a valid idle or
address codeword is received. On reception of
uncorrectable codewords, call termination takes place in
accordance with conditions shown in Table 2.
3. If it fails to re-synchronize in the ‘fade recovery’ mode,
the carrier off mode is selected, in which the decoder
attempts to regain synchronization by bit-wise shifting
its synchronization scan window. Using this technique
re-synchronization is obtained within a continuous
data stream of at least 18 batches without preamble
detection.
Table 2
Call termination on error
SPF12
SPF13
CALL TERMINATION EVENT
0
X(1)
1
0
Any single codeword uncorrectable.
1
1
Any two consecutive codewords uncorrectable.
Any two consecutive codewords or the codeword directly following the address
codeword uncorrectable.
Note
1. X = don’t care.
1997 Mar 04
13
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.5
PCF5001
Table 3 shows the outputs which are used for special
output indications, if the decoder operates in ON status.
Generation of output signals
The PCF5001 provides output indications for call alert,
repeat mode alert, out of range alert, battery-low alert,
status indication alert and start-up alert. Some of the alert
functions may be freely configured by programming of
SPF bits within the EEPROM.
Table 3
Remark: reception of special SILENT override calls
causes the decoder to generate call alert indication via AL
and AH even if it operates in SILENT status.
Output signals
OUTPUT ACTIVE(1)
ALERT FUNCTION
Start-up
AL
AH
OL
OM
OR
BL
(yes)
−
yes
yes
−
−
yes
−
−
−
−
−
Call reception
(yes)
(yes)
yes
SPF11
−
−
Repeat mode
(SPF16)
(SPF16)
SPF16
−
−
−
Status indication
−
−
SPF15
−
yes
−
Battery-low
(yes)
(yes)
−
−
−
yes
Alarm input
(yes)
(yes)
yes
−
−
−
Out-of-range
Note
1. Entries in parenthesis are not valid, if the decoder operates in SILENT status.
7.6
The call alert cadence is modulated according to the two
function bits (FC) in the received address codeword,
see Fig.9.
Alerter
The PCF5001 provides the AL and AH outputs for
acoustical LOW-level and HIGH-level signalling.
LOW-level alerting is provided by the AL output only.
For HIGH-level alerting both, AL and AH are active in
anti-phase. The square-wave output signals produce tone
alert cadences by means of a magnetic or piezo ceramic
beeper. The alert frequency, 2048 Hz or 2731 Hz
square-wave, is selected by programming of SPF31.
Valid calls received on RIC B or RIC D cause the alerter
frequency to be warbled by means of an additional 16 Hz
and 1024 Hz signal (respective 1365 Hz for SPF31 = 1)
as opposed to RIC A and RIC C where no alert frequency
warble takes place. Thus, eight different call cadences are
distinguishable.
ON status interrogation by the status request and reset
input (SR) the PCF5001 generates a status cadence at
LOW-level, in accordance with the present internal
decoder status (see Fig.10).
When valid calls are received while operating in ON status,
the PCF5001 generates call alert cadences. The first four
seconds are generated at LOW-level, a further twelve
seconds are generated at HIGH-level. Alert tone
generation and LED indication automatically terminate
after sixteen seconds unless terminated by pulsing the
status request and reset input (SR). Call alert generation
is inhibited until completion of message codeword
reception and the termination word is sent by the decoder.
Call alert generation commences after an alert delay
period, tALD, at the earliest, see Fig.8. Call alert deletion is
possible during the alert delay period.
1997 Mar 04
When detecting a battery-low condition the PCF5001
provides a battery-low indication. Operating in ON status
causes generation of a battery-low alert at HIGH-level for
sixteen seconds or until terminated by pulsing SR.
Operating in SILENT status or ‘repeat’ mode the
battery-low alert is stored and inhibited until switching to
ON status.
14
Philips Semiconductors
Product specification
POCSAG Paging Decoder
DO
DS
PCF5001
EOT
STP
AL
AH
OL
CALL1
t
CALL2
t
ALD
ALD
MCD459
Fig.8 Call alert delay.
cadence 1
(FC = 00)
t ALP
t ALC
cadence 2
(FC = 01)
t ALP
t ALP
t ALC
cadence 3
(FC = 10)
t ALP
t ALP
t ALC
cadence 4
(FC = 11)
t ALP
t ALP
t ALC
t ALC
Fig.9 Call alert cadences.
1997 Mar 04
15
MCD460
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
ON
t STON
OFF
t STON
t STOF
t STON
t STOF
SILENT
MCD461
Fig.10 Status indication cadences.
7.7
No call alert storage occurs when the decoder is
programmed for ‘display pager’ mode.
Silent call storage and repeat mode
When programmed for alert only pager the PCF5001
provides a call alert storage for storing of call alerts
received during SILENT status or for call alerts which
caused the decoder to enter repeat mode. Call alert is not
stored, when call indication is terminated by action of the
status request and reset input (SR).
7.8
The PCF5001 provides a Duplicate Call Suppression with
time-out facility, to identify duplicate call reception. When
selected by programming of SPF14, the PCF5001 inhibits
any duplicate call alert in ‘alert-only pager’ mode.
In ‘display pager’ mode, duplicate call indication is
achieved only via the serial microcontroller interface. A call
is assumed to be duplicate if its address and function bit
setting is equal to the latest received call, which initialized
the call address and function bit reference. The Duplicate
Call Suppression time-out is selectable by programming of
SPF06 and SPF07.
Allowing the call indication to time-out by expiration of a
sixteen second alert operation causes the ‘repeat’ mode to
be entered, while operating in ON status or SILENT status.
Such call alerts are stored for later repeated call alert on
interrogation by the user. When ‘repeat’ mode has been
entered and the decoder operates in ON status, the repeat
call store is interrogated by pulsing the status request and
reset input (SR) or on switching to ON status if the decoder
operates in SILENT status. When SILENT override calls
are received, which entered the ‘repeat’ mode,
interrogation of repeat call store operates as in decoder
ON status. After interrogation of repeat call store and
subsequent generation of all stored call alerts the call store
is cleared and the ‘repeat’ mode is terminated.
7.9
LED indicator
The PCF5001 provides for visual signalling using a LED
via output OL.
Call alert indication is provided by the LED with the same
cadence and warble modulation as for the alerter outputs
AL and AH. Call alert indication occurs in ON and SILENT
status and automatically terminates after sixteen seconds
time-out unless terminated by pulsing the status request
and reset input (SR).
When programmed by means of SPF16, a repeat alert
cadence is generated periodically, whenever ‘repeat’
mode has been entered. Operating in ON status causes
the repeat alert cadence to be generated at HIGH-level
and warbled by means of an additional 16 Hz and 1024 Hz
signal (respective 1365 Hz for SPF31 = 1) as shown in
Fig.11. The LED output indicates the same alert cadence
and alert warble. In SILENT status only the LED output is
active.
1997 Mar 04
Duplicate Call Suppression
When detecting an out-of-range condition and enabled by
programming of SPF15, the LED output provides an
out-of-range indication as shown in Fig.12.
16
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
The LED output can be made to provide message data by
programming SPF17. Alert signals are inhibited during
message data transfer.
When changing from OFF to SILENT status, the start-up
alert will be indicated on the LED output and the vibrator
output OM.
AL
AH
OL
AL
OL
OM
t RCR
t RPT
MCD462
t
Fig.11 Repeat alert cadence.
MCD464
SUA
Fig.13 Start-up alert.
7.12
Serial communication interface
To transmit any call message data received to an external
microcontroller for post-processing, a serial
communication interface has been provided by a serial
data output signal DO and a data strobe signal DS as
shown in Fig.14.
t
ORD
t
ORA
Upon interrogation the PCF5001 is also able to transfer
EEPROM contents via the serial communication interface,
see Section 7.21.
MCD463
Fig.12 Out-of-range indication.
7.10
7.13
The transfer of message data via DO and DS is organized
in 8-bit words providing additional start and stop conditions
as shown in Fig.15.
Vibrator output
The PCF5001 provides the OM output for activating a
vibrator-type alerter for call alert indication. The vibrator
output is enabled by programming of SPF11.
On reception of a valid call address the PCF5001
generates a start condition and outputs an address word
as shown in Fig.15a.
Calls received while operating in SILENT status cause
activation of the vibrator output for the normal call alert
cadence or until terminated by operation of the status
request and reset input (SR). SILENT override calls, calls
received in decoder ON status and repeated call alerts are
alerted normally by the AL and AH outputs.
7.11
The address word indicates call address, function bit
setting and decoder flags as shown in Table 4.
Message codewords received and concatenated to a valid
call address are transferred after completion of the
address word. The message bits received in the message
codewords are split into blocks and are converted to obtain
the message words. The message words comprise an
error flag to indicate message words, which are derived
from uncorrectable message codewords as shown in
Table 5.
Start-up alert
To indicate the establishment of operational condition
whenever the decoder status has been changed from OFF
to ON or SILENT status, the PCF5001 provides a start-up
alert indication. Switching from OFF to ON status causes
generation of a start-up alert cadence at LOW-level and on
the LED output OL (see Fig.13).
1997 Mar 04
Message data transfer
Message data is output at a rate of 2048 bits/s with a
minimum delay of 2 bits between consecutive message
words.
17
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
Termination of call reception causes a termination word to
be transferred, which indicates successful or unsuccessful
call termination as shown in Table 6.
Serial data transfer for a received call ends with a stop
condition as shown in Fig.15c.
START OF TRANSFER
start condition
address word
A0
DO
A1
A2
1st message word
A3
A4
A5
A6
A7
DS
MESSAGE TRANSFER
message word N–1
message word N
message word N+1
Mn0 Mn1 Mn2 Mn3 Mn4 Mn5 Mn6 Mn7
DO
DS
END OF TRANSFER
last message word
DO
termination word
T0
T1
T2
T3
T4
T5
stop condition
T6
T7
DS
MEA254 - 1
Fig.14 Call data transfer on the serial communication interface.
1997 Mar 04
18
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
handbook, full pagewidth
DO
DS
t DOS
t ST
a.
DO
DS
t DSW
t TDO
t DOH
t DOS
t DSD
b.
DO
DS
t
DOH
t
SP
c.
a. Start condition.
b. Data bit.
c. Stop condition.
Fig.15 Serial communication interface timing.
1997 Mar 04
19
MEA253 - 2
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.14
PCF5001
(respectively 1 and 0). The data format is shown in Fig.16.
No alert signals will appear on OL during message data
transfer. Consecutive message words have a minimum
separation of 1 start bit and 1 stop bit.
Call Data output on LED
When enabled by programming of SPF17 = 1, message
data will appear on the LED output OL. The data format
and timing are equal to the signal on DO, except that the
start/stop conditions are replaced with start/stop bits
START OF TRANSFER
address word
A1
A2
A3
A4
A5
A6
A7
stop bit
start bit
A0
start bit
OL
1st message word
MESSAGE TRANSFER
message word N–1
message word N
message word N 1
stop bit
start bit
stop bit
start bit
Mn0 Mn1 Mn2 Mn3 Mn4 Mn5 Mn6 Mn7
OL
END OF TRANSFER
last message word
termination word
T2
T3
T4
T5
T6
start bit
stop bit
T1
Fig.16 Call data transfer on the LED output.
1997 Mar 04
T7
stop bit
T0
OL
20
MEA255 - 1
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.15
PCF5001
Serial communication call data format
Table 4
Address word format
FUNCTION CODE
CALL ADDRESS
SYNC STATUS
DUPLEX CALL
BIT 5
BIT 6
0 = Data
Receive;
1 = Data fail
1 = Duplex Call
time-out active
BIT 4
BIT 0 (LSB)
BIT 1 (MSB)
BIT 2
BIT 3
RIC
Bit 21 of
address
codeword
bit 20 of
address
codeword
0
0
A
0
1
B
1
0
C
1
1
D
Table 5
1
BIT 7
0
Message word format
BIT 0
BIT 1
BIT 2
LSB
BIT 3
BIT 4
BIT 5
message bits
BIT 6
BIT 7(1)
MSB
error flag
Note
1. Bit 7 = 1, if message codeword could not be corrected.
Table 6
Termination word format
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7(1)
0
0
1
0
0
0
0
error flag
Note
1. Bit 7 = 1, if call termination on error.
7.16
into message blocks, seven bits in length. After adding the
error flag they are transferred as message words.
Data conversion
The PCF5001 automatically converts message codewords
received in numeric or alphanumeric format into ASCII
format. Depending on SPF13 and the function bit setting in
the received address codeword a conversion takes place
as shown in Table 7.
When a conversion from numeric format to ASCII takes
place, the received message codewords are split into
blocks, four bits in length. Each four bit block is converted
to a seven bit block as shown in Table 8. After adding the
error flag they are transferred as message words.
When a conversion from alphanumeric format to ASCII
takes place, the received message codewords are split
Table 7
Message data conversion
FUNCTION BITS
SPF13
MESSAGE FORMAT
BIT 20 (MSB)
BIT 21 (LSB)
0
X(1)
X(1)
numeric
1
0
0
numeric
1
X(1)
1
alphanumeric
1
1
X(1)
alphanumeric
Note
1. X = don’t care.
1997 Mar 04
21
Philips Semiconductors
Product specification
POCSAG Paging Decoder
Table 8
PCF5001
Numeric format to ASCII conversion
4-BIT BLOCK
7-BIT BLOCK
CHARACTER
LSB
MSB
LSB
MSB
0
0
0
0
‘0’
0
0
0
0
1
1
0
1
0
0
0
‘1’
1
0
0
0
1
1
0
0
1
0
0
‘2’
0
1
0
0
1
1
0
1
1
0
0
‘3’
1
1
0
0
1
1
0
0
0
1
0
‘4’
0
0
1
0
1
1
0
1
0
1
0
‘5’
1
0
1
0
1
1
0
0
1
1
0
‘6’
0
1
1
0
1
1
0
1
1
1
0
‘7’
1
1
1
0
1
1
0
0
0
0
1
‘8’
0
0
0
1
1
1
0
1
0
0
1
‘9’
1
0
0
1
1
1
0
0
1
0
1
‘*’
0
1
0
1
0
1
0
1
1
0
1
‘U’
1
0
1
0
1
0
1
0
0
1
1
‘’
0
0
0
0
0
1
0
1
0
1
1
‘−’
1
0
1
1
0
1
0
0
1
1
1
‘]’
1
0
1
1
1
0
1
1
1
1
1
‘[’
1
1
0
1
1
0
0
7.17
Memory Organization
The PCF5001 POCSAG decoder contains non-volatile
EEPROM memory to store four user addresses, two frame
numbers and specially programmed function bits (SPF01
to SPF32) for decoder application configuration.
The EEPROM is organized as three arrays of 38 bits each
as shown in Fig.17.
A user address (or RIC) in POCSAG code comprises of
21 bits, but the three least significant bits are coded in the
frame number and therefore not explicitly transmitted. In
the PCF5001, addresses A/B and C/D must share the
same frame number: addresses A and B reside in frame
FR1 (FR10, FR11 and FR12), addresses C and D reside
in frame FR2 (FR20, FR21 and FR22). Figure 18 shows an
example of decimal address to EEPROM content
conversion. Each address must be explicitly enabled by
resetting of the associated enable bit.
1997 Mar 04
22
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
EEPROM ARRAY 1
BIT18 BIT17 BIT16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10
A17
A16
A15
A14
A13
A12
A11
A10
A09
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
A08
A07
A06
A05
A04
A03
A02
A01
A00
ENA
BIT37 BIT36 BIT35 BIT34 BIT33 BIT32 BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 BIT25 BIT24 BIT23 BIT22 BIT21 BIT20 BIT19
B17
B16
B15
B14
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
ENB
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
C08
C07
C06
C05
C04
C03
C02
C01
C00
___
ENC
EEPROM ARRAY 2
BIT18 BIT17 BIT16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10
C17
C16
C15
C14
C13
C12
C11
C10
C09
BIT37 BIT36 BIT35 BIT34 BIT33 BIT32 BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 BIT25 BIT24 BIT23 BIT22 BIT21 BIT20 BIT19
D17
D16
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
END
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SPF13 SPF12 SPF11 SPF10 SPF09 SPF08 SPF07 SPF06 SPF05 SPF04 SPF03 SPF02 SPF01 FR20
FR21
FR22
FR10
FR11
FR12
EEPROM ARRAY 3
BIT18 BIT17 BIT16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10
BIT37 BIT36 BIT35 BIT34 BIT33 BIT32 BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 BIT25 BIT24 BIT23 BIT22 BIT21 BIT20 BIT19
SPF32 SPF31 SPF30 SPF29 SPF28 SPF27 SPF26 SPF25 SPF24 SPF23 SPF22 SPF21 SPF20 SPF19 SPF18 SPF17 SPF16 SPF15 SPF14
MCD469
A00 represents the MSB of RIC A, B00 is the MSB of RIC C, etc.
FR10 represents the MSB of Frame 1 (valid for RICs A and B), FR20 is the MSB of Frame 2 (RICs C and D).
Fig.17 EEPROM memory organization.
1997 Mar 04
23
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
address decimal value
(example: RIC A)
RIC A = 1 2 4 6 8
binary equivalent (18 + 3 bit available)
000000011000010110100
EEPROM Allocation
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
FR10 FR11 FR12
1
0
0
MCD470
A00 is the MSB of RIC A, FR10 is the MSB of Frame 1.
Fig.18 Decimal address to memory contents conversion example.
7.18
Description of the Special Programmed Function (SPF) bits
The following features can be selected by appropriate programming of the special programmed function bits as shown
in Table 9.
Table 9
Special Programmed Function (SPF) bits
SPF
SPF01
SPF02
SPF03
BIT
0
Alert-only pager mode.
1
Display pager mode.
0
512 bits/s data rate.
1
1200 bits/s data rate, possible with 76.8 kHz crystal only.
0
32768 Hz crystal configuration.
1
76800 Hz crystal configuration.
SPF04, SPF05
1997 Mar 04
FUNCTION
Receiver establishment time (depending on data rate).
00
7.8 ms/512 bits/s; 53.3 ms/1200 bits/s.
01
15.6 ms/512 bits/s; 6.7 ms/1200 bits/s.
10
31.3 ms/512 bits/s; 13.3 ms/1200 bits/s.
11
62.5 ms/512 bits/s; 26.7 ms/1200 bits/s.
24
Philips Semiconductors
Product specification
POCSAG Paging Decoder
SPF
BIT
SPF06, SPF07
SPF08
SPF09
SPF10
SPF11
SPF12
SPF13
SPF14
SPF15
SPF16
SPF17
SPF18
PCF5001
FUNCTION
Duplicate call suppression time-out and out-of-range hold-off time-out.
00
30 s.
01
60 s.
10
120 s.
11
240 s.
0
Voltage converter disabled, if SPF01 = 1 (‘display pager’ mode).
1
Voltage converter enabled, if SPF01 = 1 (‘display pager’ mode).
0
SILENT override on address C disabled.
1
SILENT override on address C enabled.
0
SILENT override on address D disabled.
1
SILENT override on address D enabled.
0
Vibrator output disabled.
1
Vibrator output enabled.
0
Call termination criteria combination method (note 1).
1
Call termination criteria defined by SPF13.
0
Numeric data deformatting, call termination on first uncorrectable codeword.
1
Numeric data deformatting on function code 00 only, call termination on two
uncorrectable codewords.
0
Duplicate call suppression disabled.
1
Duplicate call suppression enabled.
0
Out of range indication at OL output disabled, hold-off period is zero regardless
of SPF06 and SPF07 setting.
1
Out of range indication at OL output enabled, hold-off period is according to
SPF06 and SPF07 setting.
0
Repeat alert disabled.
1
Repeat alert enabled.
0
Call data output on OL disabled.
1
Call data output on OL enabled.
−
Spare.
SPF19
−
Program always 0.
SPF20 to SPF30
−
Spares.
SPF31
0
Alerter frequency 2048 Hz.
1
Alerter frequency 2731 Hz.
0
Frequency reference output 16384 Hz if SPF01 = 1 (‘display pager’ mode).
1
Frequency reference output 32768 Hz if SPF01 = 1 (‘display pager’ mode).
SPF32
Note
1. Call termination on:
a) First codeword immediately following address codeword uncorrectable.
b) Two consecutive codewords uncorrectable.
1997 Mar 04
25
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.19
PCF5001
EEPROM Write operation
7.21
The program mode is entered in OFF status by setting the
PD input LOW and the PS input HIGH at any time.
The ‘program’ mode is left and normal operation resumed
by either removing the power supply or setting the PD
input HIGH after the 38th data bit while continuing to clock
the PS input. The three EEPROM arrays can be
programmed in any order. Selection of array is made
during the second and third pulse on the PS input.
The ‘program’ mode has to be left after programming of
each array.
In ‘display pager’ mode, the PCF5001 is capable of
delivering the EEPROM contents to an external
microcontroller using the serial interface outputs DO and
DS. The EEPROM data transfer mode is selected by
applying a LOW to input ON and a HIGH to input SK while
pulsing the SR input, and the interface is enabled (IE is
HIGH). The data transfer is started by a logic HIGH level
on SR. The HIGH level on SR must be removed before the
end of the tenth output byte, otherwise the transfer is
aborted and restarted. The minimum pulse duration
corresponds with tSPD in the status interrogation timing
(see Fig.7). The transfer is organized as 15-byte transfers.
The contents of each array are extended to 40 bits by
trailing zeros. The EEPROM data transfer starts with array
1, bit 0. A valid data bit at DO is indicated by a LOW-level
on DS as shown in Fig.20.
After entering the ‘program’ mode, keeping input PD LOW
during the first pulse on PS selects Memory Write
operation. After selection of the current array an erase
cycle of duration tPEW has to be carried out, during which
the supply voltage at VSS input must be at least VPG.
Program data for the selected array is entered bit by bit
using PD as data input and the rising edge on PS as data
strobe pulse. See Fig.19 for timing during an EEPROM
write operation.
During EEPROM Read-back operation, the PCF5001
configuration and the outputs FL, OL are undefined.
After completion of the Read-Back operation, the
PCF5001 will re-enter the programmed configuration.
After the last bit a special write cycle of duration tPEW has
to be carried out again, during which the supply voltage at
VSS input must be VPG. During conditions when the supply
voltage is increased to VPG the maximum DC ratings at Vref
must not be exceeded. When the on-chip voltage
converter is enabled a voltage regulator diode or a
damping resistor of sufficiently low impedance has to be
connected between Vref and VSS to limit the voltage level
at Vref during program operation.
7.20
7.22
Voltage converter
The PCF5001 contains a switched capacitor-type on-chip
voltage converter, which can provide doubled supply
voltage to the external microcontroller and display control
devices. The microcontroller interface signals are level
shifted accordingly.
A capacitor of 100 nF (CS) must be connected between
pins CP and CN while a load capacitor of 10 µF is
connected to Vref as shown in Fig.23. The voltage
converter operates in ‘display pager’ mode only, when
enabled by programming SPF08 (see Table 9).
EEPROM Read operation
After entrance to the ‘program’ mode, keeping input PD
HIGH during the first pulse on PS selects Memory Read
operation. After selection of the current array the
programmed data is output bit-by-bit using PD as data
output. A positive edge on PS input switches to the next
bit. See Fig.19 for timing during an EEPROM read
operation.
1997 Mar 04
Read-back operation via Microcontroller
Interface
26
1997 Mar 04
27
PS
PD
PS
PD
t RES
t RES
1
2
t PSI
2
SEL0
t PSI
READ
1
WRITE SEL0
t PDH
3
SEL1
t PDH
3
SEL1
t PRS
4
4
t PCL
7
BIT2
t PCL
5
BIT0
7
BIT2
42
BIT37
t PCH
41
t PCH
6
BIT1
43
42
44
BIT37
45
t PEW
1.5 MHz
44
MCD471 - 2
43
45
POCSAG Paging Decoder
Fig.19 EEPROM read/write timing.
6
BIT1
t PSO
5
BIT0
t PEW
1.5 MHz
Philips Semiconductors
Product specification
PCF5001
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
SR
ENA
DO
B17
ENC
D17
FR12
SPF
32
DS
MCD472
t SDD
t DSE
Fig.20 EEPROM data transfer to microcontroller timing.
7.23
Test modes of the decoder
7.23.2
PAGER TEST MODE (TYPE APPROVAL MODE)
The decoder supports two test modes, which are intended
for use during pager production and type approval tests.
‘Pager test’ mode is entered by reception of a valid call
while ‘board test’ mode is active, see above. In ‘pager test’
mode:
7.23.1
1. Call alert cadences are terminated after 2 seconds
BOARD TEST MODE
‘Board test’ mode is selected by setting the PD input LOW
at any time. In this test mode the following features are
provided:
2. Duplicate call suppression is disabled.
Exit from ‘pager test’ mode is achieved by disconnecting
the power supply from the decoder.
1. Receiver enable output is set constantly HIGH
2. Output AL is activated by a LOW-level on ON input
3. Output AH is activated by a HIGH-level on SR input
4. Outputs OL and OM are activated by a HIGH-level on
SK input.
Exit from ‘board test’ mode is achieved by setting input PD
HIGH.
1997 Mar 04
28
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VSS
supply voltage
+0.5
−8.0
V
VPG
programming supply voltage
−5.5
−
V
Vn
voltage on pins FL, DS, DO, OR, BL,
AI, ON, SK, SR and IE
+0.8
Vref − 0.8
V
note 1
Vn1
input voltage on any other pin
+0.8
VSS − 0.8
V
Ptot
total power dissipation
−
250
mW
PO
power dissipation per output
−
100
mW
II(max)
maximum input current (any input)
−
10
mA
IO(max)
maximum output current
any output except AL
−
20
mA
output AL
−
70
mA
Tamb
operating ambient temperature
−40
+85
°C
Tstg
storage temperature
−55
+125
°C
Note
1. VDD is connected to the substrate (see Fig.1), and is referred to as common, 0 V.
9 DC CHARACTERISTICS
VDD = 0 V; VSS = −2.7 V; Vref = 2.7 V; Tamb = 25 °C; unless otherwise specified.
Quartz crystal parameters: f = 76800 Hz; RS(max) = 40 kΩ; CL = 12 pF.
Decoder Mode programmed as Alert-only (SPF01 = 0).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VSS
supply voltage
voltage converter disabled;
all outputs open-circuit
Tamb = −10 to +85 °C
−1.5
−2.7
−6.0
V
Tamb = −40 to +85 °C
−1.8
−2.7
−6.0
V
µA
ISS
supply current
note 1
−
−60
−100
VPG
programming supply voltage
note 2
−4.5
−5.0
−5.5
V
IPG
programming supply current
−
−500
−
µA
1997 Mar 04
29
Philips Semiconductors
Product specification
POCSAG Paging Decoder
SYMBOL
PCF5001
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Inputs
VIL1
LOW level input voltage
PD, PS, DI, BS, TS, TT and X1
0.7VSS
−
−
V
VIL2
LOW level input voltage AI, ON,
SR, SK and IE
0.7Vref
−
−
V
VIH1
HIGH level input voltage
PD, PS, DI, BS, TS, TT and X1
−
−
0.3VSS
V
VIH2
HIGH level input voltage
AI, ON, SR, SK and IE
−
−
0.3Vref
V
II
input current
Ci
BS, PS, TS and TT
VI = VDD
7.0
−
20.0
µA
PD
VI = VSS
−9.0
−
−24.0
µA
DI
VI = VDD; RE = 0
7.0
−
20.0
µA
DI
VI = VDD; RE = 1
0
−
0.5
µA
ON and SK
VI = VSS
−0.5
−0.8
−1.1
µA
AI and SR
VI = VDD
7.0
−
20.0
µA
2
−
−
pF
100
−
−
µA
input capacitance BS, DI, PD,
PS, TS, TT, AI, ON, SR, SK, IE
and X1
Outputs
IOL
IOH
LOW level output current
OL, OM and AH
VOL = −1.35 V
DO, DS, BL, FL and OR
VOL = −1.35 V
100
−
−
µA
AL
VOL = −1.5 V
17.5
−
−
mA
RE
VOL = 2.2 V
200
−
−
µA
OL, OM and AH
VOH = −1.35 V
−0.8
−
−1.8
mA
DO, DS, BL, FL and OR
VOH = −1.35 V
−100
−
−
µA
AL
AL high-impedance
−
−
−0.2
µA
RE
VOH = −0.5 V
−1.0
−
−
mA
−
40
−
pF
VSS = −1.5 V
15
29
43
µS
VSS = −6.0 V
25
39
55
µS
−
−1.2
−
V
HIGH level output current
Oscillator
CXO
output capacitance X2
gm
oscillator transconductance
VPU
power-up reset threshold
voltage
Notes
1. All inputs = VSS; voltage converter off; all outputs open-circuit.
2. See Section 7.19 and Chapter 8 for limitations of Vref when programming while the voltage converter is enabled.
1997 Mar 04
30
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
10 DC CHARACTERISTICS (WITH VOLTAGE CONVERTER)
VDD = 0 V; VSS = −3.0 V; Vref = −6.0 V; Tamb = 25 °C.
Quartz crystal parameters: f = 76800 Hz; RS(max) = 40 kΩ; CL = 12 pF.
Decoder Mode programmed as Display Pager (SPF01 = 1).
Voltage converter enabled (SPF08 = 1); CS = 100 nF.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VSS
supply voltage
−1.5
−
−3.0
V
Voltage converter
Vref(0)
output voltage; no load
VSS = −3.0 V
−5.8
−
−6.0
V
Vref
output voltage
VSS = −2.0 V; Iref = 250 µA
−3.0
−3.5
−
V
Iref
output current
VSS = −2.0 V; Vref = −2.7 V
400
600
−
µA
VSS = −3.0 V; Vref = −4.5 V
600
900
−
µA
AI, ON, SR and SK
VI = Vref
−
0
−0.5
µA
ON and SK
VI = VDD
−
0
±0.5
µA
SR
VI = VDD; Vref = −6.0 V
−
17
−
µA
Inputs
II
input current
11 AC CHARACTERISTICS
VDD = 0 V; VSS = −2.7 V; Tamb = 25 °C.
Quartz crystal parameters: f = 32768 or 76800 Hz; RS(max) = 40 kΩ; CL = 12 pF.
Decoder Mode programmed as Display or Alert-only Pager (SPF01 = 1 or 0).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Alert frequency
fAL
alert frequency
−
2048
−
Hz
fAWH
high alert warble frequency
−
1024
−
Hz
fAWL
low alert warble frequency
−
16
−
Hz
fAL
alert frequency
−
2731
−
Hz
fAWH
high alert warble frequency
−
1365
−
Hz
fAWL
low alert warble frequency
−
16
−
Hz
fFL
output frequency reference at FL
SPF32 = 0
−
16384
−
Hz
SPF32 = 1
−
32768
−
Hz
1997 Mar 04
SPF31 = 0
SPF31 = 1
31
Philips Semiconductors
Product specification
POCSAG Paging Decoder
SYMBOL
PARAMETER
PCF5001
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Call alert duration
tALT
time-out period
−
16
−
s
tALL
alert time LOW (AL output only)
−
4
−
s
tALH
alert time HIGH (AH and AL outputs)
−
12
−
s
tALC
call alert cycle time
see Fig.9
−
1
−
s
tALP
call alert pulse duration
see Fig.9
−
125
−
ms
tALD
call alert hold off period
see Fig.8
52
−
−
ms
tRPT
repeat alert duration
see Fig.11
−
−
4
s
tRCR
repeat alert recurrence time
see Fig.11
−
−
15
s
tRCP
repeat alert cycle time
−
−
500
ms
tRPD
repeat alert pulse duration
−
−
250
ms
tSTON
status alert time
see Fig.10
−
−
62.5
ms
tSTOF
status alert delay
see Fig.10
−
−
62.5
ms
tSUA
start-up alert time
SPF02 = 0; see Fig.13
−
−
500
ms
SPF02 = 1; see Fig.13
−
−
453
ms
tORA
out-of-range alert pulse width
see Fig.12
−
−
62.5
ms
tORD
out-of-range alert time
see Fig.12
−
−
2
s
tBLAL
battery LOW-level alert time
−
−
16
s
Receiver control
tRXT
RE transition time
CL = 5 pF
−
−
100
ns
tRXON
RE establishment time
SPF04 = 0; SPF05 = 1
−
7.8
62.5
ms
−
2048
−
bits/s
Data output
fDO
data output rate
tDSD
strobe period call data
see Fig.15
480
−
495
µs
tDSE
strobe period EEPROM data
see Fig.20
200
488
1150
µs
tDSW
data strobe pulse width
see Fig.15
230
−
250
µs
tTDO
data output transition time
CL = 10 pF; see Fig.15
−
−
100
ns
tDOS
data output set-up time
see Fig.15
−
−
135
µs
tDOH
data output hold time
see Fig.15
115
−
−
µs
tBYD
consecutive byte delay
1210
−
1225
µs
tCWD
inter-codeword delay
1200 bits/s numeric message
3420
−
−
µs
tST
start condition set-up time
see Fig.15
4750
−
−
µs
tSP
stop condition set-up time
see Fig.15
595
−
615
µs
tSTL
start bit period OL output
480
−
495
µs
tSPL
stop bit period OL output
480
488
495
µs
tSDD
SPF output delay
1
−
10
ms
1997 Mar 04
see Fig.20
32
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
12 TIMING CHARACTERISTICS
VDD = 0 V; VSS = −2.7 V; Tamb = 25 °C.
Quartz crystal parameters: f = 32768 or 76800 Hz; RS(max) = 40 kΩ; CL = 12 pF.
Decoder Mode programmed as Display or Alert-only Pager (SPF01 = 1 or 0).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Operating frequency dependent
−
32768
−
fosc
oscillator frequency
SPF03 = 0
Hz
SPF03 = 1
−
76800
−
Hz
tTDI
data input transition time
see Fig.21
−
−
100
µs
tDI1
data input logic 1
see Fig.21
tBIT
−
∞
tDI0
data input logic 0
see Fig.21
tBIT
−
∞
fDI
data input rate
SPF02 = 0
−
512
−
bits/s
tBIT
bit period
−
1.9531
−
ms
tCW
codeword duration
−
62.5
−
ms
tPA
preamble duration
1125
−
−
ms
tBAT
batch duration
−
1062.5
−
ms
fDI
data input rate
−
1200
−
bits/s
tBIT
bit period
−
833.3
−
ms
tCW
codeword duration
−
26.7
−
ms
tPA
preamble duration
480
−
−
ms
tBAT
batch duration
−
453.3
−
ms
−
62.5
−
ms
35
−
−
µs
SPF02 = 1; fosc = 76800 Hz
Alert only mode (SPF01 = 0)
tSDB
switch debounce period
Display pager mode (SPF01 = 1); see Figs 6 and 7
tSTP
status set-up time
fosc = 32768 Hz
tSTD
status change delay
−
−
35
µs
tIEH
interface enable hold time
35
−
−
µs
tSTH
status hold time
35
−
−
µs
tSPD
status pulse duration
35
−
−
µs
tSTP
status set-up time
15
−
−
µs
tSTD
status change delay
−
−
15
µs
tIEH
interface enable hold time
15
−
−
µs
tSTH
status hold time
15
−
−
µs
tSPD
status pulse duration
15
−
−
µs
1997 Mar 04
fosc = 76800 Hz
33
Philips Semiconductors
Product specification
POCSAG Paging Decoder
handbook, halfpage
PCF5001
tDI1
tDI0
t TDI
MGL100
Fig.21 Data input timing.
13 PROGRAMMING CHARACTERISTICS
VDD = 0 V; VSS = VPG = −5.0 V (see notes 1, 2 and 3); Vref = VSS; pins 2 and 3 open-circuit; Tamb = 25 °C.
Quartz crystal parameters: f = 32768 Hz; RS(max) = 40 kΩ; CL = 12 pF.
Decoder in OFF status.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Programming; see Fig.19
tRES
power-up reset pulse width
tPEW
erase/write time
note 4
35
−
−
µs
10
−
−
ms
fEW
erase/write frequency
1.0
1.5
2.0
MHz
tEW
erase/write cycles
1000
10000
−
−
tDR
data retention time
Tamb = 85 °C
10
−
−
years
tPCH
data clock HIGH time
note 4
65
−
−
µs
tPCL
data clock LOW time
note 4
65
−
−
µs
tPRS
read set-up time
note 4
−
−
35
µs
tPSI
data set-up time on input
note 4
35
−
−
µs
tPSO
data set-up time on output
note 4
−
−
35
µs
tPDH
data hold time
note 4
35
−
−
µs
Notes
1. VSS = VPG only required during erase/write (tPEW in Fig.19), otherwise VSS(min) = −1.5 V.
2. Maximum voltage for programming (VPG) is −5.5 V.
3. See Section 7.19 and Chapter 8 for limitations of Vref when programming while the voltage converter is enabled.
4. EEPROM programming is also possible at higher frequencies (76.8 kHz or 153.6 kHz). The timings shown then
become proportionally smaller.
1997 Mar 04
34
antenna
1997 Mar 04
35
V EE
battery low
indicator
Rx control
data output
RECEIVER
VCC
BS
RE
DI
X2
PD
VDD
PS
VSS
PCF5001
IE
V REF
SR
SK
ON
OM
OL
AH
AL
SIL
ON
OFF
MLB046
1.5V
1.5V
POCSAG Paging Decoder
Fig.22 Alert-only pager application example.
32768 Hz
or
76800 Hz
X1
10 pF
status
reset
M
Philips Semiconductors
Product specification
PCF5001
14 APPLICATION INFORMATION
antenna
1997 Mar 04
36
V EE
battery low
indicator
Rx control
data output
RECEIVER
VCC
CS
100 nF
32768 Hz
or
76800 Hz
10 pF
VSS
OM OL
10 µF
V SS
switch matrix
MICRO
CONTROLLER
V DD
LCD
MLB047
1.5V
1.5V
POCSAG Paging Decoder
Fig.23 Display-pager application example.
AH
CP
PS
IE
V REF
CN
SR
ON
AI
BL
SK
PD
PCF5001
OR
DO
DS
FL
AL
BS
RE
DI
X2
X1
VDD
M
Philips Semiconductors
Product specification
PCF5001
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
15 PACKAGE OUTLINES
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
HE
v M A
Z
15
28
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
e
bp
0
detail X
w M
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.71
0.69
0.30
0.29
0.050
0.42
0.39
0.055
0.043
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
inches
0.10
Z
(1)
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT136-1
075E06
MS-013AE
1997 Mar 04
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
91-08-13
95-01-24
37
o
8
0o
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
24
A
17
25
16
ZE
e
Q
E HE
A A2 A
1
(A 3)
wM
θ
bp
Lp
L
pin 1 index
32
9
detail X
8
1
e
ZD
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.4
0.3
0.18
0.12
7.1
6.9
7.1
6.9
0.8
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.69
0.59
0.2
0.25
0.1
Z D (1) Z E (1)
0.9
0.5
0.9
0.5
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
93-06-29
95-12-19
SOT358 -1
1997 Mar 04
EUROPEAN
PROJECTION
38
o
7
0o
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
16 SOLDERING
16.3.2
16.1
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
16.2
16.3.3
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
16.4
Wave soldering
LQFP
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
1997 Mar 04
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
16.3.1
METHOD (LQFP AND SO)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP and
SO packages.
16.3
SO
39
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
17 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Mar 04
40
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
NOTES
1997 Mar 04
41
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
NOTES
1997 Mar 04
42
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
NOTES
1997 Mar 04
43
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
437027/00/05/pp44
Date of release: 1997 Mar 04
Document order number:
9397 750 01626