PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PCI Bus Power Management Interface Pipelined Architecture Allows Greater Than Specification 1.0 Compliant ACPI 1.0 Compliant Fully Compatible With the Intel 430TX (Mobile Triton II) Chipset Packaged in a 208-Pin Low-Profile QFP (PDV) or GHK High Density Ball Grid Array (BGA) PCI Local Bus Specification Revision 2.2 Compliant 1997 PC Card Standard Compliant PC 99 Compliant 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments Mix-and-Match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards Supports Two PC Card or CardBus Slots With Hot Insertion and Removal Uses Serial Interface to TI TPS2202/2206 Dual-Slot PC Card Power Switch Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and CardBus Bus Supports Parallel PCI Interrupts, Parallel ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID 130-MBps Throughput From CardBus-to-PCI and From PCI-to-CardBus Supports up to Five General-Purpose I/Os Programmable Output Select for CLKRUN Multifunction PCI Device With Separate Configuration Space for Each Socket Five PCI Memory Windows and Two I/O Windows Available for Each R2 Socket Two I/O Windows and Two Memory Windows Available to Each CardBus Socket Exchangeable Card Architecture (ExCA) Compatible Regesters Are Mapped in Memory and I/O Space Intel 82365SL-DF Register Compatible Supports Distributed DMA (DDMA) and PC/PCI DMA Supports 16-Bit DMA on Both PC Card Sockets Supports Ring Indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN LED Activity Pins Supports PCI Bus Lock (LOCK) Advanced Submicron, Low-Power CMOS Technology Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Name/Terminal Number Sort Tables . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clamping Rail Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . . . 23 PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . . 46 ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . 83 CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . . . . . Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements (Memory Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements (I/O Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics (Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 114 119 120 121 122 122 123 124 125 126 126 127 128 129 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel is a trademark of Intel Corporation. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 description The TI PCI1225 is a high-performance PCI-to-PC Card controller that supports two independent card sockets compliant with the 1997 PC Card Standard. The PCI1225 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2 and defines the new 32-bit PC Card (CardBus), capable of full 32-bit data transfers at 33 MHz. The PCI1225 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required. The PCI1225 is compliant with the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1225 is also compliant with the latest PCI Bus Power Management Interface Specification. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1225 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1225 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architacture provide an unsurpassed performance level with sustained bursting. The PCI1225 can also be programmed to accept fast posted writes to improve system-bus utilization. Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1225, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification. An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption. Unused PCI1225 inputs must be pulled up using a 43-k resistor. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 system block diagram A simplified block diagram of the PCI1225 is provided below. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface terminals include multifunction terminals: SUSPEND, RI_OUT/PME (power management control signal), and SPKROUT. PCI Bus INTA Activity LEDs TPS2206 Power Switch 3 IRQSER PCI1225 INTB PCI950 IRQSER Deserializer Interrupt Controller IRQ2–15 3 PC Card Socket A 68 Zoom Video 68 23 PC Card Socket B 23 19 VGA Controller PCI930 ZV Switch Zoom Video External ZV Port 4 Audio Subsystem NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals to the VGA controller and audio subsystem. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 terminal assignments 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 SUSPEND MFUNC1 MFUNC0 GND DATA CLOCK LATCH SPKROUT VCCI A_CAD31 A_RSVD A_CAD30 A_CAD29 VCC A_CAD28 A_CAD27 A_CCD2 A_CCLKRUN A_CSTSCHG A_CAUDIO A_CSERR A_CINT A_CVS1 A_CAD26 A_CAD25 A_CAD24 A_CC/BE3 GND A_CAD23 A_CREQ A_CAD22 A_CAD21 A_CRST A_CAD20 A_CVS2 A_CAD19 VCCA A_CAD18 A_CAD17 A_CC/BE2 A_CFRAME A_CIRDY A_CTRDY VCC A_CCLK A_CDEVSEL A_CGNT A_CSTOP A_CPERR A_CBLOCK A_CPAR A_RSVD PDV LOW-PROFILE QUAD FLAT PACKAGE TOP VIEW 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Card A PCI PCI1225 Core Card B 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 AD10 AD9 AD8 C/BE0 AD7 VCC AD6 AD5 AD4 AD3 AD2 GND AD1 AD0 B_CCD1 B_CAD0 B_CAD2 B_CAD1 B_CAD4 B_CAD3 GND B_CAD6 B_CAD5 B_RSVD B_CAD7 B_CAD8 B_CC/BE0 B_CAD9 B_CAD10 VCC B_CAD11 B_CAD13 B_CAD12 B_CAD15 B_CAD14 B_CAD16 VCCB B_CC/BE1 B_RSVD B_CPAR B_CBLOCK B_CPERR GND B_CSTOP B_CGNT B_CDEVSEL B_CCLK B_CTRDY B_CIRDY B_CFRAME B_CC/BE2 V CCP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 C/BE3 RI_OUT/PME VCC AD25 PRST GND GNT REQ AD31 AD30 AD11 AD29 AD28 VCC AD27 AD26 V CCP AD24 PCLK GND IDSEL AD23 AD22 AD21 AD20 VCC AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR VCC PAR C/BE1 AD15 AD14 AD13 GND AD12 PCI-to-CardBus Terminal Diagram 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A_CC/BE1 A_CAD16 A_CAD14 A_CAD15 A_CAD12 A_CAD13 A_CAD11 A_CAD10 GND A_CAD9 A_CC/BE0 A_CAD8 A_CAD7 A_RSVD A_CAD5 A_CAD6 A_CAD3 A_CAD4 VCC A_CAD1 A_CAD2 A_CAD0 A_CCD1 B_CAD31 B_RSVD B_CAD30 B_CAD29 B_CAD28 B_CAD27 GND B_CCD2 B_CCLKRUN B_CSTSCHG B_CAUDIO B_CSERR B_CINT B_CVS1 B_CAD26 B_CAD25 B_CAD24 VCC B_CC/BE3 B_CAD23 B_CREQ B_CAD22 B_CAD21 B_CRST B_CAD20 B_CVS2 B_CAD19 B_CAD18 B_CAD17 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 terminal assignments (continued) Card A PCI PCI1225 Core Card B 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 A_A8 A_A17 A_A9 A_IOWR A_A11 A_IORD A_OE A_CE2 GND A_A10 A_CE1 A_D15 A_D7 A_D14 A_D6 A_D13 A_D5 A_D12 VCC A_D4 A_D11 A_D3 A_CD1 B_D10 B_D2 B_D9 B_D1 B_D8 B_D0 GND B_CD2 B_WP(IOIS16) B_BVD1(STSCHG/RI) B_BVD2(SPKR) B_WAIT B_READY(IREQ) B_VS1 B_A0 B_A1 B_A2 VCC B_REG B_A3 B_INPACK B_A4 B_A5 B_RESET B_A6 B_VS2 B_A25 B_A7 B_A24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 V CCP AD10 AD9 AD8 C/BE0 AD7 VCC AD6 AD5 AD4 AD3 AD2 GND AD1 AD0 B_CD1 B_D3 B_D11 B_D4 B_D12 B_D5 GND B_D13 B_D6 B_D14 B_D7 B_D15 B_CE1 B_A10 B_CE2 VCC B_OE B_IORD B_A11 B_IOWR B_A9 B_A17 V CCB B_A8 B_A18 B_A13 B_A19 B_A14 GND B_A20 B_WE B_A21 B_A16 B_A22 B_A15 B_A23 B_A12 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 C/BE3 RI_OUT/PME VCC AD25 PRST GND GNT REQ AD31 AD30 AD11 AD29 AD28 VCC AD27 AD26 V CCP AD24 PCLK GND IDSEL AD23 AD22 AD21 AD20 VCC AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR VCC PAR C/BE1 AD15 AD14 AD13 GND AD12 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 SUSPEND MFUNC1 MFUNC0 GND DATA CLOCK LATCH SPKROUT VCCI A_D10 A_D2 A_D9 A_D1 VCC A_D8 A_D0 A_CD2 A_WP(IOIS16) A_BVD1(STSCHG/RI) A_BVD2(SPKR) A_WAIT A_READY(IREQ) A_VS1 A_A0 A_A1 A_A2 A_REG GND A_A3 A_INPACK A_A4 A_A5 A_RESET A_A6 A_VS2 A_A25 VCCA A_A7 A_A24 A_A12 A_A23 A_A15 A_A22 VCC A_A16 A_A21 A_WE A_A20 A_A14 A_A19 A_A13 A_A18 PDV LOW-PROFILE QUAD FLAT PACKAGE TOP VIEW PCI-to-PC Card (16-Bit) Terminal Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 terminal assignments (continued) GHK PLASTIC BALL GRID ARRAY BOTTOM VIEW W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 signal names and terminal assignments Table 1 and Table 2 show the terminal assignments for the CardBus PC Card; Table 3 and Table 4 show the terminal assignments for the 16-bit PC Card; Table 1 and Table 3 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the associated GHK package terminal number; and Table 2 and Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name and its associated terminal numbers. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 1. CardBus PC Card Signal Names by GHK/PDV Terminal Number TERM. NO. GHK PDV D1 A4 1 208 E6 206 C6 202 F7 198 E8 194 A8 190 B9 186 C10 182 E11 178 A12 174 A13 170 A14 166 A15 162 E14 159 C15 158 A16 157 E3 2 C5 207 B5 205 A5 203 A6 199 A7 195 B8 191 C9 187 E10 183 F11 179 A11 175 E12 171 F12 167 C14 163 F13 160 E17 155 D19 156 F5 3 G6 4 E2 5 F6 204 B6 200 B7 196 C8 192 F9 188 F10 184 A10 180 B11 176 C12 172 C13 168 B14 164 B15 161 E18 153 F15 154 E1 6 SIGNAL NAME VCCP AD12 AD13 PAR STOP GND AD17 AD20 IDSEL VCCP AD28 AD31 PRST C/BE3 MFUNC4 MFUNC3 MFUNC2 AD10 GND AD14 C/BE1 PERR IRDY AD16 VCC AD23 AD24 VCC AD30 GND RI_OUT/PME MFUNC5 MFUNC1 SUSPEND AD9 AD8 C/BE0 AD15 SERR TRDY C/BE2 AD19 AD22 PCLK AD27 AD11 GNT VCC MFUNC6/CLKRUN GND MFUNC0 AD7 TERM. NO. GHK PDV F3 F2 7 8 E7 201 C7 197 F8 193 E9 189 A9 185 B10 181 C11 177 B12 173 B13 169 E13 165 G15 149 F14 152 E19 151 F17 150 F1 10 H6 11 G3 12 G5 9 G17 145 F18 148 F19 147 G14 146 G1 14 H5 15 H3 16 G2 13 H14 141 G18 144 G19 143 H15 142 H1 18 J1 19 J2 20 H2 17 J15 137 H17 140 H18 139 H19 138 J5 22 J6 23 K1 24 J3 21 J19 133 J14 136 J17 135 J18 134 K3 26 K5 27 K6 28 K2 25 SIGNAL NAME VCC AD6 VCC DEVSEL FRAME AD18 AD21 GND AD26 AD29 REQ AD25 SPKROUT DATA CLOCK LATCH AD4 AD3 AD2 AD5 A_CAD30 VCCI A_CAD31 A_RSVD AD1 AD0 B_CCD1 GND A_CAD27 A_CAD29 VCC A_CAD28 B_CAD2 B_CAD1 B_CAD4 B_CAD0 A_CAUDIO A_CCD2 A_CCLKRUN A_CSTSCHG GND B_CAD6 B_CAD5 B_CAD3 A_CAD26 A_CSERR A_CINT A_CVS1 B_CAD7 B_CAD8 B_CC/BE0 B_RSVD POST OFFICE BOX 655303 TERM. NO. GHK PDV K18 K14 129 132 K15 131 K17 130 L2 30 L3 31 L6 32 L1 29 L17 125 K19 128 L14 127 L15 126 M1 34 M2 35 M3 36 L5 33 M18 121 L18 124 L19 123 M19 122 M5 38 N1 39 N2 40 M6 37 N18 117 M17 120 M15 119 N19 118 N6 42 P1 43 P2 44 N3 41 N15 113 N17 116 M14 115 P19 114 P3 46 R1 47 P6 48 N5 45 R7 61 V7 65 V8 69 U9 73 V10 77 W11 81 R11 85 P12 89 U13 93 R13 97 P18 112 P17 111 SIGNAL NAME GND A_CAD25 A_CAD24 A_CC/BE3 B_CAD10 VCC B_CAD11 B_CAD9 A_CAD21 A_CAD23 A_CREQ A_CAD22 B_CAD12 B_CAD15 B_CAD14 B_CAD13 A_CAD19 A_CRST A_CAD20 A_CVS2 VCCB B_CC/BE1 B_RSVD B_CAD16 A_CC/BE2 VCCA A_CAD18 A_CAD17 B_CBLOCK B_CPERR GND B_CPAR VCC A_CFRAME A_CIRDY A_CTRDY B_CGNT B_CDEVSEL B_CCLK B_CSTOP B_CREQ B_CAD24 B_CINT B_CCLKRUN B_CAD28 B_CAD31 A_CAD1 A_CAD6 A_CAD8 A_CAD10 A_CCLK A_CDEVSEL • DALLAS, TEXAS 75265 TERM. NO. GHK PDV R19 P5 110 50 R2 49 V5 57 V6 60 U7 64 U8 68 V9 72 W10 76 P10 80 P11 84 U12 88 V13 92 V14 96 P14 100 R18 109 N14 108 P15 107 T1 52 R3 51 P7 56 U6 59 P8 63 R8 67 W9 71 P9 75 R10 79 U11 83 V12 87 W13 91 W14 95 W15 99 V15 101 U15 103 R17 106 W4 53 U5 54 R6 55 W5 58 W6 62 W7 66 W8 70 R9 74 U10 78 V11 82 W12 86 R12 90 P13 94 U14 98 R14 102 W16 104 T19 105 SIGNAL NAME A_CGNT B_CIRDY B_CTRDY B_CAD20 B_CAD22 VCC B_CVS1 B_CSTSCHG B_CAD27 B_RSVD A_CAD2 A_CAD3 A_CAD7 GND A_CAD12 A_CSTOP A_CPERR A_CBLOCK B_CC/BE2 B_CFRAME B_CVS2 B_CAD21 B_CC/BE3 B_CAD26 B_CAUDIO GND B_CAD30 A_CAD0 A_CAD4 A_RSVD A_CAD9 A_CAD13 A_CAD15 A_CAD16 A_CPAR B_CAD17 B_CAD18 B_CAD19 B_CRST B_CAD23 B_CAD25 B_CSERR B_CCD2 B_CAD29 A_CCD1 VCC A_CAD5 A_CC/BE0 A_CAD11 A_CAD14 A_CC/BE1 A_RSVD 7 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 2. CardBus PC Card Signal Names Sorted Alphabetically SIGNAL NAME A_CAD0 A_CAD1 A_CAD2 A_CAD3 A_CAD4 A_CAD5 A_CAD6 A_CAD7 A_CAD8 A_CAD9 A_CAD10 A_CAD11 A_CAD12 A_CAD13 A_CAD14 A_CAD15 A_CAD16 A_CAD17 A_CAD18 A_CAD19 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD28 A_CAD29 A_CAD30 A_CAD31 A_CAUDIO A_CBLOCK A_CC/BE0 A_CC/BE1 A_CC/BE2 A_CC/BE3 A_CCD1 A_CCD2 A_CCLK A_CCLKRUN A_CDEVSEL A_CFRAME A_CGNT A_CINT A_CIRDY A_CPAR A_CPERR A_CREQ A_CRST A_CSERR 8 TERM. NO. GHK PDV U11 R11 83 85 P11 84 U12 V12 88 87 R12 90 P12 V13 89 92 U13 93 W14 R13 95 97 U14 98 P14 W15 100 99 R14 102 V15 101 U15 N19 103 118 M15 119 M18 L19 121 123 L17 125 L15 K19 126 128 K15 131 K14 J19 132 133 H14 141 H15 G18 142 144 G17 145 F19 J15 147 137 P15 107 P13 W16 94 104 N18 117 K17 130 V11 H17 82 140 P18 112 H18 P17 139 111 N17 116 R19 J17 110 135 M14 115 R17 N14 106 108 L14 127 L18 J14 124 136 SIGNAL NAME A_CSTOP A_CSTSCHG A_CTRDY A_CVS1 A_CVS2 A_RSVD A_RSVD A_RSVD AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 B_CAD0 B_CAD1 B_CAD2 B_CAD3 B_CAD4 B_CAD5 B_CAD6 B_CAD7 B_CAD8 B_CAD9 B_CAD10 B_CAD11 TERM. NO. GHK PDV R18 H19 109 138 P19 114 J18 M19 134 122 G14 146 W13 T19 91 105 H5 15 G1 G3 14 12 H6 11 F1 G5 10 9 F2 8 E1 6 G6 F5 4 3 E3 2 C12 A4 172 208 E6 206 B5 F6 205 204 B8 191 A8 E9 190 189 F9 188 B9 A9 186 185 F10 184 E10 F11 183 179 E13 165 C11 B11 177 176 A12 174 B12 173 E12 A13 171 170 H2 17 J1 H1 19 18 J3 21 J2 K1 20 24 J6 23 K3 K5 26 27 L1 29 L2 L6 30 32 POST OFFICE BOX 655303 SIGNAL NAME B_CAD12 B_CAD13 B_CAD14 B_CAD15 B_CAD16 B_CAD17 B_CAD18 B_CAD19 B_CAD20 B_CAD21 B_CAD22 B_CAD23 B_CAD24 B_CAD25 B_CAD26 B_CAD27 B_CAD28 B_CAD29 B_CAD30 B_CAD31 B_CAUDIO B_CBLOCK B_CC/BE0 B_CC/BE1 B_CC/BE2 B_CC/BE3 B_CCD1 B_CCD2 B_CCLK B_CCLKRUN B_CDEVSEL B_CFRAME B_CGNT B_CINT B_CIRDY B_CPAR B_CPERR B_CREQ B_CRST B_CSERR B_CSTOP B_CSTSCHG B_CTRDY B_CVS1 B_CVS2 B_RSVD B_RSVD B_RSVD C/BE0 C/BE1 C/BE2 C/BE3 TERM. NO. GHK PDV M1 L5 34 33 M3 36 M2 M6 35 37 W4 53 U5 R6 54 55 V5 57 U6 V6 59 60 W6 62 V7 W7 65 66 R8 67 W10 76 V10 U10 77 78 R10 79 W11 W9 81 71 N6 42 K6 N1 28 39 T1 52 P8 H3 63 16 R9 74 P6 U9 48 73 R1 47 R3 P3 51 46 V8 69 P5 N3 50 41 P1 43 R7 61 W5 W8 58 70 N5 45 V9 R2 72 49 U8 68 P7 K2 56 25 N2 40 P10 E2 80 5 A5 203 C8 A15 192 162 • DALLAS, TEXAS 75265 SIGNAL NAME CLOCK DATA DEVSEL FRAME GND GND GND GND GND GND GND GND GND GND GND GNT IDSEL IRDY LATCH MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6/CLKRUN PAR PCLK PERR PRST REQ RI_OUT/PME SERR SPKROUT STOP SUSPEND TRDY VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCB VCCI VCCP VCCP PIN NO. GHK PDV E19 F14 151 152 C7 197 F8 E8 193 194 C5 207 F12 E18 167 153 B10 181 G2 J5 13 22 K18 129 P2 V14 44 96 P9 75 C13 168 C10 A7 182 195 F17 150 F15 E17 154 155 A16 157 C15 E14 158 159 F13 160 B15 C6 161 202 A10 180 A6 A14 199 166 B13 169 C14 B6 163 200 G15 149 F7 D19 198 156 B7 196 C9 187 A11 B14 175 164 F3 7 E7 G19 201 143 L3 31 N15 U7 113 64 W12 86 M17 M5 120 38 F18 148 D1 E11 1 178 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 3. 16-Bit PC Card Signal Names by GHK/PDV Terminal Number TERMINAL NO. GHK TERMINAL NO. SIGNAL NAME PDV GHK PDV TERMINAL NO. SIGNAL NAME SIGNAL NAME GHK PDV VCC AD6 K18 129 GND K14 132 A_A1 K15 131 A_A2 K17 130 A_REG D1 1 7 208 VCCP AD12 F3 A4 F2 8 E6 206 AD13 E7 201 C6 202 PAR C7 197 VCC DEVSEL F7 198 STOP F8 193 FRAME L2 30 B_CE2 E8 194 GND E9 189 AD18 L3 31 A8 190 AD17 A9 185 AD21 L6 32 VCC B_OE B9 186 AD20 B10 181 GND L1 29 B_A10 C10 182 IDSEL C11 177 AD26 L17 125 A_A5 E11 178 B12 173 AD29 K19 128 A_A3 A12 174 VCCP AD28 B13 169 REQ L14 127 A_INPACK A13 170 AD31 E13 165 AD25 L15 126 A_A4 A14 166 PRST G15 149 SPKROUT M1 34 B_A11 A15 162 C/BE3 F14 152 DATA M2 35 B_IOWR E14 159 MFUNC4 E19 151 CLOCK M3 36 B_A9 C15 158 MFUNC3 F17 150 LATCH L5 33 B_IORD A16 157 MFUNC2 F1 10 AD4 M18 121 A_A25 E3 2 AD10 H6 11 AD3 L18 124 A_RESET C5 207 GND G3 12 AD2 L19 123 A_A6 B5 205 AD14 G5 9 AD5 M19 122 A_VS2 A5 203 C/BE1 G17 145 A_D9 M5 38 A6 199 PERR F18 148 N1 39 VCCB B_A8 A7 195 IRDY F19 147 VCCI A_D10 N2 40 B_A18 B8 191 AD16 G14 146 A_D2 M6 37 B_A17 C9 187 G1 14 AD1 N18 117 A_A12 E10 183 VCC AD23 H5 15 AD0 M17 120 F11 179 AD24 H3 16 B_CD1 M15 119 VCCA A_A7 A11 175 13 GND N19 118 A_A24 171 VCC AD30 G2 E12 H14 141 A_D0 N6 42 B_A19 F12 167 GND G18 144 A_D1 P1 43 B_A14 C14 163 RI_OUT/PME G19 143 P2 44 GND F13 160 MFUNC5 H15 142 VCC A_D8 N3 41 B_A13 E17 155 MFUNC1 H1 18 B_D11 N15 113 D19 156 SUSPEND J1 19 B_D4 N17 116 VCC A_A23 F5 3 AD9 J2 20 B_D12 M14 115 A_A15 G6 4 AD8 H2 17 B_D3 P19 114 A_A22 E2 5 C/BE0 J15 137 A_BVD2(SPKR) P3 46 B_WE F6 204 AD15 H17 140 A_CD2 R1 47 B_A21 B6 200 SERR H18 139 A_WP(IOIS16) P6 48 B_A16 B7 196 TRDY H19 138 A_BVD1(STSCHG/RI) N5 45 B_A20 C8 192 C/BE2 J5 22 GND R7 61 B_INPACK F9 188 AD19 J6 23 B_D13 V7 65 B_A2 F10 184 AD22 K1 24 B_D6 V8 69 B_READY(IREQ) A10 180 PCLK J3 21 B_D5 U9 73 B_WP(IOIS16) B11 176 AD27 J19 133 A_A0 V10 77 B_D8 C12 172 AD11 J14 136 A_WAIT W11 81 B_D10 C13 168 GNT J17 135 A_READY(IREQ) R11 85 A_D4 B14 164 J18 134 A_VS1 P12 89 A_D13 B15 161 VCC MFUNC6 K3 26 B_D7 U13 93 A_D15 E18 153 GND K5 27 B_D15 R13 97 A_CE2 F15 154 MFUNC0 K6 28 B_CE1 P18 112 A_A16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 3. 16-Bit PC Card Signal Names by GHK/PDV Terminal Number (Continued) TERMINAL NO. GHK TERMINAL NO. GHK PDV SIGNAL NAME PDV E1 6 R19 P5 110 P14 50 49 57 60 64 68 72 76 80 84 88 92 96 100 R18 N14 109 108 P15 107 R2 V5 V6 U7 U8 V9 W10 P10 P11 U12 V13 V14 AD7 A_WE B_A15 B_A22 B_A6 B_A4 VCC B_VS1 B_BVD1(STSCHG/RI) B_D0 B_D2 A_D11 A_D5 A_D7 GND A_A11 A_A20 A_A14 A_A19 K2 25 T1 R3 52 51 56 59 63 67 71 75 79 83 87 91 95 99 101 103 P7 U6 P8 R8 W9 P9 R10 U11 V12 W13 W14 W15 V15 U15 R17 W4 106 53 TERMINAL NO. GHK PDV SIGNAL NAME B_D14 B_A12 B_A23 B_VS2 B_A5 B_REG B_A0 B_BVD2(SPKR) GND B_D9 A_D3 A_D12 A_D14 A_A10 A_IORD A_IOWR A_A17 A_A13 B_A24 P17 111 U5 R6 W16 54 55 58 62 66 70 74 78 82 86 90 94 98 102 104 T19 105 W5 W6 W7 W8 R9 U10 V11 W12 R12 P13 U14 R14 SIGNAL NAME A_A21 B_A7 B_A25 B_RESET B_A3 B_A1 B_WAIT B_CD2 B_D1 A_CD1 VCC A_D6 A_CE1 A_OE A_A9 A_A8 A_A18 Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically SIGNAL NAME A_A0 A_A1 A_A2 A_A3 A_A4 A_A5 A_A6 A_A7 A_A8 A_A9 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15 A_A16 A_A17 A_A18 A_A19 10 TERMINAL NO. GHK PDV J19 133 K14 132 K15 131 K19 128 L15 126 L17 125 L19 123 M15 119 W16 P14 104 102 95 100 N18 117 R17 106 N14 108 M14 115 P18 112 U15 103 T19 105 P15 107 R14 W14 TERMINAL NO. SIGNAL NAME A_A20 A_A21 A_A22 A_A23 A_A24 A_A25 A_BVD1(STSCHG/RI) A_BVD2(SPKR) A_CD1 A_CD2 A_CE1 A_CE2 A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 POST OFFICE BOX 655303 GHK PDV R18 109 P17 111 P19 114 N17 116 N19 118 M18 121 H19 138 J15 137 V11 82 H17 140 P13 R13 94 97 H14 141 G18 144 G14 146 U11 83 85 88 90 92 R11 U12 R12 V13 • DALLAS, TEXAS 75265 SIGNAL NAME A_D8 A_D9 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 A_INPACK A_IORD A_IOWR A_OE A_READY(IREQ) A_REG A_RESET A_VS1 A_VS2 A_WAIT A_WE A_WP(IOIS16) TERMINAL NO. GHK PDV H15 142 G17 145 F19 147 P11 U13 84 87 89 91 93 L14 127 W15 U14 99 101 98 V12 P12 W13 V15 J17 135 K17 130 L18 124 J18 134 M19 122 J14 136 R19 110 H18 139 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued) SIGNAL NAME AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 B_A0 B_A1 B_A2 B_A3 B_A4 B_A5 B_A6 B_A7 B_A8 B_A9 B_A10 B_A11 B_A12 B_A13 B_A14 B_A15 B_A16 B_A17 TERMINAL NO. GHK PDV H5 15 G1 14 G3 12 H6 11 F1 10 G5 9 F2 8 E1 6 G6 4 F5 3 E3 2 C12 172 A4 208 E6 206 B5 205 F6 204 B8 191 A8 190 E9 189 F9 188 B9 186 A9 185 F10 184 E10 183 F11 179 E13 165 C11 177 B11 176 A12 174 B12 173 E12 171 A13 170 R8 67 66 65 62 60 59 57 54 39 36 29 34 52 41 43 50 48 37 W7 V7 W6 V6 U6 V5 U5 N1 M3 L1 M1 T1 N3 P1 P5 P6 M6 TERMINAL NO. SIGNAL NAME B_A18 B_A19 B_A20 B_A21 B_A22 B_A23 B_A24 B_A25 B_BVD1(STSCHG/RI) B_BVD2(SPKR) B_CD1 B_CD2 B_CE1 B_CE2 B_D0 B_D1 B_D2 B_D3 B_D4 B_D5 B_D6 B_D7 B_D8 B_D9 B_D10 B_D11 B_D12 B_D13 B_D14 B_D15 B_INPACK B_IORD B_IOWR B_OE B_READY(IREQ) B_REG B_RESET B_VS1 B_VS2 B_WAIT B_WE B_WP(IOIS16) C/BE0 C/BE1 C/BE2 C/BE3 CLOCK DATA DEVSEL FRAME POST OFFICE BOX 655303 GHK PDV N2 40 42 45 47 49 51 53 55 72 71 N6 N5 R1 R2 R3 W4 R6 V9 W9 H3 16 R9 P10 74 28 30 76 78 80 H2 17 J1 19 J3 21 K1 W11 24 26 77 79 81 H1 18 J2 U9 20 23 25 27 61 33 35 32 69 63 58 68 56 70 46 73 E2 5 K6 L2 W10 U10 K3 V10 R10 J6 K2 K5 R7 L5 M2 L6 V8 P8 W5 U8 P7 W8 P3 A5 203 C8 192 A15 162 E19 151 F14 152 C7 197 F8 193 • DALLAS, TEXAS 75265 SIGNAL NAME GND GND GND GND GND GND GND GND GND GND GND GNT IDSEL IRDY LATCH MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 PAR PCLK PERR PRST REQ RI_OUT/PME SERR SPKROUT STOP SUSPEND TRDY VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCB VCCI VCCP VCCP TERMINAL NO. GHK PDV E8 194 C5 207 F12 167 E18 153 B10 181 G2 13 J5 22 K18 129 P2 P9 44 96 75 C13 168 C10 182 A7 195 F17 150 F15 154 E17 155 A16 157 C15 158 E14 159 F13 160 B15 161 C6 202 A10 180 A6 199 A14 166 B13 169 C14 163 B6 200 G15 149 F7 198 D19 156 B7 196 A11 175 C9 187 B14 164 V14 F3 7 E7 201 G19 143 L3 31 N15 113 U7 W12 64 86 M17 120 M5 38 F18 148 D1 1 E11 178 11 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. power supply TERMINAL FUNCTION NAME PDV NUMBER GHK NUMBER GND 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207 G2, J5, P2, P9, V14, K18, E18, F12, B10, E8, C5 VCC 7, 31, 64, 86, 113, 143, 164, 175, 187, 201 F3, L3, U7, W12, N15, G19, B14, A11, C9, E7 VCCA 120 M17 Rail voltage for PC Card A interface. Indicates Card A signaling environment (5 V or 3.3 V) VCCB 38 M5 Rail voltage for PC Card B interface. Indicates Card B signaling environment (5 V or 3.3 V) VCCI 148 F18 Rail voltage for interrupt subsystem miscellaneous I/O (5 V or 3.3 V) VCCP 1, 178 D1, E11 Rail voltage for PCI signaling (5 V or 3.3 V) Device ground terminals Power supply terminal for core logic (3.3 V) interface and PC Card power switch TERMINAL NAME CLOCK NUMBER PDV 151 GHK E19 I/O TYPE I/O FUNCTION Three-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1225 output by using the P2CCLK bit in the system control register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz. If a system design defines this terminal as an output, then this terminal requires an external pull down resistor. The frequency of the PCI1225 output CLOCK is derived from dividing the PCI CLK by 36. DATA 152 F14 O Three-line power switch data. DATA is used to serially communicate socket power control information to the power switch. LATCH 150 F17 O Three-line power switch latch. LATCH is asserted by the PCI1225 to indicate to the PC Card power switch that the data on the DATA line is valid. When a pulldown resistor is implemented on this terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface. PCI system TERMINAL NAME PCLK PRST 12 NUMBER PDV GHK 180 A10 166 A14 I/O TYPE FUNCTION I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. I PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1225 to place all output buffers in a high-impedance state and reset all internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI1225 is in its default state. When SUSPEND and PRST are asserted, the device is protected from PRST clearing the internal registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) PCI address and data TERMINAL NUMBER NAME PDV GHK AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 170 171 173 174 176 177 165 179 183 184 185 186 188 189 190 191 204 205 206 208 172 2 3 4 6 8 9 10 11 12 14 15 A13 E12 B12 A12 B11 C11 E13 F11 E10 F10 A9 B9 F9 E9 A8 B8 F6 B5 E6 A4 C12 E3 F5 G6 E1 F2 G5 F1 H6 G3 G1 H5 C/BE3 C/BE2 C/BE1 C/BE0 162 192 203 5 A15 C8 A5 E2 PAR 202 C6 I/O TYPE FUNCTION I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. I/O PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). I/O PCI bus parity. In all PCI bus read and write cycles, the PCI1225 calculates even parity across the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI1225 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator. A compare error results in the assertion of a parity error (PERR). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) PCI interface control TERMINAL NUMBER NAME I/O TYPE FUNCTION PDV GHK DEVSEL 197 C7 I/O PCI device select. The PCI1225 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1225 monitors DEVSEL until a target responds. If no target responds before timeout occurs, the PCI1225 terminates the cycle with an initiator abort. FRAME 193 F8 I/O PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. GNT 168 C13 I PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1225 access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. IDSEL 182 C10 I Initialization device select. IDSEL selects the PCI1225 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. IRDY 195 A7 I/O PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PERR 199 A6 I/O PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register. REQ 169 B13 O PCI bus request. REQ is asserted by the PCI1225 to request access to the PCI bus as an initiator. SERR 200 B6 O PCI system error. SERR is an output that is pulsed from the PCI1225 when enabled through the command register indicating a system error has occurred. The PCI1225 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. STOP 198 F7 I/O PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. TRDY 196 B7 I/O PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) multifunction and miscellaneous terminals TERMINAL NUMBER NAME MFUNC0 PDV GHK 154 F15 I/O TYPE FUNCTION I/O Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. MFUNC1 155 E17 I/O MFUNC2 157 A16 I/O Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. MFUNC3 158 C15 I/O Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. See the multifunction routing register description on page 64 for configuration details. Serial data (SDA). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC1 terminal provides the SDA signaling. The two-terminal serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. See the serial bus interface implementation description on page 31 for details on other serial bus applications. Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. Serial clock (SCL). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC4 terminal provides the SCL signaling. The two-terminal serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. See the serial bus interface implementation description on page 31 for details on other serial bus applications. MFUNC4 159 E14 I/O MFUNC5 160 F13 I/O Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. MFUNC6 161 B15 I/O Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. RI_OUT/PME 163 C14 O Ring indicate out and power management event output. Terminal provides an output for ring-indicate or PME signals. SPKROUT 149 G15 O Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1225 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR//CAUDIO inputs. SUSPEND 156 D19 I Suspend. SUSPEND is used to protect the internal registers from clearing when the PRST signal is asserted. See suspend mode description on page 42 for details. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) 16-bit PC Card address and data (slots A and B) TERMINAL NUMBER NAME SLOT A† SLOT B‡ I/O TYPE FUNCTION PDV GHK PDV GHK A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 121 118 116 114 111 109 107 105 103 112 115 108 106 117 100 95 102 104 119 123 125 126 128 131 132 133 M18 N19 N17 P19 P17 R18 P15 T19 U15 P18 M14 N14 R17 N18 P14 W14 R14 W16 M15 L19 L17 L15 K19 K15 K14 J19 55 53 51 49 47 45 42 40 37 48 50 43 41 52 34 29 36 39 54 57 59 60 62 65 66 67 R6 W4 R3 R2 R1 N5 N6 N2 M6 P6 P5 P1 N3 T1 M1 L1 M3 N1 U5 V5 U6 V6 W6 V7 W7 R8 O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 93 91 89 87 84 147 145 142 92 90 88 85 83 146 144 141 U13 W13 P12 V12 P11 F19 G17 H15 V13 R12 U12 R11 U11 G14 G18 H14 27 25 23 20 18 81 79 77 26 24 21 19 17 80 78 76 K5 K2 J6 J2 H1 W11 R10 V10 K3 K1 J3 J1 H2 P10 U10 W10 I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 121 and M18 is A_A25. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R6 is B_A25. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) 16-bit PC Card interface control (slots A and B) NAME BVD1 (STSCHG/RI) TERMINAL NUMBER SLOT A† SLOT B‡ PDV GHK PDV GHK 138 H19 72 V9 I/O TYPE FUNCTION I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 92 for enable bits. See ExCA card status-change register on page 91 and the ExCA interface status register on page 88 for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage detect condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. BVD2 (SPKR) 137 J15 71 W9 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 92 for enable bits. See ExCA card status-change register on page 91 and the ExCA interface status register on page 88 for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1225 and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. CD1 CD2 82 140 V11 H17 16 74 H3 R9 I PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see interface status register on page 88. CE1 CE2 94 97 P13 R13 28 30 K6 L2 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation. O I/O read. IORD is asserted by the PCI1225 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1225 asserts IORD during DMA transfers from the PC Card to host memory. O I/O write. IOWR is driven low by the PCI1225 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1225 asserts IOWR during transfers from host memory to the PC Card. O Output enable. OE is driven low by the PCI1225 to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1225 asserts OE to indicate TC for a DMA write operation. INPACK IORD IOWR OE 127 99 101 98 L14 W15 V15 U14 61 33 35 32 R7 L5 M2 L6 † Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14 is A_INPACK. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 is B_INPACK. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) 16-bit PC Card interface control (slots A and B) (continued) TERMINAL NUMBER NAME SLOT A† PDV READY (IREQ) 135 GHK J17 I/O TYPE SLOT B‡ PDV 69 FUNCTION GHK V8 I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG 130 K17 63 P8 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1225 asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET 124 L18 58 W5 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. VS1 VS2 134 122 J18 M19 68 56 U8 P7 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the 16-bit PC Card. WAIT 136 J14 70 W8 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. WE 110 R19 46 P3 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI1225 asserts WE to indicate TC for a DMA read operation. Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. WP (IOIS16) 139 H18 73 U9 I I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 110 and R19 is A_WE. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3 is B_WE. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) CardBus PC Card interface system (slots A and B) TERMINAL NUMBER NAME SLOT A† PDV GHK SLOT B‡ PDV I/O TYPE FUNCTION GHK CCLK 112 P18 48 P6 O CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CCLKRUN 139 H18 73 U9 O CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1225 to indicate that the CCLK frequency is going to be decreased. I/O CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be 3-stated, and the PCI1225 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. CRST 124 L18 58 W5 † Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 is A_CCLK. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6 is B_CCLK. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) CardBus PC Card address and data (slots A and B) TERMINAL NAME CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 CC/BE3 CC/BE2 CC/BE1 CC/BE0 CPAR PIN NUMBER SLOT A† SLOT B‡ PDV GHK PDV GHK 147 145 144 142 141 133 132 131 128 126 125 123 121 119 118 103 101 102 99 100 98 97 95 93 92 89 90 87 88 84 85 83 F19 G17 G18 H15 H14 J19 K14 K15 K19 L15 L17 L19 M18 M15 N19 U15 V15 R14 W15 P14 U14 R13 W14 U13 V13 P12 R12 V12 U12 P11 R11 U11 81 79 78 77 76 67 66 65 62 60 59 57 55 54 53 37 35 36 33 34 32 30 29 27 26 23 24 20 21 18 19 17 W11 R10 U10 V10 W10 R8 W7 V7 W6 V6 U6 V5 R6 U5 W4 M6 M2 M3 L5 M1 L6 L2 L1 K5 K3 J6 K1 J2 J3 H1 J1 H2 130 117 104 94 106 K17 N18 W16 P13 R17 63 52 39 28 41 P8 T1 N1 K6 N3 I/O TYPE FUNCTION I/O PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit. I/O CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD8), and CC/BE3 applies to byte 3 (CAD31–CAD24). I/O CardBus parity. In all CardBus read and write cycles, the PCI1225 calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1225 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator parity indicator; a compare error results in a parity error assertion. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and R17 is A_CPAR. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3 is B_CPAR. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Terminal Functions (Continued) CardBus PC Card interface control (slots A and B) TERMINAL NAME PIN NUMBER SLOT A† SLOT B‡ I/O TYPE FUNCTION CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1225 supports the binary audio mode and outputs a binary signal from the card to SPKROUT. PDV GHK PDV GHK CAUDIO 137 J15 71 W9 I CBLOCK 107 P15 42 N6 I/O CCD1 CCD2 82 140 V11 H17 16 74 H3 R9 I CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with ith CVS1 and d CVS2 tto id identify tif card d iinsertion ti and d iinterrogate t t cards d tto d determine t i th the operating voltage and card type. I/O CardBus device select. The PCI1225 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1225 monitors CDEVSEL until a target responds. If no target responds before timeout occurs, the PCI1225 terminates the cycle with an initiator abort. CDEVSEL 111 P17 47 R1 CardBus lock. CBLOCK is used to gain exclusive access to a target. CFRAME 116 N17 51 R3 I/O CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. CGNT 110 R19 46 P3 I CardBus bus grant. CGNT is driven by the PCI1225 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CINT 135 J17 69 V8 I CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. CIRDY 115 M14 50 P5 I/O CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. CPERR 108 N14 43 P1 I/O CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CREQ 127 L14 61 R7 I CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CSERR 136 J14 70 W8 I CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1225 can report CSERR to the system by assertion of SERR on the PCI interface. CSTOP 109 R18 45 N5 I/O CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CSTSCHG 138 H19 72 V9 I CardBus status change. CSTSCHG is used to alert the system to a change in the card status, and is used as a wake-up mechanism. CTRDY 114 P19 49 R2 I/O CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. CVS1 CVS2 134 122 J18 M19 68 56 U8 P7 I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 137 and J15 is A_CAUDIO. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 71 and W9 is B_CAUDIO. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 power supply sequencing The PCI1225 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp power supplies. The core power supply is always 3.3 V. The clamp power supplies can be either 3.3 V or 5 V, depending on the interface. The following power-up and power-down sequences are recommended. The power-up sequence is: 1. Apply 3.3-V power to the core. 2. Assert PRST to the device to disable the outputs during power up. Output drivers must be powered up in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply. 3. Apply the clamp power. The power-down sequence is: 1. Use PRST to switch outputs to a high-impedance state. 2. Remove the clamp power. 3. Remove the 3.3-V power from the core. I/O characteristics Figure 1 shows a 3-state bidirectional buffer. The recommended operating conditions table, on page 120, provides the electrical characteristics of the inputs and outputs. NOTE: The PCI1225 meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus Specification Rev. 2.2. VCCP Tied for Open Drain OE Pad Figure 1. 3-State Bidirectional Buffer NOTE: Unused pins (input or I/O) must be held high or low to prevent them from floating. clamping rail voltages The clamping rail voltages are set to match whatever external environment the PCI1225 will be working with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a power rail that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping rail voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI1225 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping rail voltage applied. If a system designer desires a 5-V PCI bus, VCCP can be connected to a 5-V power supply. The PCI1225 requires four separate clamping rails because it supports a wide range of features. The four rails are listed and defined in the recommended operating conditions, on page 120. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 peripheral component interconnect (PCI) interface The PCI1225 is fully compliant with the PCI Local Bus Specification Rev. 2.2. The PCI1225 provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the VCCP terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI1225 provides the optional interrupt signals INTA and INTB. PCI bus lock (LOCK) The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1225 as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal via the multifunction routing register; see the multifunction routing register description on page 64 for details. Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor). PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock. An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario, the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. The PCI1225 supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the 2.2 PCI specification, and the issue is resolved by the PCI master using LOCK. loading subsystem identification The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC 95 requirement. The PCI1225 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by setting the SUBSYSRW bit in the system control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 loading subsystem identification (continued) In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The PCI1225 loads the data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI1225 core, including the serial bus state machine (see suspend mode, on page 42, for details on using SUSPEND). The PCI1225 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM. See serial bus interface on page 31 for details on the two-wire serial bus controller and applications. PC Card applications This section describes the PC Card interfaces of the PCI1225: Card insertion/removal and recognition P2C power-switch interface Zoom video support Speaker and audio applications LED socket activity indicators 16-bit PC Card DMA support CardBus socket registers PC Card insertion/removal and recognition The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (16 bit versus CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1997 PC Card Standard and in Table 5. Table 5. PC Card Card-Detect and Voltage-Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE Ground Ground Ground Ground Ground VOLTAGE Open Open 5V 16-bit PC Card 5V Open Ground 5V 16-bit PC Card 5 V and 3.3 V Ground Ground Ground 5V 16-bit PC Card 5 V, 3.3 V, and X.X V Ground Ground Open Ground LV 16-bit PC Card 3.3 V Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V 3.3 V and X.X V Ground Ground Ground Ground LV 16-bit PC Card Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V Ground Ground Ground Open LV 16-bit PC Card Y.Y V Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 P2C power-switch interface (TPS2202A/2206) The PCI1225 provides a P2C (PCMCIA peripheral control) interface for control of the PC Card power switch. The CLOCK, DATA, and LATCH terminals interface with the TI TPS2202A/2206 dual-slot PC Card power interface switches to provide power switch support. Figure 2 shows the terminal assignments of the TPS2206, and Figure 3 illustrates a typical application where the PCI1225 represents the PCMCIA controller. 5V 5V DATA CLOCK LATCH RESET 12 V AVPP AVCC AVCC AVCC GND NC RESET 3.3 V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5V NC NC NC NC NC 12 V BVPP BVCC BVCC BVCC NC OC 3.3 V 3.3 V NC – No internal connection Figure 2. TPS2206 Terminal Assignments The CLOCK terminal on the PCI1225 can be an input or an output. The PCI1225 defaults the CLOCK terminal as an input to control the serial interface and the internal state machine. The P2CCLK bit in the system control register can be set by the platform BIOS to enable the PCI1225 to generate and drive the CLOCK internally from the PCI clock. When the system design implements CLOCK as an output from the PCI1225, an external pulldown is required. Power Supply 12 V 5V 3.3 V 12 V 5V 3.3 V Supervisor RESET RESET PCI1225 (PCMCIA Controller) CLOCK DATA LATCH TPS2206 AVPP AVCC AVCC VPP1 VPP2 VCC VCC PC Card A VPP1 VPP2 VCC VCC PC Card B AVCC BVPP BVCC BVCC BVCC Figure 3. TPS2206 Typical Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 zoom video support The PCI1225 allows for the implementation of zoom video for PC Cards. Zoom video is supported by setting the ZVENABLE bit in the card control register on a per-socket-function basis. Setting this bit puts 16-bit PC Card address lines A25–A4 of the PC Card interface in the high-impedance state. These lines can then be used to transfer video and audio data directly to the appropriate controller. Card address lines A3–A0 can still be used to access PC Card CIS registers for PC Card configuration. Figure 4 illustrates a PCI1225 ZV implementation. Speakers CRT Motherboard PCI Bus VGA Controller Audio Codec Zoom Video Port PCM Audio Input 19 4 PC Card 19 PC Card Interface PCI1225 Video Audio 4 Figure 4. Zoom Video Implementation Using PCI1225 Not shown in Figure 4 is the multiplexing scheme used to route either socket 0 or socket 1 ZV source to the graphics controller. The PCI1225 provides ZVSTAT, ZVSEL0, and ZVSEL1 signals on the multifunction terminals to switch external bus drivers. Figure 5 shows an implementation for switching between three ZV streams using external logic. 2 PCI1225 ZVSTAT ZVSEL0 ZVSEL1 0 1 Figure 5. Zoom Video Switching Application 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 zoom video support (continued) Figure 5 illustrates an implementation using standard three-state bus drivers with active-low output enables. ZVSEL0 is an active-low output indicating that the socket 0 ZV mode is enabled, and ZVSEL1 is an active-low output indicating that socket 1 ZV is enabled. When both sockets have ZV mode enabled, the PCI1225 defaults to indicating socket 0 enabled through ZVSEL0; however, the PORTSEL bit in the card control register allows software to select the socket ZV source priority. Table 6 illustrates the functionality of the ZV output signals. Table 6. PC Card Card-Detect and Voltage-Sense Connections INPUTS OUTPUTS PORTSEL SOCKET 0 ENABLE SOCKET 1 ENABLE ZVSEL0 ZVSEL1 ZVSTAT X 0 0 1 1 0 0 1 X 0 1 1 0 0 1 1 0 1 1 X 1 1 0 1 1 1 0 0 1 1 Also shown in Figure 5 is a third ZV source that may be provided from a source such as a high-speed serial bus like IEEE 1394. The ZVSTAT signal provides a mechanism to switch the third ZV source. ZVSTAT is an active-high output indicating that one of the PCI1225 sockets is enabled for ZV mode. The implementation shown in Figure 5 can be used if PC Card ZV is prioritized over other sources. SPKROUT and CAUDPWM usage SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 terminal becomes SPKR. This terminal is also used in CardBus binary audio applications, and is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI1225. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the two PC Card sockets are XORed in the PCI1225 to produce SPKROUT. This output is enabled by the SPKROUTEN bit in the card control register. Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM. The PCI1225 implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal. The AUD2MUX bit located in the card control register is programmed on a per-socket-function basis to route a CardBus CAUDIO PWM terminal to CAUDPWM. If both CardBus functions enable CAUDIO PWM routing to CAUDPWM, then socket 0 audio takes precedence. See the multifunction routing register description on page 64 for details on configuring the MFUNC terminals. Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM. System Core Logic BINARY_SPKR SPKROUT Speaker Subsystem PCI1225 CAUDPWM PWM_SPKR Figure 6. Sample Application of SPKROUT and CAUDPWM POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 LED socket activity indicators The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LEDA1 and LEDA2 signals can be routed to the multifunction terminals. When configured for LED outputs, these terminals output an active high signal to indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity. The LED_SKT output indicates socket activity to either socket 0 or socket 1. See the multifunction routing register description on page 64 for details on configuring the multifunction terminals. The LED signal is active high and is driven for 64-ms durations. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 7 can be implemented to provide LED signaling, and it is left for the board designer to implement the circuit that best fits the application. The LED activity signals are valid when a card is inserted, powered, and not in reset. For a 16-bit PC Card, the LED activity signals are pulsed when READY/IREQ is low. For CardBus cards, the LED activity signals are pulsed if CFRAME, IRDY, or CREQ is active. Current Limiting R ≈ 500 Ω PCI1225 LED ApplicationSpecific Delay Current Limiting R ≈ 500 Ω PCI1225 LED Figure 7. Two Sample LED Circuits As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut-off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state. If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), the LED signals remain driven. 16-bit PC Card Distributed DMA support The PCI1225 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. The DDMA register configuration is provided in Table 7. Two socket function dependent PCI configuration header registers that are critical for DDMA are the socket DMA register 0 and the socket DMA register 1. Distributed DMA is enabled through socket DMA register 0 and the contents of this register configure the 16-bit PC Card terminal (SPKR, IOIS16, or INPACK) which is used for the DMA request signal, DREQ. The base address of the DDMA slave registers and the transfer size (bytes or words) are programmed through the socket DMA register 1. See the programming model and register descriptions for details. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 16-bit PC Card distributed DMA support (continued) Table 7. Distributed DMA Registers TYPE DMA BASE ADDRESS OFFSET REGISTER NAME R W Current address Reserved Page Reserved Reserved R W 00h Base address Current count R N/A W Mode R Multichannel W Mask Reserved 04h Base count N/A Status Request Command N/A Reserved Master clear 08h 0Ch Reserved The DDMA registers contain control and status information consistent with the 8237 DMA controller; however, the register locations are reordered and expanded in some cases. While the DDMA register definitions are identical to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI1225 implements these obsolete register bits as read-only, nonfunctional bits. The reserved registers shown in Table 7 are implemented as read-only and return zeros when read. Write transactions to reserved registers have no effect. The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ signal assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed above, this is done through socket DMA register 0 and socket DMA register 1. The DMA register set is then programmed similarly to an 8237 controller, and the PCI1225 awaits a DREQ assertion from the PC Card requesting a DMA transfer. DMA writes transfer data from the PC Card to PCI memory addresses. The PCI1225 accepts data 8 or 16 bits at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its REQ signal. Once the PCI bus is granted in an idle state, the PCI1225 initiates a PCI memory write command to the current memory address and transfers the data in a single data phase. After terminating the PCI cycle, the PCI1225 accepts the next byte(s) from the PC Card until the transfer count expires. DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ, the PCI1225 asserts REQ to acquire the PCI bus. Once the bus is granted in an idle state, the PCI1225 initiates a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the programmed data width. After terminating the PCI cycle, the data is passed onto the PC Card. After terminating the PC Card cycle, the PCI1225 requests access to the PCI bus again until the transfer count has expired. The PCI1225 target interface acts normally during this procedure and accepts I/O reads and writes to the DDMA registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1225 asserts TC and ends the PC Card cycle(s). TC is indicated in the DDMA status register. At the PC Card interface, the PCI1225 supports demand mode transfers. The PCI1225 asserts DACK during the transfer unless DREQ is deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations and is mapped to WE PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all transfers, and the DREQ terminal is routed to one of three options which is programmed through socket DMA register 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 16-bit PC Card PC/PCI DMA Some chip sets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol, the PCI1225 acts as a PCI target device to certain DMA related I/O addresses. The PCI1225 PCREQ and PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. See the multifunction routing register description on page 64 for details on configuring the multifunction terminals. Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1225) requests a DMA transfer on a particular channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus, and grants the channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle and memory cycles are then presented on the PCI bus, which performs the DMA transfers similarly to legacy DMA master devices. PC/PCI DMA is enabled for each 16-bit PC Card slot by setting bit 19 in the respective system control register. On power up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 of the system control register is a global enable for PC/PCI DMA, and is set at power-up and never cleared if the PC/PCI DMA mechanism is implemented. The desired DMA channel for each 16-bit PC Card slot must be configured through bits 18–16 in the system control register. The channels are configured as indicated in Table 8. Table 8. PC/PCI Channel Assignments SYSTEM CONTROL REGISTER DMA CHANNEL CHANNEL TRANSFER DATA WIDTH 0 Channel 0 8-bit DMA transfers 1 Channel 1 8-bit DMA transfers 1 0 Channel 2 8-bit DMA transfers 0 1 1 Channel 3 8-bit DMA transfers 1 0 0 Channel 4 Not used 1 0 1 Channel 5 16-bit DMA transfers 1 1 0 Channel 6 16-bit DMA transfers 1 1 1 Channel 7 16-bit DMA transfers BIT 18 BIT 17 BIT16 0 0 0 0 0 As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA register 0. The data transfer width is a function of channel number, and the DDMA slave registers are not used. When a DREQ is received from a PC Card and the channel has been granted, the PCI1225 decodes the I/O addresses listed in Table 9 and performs actions dependent upon the address. Table 9. I/O Addresses Used for PC/PCI DMA DMA I/O ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE 00h Normal 0 I/O read/write 04h Normal TC 1 I/O read/write C0h Verify 0 I/O read C4h Verify TC 1 I/O read When the PC/PCI DMA is used as a 16-bit PC Card DMA mechanism, it may not provide the performance levels of DDMA; however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master state machine is required to support PC/PCI DMA, since the DMA control is centralized in the chipset. This DMA scheme is often referred to as centralized DMA for this reason. CardBus socket registers The PCI1225 contains all registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge specification. These registers exist as the CardBus socket registers, and are listed in Table 10. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 10. CardBus Socket Registers REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket power management 20h serial bus interface The PCI1225 provides a serial bus interface to load subsystem identification and select register defaults through a serial EEPROM and to provide a PC Card power switch interface alternative to P2C. See P 2C power-switch interface (TPS2202A/2206) on page 25 for details. The PCI1225 serial bus interface is compatible with various I2C and SMBus components. serial bus interface implementation The PCI1225 defaults to serial bus interface are disabled. To enable the serial interface, a pulldown resistor must be implemented on the LATCH terminal and the appropriate pullup must be implemented on the SDA and SCL signals, i.e. the MFUNC1 and MFUNC4 terminals. When the interface is detected, the SBDETECT bit in the system control register is set. The SBDETECT bit is cleared by a writeback of 1. The PCI1225 implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA). When a pulldown is provided on the LATCH terminal, the SCL signal is mapped to the MFUNC4 terminal and the SDA signal is mapped to the MFUNC1 terminal. The PCI1225 drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for standard mode I2C. An example application implementing the two-wire serial bus is illustrated in Figure 8. VCC Serial EEPROM PCI1225 LATCH A0 A1 A2 SCL MFUNC4 SDA MFUNC1 Figure 8. Serial EEPROM Application Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow. serial bus interface protocol The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure Figure 8. The PCI1225 supports up to 100 Kb/s data transfer rate and is compatible with standard mode I2C using seven-bit addressing. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 serial bus interface protocol (continued) All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signalled when the SDA line transitions to low state while SCL is in the high state, as illustrated in Figure 9. The end of a requested data transfer is indicated by a stop condition, which is signalled by a low to high transition of SDA while SCL is in the high state, as shown in Figure 9. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or a stop condition. SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data Valid Figure 9. Serial Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited, however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. The acknowledge protocol is illustrated in Figure 10. SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 10. Serial Bus Protocol Acknowledge The PCI1225 is a serial bus master; all other devices connected to the serial bus external to the PCI1225 are slave devices. As the bus master, the PCI1225 drives the SCL clock at nearly 100 kHz during bus cycles and three-states SCL (zero frequency) during idle states. Typically, the PCI1225 masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See serial bus EEPROM application on page 34 for details on how the PCI1225 automatically loads the subsystem identification and other register defaults through a serial bus EEPROM. A byte write is illustrated in Figure 11. The PCI1225 issues a start condition and sends the seven-bit slave device address and the command bit zero. A zero in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1225, then an appropriate status bit is set in the serial bus control and status register. The word address byte is then sent by the PCI1225 and another slave acknowledgment is expected. Then the PCI1225 delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 serial bus interface protocol (continued) Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 Start 0 A Data Byte b7 b6 b5 b4 b3 b2 b1 b0 A b7 b6 b5 b4 b3 b2 b1 b0 A P Stop R/W A = Slave Acknowledgement S/P = Start/Stop Condition Figure 11. Serial Bus Protocol – Byte Write A byte read is illustrated in Figure 12. The read protocol is very similar to the write protocol except the R/W command bit must be set to one to indicate a read-data transfer. In addition, the PCI1225 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCI1225 master. Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 R/W Start A S b6 b5 b4 b3 b2 b1 b0 Restart 1 A R/W Data Byte b7 b6 b5 b4 b3 b2 b1 b0 M P Stop A = Slave Acknowledgement M = Master Acknowledgement S/P = Start/Stop Condition Figure 12. Serial Bus Protocol – Byte Read Figure 13 illustrates EEPROM interface doubleword data collection protocol. Slave Address S Start 1 0 1 0 0 Word Address 0 0 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 A R/W 1 0 1 0 0 0 M Data Byte 2 M Data Byte 1 M = Master Acknowledgement 0 1 A R/W Restart Data Byte 3 A = Slave Acknowledgement S M Data Byte 0 M P S/P = Start/Stop Condition Figure 13. EEPROM Interface Doubleword Data Collection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 serial bus EEPROM application When the PCI bus is reset and the serial bus interface is detected, the PCI1225 attempts to read the subsystem identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be loaded with defaults through the EEPROM are provided in Table 11. Table 11. Registers and Bits Loadable Through Serial EEPROM PCI OFFSET OFFSET REFERENCE 40h 01h Subsystem identification 31–0 REGISTER BITS LOADED FROM EEPROM 80h 02h System control register 31–29, 27, 26, 24, 15, 14, 6–3, 1 8Ch 03h Multifunction routing register 27–0 90h 04h Retry status, card control, device control, diagnostic 31, 28–24, 22, 19–16, 15, 13, 7, 6 The EEPROM data format is detailed in Figure 14. This format must be followed for the PCI1225 to properly load initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets the ROM_ERR bit in the serial bus control and status register. Slave Address = 1010 000 Reference(0) Word Address 00h Byte 3 (0) Word Address 01h Reference(n) Byte 2 (0) Word Address 02h Byte 3 (n) Word Address 8 × (n–1) + 1 Byte 1 (0) Word Address 03h Byte 2 (n) Word Address 8 × (n–1) + 2 Byte 0 (0) Word Address 04h Word Address 8 × (n–1) Byte 1 (n) Word Address 8 × (n–1) + 3 RSVD Byte 0 (n) Word Address 8 × (n–1) + 4 RSVD RSVD RSVD Reference(1) RSVD Word Address 08h RSVD EOL Word Address 8 × (n) Figure 14. EEPROM Data Format The byte at the EEPROM word address 00h must either contain a valid PCI offset, as listed in Table 11, or an end-of-list (EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load from the EEPROM. Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered when programming the EEPROM. The serial EEPROM is addressed at slave address 1010 000b by the PCI1225. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 8) assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 13. The address autoincrements after every byte transfer according to the doubleword read protocol. Note that the word addresses align with the data format illustrated in Figure 14. The PCI1225 continues to load data from the serial EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain eight-byte data structures. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 serial bus EEPROM application (continued) Note, the eight-byte data structure is important to provide correct addressing per the doubleword read format shown in Figure 13. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is 01h, 02h, 03h, 04h. If the offsets are not sequential, the registers may be loaded incorrectly. serial bus power switch application The PCI1225 does not automatically control a serial bus power switch transparently to host software as it does for P2C power switches. But, the PCI1225 serial bus interface can be used in conjunction with the power status, GPE, output, and support software to control a serial bus power switch. If a serial bus power switch interface is implemented, a pulldown resistor must be provided on the PCI1225 CLOCK terminal to reduce power consumption. The PCI1225 supports two common SMBus data write protocols, write byte and send byte formats. The write byte protocol using a word address of 00h is discussed in serial bus interface protocol on page 32. The send byte protocol is shown in Figure 15 using a slave address 101 001Xb. The PROT_SEL bit in the serial bus control and status register, see Table 42 on page 82, allows the serial bus interface to operate with the send byte protocol. For more information on programming the serial bus interface, see accessing serial bus devices through software. Slave Address S 1 0 1 0 0 Command Code 1 X 0 A b7 b6 b5 b4 b3 b2 b1 b0 A P R/W A = Slave Acknowledgement S/P = Start/Stop Condition Figure 15. Send Byte Protocol The power switch may support an interrupt mode to indicate overcurrent or other power switch related events. The PCI1225 does not implement logic to respond to these events, but does implement a flexible general purpose interface to control these events through ACPI and other handlers. See Advanced Configuration and Power Interface Specification for details on implementing the PCI1225 in an ACPI system. accessing serial bus devices through software The PCI1225 provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 12 lists the registers used to program a serial bus device through software. Table 12. PCI1225 Registers Used to Program Serial Bus Devices PCI OFFSET REGISTER NAME DESCRIPTION B0h Serial bus data Contains the data byte to send on write commands or the received data byte on read commands. B1h Serial bus index The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol. B2h Serial bus slave address Write transactions to this register initiate a serial bus transaction. The slave device address and the R/W command selector are programmed through this register. B3h Serial bus control and status Read data valid, general busy, and general error status are communicated through this register. In addition, the protocol select bit is programmed through this register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 programmable interrupt subsystem Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI1225. The PCI1225 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1225 is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. The PCI1225 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1225, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts. The method by which any type of PCI1225 interrupt is communicated to the host interrupt controller varies from system to system. The PCI1225 offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All interrupt signalling is provided through the seven multifunction terminals, MFUNC0–MFUNC6. PC Card functional and card status change interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCI1225 and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals. Table 13 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are: 16-bit memory card 16-bit I/O card CardBus cards 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 13. Interrupt Mask and Flag Registers CARD TYPE 16-bit 16 bit memory 16 bit I/O 16-bit All 16-bit PC Cards CardBus EVENT MASK FLAG Battery conditions (BVD1, BVD2) ExCA offset 05h/45h/805h bits 1 and 0 ExCA offset 04h/44h/804h bits 1 and 0 ExCA offset 04h/44h/804h bit 2 Wait states (READY) ExCA offset 05h/45h/805h bit 2 Change in card status (STSCHG) ExCA offset 05h/45h/805h bit 0 ExCA offset 04h/44h/804h bit 0 Interrupt request (IREQ) Always enabled PCI configuration offset 91h bit 0 Power cycle complete ExCA offset 05h/45h/805h bit 3 ExCA offset 04h/44h/804h bit 3 Change in card status (CSTSCHG) Socket mask bit 0 Socket event bit 0 Interrupt request (CINT) Always enabled PCI configuration offset 91h bit 0 Power cycle complete Socket mask bit 3 Socket event bit 3 Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1 Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type. Table 14. PC Card Interrupt Events and Description CARD TYPE 16-bit memory 16 bit I/O 16-bit CardBus All PC Cards EVENT TYPE SIGNAL DESCRIPTION BVD1(STSCHG)//CSTSCHG A transition on BVD1 indicates a change in the PC Card battery conditions. BVD2(SPKR)//CAUDIO A transition on BVD2 indicates a change in the PC Card battery conditions. Battery conditions (BVD1, BVD2) CSC Wait states (READY) CSC READY(IREQ)//CINT A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data. Change in card status (STSCHG) CSC BVD1(STSCHG)//CSTSCHG The assertion of STSCHG indicates a status change on the PC Card. Interrupt request (IREQ) Functional READY(IREQ)//CINT The assertion of IREQ indicates an interrupt request from the PC Card. Change in card status (CSTSCHG) CSC BVD1(STSCHG)//CSTSCHG The assertion of CSTSCHG indicates a status change on the PC Card. Interrupt request (CINT) Functional READY(IREQ)//CINT The assertion of CINT indicates an interrupt request from the PC Card. Card insertion or removal CSC CD1//CCD1, CD2//CCD2 A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit or CardBus PC Card. Power cycle complete CSC N/A An interrupt is generated when a PC Card power-up cycle has completed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PC Card functional and CSC interrupts (continued) The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The CardBus signal name follows after a forward double slash (//). The PC Card standard describes the power-up sequence that must be followed by the PCI1225 when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI1225 interrupt scheme can be used to notify the host system (see Table 14), denoted by the power cycle complete event. This interrupt source is considered a PCI1225 internal event because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface. interrupt masks and flags Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 14 by setting the appropriate bits in the PCI1225. By individually masking the interrupt sources listed, software can control those events that cause a PCI1225 interrupt. Host software has some control over the system interrupt the PCI1225 asserts by programming the appropriate routing registers. The PCI1225 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections. When an interrupt is signaled by the PCI1225, the interrupt service routine must determine which of the events listed in Table 13 caused the interrupt. Internal registers in the PCI1225 provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken. Table 13 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts. Notice that there is not a mask bit to stop the PCI1225 from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization. Various methods of clearing the interrupt flag bits are listed in Table 13. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the flag cleared on read method. The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning. using parallel IRQ interrupts The seven multifunction terminals, MFUNC6:0, implemented in the PCI1225 may be routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA type IRQ interrupt signaling, software must program the device control register, located at PCI offset 92h, to select the parallel IRQ signaling scheme. See the multifunction routing register description on page 64 for details on configuring the multifunction terminals. A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal for INTA signaling. The INTRTIE bit is used, in this case, to route socket 1 interrupt events to INTA. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions. 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 using parallel IRQ interrupts (continued) As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11, and IRQ15. The multifunction control register must be programmed to a value of 0x0FBA5432. This value routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 16. Not shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel PCI interrupts to the host. PCI1225 MFUNC1 IRQ3 PIC MFUNC2 IRQ4 MFUNC3 IRQ5 MFUNC4 IRQ10 MFUNC5 IRQ11 MFUNC6 IRQ15 Figure 16. IRQ Implementation Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration of a system implementing the PCI1225. The multifunction routing register is shared between the two PCI1225 functions, and only one write to function 0 or 1 is necessary to configure the MFUNC6:0 signals. Writing to only function 0 is recommended. See the multifunction routing register description on page 64 for details on configuring the multifunction terminals. The parallel ISA type IRQ signaling from the MFUNC6:0 terminals is compatible with those input directly into the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design constraints may demand more MFUNC6:0 IRQ terminals than the PCI1225 makes available. A system designer may choose to implement an IRQSER deserializer companion chip, such as the Texas Instruments PCI950. To use a deserializer, the MFUNC3 terminal must be configured as IRQSER and connected to the deserializer, which outputs all 15 ISA IRQs and four PCI interrupts as decoded from the IRQSER stream. using parallel PCI interrupts Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode parallel ISA IRQ signaling mode, and when only IRQs are serialized with the IRQSER protocol. Both INTA and INTB can be routed to MFUNC terminals (MFUNC0 and MFUNC1). However, interrupts of both socket functions can be routed to INTA (MFUNC0) if the INTRTIE bit is set in the system control register. The INTRTIE bit effects the read-only value provided through accesses to the interrupt pin register. When INTRTIE bit is set, both functions return a value of 0x01 on reads from the interrupt pin register for both parallel and serial PCI interrupts. The interrupt signalling modes are summarized in Table 15. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 using parallel PCI interrupts (continued) Table 15. Interrupt Pin Register Cross Reference INTRTIE BIT INTPIN FUNCTION 0 INTPIN FUNCTION 1 Parallel PCI interrupts only 0 01h (INTA) 02h (INTB) Parallel IRQ and parallel PCI interrupts 0 01h (INTA) 02h (INTB) IRQ serialized (IRQSER) and parallel PCI interrupts 0 01h (INTA) 02h (INTB) IRQ and PCI serialized (IRQSER) interrupts (default) 0 01h (INTA) 02h (INTB) Parallel PCI interrupts only 1 01h (INTA) 01h (INTA) Parallel IRQ and parallel PCI interrupts 1 01h (INTA) 01h (INTA) IRQ serialized (IRQSER) and parallel PCI interrupts† IRQ and PCI serialized (IRQSER) interrupts† 1 01h (INTA) 01h (INTA) INTERRUPT SIGNALING MODE 1 01h (INTA) 01h (INTA) † When configuring the PCI1225 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit. using serialized IRQSER interrupts The serialized interrupt protocol implemented in the PCI1225 uses a single terminal to communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data describes sixteen parallel ISA IRQ signals and the optional four PCI interrupts INTA, INTB, INTC, and INTD. For details on the IRQSER protocol see the document Serialized IRQ Support for PCI Systems. SMI support in the PCI1225 The PCI1225 provides a mechanism for interrupting the system when power changes have been made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme. SMI interrupts are generated by the PCI1225, when enabled, after a write cycle to either the socket control register of the CardBus register set or the power control register of the ExCA register set causes a power cycle change sequence sent on the power switch interface. The SMI control is programmed through three bits (bits 26–24) in the system control register. These bits are SMIROUTE, SMISTATUS, and SMIENB. The SMI control bits function as described in Table 16. Table 16. SMI Control BIT NAME FUNCTION SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1. SMIENB When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1. If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register. If IRQ2 is selected by SMIROUTE, the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC3 or MFUNC6 through the multifunction routing register. 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 power management overview TI has expended great effort to provide a high-performance device with low power consumption. In addition to the low-power CMOS technology process used for the PCI1225, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section. clock run protocol The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1225. CLKRUN signalling is provided through the MFUNC6 terminal. Since some chipsets do not implement CLKRUN, this is not always available to the system designer, and alternate power-saving features are provided. For details on the CLKRUN protocol see the PCI Mobile Design Guide. The PCI1225 does not permit the central resource to stop the PCI clock under any of the following conditions: The KEEPCLK bit in the system control register is set. The 16-bit PC Card resource manager is busy. The PCI1225 CardBus master state machine is busy. A cycle may be in progress on CardBus. The PCI1225 master is busy. There may be posted data from CardBus to PCI in the PCI1225. There are pending interrupts. The CardBus CCLK for either socket has not been stopped by the PCI1225 CLKRUN manager. The PCI1225 restarts the PCI clock using the CLKRUN protocol under any of the following conditions: A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card. A CardBus wake-up (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in either socket. A CardBus attempts to start CCLK using CCLKRUN. A CardBus card arbitrates for the CardBus bus using CREQ. A 16-bit DMA PC Card asserts DREQ. CardBus PC card power management The PCI1225 implements its own card power management engine that can be used to turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface to control this clock management. 16-Bit PC card power management The COE and PWRDOWN bits in the ExCA registers are provided for 16-bit PC Card power management. The COE bit three states the card interface to save power. The power savings when using this feature are minimal. The COE bit will reset the PC Card when used, and the PWRDOWN bit will not. Furthermore, the PWRDOWN bit is an automatic COE, that is, the PWRDOWN performs the COE function when there is no card activity. NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDOWN modes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 suspend mode The SUSPEND signal provides backward compatibility and gates the PCI reset (PRST) signal from the PCI1225. However, additional functionality has been defined for SUSPEND to provide additional power-management options. SUSPEND provides a mechanism to gate PCLK from the PCI1225, as well as gate PRST. This can potentially save power while in an idle state; however, it requires substantial design effort to implement. Some issues to consider are: What if cards are present in the sockets? What if the cards in the sockets are powered? How to pass CSC (insertion/removal) events. Even without the PCI clock to the PCI1225 core, asynchronous-type functions (such as RI_OUT) can pass CSC events, wake-up events, etc., back to the system. If a system designer chooses to not pass card removal events through to the system, then the PCI1225 would not be able to power down the empty socket without the power switch clock (CLOCK) generated externally. See the P2C power switch interface for details. Figure 17 is a functional implementation diagram. PRST PCI1225 Core SUSPEND GNT PCLK Figure 17. SUSPEND Functional Implementation Figure 18 is a signal diagram of the suspend function. 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 suspend mode (continued) PRST GNT SUSPEND PCLK External Terminals Internal Signals PRSTIN SUSPENDIN PCLKIN Figure 18. Signal Diagram of Suspend Function ring indicate The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform requirements. RI_OUT on the PCI1225 can be asserted under any of the following conditions: A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call. A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up. A CSC event occurs, such as insertion/removal of cards, battery voltage levels. CSTSCHG from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two RI_OUT events are enabled separately. Figure 19 shows various enable bits for the PCI1225 RI_OUT function; however, it does not show the masking of CSC events. See Table 13 for a detailed description of CSC interrupt masks and flags. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ring indicate (continued) RI_OUT Function CSTSMASK PC Card Socket 0 CSC Card I/F RINGEN RI CDRESUME RIENB CSC RI_OUT CSTSMASK PC Card Socket 1 CSC Card I/F RINGEN RI CDRESUME CSC Figure 19. RI_OUT Functional Diagram RI from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the interrupt and general control register. This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket. The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers. PCI power management (PCIPM) The PCI power-management (PCIPM) specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software-visible power-management states that result in varying levels of power savings. The four power-management states of PCI functions are: D0 – Fully-on state D1 and D2 – Intermediate states D3 – Off state Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power state of the originating bridge device. For the operating system (OS) to power manage the device power states on the PCI bus, the PCI function should support four power-management operations. These operations are: 44 Capabilities reporting Power status reporting Setting the power state System wake up POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PCI power management (PCIPM) (continued) The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1 in the capabilities list (CAPLIST) bit in the status register (bit 4) and providing access to a capabilities list. The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1225, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, the next item pointer should be set to 0. The registers following the next item pointer are specific to the function capability. The PCIPM capability implements the register block outlined in Table 17. Table 17. Power-Management Registers REGISTER NAME Power-management capabilities Data OFFSET Next item pointer PMCSR bridge support extensions Capability ID 0 Power-management control status (CSR) 4 The power management capabilities register is a static read-only register that provides information on the capabilities of the function related to power management. The PMCSR register enables control of power-management states and enables/monitors power-management events. The data register is an optional register that can provide dynamic data. For more information on PCI power management see the PCI Bus Power Management Interface Specification. ACPI support The ACPI specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCI1225 offers a generic interface that is compliant with ACPI design rules. Two doublewords of general purpose ACPI programming bits reside in PCI1225 PCI configuration space at offset A8h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in GPE_STS and GPE_EN registers. The status and enable bits are implemented as defined by ACPI, and illustrated in Figure 20. Status Bit Event Input Enable Bit Event Output Figure 20. Block Diagram of a Status/Enable Cell The status and enable bits are used to generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events. For more information of ACPI see the Advanced Configuration and Power Interface Specification. PC Card controller programming model This section describes the PCI1225 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI1225 function. As noted, some bits are global in nature and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PCI configuration registers (functions 0 and 1) The PCI1225 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The configuration header is compliant with the PCI specification as a CardBus bridge header and is PC98 compliant as well. Table 18 shows the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers. Table 18. PCI Configuration Registers (Functions 0 and 1) REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code BIST Header type Latency timer Revision ID 08h Cache line size 0Ch CardBus socket/ExCA base address Secondary status CardBus latency timer Subordinate bus number 10h Reserved Capability pointer 14h CardBus bus number PCI bus number 18h CardBus memory base register 0 1Ch CardBus memory limit register 0 20h CardBus memory base register 1 24h CardBus memory limit register 1 28h CardBus I/O base register 0 2Ch CardBus I/O limit register 0 30h CardBus I/O base register 1 34h CardBus I/O limit register 1 38h Bridge control Interrupt pin Subsystem ID Interrupt line Subsystem vendor ID 44h Reserved 48h–7Ch System control 80h Reserved 84h–88h Device control 8Ch Card control Retry status 94h Socket DMA register 1 98h Reserved 9Ch Next-item pointer PMCSR bridge support extensions Capability ID Power-management control/status A0h A4h General-purpose event enable General-purpose event status A8h General-purpose output General-purpose input ACh Serial bus control/status Serial bus slave address Serial bus index Reserved 46 90h Socket DMA register 0 Power-management capabilities PM data 40h PC Card 16-bit I/F legacy-mode base address Multifunction routing Diagnostic 3Ch POST OFFICE BOX 655303 Serial bus data B0h B4h–FCh • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 vendor ID register Bit 15 14 13 12 11 10 9 8 Type R R R R R R R R Default 0 0 0 1 0 0 0 0 Name 7 6 5 4 3 2 1 0 R R R R R R R R 0 1 0 0 1 1 0 0 Vendor ID Register: Type: Offset: Default: Description: Vendor ID Read-only 00h (functions 0, 1) 104Ch This 16-bit read-only register contains a value allocated by the PCI Special Interest Group (SIG) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch. device ID register Bit 15 14 13 12 11 10 9 8 Name 7 6 5 4 3 2 1 0 Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 Register: Type: Offset: Default: Description: Device ID Read-only 02h (functions 0, 1) AC1Ch This 16-bit read-only register contains a value assigned to the PCI1225 by TI. The device identification for the PCI1225 is AC1Ch. command register Bit 15 14 13 12 11 10 9 8 Name 7 6 5 4 3 2 1 0 Command Type R R R R R R R R/W R R/W R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Command Read-only, read/write (see individual bit descriptions) 04h 0000h The command register provides control over the PCI1225 interface to the PCI bus. All bit functions adhere to the definitions in PCI Local Bus Specification 2.2. None of the bit functions in this register are shared between the two PCI1225 PCI functions. Two command registers exist in the PCI1225, one for each function. Software must manipulate the two PCI1225 functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally wired-OR between the two functions, and these control bits appear separately according to their software function. See Table 19 for the complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 19. Command Register BIT SIGNAL TYPE 15–10 RSVD R Reserved. Bits 15–10 are read-only and return 0s when read. Write transactions have no effect. 9 FBB_EN R Fast back-to-back enable. The PCI1225 does not generate fast back-to-back transactions; therefore, bit 9 is read-only and returns 0s when read. 48 FUNCTION 8 SERR_EN R/W System Error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both bit 8 and bit 6 must be set for the PCI1225 to report address parity errors. 0 = Disable SERR output driver (default) 1 = Enable SERR output driver 7 STEP_EN R Address/data stepping control. The PCI1225 does not support address/data stepping, and bit 7 is hardwired to 0. Write transactions to this bit have no effect. 6 PERR_EN R/W Parity error response enable. Bit 6 controls the PCI1225 response to parity errors through PERR. Data parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting SERR. 0 = PCI1225 ignores detected parity error (default) 1 = PCI1225 responds to detected parity errors 5 VGA_EN R VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette registers. The PCI1225 does not support VGA palette snooping; therefore, this bit is hardwired to 0. Bit 5 is read-only and returns 0 when read. Write transactions to this bit have no effect. 4 MWI_EN R Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and Invalidate commands. The PCI1225 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. Bit 4 is read-only and returns 0 when read. Write transactions to this bit have no effect. 3 SPECIAL R Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1225 does not respond to special cycle operations; therefore, this bit is hardwired to 0. Bit 3 is read-only and returns 0 when read. Write transactions to this bit have no effect. 2 MAST_EN R/W Bus master control. Bit 2 controls whether or not the PCI1225 can act as a PCI bus initiator (master). The PCI1225 can take control of the PCI bus only when this bit is set. 0 = Disables the PCI1225 ability to generate PCI bus accesses (default) 1 = Enables the PCI1225 ability to generate PCI bus accesses 1 MEM_EN R/W Memory space enable. Bit 1 controls whether or not the PCI1225 can claim cycles in PCI memory space. 0 = Disables the PCI1225 response to memory space accesses (default) 1 = Enables the PCI1225 response to memory space accesses 0 IO_EN R/W I/O space control. Bit 0 controls whether or not the PCI1225 can claim cycles in PCI I/O space. 0 = Disables the PCI1225 from responding to I/O space accesses (default) 1 = Enables the PCI1225 to respond to I/O space accesses POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 status register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/C R/C R/C R/C R/C R R R/C 0 0 0 0 0 0 1 R R R R R R R R 0 0 0 0 1 0 0 0 0 Name Type Default Status Register: Type: Offset: Default: Description: Status Read-only, read/clear (see individual bit descriptions) 06h (functions 0, 1) 0210h The status register provides device information to the host system. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Local Bus Specification 2.2. PCI bus status is shown through each function. See Table 20 for the complete description of the register contents. Table 20. Status Register BIT SIGNAL TYPE FUNCTION 15 PAR_ERR R/C Detected parity error. Bit 15 is set when a parity error is detected (either address or data). 14 SYS_ERR R/C Signaled system error. Bit 14 is set when SERR is enabled and the PCI1225 signals a system error to the host. 13 MABORT R/C Received master abort. Bit 13 is set when a cycle initiated by the PCI1225 on the PCI bus has been terminated by a master abort. 12 TABT_REC R/C Received target abort. Bit 12 is set when a cycle initiated by the PCI1225 on the PCI bus was terminated by a target abort. 11 TABT_SIG R/C Signaled target abort. Bit 11 is set by the PCI1225 when it terminates a transaction on the PCI bus with a target abort. 10–9 PCI_SPEED R DEVSEL timing. These read-only bits encode the timing of DEVSEL and are hardwired 01b, indicating that the PCI1225 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses. Data parity error detected. 0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred, and the following conditions were met: a. PERR was asserted by any PCI device including the PCI1225. b. The PCI1225 was the bus master during the data parity error. c. The PERR_EN bit is set in the command register. 8 DATAPAR R/C 7 FBB_CAP R Fast back-to-back capable. The PCI1225 cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0. 6 UDF R User-definable feature support. The PCI1225 does not support the user-definable features; thus, bit 6 is hardwired to 0. 5 66MHZ R 66-MHz capable. The PCI1225 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4 CAPLIST R Capabilities list. Bit 4 is read-only and returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3–0 RSVD R Reserved. Bits 3–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 revision ID register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 1 Name Revision ID Register: Type: Offset: Default: Description: Revision ID Read-only 08h (functions 0, 1) 01h This read-only register indicates the silicon revision of the PCI1225. PCI class code register Bit 23 22 21 20 19 18 17 16 15 14 13 12 Name 11 10 9 8 7 6 5 4 3 2 1 0 Class code Base class Sub class Programming interface Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: PCI Class code Read-only 09h (functions 0, 1) 060700h The class code register recognizes the PCI1225 functions 0 and 1 as a bridge device (06h), and CardBus bridge device (07h) with a 00h programming interface. cache line size register Bit 7 6 5 Name Type Default 3 2 1 0 Cache line size R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: 50 4 Cache line size Read/write 0Ch (functions 0, 1) 00h The cache line size register is programmed by host software to indicate the system cache line size. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 latency timer register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 Name Latency timer Type Default Register: Type: Offset: Default: Description: Latency timer Read/write 0Dh 00h The latency timer register specifies the latency timer for the PCI1225 in units of PCI clock cycles. When the PCI1225 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI1225 transaction has terminated, the PCI1225 terminates the transaction when its GNT is deasserted. This register is separate for each of the two PCI1225 functions. This allows platforms to prioritize the two PCI1225 functions’ use of the PCI bus. header type register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 1 0 0 R R R R 0 0 0 1 0 Name Header type Register: Type: Offset: Default: Description: Header type Read-only 0Eh (functions 0, 1) 82h This read-only register returns 82h when read, indicating that the PCI1225 functions 0 and 1 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 00h to 7Fh, and 80h–FFh is user-definable extension registers. BIST register Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name BIST Register: Type: Offset: Default: Description: BIST Read-only 0Fh (functions 0, 1) 00h Because the PCI1225 does not support a built-in self-test (BIST), this register is read-only and returns the value of 00h when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 CardBus socket registers/ExCA base-address register Bit 31 30 29 28 27 26 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 24 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 CardBus socket/ExCA base address Name Type 25 CardBus socket/ExCA base address R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: CardBus socket/ExCA base address Read-only, read/write 10h 0000 0000h The CardBus socket registers/ExCA base-address register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11–0 are read-only, returning 0s when read. When software writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4 Kbytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. Since this register is not shared by functions 0 and 1, mapping of each socket control is performed separately. capability pointer register Bit 7 6 5 Name 4 3 2 1 0 Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0 Register: Type: Offset: Default: Description: 52 Capability pointer Read-only 14h A0h The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register is read-only and returns A0h when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 secondary status register Bit 15 14 13 12 11 10 9 R/C R/C R/C R/C R/C R R R/C 0 0 0 0 0 0 1 0 Name Type Default 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Secondary status Register: Type: Offset: Default: Description: Secondary status Read-only, read/clear (see individual bit descriptions) 16h 0200h The secondary status register is compatible with the PCI-to-PCI bridge secondary status register, and indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (offset 06h); status bits are cleared by writing a 1. See Table 21 for a complete description of the register contents. Table 21. Secondary Status Register BIT SIGNAL TYPE FUNCTION 15 CBPARITY R/C Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). 14 CBSERR R/C Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1225 does not assert CSERR. 13 CBMABORT R/C Received master abort. Bit 13 is set when a cycle initiated by the PCI1225 on the CardBus bus has been terminated by a master abort. 12 REC_CBTA R/C Received target abort. Bit 12 is set when a cycle initiated by the PCI1225 on the CardBus bus is terminated by a target abort. 11 SIG_CBTA R/C Signaled target abort. Bit 11 is set by the PCI1225 when it terminates a transaction on the CardBus bus with a target abort. 10–9 CB_SPEED R CDEVSEL timing. These read-only bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the PCI1225 asserts CB_SPEED at a medium speed. CardBus data parity error detected. 0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred and the following conditions were met: a. CPERR was asserted on the CardBus interface. b. The PCI1225 was the bus master during the data parity error. c. The PERR_EN bit is set in the bridge control register. 8 CB_DPAR R/C 7 CBFBB_CAP R Fast back-to-back capable. The PCI1225 cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0. 6 CB_UDF R User-definable feature support. The PCI1225 does not support the user-definable features; thus, bit 6 is hardwired to 0. 5 CB66MHZ R 66-MHz capable. The PCI1225 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4–0 RSVD R Reserved. Bits 4–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PCI bus number register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 PCI bus number Register: Type: Offset: Default: Description: PCI bus number Read/write 18h (functions 0, 1) 00h This read/write register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI1225 is connected. The PCI1225 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. CardBus bus number register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CardBus bus number Register: Type: Offset: Default: Description: CardBus bus number Read/write 19h 00h This read/write register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI1225 is connected. The PCI1225 uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI1225 controller function. subordinate bus number register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 Subordinate bus number Register: Type: Offset: Default: Description: 54 4 Subordinate bus number Read/write 1Ah 00h This read/write register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The PCI1225 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each CardBus controller function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 CardBus latency timer register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CardBus latency timer Type Default Register: Type: Offset: Default: Description: CardBus latency timer Read/write 1Bh (functions 0, 1) 00h This read/write register is programmed by the host system to specify the latency timer for the PCI1225 CardBus interface in units of CCLK cycles. When the PCI1225 is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI1225 transaction has terminated, then the PCI1225 terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed. memory base registers 0, 1 Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Memory base registers 0, 1 Name Type 24 Memory base registers 0, 1 R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Memory base registers 0, 1 Read-only, read/write 1Ch, 24h 0000 0000h The memory base registers indicate the lower address of a PCI memory address range. These registers are used by the PCI1225 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1225 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4 Kbytes of memory to CardBus). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 memory limit registers 0, 1 Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Memory limit registers 0, 1 Name Type 24 Memory limit registers 0, 1 R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Memory limit registers 0, 1 Read-only, read/write 20h, 28h 0000 0000h The memory limit registers indicate the upper address of a PCI memory address range. These registers are used by the PCI1225 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1225 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4 Kbytes of memory to CardBus). I/O base registers 0, 1 Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 I/O base registers 0, 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Type Default I/O base registers 0, 1 Register: Type: Offset: Default: Description: I/O base registers 0, 1 Read-only, read/write 2Ch, 34h 0000 0000h The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the PCI1225 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64K byte page, and the upper sixteen bits (31–16) are a page register which locates this 64K byte page in 32-bit PCI I/O address space. Bits 31–2 are read/write. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. NOTE: Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions. 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 I/O limit registers 0, 1 Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Default 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 I/O limit registers 0, 1 Name Type 24 I/O limit registers 0, 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: I/O limit registers 0, 1 Read-only, read/write 30h, 38h 0000 0000h The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the PCI1225 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16 of the appropriate I/O base) on doubleword boundaries. Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Write transactions to read-only bits have no effect. The PCI1225 assumes that the lower two bits of the limit address are 1s. NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction. interrupt line register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 1 1 1 R/W R/W R/W R/W 1 1 1 1 1 Name Type Default Interrupt line Register: Type: Offset: Default: Description: Interrupt line Read/write 3Ch FFh The interrupt line register is read/write and is used to communicate interrupt line routing information. Each PCI1225 function has an interrupt line register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 interrupt pin register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 1 1 Name Interrupt pin Register: Type: Offset: Default: Description Interrupt pin Read-only 3Dh Depends on the interrupt signaling mode (sample shown is 03h) The value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode, selected through the device control register and the state of the INTRTIE bit in the system control register. When the INTRTIE bit is set, this register reads 0x01 (INTA) for both functions. See Table 22 for the complete description of the register contents. Table 22. Interrupt Pin Register Cross Reference INTRTIE BIT INTPIN FUNCTION 0 INTPIN FUNCTION 1 Parallel PCI interrupts only 0 01h (INTA) 02h (INTB) Parallel IRQ and parallel PCI interrupts 0 01h (INTA) 02h (INTB) IRQ serialized (IRQSER) and parallel PCI interrupts 0 01h (INTA) 02h (INTB) IRQ and PCI serialized (IRQSER) interrupts (default) 0 01h (INTA) 02h (INTB) Parallel PCI interrupts only 1 01h (INTA) 01h (INTA) Parallel IRQ and parallel PCI interrupts 1 01h (INTA) 01h (INTA) IRQ serialized (IRQSER) and parallel PCI interrupts† IRQ and PCI serialized (IRQSER) interrupts† 1 01h (INTA) 01h (INTA) 1 01h (INTA) INTERRUPT SIGNALING MODE 01h (INTA) † When configuring the PCI1225 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit. 58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 bridge control register Bit 15 14 13 12 11 10 9 Type R R R R R R/W R/W R/W Default 0 0 0 0 0 0 1 1 Name 8 7 6 5 4 3 2 1 0 R/W R/W R/W R R/W R/W R/W R 0 1 0 0 0 0 0 0 Bridge control Register: Type: Offset: Default: Description: Bridge control Read-only, read/write (see individual bit descriptions) 3Eh (functions 0, 1) 0340h The bridge control register provides control over various PCI1225 bridging functions. Some bits in this register are global and should be accessed only through function 0. See Table 23 for a complete description of the register contents. Table 23. Bridge Control Register BIT SIGNAL TYPE 15–11 RSVD R FUNCTION Reserved. Bits 15–11 return 0s when read. 10 POSTEN R/W Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles. Note that burst write data can be posted, but various write transactions may not. Bit 10 is socket dependent and is not shared between functions 0 and 1. 9 PREFETCH1 R/W Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. Bit 9 is encoded as: 0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default). 8 PREFETCH0 R/W Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is encoded as: 0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default). 7 INTR R/W PCI interrupt – IREQ routing enable. Bit 7 is used to select whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers. 0 = Functional interrupts routed to PCI interrupts (default) 1 = Functional interrupts routed by ExCAs R/W CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted by passing a PRST assertion to CardBus. 0 = CRST deasserted 1 = CRST asserted (default) Master abort mode. Bit 5 controls how the PCI1225 responds to a master abort when the PCI1225 is an initiator on the CardBus interface. This bit is common between each socket. 0 = Master aborts not reported (default) 1 = Signal target abort on PCI and SERR (if enabled) 6 CRST 5† MABTMODE R/W 4 RSVD R 3 VGAEN R/W VGA enable. Bit 3 affects how the PCI1225 responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded. 2 ISAEN R/W ISA mode enable. Bit 2 affects how the PCI1225 passes I/O cycles within the 64-Kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI1225 does not forward the last 768 bytes of each 1K I/O range to CardBus. Reserved. Bit 4 returns 0 when read. 1† CSERREN R/W CSERR enable. Bit 1 controls the response of the PCI1225 to CSERR signals on the CardBus bus. This bit is common between the two sockets. 0 = CSERR is not forwarded to PCI SERR. 1 = CSERR is forwarded to PCI SERR. 0† CPERREN R CardBus parity error response enable. Bit 0 controls the response of the PCI1225 to CardBus parity errors. This bit is common between the two sockets. 0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR. † These bits are global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 subsystem vendor ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Subsystem vendor ID Register: Type: Offset: Default: Description: Subsystem vendor ID Read-only (read/write when bit 5 in the system control register is 0) 40h (functions 0, 1) 0000h The subsystem vendor ID register is used for system and option-card identification purposes and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. subsystem ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Subsystem ID Register: Type: Offset: Default: Description: 60 8 Subsystem ID Read-only (read/write when bit 5 in the system control register is 0) 42h (functions 0, 1) 0000h The subsystem ID register is used for system and option-card identification purposes and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PC Card 16-bit I/F legacy-mode base address register Bit 31 30 29 28 27 26 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 Name Type Default 24 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 5 4 3 2 1 0 PC Card 16-bit I/F legacy-mode base address Name Type 25 PC Card 16-bit I/F legacy-mode base address R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: Type: Offset: Default: Description: PC Card 16-bit I/F legacy-mode base address Read-only, read/write (see individual bit descriptions) 44h (functions 0, 1) 0000 0001h The PCI1225 supports the index/data scheme of accessing the ExCA registers, which are mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. As specified in the PCI to PCMCIA CardBus Bridge Register Description (Yenta), this register is shared by functions 0 and 1. See ExCA compatibility registers on page 83 for register offsets. system control register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 System control R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 Name Type Default System control Register: Type: Offset: Default: Description: System control Read-only, read/write (see individual bit descriptions) 80h (functions 0, 1) 0044 9060h System-level initializations are performed through programming this doubleword register. Some of the bits are global and should be written only through function 0. See Table 24 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 24. System Control Register BIT 31–30† SIGNAL SER_STEP TYPE FUNCTION R/W Serialized PCI interrupt routing step. Bits 31–30 are used to configure the serialized PCI interrupt stream signaling, and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. Bits 31–30 are global to all PCI1225 functions. 00 = INTA/INTB signal in INTA/INTB IRQSER slots 01 = INTA/INTB signal in INTB/INTC IRQSER slots 10 = INTA/INTB signal in INTC/INTD IRQSER slots 11 = INTA/INTB signal in INTD/INTA IRQSER slots Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally and are signaled as INTA. INTA can then be shifted by using the SER_STEP bits. This bit is global to all PCI1225 functions. When configuring the PCI1225 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit. 29† INTRTIE R/W 28 RSVD R Reserved. Bit 28 is read-only and returns 0 when read. 27† P2CCLK R/W P2C power switch clock. The PCI1225 defaults CLOCK as an input clock to control the serial interface and the internal state machine. Bit 27 can be set to enable the PCI1225 to generate and drive the CLOCK from the PCI clock. When in a SUSPEND state, however, CLOCK must be input to the PCI1225 to successfully power down sockets after card removal without indicating to the system the removal event. 0 = CLOCK provided externally, input to PCI1225 (default) 1 = CLOCK generated by PCI clock and driven by PCI1225 26† SMIROUTE R/W SMI interrupt routing. Bit 26 is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket. 0 = PC Card power change interrupts routed to IRQ2 (default) 1 = A CSC interrupt is generated on PC Card power changes. 25 SMISTATUS R/W SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to bit 25 clears the status. 0= SMI interrupt signaled (default) 1 = SMI interrupt not signaled 24† SMIENB R/W SMI interrupt mode enable. When bit 24 is set, the SMI interrupt signaling is enabled and generates an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled). 23 RSVD R Reserved. This bit is read-only and returns 0 when read. 22 CBRSVD R/W CardBus reserved terminals signaling. When bit 22 is set, the RSVD CardBus terminals are driven low when a CardBus card is inserted. When this bit is low (as default), these signals are 3-stated. 0 = 3-state CardBus RSVD 1 = Drive Cardbus RSVD low (default) 21 VCCPROT R/W VCC protection enable. Bit 21 is socket dependent. 0 = VCC protection enabled for 16-bit cards (default) 1 = VCC protection disabled for 16-bit cards R/W Reduced zoom video enable. When this bit is enabled, A25–A22 of the card interface for 16-bit PC Cards is placed in the high impedance state. This bit should not be set for normal ZV operation. This bit is encoded as: 0 = Reduced zoom video disabled (default) 1 = Reduced zoom video enabled 20 REDUCEZV 19 CDREQEN R/W PC/PCI DMA card enable. When bit 19 is set, the PCI1225 allows 16-bit PC Cards to request PC/PCI DMA using the DREQ signaling. DREQ is selected through the socket DMA register 0. 0 = Ignore DREQ signaling from PC Cards (default) 1 = Signal DMA request on DREQ 18–16 CDMACHAN R/W PC/PCI DMA channel assignment. Bits 18–16 are encoded as: 0–3 = 8-bit DMA channels 4 = PCI master; not used (default). 5–7 = 16-bit DMA channels † These bits are global and should be accessed only through function 0. 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 24. System Control Register (Continued) BIT SIGNAL TYPE FUNCTION 15† MRBURSTDN R/W Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst downstream. 0 = Downstream memory read burst is disabled. 1 = Downstream memory read burst is enabled (default). 14† MRBURSTUP R/W Memory read burst enable upstream. When bit 14 is set, the PCI1225 allows memory read transactions to burst upstream. 0 = Upstream memory read burst is disabled (default). 1 = Upstream memory read burst is enabled. 13 SOCACTIVE R Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and is cleared upon read of this status bit. This bit is socket dependent. 0 = No socket activity (default) 1 = Socket activity 12 RSVD R Reserved. Bit 12 is read-only and returns 1 when read. 11† PWRSTREAM R Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. This bit is cleared when the power stream is complete. 0 = Power stream is complete and delay has expired. 1 = Power stream is in progress. 10† DELAYUP R Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay has expired. 9† DELAYDOWN R Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-down delay has expired. 8 INTERROGATE R Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when interrogation completes. This bit is socket dependent. 0 = Interrogation not in progress (default) 1 = Interrogation in progress 7 RSVD R Reserved. Bit 7 is read-only and returns 0 when read. 6 PWRSAVINGS R/W Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock, the applicable CB state machine will not be clocked. 5† SUBSYSRW R/W Subsystem ID (SSID), subsystem vendor ID (SSVID), ExCA ID, and revision register read/write enable. Bit 5 is shared by functions 0 and 1. 0 = SSID, SSVID, ExCA ID, and revision register are read/write. 1 = SSID, SSVID, ExCA ID, and revision register are read-only (default). 4† CB_DPAR R/W CardBus data parity SERR signaling enable 0 = CardBus data parity not signaled on PCI SERR 1 = CardBus data parity signaled on PCI SERR 3† CDMA_EN R/W PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set if MFUNC0–MFUNC6 are configured for centralized DMA. 0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled 2 RSVD R 1† KEEPCLK R/W Keep clock. This bit works with PCI and CB CLKRUN protocols. 0 = Allows normal functioning of both CLKRUN protocols.(default) 1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols. 0 RIMUX R/W RI_OUT/PME multiplex enable. 0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both are enabled at the same time, RI_OUT has precedence over PME. 1 = Only PME is routed to the RI_OUT/PME terminal. Reserved † These bits are global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 multifunction routing register Bit 31 30 29 28 27 26 25 Type R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Multifunction routing Name Type 24 Multifunction routing R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Multifunction routing Read-only, read/write (see individual bit descriptions) 8Ch (functions 0, 1) 0000 0000h The multifunction routing register is used to configure the MFUNC0–MFUNC6 terminals. These terminals may be configured for various functions. All multifunction terminals default to the general-purpose input configuration. Pullup resistors are required for terminals configured as outputs. This register is intended to be programmed once at power-on initialization. The default value for this register may also be loaded through a serial bus EEPROM. See Table 25 for a complete description of the register contents. Table 25. Multifunction Routing Register BIT SIGNAL TYPE 31–28 RSVD R 27–24 64 MFUNC6 R/W FUNCTION Bits 31–28 are read/only and return 0s when read. Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal as follows: 0000 – RSVD = Reserved input – high impedance (default) 0001 – CLKRUN = PCI clock control signal 0010 – IRQ2 = Parallel ISA type IRQ2 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – IRQ6 = Parallel ISA type IRQ6 0111 – IRQ7 = Parallel ISA type IRQ7 1000 – IRQ8 = Parallel ISA type IRQ8 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – IRQ12 = Parallel ISA type IRQ12 1101 – IRQ13 = Parallel ISA type IRQ13 1110 – IRQ14 = Parallel ISA type IRQ14 1111 – IRQ15 = Parallel ISA type IRQ15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 25. Multifunction Routing Register (Continued) BIT 23–20 SIGNAL MFUNC5 TYPE FUNCTION R/W Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal as follows: 0000 – GPI4 = General-purpose input (default) 0001 – GPO4 = General-purpose output 0010 – PCGNT = PC/PCI (centralized) DMA grant 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL1 = Zoom video function 1 select output 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – LEDA1 = Socket 0 activity LED 1101 – LED_SKT = Socket 0 or socket 1 activity LED 1110 – GPE = General-Purpose event signal 1111 – IRQ15 = Parallel ISA type IRQ15 Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal as follows: NOTE: When the serial bus mode is implemented by pulling down the LATCH terminal, the MFUNC4 terminal provides the SCL signaling. 19–16 15–12 MFUNC4 MFUNC3 R/W R/W 0000 – GPI3 = General-purpose input (default) 0001 – GPO3 = General-purpose output 0010 – LOCK PCI = Atomic transfer support mechanism 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL1 = Zoom video function 1 select output 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – RI_OUT = Ring-indicate output 1101 – LED_SKT = Socket 0 or socket 1 activity LED 1110 – GPE = General-purpose event signal 1111 – IRQ15 = Parallel ISA type IRQ15 Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal as follows: 0000 – RSVD = Reserved input – high impedance (default) 0001 – IRQSER = Serial interrupt stream, IRQ and optional PCI 0010 – IRQ2 = Parallel ISA type IRQ2 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – IRQ6 = Parallel ISA type IRQ6 0111 – IRQ7 = Parallel ISA type IRQ7 1000 – IRQ8 = Parallel ISA type IRQ8 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – IRQ12 = Parallel ISA type IRQ12 1101 – IRQ13 = Parallel ISA type IRQ13 1110 – IRQ14 = Parallel ISA type IRQ14 1111 – IRQ15 = Parallel ISA type IRQ15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 25. Multifunction Routing Register (Continued) BIT 11–8 SIGNAL MFUNC2 TYPE FUNCTION R/W Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal as follows: 0000 – GPI2 = General-purpose input (default) 0001 – GPO2 = General-purpose output 0010 – PCREQ = PC/PCI (centralized) DMA request 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL0 = Zoom video function 0 select output 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – RI_OUT = Ring-indicate output 1101 – LEDA2 = Socket 1 activity LED 1110 – GPE = General-purpose event signal 1111 – IRQ7 = Parallel ISA type IRQ7 Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows: NOTE: When the serial bus mode is implemented by pulling down the LATCH terminal, the MFUNC1 terminal provides the SDA signaling. 7–4 3–0 66 MFUNC1 MFUNC0 R/W R/W 0000 – GPI1 = General-purpose input (default) 0001 – GPO1 = General-purpose output 0010 – INTB = PCI interrupt signal, INTB 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL0 = Zoom video function 0 select output 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – LEDA1 = Socket 0 activity LED 1101 – LEDA2 = Socket 1 activity LED 1110 – GPE = General-purpose event signal 1111 – IRQ15 = Parallel ISA type IRQ15 Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal as follows: 0000 – GPI0 = General-purpose input (default) 0001 – GPO0 = General-purpose output 0010 – INTA = PCI interrupt signal, INTA 0011 – IRQ3 = Parallel ISA type IRQ3 0100 – IRQ4 = Parallel ISA type IRQ4 0101 – IRQ5 = Parallel ISA type IRQ5 0110 – ZVSTAT = Zoom video status output 0111 – ZVSEL0 = Zoom video function 0 select output 1000 – CAUDPWM = PWM output of CAUDIO CardBus terminal 1001 – IRQ9 = Parallel ISA type IRQ9 1010 – IRQ10 = Parallel ISA type IRQ10 1011 – IRQ11 = Parallel ISA type IRQ11 1100 – LEDA1 = Socket 0 activity LED 1101 – LEDA2 = Socket 1 activity LED 1110 – GPE = General-purpose event signal 1111 – IRQ15 = Parallel ISA type IRQ15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 retry status register Bit 7 6 5 4 3 2 1 0 R/W R/W R/C R 1 1 0 R/C R R/C R 0 0 0 0 0 Name Type Default Retry status Register: Type: Offset: Default: Description: Retry status Read-only, read/write, read/clear (see individual bit descriptions) 90h (functions 0, 1) C0h The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set when the PCI1225 retries a PCI or CardBus master request, and the master does not return within 215 PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI command, PCI status, and bridge control registers by the PCI SIG. Access this register only through function 0. See Table 26 for a complete description of the register contents. Table 26. Retry Status Register BIT SIGNAL TYPE FUNCTION 7 PCIRETRY R/W PCI retry time-out counter enable. Bit 7 is encoded: 0 = PCI retry counter disabled 1 = PCI retry counter enabled (default) 6† CBRETRY R/W CardBus retry time-out counter enable. Bit 6 is encoded: 0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default) 5 TEXP_CBB R/C CardBus target B retry expired. Write a 1 to clear bit 5. 0 = Inactive (default) 1 = Retry has expired 4 RSVD R 3† TEXP_CBA R/C 2 RSVD R 1 TEXP_PCI R/C Reserved. Bit 4 returns 0 when read. CardBus target A retry expired. Write a 1 to clear bit 3. 0 = Inactive (default) 1 = Retry has expired. Reserved. Bit 2 returns 0 when read. PCI target retry expired. Write a 1 to clear bit 1. 0 = Inactive (default) 1 = Retry has expired. 0 RSVD R Reserved. Bit 0 returns 0 when read. † These bits are global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 67 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 card control register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R 0 0 0 R R/W R/W R/C 0 0 0 0 0 Name Type Default Card control Register: Type: Offset: Default: Description: Card control Read-only, read/write, read/clear (see individual bit descriptions) 91h 00h The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and the enable bit is shared between functions 0 and 1. See Table 27 for a complete description of the register contents. Table 27. Card Control Register BIT SIGNAL TYPE 7† RIENB R/W Ring indicate output enable. 0 = Disables any routing of RI_OUT signal (default). 1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal when RIMUX is set to 0, and for routing to MFUNC2/4. 6 ZVENABLE R/W Compatibility ZV mode enable. When set, the corresponding PC Card socket interface ZV terminals enter a high-impedance state. This bit defaults to 0. 5 PORT_SEL R/W Port select. This bit controls the priority for the ZVSEL0 and ZVSEL1 signaling if ZVENABLE is set in both functions. 0 = Socket 0 takes priority, as signaled through ZVSEL0, when both sockets are in ZV mode. 1 = Socket 1 takes priority, as signaled through ZVSEL1, when both sockets are in ZV mode. 4–3 RSVD R 2 AUD2MUX R/W CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding multifunction terminal which may be configured for CAUDPWM. When both socket 0 and 1 functions have AUD2MUX set, socket 0 takes precedence. R/W Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The SPKR signal from socket 0 is exclusive ORed with the SPKR signal from socket 1 and sent to SPKROUT. The SPKROUT terminal drives data only when the SPKROUTEN bit of either function is set. This bit is encoded as: 0 = SPKR to SPKROUT not enabled 1 = SPKR to SPKROUT enabled R/C Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a functional interrupt is signaled from a PC Card interface and is socket dependent (i.e., not global). Write back a 1 to clear this bit. 0 = No PC Card functional interrupt detected (default). 1 = PC Card functional interrupt detected. 1 0 SPKROUTEN IFG FUNCTION Reserved. Bits 4–3 are read-only and default to 0. † This bit is global and should be accessed only through function 0. 68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 device control register Bit 7 6 5 4 3 2 1 0 Type R R/W R/W R Default 0 1 1 R/W R/W R/W R/W 0 0 1 1 0 Name Device control Register: Type: Offset: Default: Description: Device control Read-only, read/write (see individual bit descriptions) 92h (functions 0, 1) 66h The device control register is provided for PCI1130 compatibility and contains bits that are shared between functions 0 and 1. The interrupt mode select is programmed through this register which is composed of PCI1225 global bits. The socket-capable force bits are also programmed through this register. See Table 28 for a complete description of the register contents. Table 28. Device Control Register BIT SIGNAL TYPE 7 RSVD R Reserved. Bit 7 Returns 0 when read. 6† 3VCAPABLE R/W 3-V socket capable force 0 = Not 3-V capable 1 = 3-V capable (default) 5 IO16R2 R/W Diagnostic bit. This bit defaults to 1. 4 3† RSVD R TEST R/W TI test. Only a 0 should be written to bit 3. R/W Interrupt mode. Bits 2–1 select the interrupt signaling mode. The interrupt mode bits are encoded: 00 = Parallel PCI interrupts only 01 = Parallel IRQ and parallel PCI interrupts 10 = IRQ serialized interrupts and parallel PCI interrupt 11 = IRQ and PCI serialized interrupts (default) 2–1 INTMODE FUNCTION Reserved. Bit 4 returns 0 when read. Write transactions have no effect. 0† RSVD R/W Reserved. This read/write bit is reserved for test purposes. Only 0 should be written to this bit. † These bits are global and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 69 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 diagnostic register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 1 1 R/W R/W R/W R/W 0 0 0 0 1 Name Diagnostic Type Default Register: Type: Offset: Default: Description: Diagnostic Read/write 93h (functions 0, 1) 61h The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s should be written to this register. See Table 29 for a complete description of the register contents. Table 29. Diagnostic Register BIT SIGNAL TYPE FUNCTION 7† TRUE_VAL R/W This bit defaults to 0. This bit is encoded as: 0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Reads all 1s in reads from the PCI vendor ID and PCI device ID registers 6 RSVD R/W Reserved. These bits are R/W with no function. 5 CSC R/W CSC interrupt routing control 0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1 1 = CSC interrupts routed to PCI if ExCA 805 bits 7:4 = 0000b (default). In this case, the setting of ExCA 803 bit 4 is a don’t care. 4† 3† DIAG4 R/W Diagnostic RETRY_DIS. Delayed transaction disable. DIAG3 R/W 2† 1† DIAG2 R/W Diagnostic RETRY_EXT. Extends the latency from 16 to 64. Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. DIAG1 R/W Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215. 0 ASYNC R/W Asynchronous interrupt enable. 0 = CSC interrupt is not generated asynchronously 1 = CSC interrupt is generated asynchronously (default) † These bits are global and should be accessed only through function 0. socket DMA register 0 Bit 31 30 29 28 27 26 25 R R R R R R R R R Name Type 24 23 22 21 20 19 18 17 16 R R R R R R R Socket DMA register 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: 70 Socket DMA register 0 Read-only, read/write (see individual bit descriptions) 94h (functions 0, 1) 0000 0000h The socket DMA register 0 provides control over the PC Card DMA request (DREQ) signaling. See Table 30 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 30. Socket DMA Register 0 BIT SIGNAL TYPE 31–2 RSVD R 1–0 DREQPIN FUNCTION Reserved. Bits 31–2 are read-only and return 0s when read. DMA request (DREQ). Bits 1–0 indicate which terminal on the 16-bit PC Card interface acts as DREQ during DMA transfers. This field is encoded as: 00 = Socket not configured for DMA (default). 01 = DREQ uses SPKR. 10 = DREQ uses IOIS16. 11 = DREQ uses INPACK. R/W socket DMA register 1 Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Socket DMA register 1 R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Socket DMA register 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket DMA register 1 Read-only, read/write (see individual bit descriptions) 98h (functions 0, 1) 0000 0000h The socket DMA register 1 provides control over the distributed DMA (DDMA) registers and the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64 Kbytes of PCI I/O address space. See Table 31 for a complete description of the register contents. NOTE: 32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits. Table 31. Socket DMA Register 1 BIT SIGNAL TYPE 31–16 RSVD R 15–4 DMABASE R/W 3 EXTMODE R FUNCTION Reserved. Bits 31–16 are read-only and return 0s when read. DMA base address. Locates the socket DMA registers in PCI I/O space. This field represents a 16-bit PCI I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K-bytes of I/O address space. The lower four bits are hardwired to 0 and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary. Extended addressing. This feature is not supported by the PCI1225 and and always returns a 0. 2–1 XFERSIZE R/W Transfer size. Bits 2–1 specify the width of the DMA transfer on the PC Card interface and are encoded as: 00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved 0 DDMAEN R/W DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value of DMABASE. 0 = Disabled (default) 1 = Enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 71 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 capability ID register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 1 Name Capability ID Register: Type: Offset: Default: Description: Capability ID Read-only A0h 01h The capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. next-item pointer register Bit 7 6 5 4 Type R R R R Default 0 0 0 0 Name 2 1 0 R R R R 0 0 0 0 Next-item pointer Register: Type: Offset: Default: Description: 72 3 Next-item pointer Read-only A1h 00h The next-item pointer register is used to indicate the next item in the linked list of the PCI power management capabilities. Because the PCI1225 functions include only one capabilities item, this register returns 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 power-management capabilities register Bit 15 14 13 12 11 10 Type R R R R R R R R R Default 0 1 1 1 1 1 1 0 0 Name 9 8 7 6 5 4 3 2 1 0 R R R R R R R 0 1 0 0 0 0 1 Power-management capabilities Register: Type: Offset: Default: Description: Power-management capabilities Read-only (see individual bit descriptions) A2h (functions 0, 1) 7E21h The power-management capabilities register contains information on the capabilities of the PC Card function related to power management. Both PCI1225 CardBus bridge functions support D0, D2, and D3 power states. See Table 32 for a complete description of the register contents. Table 32. Power-Management Capabilities Register BIT SIGNAL TYPE FUNCTION 15–11 PME_CAP R PME support. This 5-bit field indicates the power states from which the PCI1225 supports asserting PME. A 0 for any bit indicates that the CardBus function cannot assert PME from that power state. These five bits return 01111b when read. Each of these bits is described below: Bit 15 contains the value 0, indicating that PME cannot be asserted from D3cold state. Bit 14 contains the value 1, indicating that PME can be asserted from D3hot state. Bit 13 contains the value 1, indicating that PME can be asserted from D2 state. Bit 12 contains the value 1, indicating that PME can be asserted from D1 state. Bit 11 contains the value 1, indicating that PME can be asserted from the D0 state. 10 D2_CAP R D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device power state. 9 D1_CAP R D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device power state. 8 DYN_DATA R Dynamic data support. Bit 8 returns a 0 when read, indicating that the CardBus function does not report dynamic power consumption data. 7–6 RSVD R Reserved. These bits are reserved and return 00b when read. 5 DSI R Device-specific initialization. Bit 5 is read-only and returns 1 when read, indicating that the CardBus controller functions require special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it. 4 AUX_PWR R Auxiliary power source. Bit 4 is meaningful only if bit 15 (D3cold supporting PME) is set. When set, bit 4 indicates that the function supplies its own auxiliary power source. 3 PMECLK R PME clock. Bit 3 is read-only and returns 0 when read, indicating that no host bus clock is required for the PCI1225 to generate PME. 2–0 VERSION R Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power management (PM) registers as described in the PCI Bus Power Management Interface Specification, Revision 1.0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 73 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 power-management control/status register Bit 15 14 13 12 11 10 R/C R R R R R R R/W R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R R R R/W R/W 0 0 0 0 0 0 0 Power-management control/status Register: Type: Offset: Default: Description: Power-management control/status Read-only, read/write, read/clear (see individual bit descriptions) A4h (functions 0, 1) 0000h The power-management control/status register determines and changes the current power state of the PCI1225 CardBus function. The contents of this register are not affected by the internally-generated reset caused by the transition from D3hot to D0 state. See Table 33 for a complete description of the register contents. Table 33. Power-Management Control/Status Register BIT SIGNAL TYPE FUNCTION 15 PMESTAT R/C PME status. Bit 15 is set when the CardBus function would normally assert PME, independent of the state of the PME_EN bit. Bit 15 is cleared by a writeback of 1, and this also clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect. 14–13 DATASCALE R Data scale. This 2-bit field is read-only, returning 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit. 12–9 DATASEL R Data select. This 4-bit field is read-only and returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit. R/W PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, assertion of PME is disabled. 8 7–2 1–0 74 RSVD PWR_STATE R R/W Reserved. Bits 7–2 are read-only and return 0s when read. Power state. This 2-bit field is used both to determine the current power state of a function, and to set the function into a new power state. This field is encoded as: 00 = D0 01 = D1 10 = D2 11 = D3hot POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 power-management control/status register bridge support extensions Bit 7 6 Type R R R R R Default 0 0 0 0 0 Name 5 4 3 2 1 0 R R R 0 0 0 Power-management control/status register bridge support extensions Register: Type: Offset: Default: Description: Power-management control/status register bridge support extensions Read-only A6h (functions 0, 1) 00h The power-management control/status register bridge support extensions support PCI bridge specific functionality. See Table 34 for a complete description of the register contents. Table 34. Power-Management Control/Status Register Bridge Support Extensions BIT SIGNAL TYPE FUNCTION 7 BPCC_EN R Bus power/clock control. When read, bit 7 returns 1b. 6 B2_B3 R B2/B3 support for D3hot. ThIs bit is read-only and returns a 0 when read. 5–0 RSVD R Reserved. These bits are read-only and return 0s when read. power management data register Bit 7 6 5 Name 4 3 2 1 0 Power management data Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Power management data Read-only A7h (functions 0, 1) 00h The power management data register is read-only and returns zeros when read, since the CardBus functions do not report dynamic data. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 75 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 general-purpose event status register Bit 15 14 13 12 11 10 R/C R/C R R R/C R R R/C R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R/C R/C R/C R/C R/C 0 0 0 0 0 0 0 Power-management control/status Register: Type: Offset: Default: Description: General-purpose event status Read-only, read/clear (see individual bit descriptions) A8h (function 0) 0000h The general-purpose event status register contains status bits that are set when events occur that are controlled by the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1 to the corresponding bit location. The status bits in this register do not depend upon the state of a corresponding bit in the general-purpose enable register. Access this register only through function 0. See Table 35 for a complete description of the register contents. Table 35. General-Purpose Event Status Register BIT SIGNAL TYPE FUNCTION 15 ZV0_STS R/C PC card socket 0 ZV Status. Bit 15 is set on a change in status of the ZVENABLE bit in the function 0 PC card controller function of the PCI1225. 14 ZV1_STS R/C PC card socket 1 ZV Status. Bit 14 is set on a change in status of the ZVENABLE bit in the function 1 PC card controller function of the PCI1225. 13–12 RSVD R 11 PWR_STS R/C 10–9 RSVD R 8 VPP12_STS R/C 76 Reserved. These bits are read-only and return zero when read. Power change status. Bit 11 is set when software has changed the power state of either socket. A change in either VCC or VPP for either socket causes this bit to be set. Reserved. These bits are read-only and return zero when read. 12-V VPP request status. Bit 8 is set when software has changed the requested VPP level to or from 12 V for either of the two PC Card sockets. 7–5 RSVD R 4 GP4_STS R/C Reserved. These bits are read-only and return zero when read. GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level. 3 GP3_STS R/C GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level . 2 GP2_STS R/C GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level. 1 GP1_STS R/C GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level. 0 GP0_STS R/C GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 general-purpose event enable register Bit 15 14 13 12 11 10 R/W R/W R R R/W R R R/W R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 General-purpose event enable Register: Type: Offset: Default: Description: General-purpose event enable Read-only, read/write (see individual bit descriptions) AAh (function 0) 0000h The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven until the corresponding status bit is cleared and the event is serviced. The GPE can only be signaled if one of the multifunction terminals, MFUNC6:0, is configured for GPE signaling. Access this register only through function 0. See Table 36 for a complete description of the register contents. Table 36. General-Purpose Event Enable Register BIT SIGNAL TYPE FUNCTION 15 ZV0_EN R/W PC card socket 0 ZV enable. When bit 15 is set, a GPE is signaled on a change in status of ZVENABLE in the function 0 PC Card controller function of the PCI1225. 14 ZV1_EN R/W PC card socket 1 ZV enable. When bit 14 is set, a GPE is signaled on a change in status of ZVENABLE in the function 1 PC Card controller function of the PCI1225. 13–12 RSVD R 11 PWR_EN R/W 10–9 RSVD R 8 VPP12_EN R/W 7–5 RSVD R 4 GP4_EN R/W GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5 terminal input level if configured as GPI4. 3 GP3_EN R/W GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4 terminal input level if configured as GPI3. 2 GP2_EN R/W GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2 terminal input if configured as GPI2. 1 GP1_EN R/W GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1 terminal input if configured as GPI1. 0 GP0_EN R/W GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0 terminal input if configured as GPI0. Reserved. These bits are read-only and return zero when read. Power change enable. When bit 11 is set, a GPE is signaled on when software has changed the power state of either socket. Reserved. These bits are read-only and return zero when read. 12-V VPP request enable. When bit 8 is set, a GPE is signaled when software has changed the requested VPP level to or from 12 V for either card socket. Reserved. These bits are read-only and return zero when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 77 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 general-purpose input register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 X X X X X General-purpose input Register: Type: Offset: Default: Description: General-purpose input Read-only (see individual bit descriptions) ACh (function 0) 00XXh The general-purpose input register provides the logical value of the data input from the GPI terminals, MFUNC5–MFUNC4 and MFUNC2–MFUNC0. Access this register only through function 0. See Table 37 for a complete description of the register contents. Table 37. General-Purpose Input Register 78 BIT SIGNAL TYPE FUNCTION 15–5 RSVD R Reserved. Bits 15–5 are read-only and return 0 when read. Write transactions have no effect. 4 GPI4_DATA R GPI4 data bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal. Write transactions have no effect. 3 GPI3_DATA R GPI3 data bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal. Write transactions have no effect. 2 GPI2_DATA R GPI2 data bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal. Write transactions have no effect. 1 GPI1_DATA R GPI1 data bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal. Write transactions have no effect. 0 GPI0_DATA R GPI0 data bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal. Write transactions have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 general-purpose output register Bit 15 14 13 12 11 10 9 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 General-purpose output Register: Type: Offset: Default: Description: General-purpose output Read-only, read/write (see individual bit descriptions) AEh (function 0) 0000h The general-purpose output register is used for control of the general-purpose outputs. Access this register only through function 0. See Table 38 for a complete description of the register contents. Table 38. General-Purpose Output Register BIT SIGNAL TYPE FUNCTION 15–5 RSVD R Reserved. Bits 15–5 are read-only and return 0 when read. Write transactions have no effect. 4 GPO4_DATA R/W GPO4 data bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5 terminal if configured as GPO4. Read transactions return the last data value written. 3 GPO3_DATA R/W GPIO3 data bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4 terminal if configured as GPO3. Read transactions return the last data value written. 2 GPO2_DATA R/W GPO2 data bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2 terminal if configured as GPO2. Read transactions return the last data value written. 1 GPO1_DATA R/W GPO1 data bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1 terminal if configured as GPO1. Read transactions return the last data value written. 0 GPO0_DATA R/W GPO0 data bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0 terminal if configured as GPO0. Read transactions return the last data value written. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 79 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 serial bus data register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 Serial bus data Register: Type: Offset: Default: Description: Serial bus data Read/write B0h (function 0) 00h The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial bus slave address must be programmed with the 7-bit slave address, and the read/write indicator bit must be reset. On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address must be programmed with the 7-bit slave address, the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of this register are valid read data from the serial bus interface. See Table 39 for a complete description of the register contents. Table 39. Serial Bus Data Register BIT 7–0 SIGNAL SBDATA TYPE FUNCTION R/W Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid. serial bus index register Bit 7 6 5 Name Type Default 4 3 2 1 0 Serial bus index R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Serial bus index Read/write B1h (function 0) 00h The serial bus index register is for programmable serial bus byte reads and writes. This register represents the byte address when generating cycles on the serial bus interface. To write a byte, the serial bus data register must be programmed with the data, this register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator. On byte reads, the word address is programmed into this register, the serial bus slave address must be programmed with the 7-bit slave address, the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 40 for a complete description of the register contents. 80 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 40. Serial Bus Index Register BIT SIGNAL TYPE FUNCTION 7–0 SBINDEX R/W Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface. serial bus slave address register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 Serial bus slave address Register: Type: Offset: Default: Description: Serial bus slave address Read/write B2h (function 0) 00h The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit. On byte reads, the byte address is programmed into the serial bus index register, this register must be programmed with the 7-bit slave address, the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 41 for a complete description of the register contents. Table 41. Serial Bus Slave Address Register BIT 7–1 0 SIGNAL SLAVADDR RWCMD TYPE FUNCTION R/W Serial bus slave address. This bit field represents the slave address of a read or write transaction on the serial interface. R/W Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses. 0 = A byte write access is requested to the serial bus interface. 1 = A byte read access is requested to the serial bus interface. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 81 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 serial bus control and status register Bit 7 6 5 R/W R R R 0 0 0 0 Name Type Default 4 3 2 1 0 R/C R/W R/C R/C 0 0 0 0 Serial bus control and status Register: Type: Offset: Default: Description: Serial bus control and status Read-only, read/write, read/clear (see individual bit descriptions) B3h (function 0) 00h The serial bus control and status register is used to communicate serial bus status information and select the quick command protocol. The REQBUSY bit in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 42 for a complete description of the register contents. Table 42. Serial Bus Control and Status Register BIT SIGNAL TYPE FUNCTION 7 PROT_SEL R/W Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte protocol is used on read commands. The word address byte in the serial bus index register is not output by the PCI1225 when bit 7 is set. 6 RSVD R Reserved. Bit 6 is read-only and returns zero when read. 5 REQBUSY R Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write) is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register. Bit 5 must be polled on reads from the serial interface. After the byte read access has been requested, the read data is valid in the serial bus data register. R Serial EEPROM busy status. Bit 4 indicates the status of the PCI1225 serial EEPROM circuitry. Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus EEPROM. 0 = Serial EEPROM circuitry is not busy 1 = Serial EEPROM circuitry is busy 4 3 SBDETECT R/C Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected. A pulldown resistor must be implemented on the LATCH terminal for bit 3 to be set. If bit 3 is reset, then the MFUNC4 and MFUNC1 terminals can be used for alternate functions such as general-purpose inputs and outputs. 0 = Serial bus interface not detected 1 = Serial bus interface detected 2 SBTEST R/W Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes. 0 = Serial bus clock at normal operating frequency, 100 kHz (default) 1 = Serial bus clock frequency increased for test purposes R/C Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1. 0 = No error detected during user requested byte read or write cycle 1 = Data error detected during user requested byte read or write cycle R/C EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on invalid EEPROM data formats. See serial bus interface implementation on page 31 for details on EEPROM data format. Bit 0 is cleared by a writeback of 1. 0 = No error detected during auto-load from serial bus EEPROM 1 = Data error detected during auto-load from serial bus EEPROM 1 0 82 ROMBUSY REQ_ERR ROM_ERR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA compatibility registers (functions 0 and 1) The ExCA registers implemented in the PCI1225 are register-compatible with the Intel 82365SL–DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy mode base address register, which is shared by both card sockets. The offsets from this base address run contiguous from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. See Figure 21 for an ExCA I/O mapping illustration. Offset Host I/O Space PCI1225 Configuration Registers 00h Card Bus Socket / ExCA Base Address 10h Index PC Card A ExCA Registers Data 16–bit Legacy Mode Base Address 3Fh 40h 44h PC Card B ExCA Registers Note: The 16–bit legacy mode base address register is shared by function 0 and 1 as indicated by the shading. 7Fh Offset of desired register is placed in the index register and the data from that location is returned in the data register. Figure 21. ExCA Register Access Through I/O POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 83 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA compatibility registers (functions 0 and 1) (continued) The TI PCI1225 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus socket registers/ExCA registers base address register (PCI offset 10h) at memory offset 800h. Each socket has a separate base address programmable by function. See Figure 22 for an ExCA memory mapping illustration. Note that memory offsets are 800h–844h for both functions 0 and 1. This illustration also identifies the CardBus socket register mapping, which are mapped into the same 4-Kbyte window at memory offset 0h. Host Memory Space PCI1225 Configuration Registers Host Memory Space Offset 00h . . . CardBus Socket/ExCA Base Address 10h CardBus Socket A Registers 16-bit Legacy-Mode Base Address Offset 00h 20h . . 44h . . . ExCA Registers Card A 800h CardBus Socket B Registers 20h 844h 800h ExCA Registers Card B Note: The CardBus socket/ExCA base address mode register is separate for functions 0 and 1. 844h Figure 22. ExCA Register Access Through Memory The interrupt registers in the ExCA register set, as defined by the 82365SL–DL Specification, control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1225 to ensure that all possible PCI1225 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h. Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity. Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. (Table 43 identifies each ExCA register and its respective ExCA offset.) Memory windows have 4-Kbyte granularity. 84 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 43. ExCA Registers and Offsets ExCA OFFSET (HEX) PCI MEMORY ADDRESS OFFSET (HEX) CARD A CARD B Identification and revision 800 00 40 Interface status 801 01 41 Power control 802 02 42 Interrupt and general control 803 03 43 Card status change 804 04 44 Card status-change-interrupt configuration 805 05 45 Address window enable 806 06 46 I / O window control 807 07 47 I / O window 0 start-address low byte 808 08 48 EXCA REGISTER NAME I / O window 0 start-address high byte 809 09 49 I / O window 0 end-address low byte 80A 0A 4A I / O window 0 end-address high byte 80B 0B 4B I / O window 1 start-address low byte 80C 0C 4C I / O window 1 start-address high byte 80D 0D 4D I / O window 1 end-address low byte 80E 0E 4E I / O window 1 end-address high byte 80F 0F 4F Memory window 0 start-address low byte 810 10 50 Memory window 0 start-address high byte 811 11 51 Memory window 0 end-address low byte 812 12 52 Memory window 0 end-address high byte 813 13 53 Memory window 0 offset-address low byte 814 14 54 Memory window 0 offset-address high byte 815 15 55 Card detect and general control 816 16 56 Reserved 817 17 57 Memory window 1 start-address low byte 818 18 58 Memory window 1 start-address high byte 819 19 59 Memory window 1 end-address low byte 81A 1A 5A Memory window 1 end-address high byte 81B 1B 5B Memory window 1 offset-address low byte 81C 1C 5C Memory window 1 offset-address high byte 81D 1D 5D Global control 81E 1E 5E Reserved 81F 1F 5F POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 85 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 43. ExCA Registers and Offsets (Continued) 86 ExCA OFFSET (HEX) PCI MEMORY ADDRESS OFFSET (HEX) CARD A CARD B Memory window 2 start-address low byte 820 20 60 Memory window 2 start-address high byte 821 21 61 Memory window 2 end-address low byte 822 22 62 Memory window 2 end-address high byte 823 23 63 Memory window 2 offset-address low byte 824 24 64 Memory window 2 offset-address high byte 825 25 65 Reserved 826 26 66 Reserved 827 27 67 Memory window 3 start-address low byte 828 28 68 EXCA REGISTER NAME Memory window 3 start-address high byte 829 29 69 Memory window 3 end-address low byte 82A 2A 6A Memory window 3 end-address high byte 82B 2B 6B Memory window 3 offset-address low byte 82C 2C 6C Memory window 3 offset-address high byte 82D 2D 6D Reserved 82E 2E 6E Reserved 82F 2F 6F Memory window 4 start-address low byte 830 30 70 Memory window 4 start-address high byte 831 31 71 Memory window 4 end-address low byte 832 32 72 Memory window 4 end-address high byte 833 33 73 Memory window 4 offset-address low byte 834 34 74 Memory window 4 offset-address high byte 835 35 75 I/O window 0 offset-address low byte 836 36 76 I/O window 0 offset-address high byte 837 37 77 I/O window 1 offset-address low byte 838 38 78 I/O window 1 offset-address high byte 839 39 79 Reserved 83A 3A 7A Reserved 83B 3B 7B Reserved 83C 3C 7C Reserved 83D 3D 7D Reserved 83E 3E 7E Reserved 83F 3F 7F Memory window page 0 840 – – Memory window page 1 841 – – Memory window page 2 842 – – Memory window page 3 843 – – Memory window page 4 844 – – POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA identification and revision register Bit 7 6 5 Type R R R/W R/W Default 1 0 0 0 Name 4 3 2 1 0 R/W R/W R/W R/W 0 1 0 0 ExCA identification and revision Register: Type: Offset: ExCA identification and revision Read-only, read/write (see individual bit descriptions) CardBus socket address + 800h; Card A ExCA offset 00h Card B ExCA offset 40h Default: 84h Description: This register provides host software with information on 16-bit PC Card support and Intel 82365SL-DF compatibility. See Table 44 for a complete description of the register contents. Table 44. ExCA Identification and Revision Register BIT SIGNAL TYPE FUNCTION 7–6 IFTYPE R Interface type. These read-only bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the PCI1225. The PCI1225 supports both I/O and memory 16-bit PC cards. 5–4 RSVD R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation. 3–0 365REV R/W Intel 82365SL-DF revision. This read/write field stores the Intel 82365SL-DF revision supported by the PCI1225. Host software can read this field to determine compatibility to the Intel 82365SL-DF register set. This field defaults to 0100b upon PCI1225 reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 87 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA interface status register Bit 7 6 5 Type R R R R Default 0 0 X X Name 4 3 2 1 0 R R R R X X X X ExCA interface status Register: Type: Offset: ExCA interface status Read-only (see individual bit descriptions) CardBus socket address + 801h; Card A ExCA offset 01h Card B ExCA offset 41h Default: 00XX XXXXb Description: This register provides information on the current status of the PC Card interface. An X in the default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 45 for a complete description of the register contents. Table 45. ExCA Interface Status Register BIT SIGNAL TYPE FUNCTION 7 RSVD R Reserved. Bit 7 is read-only and returns 0 when read. Write transactions have no effect. 6 CARDPWR R Card power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the power control register is programmed. Bit 6 is encoded as: 0 = VCC and VPP to the socket turned off (default) 1 = VCC and VPP to the socket turned on 5 READY R Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface. 0 = PC Card not ready for data transfer 1 = PC Card ready for data transfer R Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to the PCI1225 whether or not the memory card is write protected. Furthermore, write protection for an entire PCI1225 16-bit memory window is available by setting the appropriate bit in the memory window offset high-byte register. 0 = WP is 0. PC Card is R/W. 1 = WP is 1. PC Card is read-only. R Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket. 0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted. R Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket. 0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted. 4 3 2 1–0 CARDWP CDETECT2 CDETECT1 BVDSTAT R Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0 reflects BVD1. 00 = Battery dead 01 = Battery dead 10 = Battery low; warning 11 = Battery good When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs. 88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA power-control register Bit 7 6 5 4 R/W R R R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R R/W R/W 0 0 0 0 ExCA power control Register: Type: Offset: ExCA power control Read-only, read/write (see individual bit descriptions) CardBus socket address + 802h; Card A ExCA offset 02h Card B ExCA offset 42h Default: 00h Description: This register provides PC Card power control. Bit 7 of this register controls the 16-bit outputs on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 46 for a complete description of the register contents. Table 46. ExCA Power-Control Register BIT SIGNAL TYPE FUNCTION 7 COE R/W Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1225. This bit is encoded as: 0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled 6–5 RSVD R 4–3 EXCAVCC R/W 2 RSVD R 1–0 EXCAVPP R/W Reserved. Bits 6–5 are read-only and return 0s when read. Write transactions have no effect. VCC. Bits 4–3 are used to request changes to card VCC. This field is encoded as: 00 = 0 V (default) 01 = 0 V reserved 10 = 5 V 11 = 3 .3V Reserved. Bit 2 is read-only and returns 0 when read. Write transactions have no effect. VPP. Bits 1–0 are used to request changes to card VPP. The PCI1225 ignores this field unless VCC to the socket is enabled (i.e., 5 V or 3.3 V). This field is encoded as: 00 = 0 V (default) 01 = VCC 10 = 12 V 11 = 0 V reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 89 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA interrupt and general-control register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA interrupt and general control Register: Type: Offset: ExCA interrupt and general control Read/write (see individual bit descriptions) CardBus socket address + 803h; Card A ExCA offset 03h Card B ExCA offset 43h Default: 00h Description: This register controls interrupt routing for I/O interrupts, as well as other critical 16-bit PC Card functions. See Table 47 for a complete description of the register contents. Table 47. ExCA Interrupt and General-Control Register BIT SIGNAL TYPE 7 RINGEN R/W Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as: 0 = Ring indicate disabled (default) 1 = Ring indicate enabled 6 RESET R/W Card reset. Bit 6 controls the 16-bit PC Card PRST, and allows host software to force a card reset. Bit 6 affects 16-bit cards only. This bit is encoded as 0 = RESET signal asserted (default) 1 = RESET signal deasserted 5 CARDTYPE R/W Card type. Bit 5 indicates the PC card type. This bit is encoded as: 0 = Memory PC Card installed (default) 1 = I/O PC Card installed R/W PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7–4 in the ExCA card status change interrupt configuration register. This bit is encoded as: 0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts. R/W Card interrupt select for I/O PC Card functional interrupts. Bits 3–0 select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as: 0000 = No interrupt routing (default) . CSC interrupts routed to PCI interrupts. This bit setting is ORed with ExCA bit 4 for backwards compatibility. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0100 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 4 3–0 90 FUNCTION CSCROUTE INTSELECT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA card status-change register Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 4 3 2 1 0 R R R R 0 0 0 0 ExCA card status change Register: Type: Offset: ExCA card status change Read-only (see individual bit descriptions) CardBus socket address + 804h; Card A ExCA offset 04h Card B ExCA offset 44h Default: 00h Description: The card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit writeback of 1 to the status bit. The choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the global control register. See Table 48 for a complete description of the register contents. Table 48. ExCA Card Status-Change Register BIT SIGNAL TYPE 7–4 RSVD R Reserved. Bits 7–4 are read-only and return 0s when read. Write transactions have no effect. R Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface. This bit is encoded as: 0 = No change detected on either CD1 or CD2 1 = Change detected on either CD1 or CD2 3 2 CDCHANGE READYCHANGE R FUNCTION Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCI1225 interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now ready to accept new data. This bit is encoded as: 0 = No low-to-high transition detected on READY (default) 1 = Detected low-to-high transition on READY When a 16-bit I/O card is installed, bit 2 is always 0. 1 BATWARN R Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the source of a PCI1225 interrupt was due to a battery-low warning condition. This bit is encoded as: 0 = No battery warning condition (default) 1 = Detected battery warning condition When a 16-bit I/O card is installed, bit 1 is always 0. 0 BATDEAD R Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates whether the source of a PCI1225 interrupt was due to a battery dead condition. This bit is encoded as: 0 = STSCHG deasserted (default) 1 = STSCHG asserted Ring indicate. When the PCI1225 is configured for ring indicate operation, bit 0 indicates the status of RI. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 91 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA card status-change-interrupt configuration register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA status-change-interrupt configuration Register: Type: Offset: ExCA card status-change-interrupt configuration Read/write (see individual bit descriptions) CardBus socket address + 805h; Card A ExCA offset 05h Card B ExCA offset 45h Default: 00h Description: This register controls interrupt routing for card status-change interrupts, as well as masking CSC interrupt sources. See Table 49 for a complete description of the register contents. Table 49. ExCA Card Status-Change-Interrupt Configuration Register BIT TYPE FUNCTION 7–4 CSCSELECT R/W Interrupt select for card status change. Bits 7–4 select the interrupt routing for card status change interrupts. 0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) is set to 1b. In this case bit 4 of ExCA 803 is a don’t care. This is the default setting. 0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI offset 93h) is set to 0b. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803 to 1b. This field is encoded as: 0000 = No interrupt routing (default) 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 3 CDEN R/W Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as: 0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes 2 READYEN R/W Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation R/W Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation R/W Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt. 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation 1 0 92 SIGNAL BATWARNEN BATDEADEN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA address window enable register Bit 7 6 5 R/W R/W R R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA address window enable Register: Type: Offset: ExCA address window enable Read-only, read/write (see individual bit descriptions) CardBus socket address + 806h; Card A ExCA offset 06h Card B ExCA offset 46h Default: 00h Description: This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI1225 does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 50 for a complete description of the register contents. Table 50. ExCA Address Window Enable Register BIT SIGNAL TYPE 7 IOWIN1EN R/W I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as: 0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled 6 IOWIN0EN R/W I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as: 0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled 5 RSVD R 4 MEMWIN4EN FUNCTION Reserved. Bit 5 is read-only and returns 0 when read. Write transactions have no effect. R/W Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is encoded as: 0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled 3 MEMWIN3EN R/W Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is encoded as: 0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled 2 MEMWIN2EN R/W Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is encoded as: 0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled R/W Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is encoded as: 0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled R/W Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is encoded as: 0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled 1 0 MEMWIN1EN MEMWIN0EN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 93 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA I/O window control register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA I/O window control ExCA I/O window control Read/write (see individual bit descriptions) CardBus socket address + 807h; Card A ExCA offset 07h Card B ExCA offset 47h Default: 00h Description: This register contains parameters related to I/O window sizing and cycle timing. See Table 51 for a complete description of the register contents. Register: Type: Offset: Table 51. ExCA I/O Window Control Register BIT 7 6 5 4 3 2 1 0 94 SIGNAL WAITSTATE1 ZEROWS1 IOSIS16W1 DATASIZE1 WAITSTATE0 ZEROWS0 IOSIS16W0 DATASIZE0 TYPE FUNCTION R/W I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. R/W I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. R/W I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16. R/W I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if the I/O window 1 IOIS16 source bit (bit 5) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. R/W I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. R/W I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. R/W I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16. R/W I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if the I/O window 0 IOIS16 source bit (bit 1) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA I/O window 0 and 1 start-address low-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 start-address low byte Register: Offset: ExCA I/O window 0 start-address low byte CardBus socket address + 808h; Card A ExCA offset 08h Card B ExCA offset 48h Register: ExCA I/O window 1 start-address low byte Offset: CardBus socket address + 80Ch; Card A ExCA offset 0Ch Card B ExCA offset 4Ch Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the start address. ExCA I/O window 0 and 1 start-address high-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 start-address high byte Register: Offset: ExCA I/O window 0 start-address high byte CardBus socket address + 809h; Card A ExCA offset 09h Card B ExCA offset 49h Register: ExCA I/O window 1 start-address high byte Offset: CardBus socket address + 80Dh; Card A ExCA offset 0Dh Card B ExCA offset 4Dh Type: Read/write Default: 00h Description: These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 95 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA I/O window 0 and 1 end-address low-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 end-address low byte ExCA I/O window 0 end-address low byte CardBus socket address + 80Ah; Card A ExCA offset 0Ah Card B ExCA offset 4Ah Register: ExCA I/O window 1 end-address low byte Offset: CardBus socket address + 80Eh; Card A ExCA offset 0Eh Card B ExCA offset 4Eh Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the end address. Register: Offset: ExCA I/O window 0 and 1 end-address high-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 end-address high byte ExCA I/O window 0 end-address high byte CardBus socket address + 80Bh; Card A ExCA offset 0Bh Card B ExCA offset 4Bh Register: ExCA I/O window 1 end-address high byte Offset: CardBus socket address + 80Fh; Card A ExCA offset 0Fh Card B ExCA offset 4Fh Type: Read/write Default: 00h Description: These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address. Register: Offset: 96 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA memory window 0–4 start-address low-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 start-address low byte Register: Offset: Register: Offset: Register: Offset: ExCA memory window 0 start-address low byte CardBus socket address + 810h; Card A ExCA offset 10h Card B ExCA offset 50h ExCA memory window 1 start-address low byte CardBus socket address + 818h; Card A ExCA offset 18h Card B ExCA offset 58h ExCA memory window 2 start-address low byte CardBus socket address + 820h; Card A ExCA offset 20h Card B ExCA offset 60h Register: Offset: ExCA memory window 3 start-address low byte CardBus socket address + 828h; Card A ExCA offset 28h Card B ExCA offset 68h Register: ExCA memory window 4 start-address low byte Offset: CardBus socket address + 830h; Card A ExCA offset 30h Card B ExCA offset 70h Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 97 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA memory window 0–4 start-address high-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 start-address high byte Register: Offset: ExCA memory window 0 start-address high byte CardBus socket address + 811h; Card A ExCA offset 11h Card B ExCA offset 51h Register: ExCA memory window 1 start-address high byte Offset: CardBus socket address + 819h; Card A ExCA offset 19h Card B ExCA offset 59h Register: ExCA memory window 2 start-address high byte Offset: CardBus socket address + 821h; Card A ExCA offset 21h Card B ExCA offset 61h Register: ExCA memory window 3 start-address high byte Offset: CardBus socket address + 829h; Card A ExCA offset 29h Card B ExCA offset 69h Register: ExCA memory window 4 start-address high byte Offset: CardBus socket address + 831h; Card A ExCA offset 31h Card B ExCA offset 71h Type: Read/write Default: 00h Description: These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory window data width and wait states are set in this register. See Table 52 for a complete description of the register contents. Table 52. ExCA Memory Window 0–4 Start-Address High-Byte Register 98 BIT SIGNAL TYPE FUNCTION 7 DATASIZE R/W Data size. Bit 7 controls the memory window data width. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. 6 ZEROWAIT R/W Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 16-bit cycles are reduced to equivalent of two ISA cycles. 5–4 SCRATCH R/W Scratch pad bits. Bits 5–4 are read/write and have no effect on memory window operation. 3–0 STAHN R/W Start-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window start address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA memory window 0–4 end-address low-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 end-address low byte Register: Offset: ExCA memory window 0 end-address low byte CardBus socket address + 812h; Card A ExCA offset 12h Card B ExCA offset 52h Register: ExCA memory window 1 end-address low byte Offset: CardBus socket address + 81Ah; Card A ExCA offset 1Ah Card B ExCA offset 5Ah Register: ExCA memory window 2 end-address low byte Offset: CardBus socket address + 822h; Card A ExCA offset 22h Card B ExCA offset 62h Register: ExCA memory window 3 end-address low byte Offset: CardBus socket address + 82Ah; Card A ExCA offset 2Ah Card B ExCA offset 6Ah Register: ExCA memory window 4 end-address low byte Offset: CardBus socket address + 832h; Card A ExCA offset 32h Card B ExCA offset 72h Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 99 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA memory window 0–4 end-address high-byte register Bit 7 6 5 R/W R/W R R R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 end-address high byte Register: Offset: ExCA memory window 0 end-address high byte CardBus socket address + 813h; Card A ExCA offset 13h Card B ExCA offset 53h Register: ExCA memory window 1 end-address high byte Offset: CardBus socket address + 81Bh; Card A ExCA offset 1Bh Card B ExCA offset 5Bh Register: ExCA memory window 2 end-address high byte Offset: CardBus socket address + 823h; Card A ExCA offset 23h Card B ExCA offset 63h Register: ExCA memory window 3 end-address high byte Offset: CardBus socket address + 82Bh; Card A ExCA offset 2Bh Card B ExCA offset 6Bh Register: ExCA memory window 4 end-address high byte Offset: CardBus socket address + 833h; Card A ExCA offset 33h Card B ExCA offset 73h Type: Read-only, read/write (see individual bit descriptions) Default: 00h Description: These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory window wait states are set in this register. See Table 53 for a complete description of the register contents. Table 53. ExCA Memory Window 0–4 End-Address High-Byte Register BIT SIGNAL TYPE FUNCTION Wait state. Bits 7–6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits. 7–6 MEMWS R/W 5–4 RSVD R 3–0 ENDHN R/W 100 Reserved. Bits 5–4 are read-only and return 0s when read. Write transactions have no effect. End-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA memory window 0–4 offset-address low-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 offset-address low byte Register: Offset: ExCA memory window 0 offset-address low byte CardBus socket address + 814h; Card A ExCA offset 14h Card B ExCA offset 54h Register: ExCA memory window 1 offset-address low byte Offset: CardBus socket address + 81Ch; Card A ExCA offset 1Ch Card B ExCA offset 5Ch Register: ExCA memory window 2 offset-address low byte Offset: CardBus socket address + 824h; Card A ExCA offset 24h Card B ExCA offset 64h Register: ExCA memory window 3 offset-address low byte Offset: CardBus socket address + 82Ch; Card A ExCA offset 2Ch Card B ExCA offset 6Ch Register: ExCA memory window 4 offset-address low byte Offset: CardBus socket address + 834h; Card A ExCA offset 34h Card B ExCA offset 74h Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3 and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 101 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA memory window 0–4 offset-address high-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 offset-address high byte Default Register: Offset: ExCA memory window 0 offset-address high byte CardBus socket address + 815h; Card A ExCA offset 15h Card B ExCA offset 55h Register: ExCA memory window 1 offset-address high byte Offset: CardBus socket address + 81Dh; Card A ExCA offset 1Dh Card B ExCA offset 5Dh Register: ExCA memory window 2 offset-address high byte Offset: CardBus socket address + 825h; Card A ExCA offset 25h Card B ExCA offset 65h Register: ExCA memory window 3 offset-address high byte Offset: CardBus socket address + 82Dh; Card A ExCA offset 2Dh Card B ExCA offset 6Dh Register: ExCA memory window 4 offset-address high byte Offset: CardBus socket address + 835h; Card A ExCA offset 35h Card B ExCA offset 75h Type: Read/write (see individual bit descriptions) Default: 00h Description: These registers contain the high six bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3 and 4. The lower six bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. See Table 54 for a complete description of the register contents. Table 54. ExCA Memory Window 0–4 Offset-Address High-Byte Register BIT SIGNAL TYPE FUNCTION 7 WINWP R/W Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is encoded as: 0 = Write operations are allowed (default). 1 = Write operations are not allowed. 6 REG R/W Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as: 0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory. 5–0 OFFHB R/W Offset-address high byte. Bits 5–0 represent the upper address bits A25–A20 of the memory window offset address. 102 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA I/O window 0 and 1 offset-address low-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R 0 0 0 ExCA I/O window 0 and 1 offset-address low byte Register: Offset: ExCA I/O window 0 offset-address low byte CardBus socket address + 836h; Card A ExCA offset 36h Card B ExCA offset 76h Register: ExCA I/O window 1 offset-address low byte Offset: CardBus socket address + 838h; Card A ExCA offset 38h Card B ExCA offset 78h Type: Read-only, read/write Default: 00h Description: These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the offset address, and bit 0 is always 0. ExCA I/O window 0 and 1 offset-address high-byte register Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 offset-address high byte Register: Offset: ExCA I/O window 0 offset-address high byte CardBus socket address + 837h; Card A ExCA offset 37h Card B ExCA offset 77h Register: ExCA I/O window 1 offset-address high byte Offset: CardBus socket address + 839h; Card A ExCA offset 39h Card B ExCA offset 79h Type: Read/write Default: 00h Description: These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the offset address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 103 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA card detect and general-control register Bit 7 6 5 Type R R R/W R/W Default X X 0 0 Name 4 3 2 1 0 R R R/W R 0 0 0 0 ExCA I/O card detect and general control Register: Type: Offset: ExCA card detect and general control Read-only, read/write (see individual bit descriptions) CardBus socket address + 816h; Card A ExCA offset 16h Card B ExCA offset 56h Default: XX00 0000b Description: This register controls how the ExCA registers for the socket respond to card removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 55 for a complete description of the register contents. Table 55. ExCA Card Detect and General-Control Register BIT SIGNAL TYPE FUNCTION 7 VS2STAT R VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have a default value. 0 = VS2 low 1 = VS2 high 6 VS1STAT R VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have a default value. 0 = VS1 low 1 = VS1 high R/W Software card detect interrupt. If the card detect enable bit in the card status change interrupt configuration register is set, writing a 1 to bit 5 causes a card-detect card-status change interrupt for the associated card socket. If the card detect enable bit is cleared to 0 in the card status change interrupt configuration register, writing a 1 to the software card detect interrupt bit has no effect A read operation of this bit always returns 0. Card detect resume enable. If bit 4 is set to 1, then once a card detect change has been detected on CD1 and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until the card status change bit in the card status change register is cleared. If this bit is a 0, then the card detect resume functionality is disabled. 0 = Card detect resume disabled (default) 1 = Card detect resume enabled 5 SWCSC 4 CDRESUME R/W 3–2 RSVD R 104 1 REGCONFIG R/W 0 RSVD R Reserved. Bits 3–2 are read-only and return 0s when read. Write transactions have no effect. Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card removal event. This bit is encoded as: 0 = No change to ExCA registers on card removal (default) 1 = Reset ExCA registers on card removal Reserved. Bit 0 is read-only and returns 0 when read. Write transactions have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA global-control register Bit 7 6 5 4 Type R R R R/W Default 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA global control Register: Type: Offset: ExCA global control Read-only, read/write (see individual bit descriptions) CardBus socket address + 81Eh; Card A ExCA offset 1Eh Card B ExCA offset 5Eh Default: 00h Description: This register controls both PC Card sockets and is not duplicated for each socket. The host interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See Table 56 for a complete description of the register contents. Table 56. ExCA Global-Control Register BIT SIGNAL TYPE 7–5 RSVD R 4 INTMODEB FUNCTION Reserved. Bits 7–5 are is read-only and return 0s when read. Write transactions have no effect. R/W Level/edge interrupt mode select – card B. Bit 4 selects the signaling mode for the PCI1225 host interrupt for card B interrupts. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. 3 INTMODEA R/W Level/edge interrupt mode select – card A. Bit 3 selects the signaling mode for the PCI1225 host interrupt for card A interrupts. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. 2 IFCMODE R/W Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA card status change register. This bit is encoded as: 0 = Interrupt flags are cleared by read of CSC register (default). 1 = Interrupt flags are cleared by explicit writeback of 1. 1 CSCMODE R/W Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1225 host interrupt for card status changes. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. R/W Power-down mode select. When bit 0 is set to 1, the PCI1225 is in power-down mode. In power-down mode, the PCI1225 card outputs are placed in a high-impedance state until an active cycle is executed on the card interface. Following an active cycle, the outputs are again placed in a high-impedance state. The PCI1225 still receives DMA requests, functional interrupts, and/or card status change interrupts; however, an actual card access is required to wake up the interface. This bit is encoded as: 0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled. 0 PWRDWN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 105 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 ExCA memory window 0–4 page register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA memory window 0–4 page Type Default Register: Type: Offset: Default: Description: ExCA memory window 0–4 page Read/write CardBus socket address + 840h 841h, 842h, 843h, 844h 00h The upper eight bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256 16-Mbyte regions in the 4-Gbyte PCI address space. These registers are only accessible when the ExCA registers are memory mapped, i.e., these registers can not be accessed using the index/data I/O scheme. CardBus socket registers (functions 0 and 1) The PCMCIA CardBus specification requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI1225 provides the CardBus socket/ExCA base address register (PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each socket has a separate base address register for accessing the CardBus socket registers (see Figure 23). Table 57 gives the location of the socket registers in relation to the CardBus socket/ExCA base address. The PCI1225 implements an additional register at offset 20h that provides power management control for the socket. Host Memory Space PCI1225 Configuration Registers Offset 00h . . . CardBus Socket/ExCA Base Address Host Memory Space 10h CardBus Socket A Registers 16-bit Legacy-Mode Base Address Offset 00h 20h . . 44h . . . ExCA Registers Card A 800h CardBus Socket B Registers 20h 844h 800h ExCA Registers Card B Note: The CardBus socket/ExCA base address mode register is separate for functions 0 and 1. 844h Figure 23. Accessing CardBus Socket Registers Through PCI Memory 106 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 57. CardBus Socket Registers REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket power management 20h socket event register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Socket event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket event Type R R R R R R R R R R R R R/C R/C R/C R/C Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket event Read-only, read/clear (see individual bit descriptions) CardBus socket address + 00h 0000 0000h The socket event register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software must clear this register before enabling interrupts. If it is not cleared, when interrupts are enabled an interrupt is generated (but not masked) based on any bit set. See Table 58 for a complete description of the register contents. Table 58. Socket Event Register BIT SIGNAL TYPE FUNCTION 31–4 RSVD R 3 PWREVENT R/C Power cycle. Bit 3 is set when the PCI1225 detects that the PWRCYCLE bit in the socket present-state register has changed. This bit is cleared by writing a 1. 2 CD2EVENT R/C CCD2. Bit 2 is set when the PCI1225 detects that the CDETECT2 field in the socket present-state register has changed. This bit is cleared by writing a 1. 1 CD1EVENT R/C CCD1. Bit 3 is set when the PCI1225 detects that the CDETECT1 field in the socket present-state register has changed. This bit is cleared by writing a 1. 0 CSTSEVENT R/C CSTSCHG. Bit 0 is set when the CARDSTS field in the socket present-state register has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For 16-bit PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1. Reserved. Bits 31–4 are read-only and return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 107 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 socket mask register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket mask Name Socket mask Type R R R R R R R R R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket mask Read-only, read/write (see individual bit descriptions) CardBus socket address + 04h 0000 0000h The socket mask register allows software to control the CardBus card events that generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register. See Table 59 for a complete description of the register contents. Table 59. Socket Mask Register BIT SIGNAL TYPE 31–4 RSVD R 3 PWRMASK R/W Power cycle. Bit 3 masks the PWRCYCLE bit in the socket present state register from causing a status change interrupt. 0 = PWRCYCLE event does not cause CSC interrupt (default). 1 = PWRCYCLE event causes CSC interrupt. R/W Card detect mask. Bits 2–1 mask the CDETECT1 and CDETECT2 bits in the socket present-state register from causing a CSC interrupt. 00 = Insertion/removal does not cause CSC interrupt (default). 01 = Reserved (undefined) 10 = Reserved (undefined) 11 = Insertion/removal causes CSC interrupt. R/W CSTSCHG mask. Bit 0 masks the CARDSTS field in the socket present-state register from causing a CSC interrupt. 0 = CARDSTS event does not cause CSC interrupt (default). 1 = CARDSTS event causes CSC interrupt. 2–1 0 108 CDMASK CSTSMASK FUNCTION Reserved. Bits 31–4 are read-only and return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 socket present-state register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 1 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket present-state Name Socket present-state Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X Register: Type: Offset: Default: Description: Socket present-state Read-only CardBus socket address + 08h 3000 00XXh The socket present-state register reports information about the socket interface. Write transactions to the socket force event register are reflected here, as well as general socket interface status. Information about PC Card VCC support and card type is only updated at each insertion. Also note that the PCI1225 uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected in this register. See Table 60 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 109 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 60. Socket Present-State Register BIT SIGNAL TYPE FUNCTION 31 YVSOCKET R YV socket. Bit 31 indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The PCI1225 does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event register. This bit is hardwired to 0. 30 XVSOCKET R XV socket. Bit 30 indicates whether or not the socket can supply VCC = X.X V to PC Cards. The PCI1225 does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force event register. This bit is hardwired to 0. 29 3VSOCKET R 3-V socket. Bit 29 indicates whether or not the socket can supply VCC = 3.3 V to PC Cards. The PCI1225 does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force event register. 28 5VSOCKET R 5-V socket. Bit 28 indicates whether or not the socket can supply VCC = 5 V to PC Cards. The PCI1225 does support 5-V VCC; therefore, this bit is always set unless overridden by the socket force event register. 27–14 RSVD R Reserved. Bits 27–14 are read-only and return 0s when read. 13 YVCARD R YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V. 12 XVCARD R XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V. 11 3VCARD R 3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V. 10 5VCARD R 5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V. R Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software R Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI1225. 0 = Normal operation (default) 1 = Potential data loss due to card removal R Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not updated until a valid PC Card is inserted into the socket. 0 = Normal operation (default) 1 = Unrecognizable PC Card detected 9 8 7 DATALOST NOTACARD 6 IREQCINT R READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface. 0 = READY(IREQ)//CINT low 1 = READY(IREQ)//CINT high 5 CBCARD R CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 4 16BITCARD R 16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 3 PWRCYCLE R Power cycle. Bit 3 indicates that the status of each card powering request. This bit is encoded as: 0 = Socket powered down (default) 1 = Socket powered up R CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD2 low (PC Card may be present) 1 = CCD2 high (PC Card not present) 2 110 BADVCCREQ CDETECT2 1 CDETECT1 R CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD1 low (PC Card may be present) 1 = CCD1 high (PC Card not present) 0 CARDSTS R CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface. 0 = CSTSCHG low 1 = CSTSCHG high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 socket force event register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket force event Name Socket force event Type R W W W W W W W W R W W W W W W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket force event Read-only, write-only (see individual bit descriptions) CardBus socket address + 0Ch 0000 0000h The socket force event register is used to force changes to the socket event register and the socket present state register. The CVSTEST bit in this register must be written when forcing changes that require card interrogation. See Table 61 for a complete description of the register contents. Table 61. Socket Force Event Register BIT SIGNAL TYPE FUNCTION 31–15 RSVD R Reserved. Bits 31–15 are read-only and return 0s when read. 14 CVSTEST W Card VS test. When bit 14 is set, the PCI1225 re-interrogates the PC Card, updates the socket present state register, and enables the socket power control. 13 FYVCARD W Force YV card. Write transactions to bit 13 cause the YVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 12 FXVCARD W Force XV card. Write transactions to bit 12 cause the XVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 11 F3VCARD W Force 3-V card. Write transactions to bit 11 cause the 3VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 10 F5VCARD W Force 5-V card. Write transactions to bit 10 cause the 5VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 9 FBADVCCREQ W Force bad VCC request. Changes to the BADVCCREQ bit in the socket present state register can be made by writing to bit 9. 8 FDATALOST W Force data lost. Write transactions to bit 8 cause the DATALOST bit in the socket present state register to be written. 7 FNOTACARD W Force not a card. Write transactions to bit 7 cause the NOTACARD bit in the socket present state register to be written. 6 RSVD R Reserved. Bit 6 is read-only and returns 0 when read. 5 FCBCARD W Force CardBus card. Write transactions to bit 5 cause the CBCARD bit in the socket present state register to be written. 4 F16BITCARD W Force 16-bit card. Write transactions to bit 4 cause the 16BITCARD bit in the socket present state register to be written. 3 FPWRCYCLE W Force power cycle. Write transactions to bit 3 cause the PWREVENT bit in the socket event register to be written, and the PWRCYCLE bit in the socket present state register is unaffected. 2 FCDETECT2 W Force CCD2. Write transactions to bit 2 cause the CD2EVENT bit in the socket event register to be written, and the CDETECT2 bit in the socket present state register is unaffected. 1 FCDETECT1 W Force CCD1. Write transactions to bit 1 cause the CD1EVENT bit in the socket event register to be written, and the CDETECT1 bit in the socket present state register is unaffected. 0 FCARDSTS W Force CSTSCHG. Write transactions to bit 0 cause the CSTSEVENT bit in the socket event register to be written, and the CARDSTS bit in the socket present state register is unaffected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 111 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 socket control register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket control Name Socket control Type R R R R R R R R R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket control Read-only, read/write (see individual bit descriptions) CardBus socket address + 10h 0000 0000h The socket control register provides control of the voltages applied to the socket and instructions for CB CLKRUN protocol. The PCI1225 ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 62 for a complete description of the register contents. Table 62. Socket Control Register BIT SIGNAL TYPE 31–8 RSVD R 7 STOPCLK R/W CB CLKRUN protocol instructions. 0 = CB CLKRUN protocol can only attempt to stop/slow the CB clock if the socket is idle and the PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock. 1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle. VCC control. Bits 6–4 are used to request card VCC changes. 000 = Request power off (default) 001 = Reserved 010 = Request VCC = 5 V 011 = Request VCC = 3.3 V 100 = Request VCC = X.X V 101 = Request VCC = Y.Y V 110 = Reserved 111 = Reserved 6–4 VCCCTRL R/W 3 RSVD R 2–0 112 VPPCTRL R/W FUNCTION Reserved. Bits 31–8 are read-only and return 0s when read. Reserved. Bit 3 is read-only and returns 0 when read. VPP control. Bits 2–0 are used to request card VPP changes. 000 = Request power off (default) 001 = Request VPP = 12 V 010 = Request VPP = 5 V 011 = Request VPP = 3.3 V 100 = Request VPP = X.X V 101 = Request VPP = Y.Y V 110 = Reserved 111 = Reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 socket power management register Bit 31 30 29 28 27 26 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name 25 24 23 22 21 20 19 18 17 16 R R R R R R R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Socket power management Name Socket power management Type R R R R R R R R R R R R R R R R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket power management Read-only, read/write (see individual bit descriptions) CardBus socket address + 20h 0000 0000h This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See Table 63 for a complete description of the register contents. Table 63. Socket Power Management Register BIT SIGNAL TYPE 31–26 RSVD R Reserved. Bits 31–26 are read-only and return 0s when read. 25 SKTACCES R Socket access status. This bit provides information on when a socket access has occurred. This bit is cleared by a read access. 0 = A PC Card access has not occurred (default). 1 = A PC Card access has occurred. 24 SKTMODE R Socket mode status. This bit provides clock mode information. 0 = Clock is operating normally. 1 = Clock frequency has changed. 23–17 RSVD R Reserved. Bits 23–17 are read-only and return 0s when read. 16 CLKCTRLEN R/W 15–1 RSVD R 0 CLKCTRL R/W FUNCTION CardBus clock control enable. When bit 16 is set, clock control (CLKCTRL bit 0) is enabled. 0 = Clock control is disabled (default). 1 = Clock control is enabled. Reserved. Bits 15–1 are read-only and return 0s when read. CardBus clock control. This bit determines whether the CB CLKRUN protocol will attempt to stop or slow the CB clock during idle states. Bit 16 enables this bit. 0 = Allows CB CLKRUN protocol to stop the CB clock (default). 1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 113 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 distributed DMA (DDMA) registers The DMA base address, programmable in PCI configuration space at offset 98h, points to a 16-byte region in PCI I/O space where the DDMA registers reside. The names and locations of these registers are summarized in Table 64. These PCI1225 register definitions are identical in function, but differ in location, to the 8237 DMA controller. The similarity between the register models retains some level of compatibility with legacy DMA and simplifies the translation required by the master DMA device when it forwards legacy DMA writes to DMA channels. While the DMA register definitions are identical to those of the same name in the 8237, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment. In such cases, the PCI1225 implements these obsolete register bits as read-only nonfunctional bits. The reserved registers shown in Table 64 are implemented as read-only and return 0s when read. Write transactions to reserved registers have no effect. Table 64. Distributed DMA Registers TYPE DMA BASE ADDRESS OFFSET REGISTER NAME R W Current address Reserved Page Reserved Reserved Base address R W 00h Current count R N/A W Mode R Multichannel W Mask 04h Base count Reserved N/A Status Request Command N/A Reserved Master clear 08h 0Ch Reserved DMA current address/base address register Bit 15 14 13 Name Type 12 11 10 9 8 DMA current address/base address R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Name Type Default DMA current address/base address Register: Type: Offset: Default: Description: DMA current address/base address Read/write DMA base address + 00h 0000h This read/write register is used to set the starting (base) memory address of a DMA transfer. Read transactions from this register indicate the current memory address of a direct memory transfer. For the 8-bit DMA transfer mode, the current address register contents are presented on AD15–AD0 of the PCI bus during the address phase. Bits 7–0 of the page register are presented on AD23–AD16 of the PCI bus during the address phase. 114 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 DMA current address/base address register (continued) For the 16-bit DMA transfer mode, the current address register contents are presented on AD16–AD1 of the PCI bus during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the page register are presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored. DMA page register Bit 7 6 5 4 Name Type Default 3 2 1 0 DMA page R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: DMA page Read/write DMA base address + 02h 00h This read/write register is used to set the upper byte of the address of a DMA transfer. Details of the address represented by this register are explained in DMA current address/base address register. DMA current count/base count register Bit 15 14 13 Name Type 12 11 10 9 8 DMA current count/base count R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Type Default DMA current count/base count R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: DMA current count/base count Read/write DMA base address + 04h 0000h This read/write register is used to set the total transfer count, in bytes, of a direct memory transfer. Read transactions to this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after each transfer, and the count is decremented by 2 after each transfer in the 16-bit transfer mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 115 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 DMA command register Bit 7 6 5 4 Type R R R R Default 0 0 0 0 Name 3 2 1 0 R R/W R R 0 0 0 0 DMA command Register: Type: Offset: Default: Description: DMA command Read-only, read/write (see individual bit descriptions) DMA base address + 08h 00h This register is used to enable and disable the DMA controller. Bit 2, the only read/write bit, defaults to 0 enabling the DMA controller. All other bits are reserved. See Table 65 for a complete description of the register contents. Table 65. DMA Command Register BIT SIGNAL TYPE 7–3 RSVD R 2 DMAEN R/W 1–0 RSVD R FUNCTION Reserved. Bits 7–3 are read-only and return 0s when read. DMA controller enable. Bit 2 enables and disables the distributed DMA slave controller in the PCI1225 and defaults to the enabled state. 0 = DMA controller enabled (default) 1 = DMA controller disabled Reserved. Bits 1–0 are read-only and return 0s when read. DMA status register Bit 7 6 5 4 Name 3 2 1 0 DMA status Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: DMA status Read-only (see individual bit descriptions) DMA base address + 08h 00h This read-only register indicates the terminal count and DMA request (DREQ) status. See Table 66 for a complete description of the register contents. Table 66. DDMA Status Register BIT 7–4 3–0 116 SIGNAL DREQSTAT TC TYPE FUNCTION R Channel request. In the 8237, bits 7–4 indicate the status of DREQ of each DMA channel. In the PCI1225, these bits indicate the DREQ status of the single socket being serviced by this register. All four bits are set when the PC Card asserts DREQ and are reset when DREQ is deasserted. The status of the mask bit in the multichannel mask register has no effect on these bits. R Channel terminal count. The 8327 uses bits 3–0 to indicate the TC status of each of its four DMA channels. In the PCI1225, these bits report information about a single DMA channel; therefore, all four of these register bits indicate the TC status of the single socket being serviced by this register. All four bits are set when the TC is reached by the DMA channel. These bits are reset when read or the DMA channel is reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 DMA request register Bit 7 6 5 4 3 2 1 0 Type W W W W Default 0 0 0 W W W W 0 0 0 0 0 Name DMA request Register: Type: Offset: Default: Description: DMA request Write-only DMA base address + 09h 00h This write-only register is used to request a DDMA transfer through software. Any write to this register enables software requests, and this register is to be used in block mode only. DMA mode register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 Name Type Default DMA mode Register: Type: Offset: Default: Description: DMA mode Read-only, read/write (see individual bit descriptions) DMA base address + 0Bh 00h This register is used to set the DMA transfer mode. See Table 67 for a complete description of the register contents. Table 67. DMA Mode Register BIT 7–6 SIGNAL DMAMODE TYPE FUNCTION R/W Mode select. The PCI1225 uses bits 7–6 to determine the transfer mode. 00 = Demand mode select (default) 01 = Single mode select 10 = Block mode select 11 = Reserved 5 INCDEC R/W Address increment/decrement. The PCI1225 uses bit 5 to select the memory address in the current address/base address register to increment or decrement after each data transfer. This is in accordance with the 8237 use of this register bit, and is encoded as follows: 0 = Addresses increment (default). 1 = Addresses decrement. 4 AUTOINIT R/W Auto initialization 0 = Autoinitialization disabled (default) 1 = Autoinitialization enabled Transfer type. Bits 3–2 select the type of direct memory transfer to be performed. A memory write transfer moves data from the PCI1225 PC Card interface to memory, and a memory read transfer moves data from memory to the PCI1225 PC Card interface. The field is encoded as: 00 = No transfer selected (default) 01 = Write transfer 10 = Read transfer 11 = Reserved 3–2 XFERTYPE R/W 1–0 RSVD R Reserved. Bits 1–0 are read-only and return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 117 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 DMA master clear register Bit 7 6 5 4 Type W W W W Default 0 0 0 0 Name 3 2 1 0 W W W W 0 0 0 0 DMA master clear Register: Type: Offset: Default: Description: DMA master clear Write-only DMA base address + 0Dh 00h This write-only register is used to reset the DDMA controller and resets all DDMA registers. DMA multichannel/mask register Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 4 3 2 1 0 R R R R 0 0 0 0 DMA multichannel/mask Register: Type: Offset: Default: Description: DMA multichannel/mask Read-only (see individual bit descriptions) DMA base address + 0Fh 00h The PCI1225 uses only the least-significant bit of this register to mask the PC Card DMA channel. The PCI1225 sets the mask bit when the PC Card is removed. Host software is responsible for either resetting the socket’s DMA controller or enabling the mask bit. See Table 68 for a complete description of the register contents. Table 68. DMA Multichannel/Mask Register BIT SIGNAL TYPE 7–1 RSVD R Reserved. Bits 7–1 are read-only and return 0s when read. R Mask select. Bit 0 masks incoming DREQ signals from the PC Card. When set, the socket ignores DMA requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced normally. 0 = DDMA service provided on card DREQ 1 = Socket DREQ signal ignored (default) 0 118 MASKBIT FUNCTION POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 absolute maximum ratings over operating temperature ranges (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Clamping voltage range, VCCP, VCCA, VCCB, VCCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCA + 0.5 V Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCB + 0.5 V MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCI + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCA + 0.5 V Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCB + 0.5 V MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCI + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCA or VCCB. Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. 2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCA or VCCB. Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 119 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 recommended operating conditions (see Note 3) OPERATION VCC Commercial Core voltage VCCP PCI I/O clamping rail voltage Commercial VCCA VCCB PC Card I/O clamping rail voltage Commercial VCCI Miscellaneous I/O clamping rail voltage Commercial MIN NOM MAX 3.3 V 3 3.3 3.6 3.3 V 3 3.3 3.6 4.75 5 5.25 5V 3.3 V 5V 3.3 V 5V 3.3 V PCI VIH† 5V 3.3 V PC Card High level in ut voltage High-level input 5V MISC‡ Fail safe§ VI VO¶ Input voltage Output voltage 3.6 5 5.25 3 3.3 3.6 4.75 5 5.25 0.5 VCCP VCCP 2 VCCP 0.475 VCC(A/B) VCC(A/B) 2.4 VCC(A/B) 2 VCCI 2 VCC 0 0.3 VCCP 5V 0 0.8 3.3 V 0 0.325 VCC(A/B) 5V 0 0.8 MISC‡ 0 0.8 Fail safe§ 0 0.8 PCI 0 VCCP PC Card 0 VCC(A/B) MISC‡ 0 VCCI Fail safe§ 0 VCC PCI 0 VCC PC Card 0 VCC MISC‡ 0 VCC Fail safe§ 0 VCC PCI and PC Card 1 4 MISC‡ and fail safe§ 0 6 PC Card Low level in ut voltage Low-level input 3.3 3.3 V PCI VIL† 3 4.75 UNIT V V V V V V V V tt Input transition time (tr and tf) ns TA TJ# Operating ambient temperature range 0 25 70 °C Virtual junction temperature 0 25 115 °C NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating. † Applies to external inputs and bidirectional buffers without hysteresis ‡ Miscellaneous terminals are 149, 150, 151, 152, 154, 155, 156, 157, 158, 159, 161, 163 for the PDV packaged device and G15, F17, E19, F14, F15, E17, D19, A16, A16, C15, C15, E14, B15 and C14 for the GHK packaged device (SUSPEND, SPKROUT, RI_OUT, multifunction terminals (MFUNC0–MFUNC6), and power switch control terminals). § Fail-safe terminals are 16, 56, 68, 74, 82, 122, 134, and 140 for the PDV packaged device and H3, P7, U8, R9, V11, M19, J18, and H17 for the GHK packaged device (card detect and voltage sense terminals). ¶ Applies to external output buffers # These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. 120 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER PINS OPERATION 3.3 V PCI VOH High-level High level out output ut voltage PC Card 5V Low level output voltage Low-level PC Card 0.9 VCC 2.4 5V Output pins IOZH 3-state, high-impedance high-im edance high-level output current Output pins IIL L Low-level l l input i t currentt V 06 VCC–0.6 0.1 VCC 0.55 3.3 V IOL = 0.7 mA 0.1 VCC 5V IOL = 0.7 mA 0.55 IOL = 4 mA 0.5 IOL = 12 mA VI = VCC 0.5 3.6 V 5.25 V VI = VCC –1 3.6 V VI = VCC† VI = VCC† 10 VI = GND VI = GND –1 SERR 3-state, high-im high-impedance edance low-level output current IOL = 6 mA 5.25 V Input pins I/O pins –1 25 –10 VI = VCC‡ VI = VCC‡ 10 VI = VCC‡ VI = VCC‡ 10 VI = VCC † For PCI pins, VI = VCCP. For PC Card pins, VI = VCC(A/B). For miscellaneous pins, VI = VCCI ‡ For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. 10 3.6 V Input pins IIH 5.25 V 3.6 V High-level High level in input ut current I/O pins Fail-safe pins 5.25 V 3.6 V UNIT 2.4 IOH = –0.15 mA 4 mA IOH = –4 IOL = 1.5 mA MAX 0.9 VCC IOH = –0.15 mA MISC IOZL IOH = –2 mA 5V 3.3 V VOL IOH = –0.5 mA MIN 3.3 V MISC PCI TEST CONDITIONS V µA A µA A µA A 20 µA µ 25 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 121 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 25 and Figure 26) ALTERNATE SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT tc Cycle time, PCLK tcyc 30 ns twH Pulse duration (width), PCLK high thigh 11 ns twL Pulse duration (width), PCLK low tlow 11 ns ∆v/∆t Slew rate, PCLK tr, tf 1 tw Pulse duration (width), RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN 100 s trst-clk 4 V/ns PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4 and Figure 24 and Figure 27) ALTERNATE SYMBOL PARAMETER tpd Pro agation delay time, Propagation See Note 5 PCLK-to-shared signal valid delay time tval PCLK-to-shared signal invalid delay time tinv ten tdis Enable time, high impedance-to-active delay time from PCLK tsu th Setup time before PCLK valid Disable time, active-to-high impedance delay time from PCLK Hold time after PCLK high TEST CONDITIONS CL = 50 pF, F, See Note 5 MIN MAX UNIT 11 ns 2 ton toff 2 ns tsu th 7 ns 0 ns 28 ns NOTES: 4. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 5. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR. 122 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PARAMETER MEASUREMENT INFORMATION LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD† (pF) IOL (mA) IOH (mA) VLOAD (V) 50 8 –8 0 3 50 8 –8 1.5 50 8 –8 ‡ IOL Test Point From Output Under Test VLOAD CLOAD † CLOAD includes the typical load-circuit distributed capacitance IOH ‡ VLOAD – VOL = 50 Ω, where V OL = 0.6 V, IOL = 8 mA IOL LOAD CIRCUIT VCC Timing Input (see Note A) 50% VCC High-Level Input 0V th tsu 90% VCC Data Input 10% VCC 50% VCC 50% VCC Low-Level Input 0V tf VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES Output Control (low-level enabling) 50% VCC tPLZ tpd 50% VCC tpd 50% VCC VOH 50% VCC VOL tpd Waveform 1 (see Notes B and C) VOH 50% VCC VOL Waveform 2 (see Notes B and C) 50% VCC tPHZ tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 50% VCC 0V 0V In-Phase Output VCC 50% VCC 0V VCC tPZL 50% VCC tpd Out-of-Phase Output 50% VCC VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC VCC 50% VCC 0V tw VCC tr Input (see Note A) 50% VCC 50% VCC VCC ≅ 50% VCC VOL + 0.3 V VOL VOH VOH – 0.3 V ≅ 50% VCC 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the following characteristics: PRR = 1 MHz, ZO = 50 Ω, tr = 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ, VOL and VOH are measured values. Figure 24. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 123 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PCI BUS PARAMETER MEASUREMENT INFORMATION thigh tlow 2V 0.8 V tf tr 2 V MIN Peak-to-Peak tcyc Figure 25. PCLK Timing Waveform PCLK trst RSTIN tsrst-clk Figure 26. RSTIN Timing Waveforms PCLK 1.5 V tval PCI Output tinv Valid 1.5 V ton toff PCI Input Valid tsu th Figure 27. Shared Signals Timing Waveforms 124 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PC Card cycle timing The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and hold times, and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL-DF timing as possible, while always slightly exceeding the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. The PC Card address setup and hold times are a function of the wait-state bits. Table 69 shows address setup time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 70 and Table 71 show command active time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 72 shows address hold time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 69. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles TS1 – 0 = 01 (PCLK/ns) WAIT-STATE BITS I/O 3/90 Memory WS1 0 2/60 Memory WS1 1 4/120 Table 70. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles WAIT-STATE BITS ZWS TS1 – 0 = 01 (PCLK/ns) 0 0 19/570 1 X 23/690 0 1 7/210 00 0 19/570 01 X 23/690 10 X 23/690 11 X 23/690 00 1 7/210 WS I/O Memory Table 71. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles WAIT-STATE BITS I/O Memory y WS ZWS TS1 – 0 = 01 (PCLK/ns) 0 0 7/210 1 X 11/330 0 1 N/A 00 0 9/270 01 X 13/390 10 X 17/510 11 X 23/630 00 1 5/150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 Table 72. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles TS1 – 0 = 01 (PCLK/ns) WAIT-STATE BITS I/O 2/60 Memory WS1 0 2/60 Memory WS1 1 3/90 timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see Note 6 and Figure 28) ALTERNATE SYMBOL tsu tsu Setup time, CE1 and CE2 before WE/OE low T1 Setup time, CA25–CA0 before WE/OE low T2 tsu tpd Setup time, REG before WE/OE low T3 Propagation delay time, WE/OE low to WAIT low T4 tw th Pulse duration (width), WE/OE low T5 Hold time, WE/OE low after WAIT high T6 th tsu Hold time, CE1 and CE2 after WE/OE high T7 Setup time (read), CDATA15–CDATA0 valid before OE high T8 th th Hold time (read), CDATA15–CDATA0 valid after OE high T9 Hold time, CA25–CA0 and REG after WE/OE high T10 tsu th Setup time (write), CDATA15–CDATA0 valid before WE low Hold time (write), CDATA15–CDATA0 valid after WE low MIN MAX 60 UNIT ns tsu(A)+2PCLK 90 ns ns ns 200 ns ns 120 ns ns 0 ns ns T11 th(A)+1PCLK 60 T12 240 ns ns NOTE 6: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock. timing requirements over recommended ranges of supply voltage and operating free-air temperature, I/O cycles (see Figure 29) ALTERNATE SYMBOL MIN MAX UNIT tsu tsu Setup time, REG before IORD/IOWR low T13 Setup time, CE1 and CE2 before IORD/IOWR low T14 tsu tpd Setup time, CA25–CA0 valid before IORD/IOWR low T15 Propagation delay time, IOIS16 low after CA25–CA0 valid T16 tpd tw Propagation delay time, IORD low to WAIT low T17 35 ns Pulse duration (width), IORD/IOWR low T18 TcA ns th th Hold time, IORD low after WAIT high T19 Hold time, REG low after IORD high T20 th th Hold time, CE1 and CE2 after IORD/IOWR high Hold time, CA25–CA0 after IORD/IOWR high tsu th Setup time (read), CDATA15–CDATA0 valid before IORD high T23 Hold time (read), CDATA15–CDATA0 valid after IORD high T24 0 ns tsu th Setup time (write), CDATA15–CDATA0 valid before IOWR low T25 90 ns Hold time (write), CDATA15–CDATA0 valid after IOWR high T26 90 ns 126 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 60 ns 60 ns tsu(A)+2PCLK ns 35 ns ns 0 ns T21 120 ns T22 th(A)+1PCLK 10 ns ns PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see Figure 30) ALTERNATE SYMBOL PARAMETER BVD2 low to SPKROUT low tpd d MAX UNIT 30 BVD2 high to SPKROUT high Propagation delay time MIN IREQ to IRQ15–IRQ3 T27 30 30 T28 STSCHG to IRQ15–IRQ3 ns 30 PC Card PARAMETER MEASUREMENT INFORMATION CA25–CA0 T10 REG CE1, CE2 T1 WE, OE T5 T7 T3 T2 T6 T4 WAIT T12 T11 CDATA15–CDATA0 (write) T8 T9 CDATA15–CDATA0 (read) With no wait state With wait state Figure 28. PC Card Memory Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 127 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 PC Card PARAMETER MEASUREMENT INFORMATION CA25–CA0 T16 T22 IOIS16 REG T20 CE1, CE2 T14 IORD, IOWR T13 T15 T18 T21 T19 T17 WAIT T26 T25 CDATA15–CDATA0 (write) T23 T24 CDATA15–CDATA0 (read) With no wait state With wait state Figure 29. PC Card I/O Cycle BVD2 T27 SPKROUT IREQ T28 IRQ15–IRQ3 Figure 30. Miscellaneous PC Card Delay Times 128 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 MECHANICAL DATA GHK (S-PBGA-N257) PLASTIC BALL GRID ARRAY 16,10 SQ 15,90 14,40 TYP 0,80 0,80 W V U T R P N M L K J H G F E D C B A 1 3 2 0,95 0,85 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4145273–3/B 12/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 129 PCI1225 GHK/PDV PC CARD CONTROLLERS SCPS035B – MAY 1998 – REVISED – MAY 2000 MECHANICAL DATA PDV (S-PQFP-G208) PLASTIC QUAD FLATPACK 156 105 157 104 0,27 0,17 0,08 M 0,50 0,13 NOM 208 53 1 52 Gage Plane 25,50 TYP 28,05 SQ 27,95 0,25 0,05 MIN 0°–7° 30,10 SQ 29,90 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4087729/B 06/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136 130 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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