PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 D 1997 PC Standard Compliant D PCI Bus Power Management Interface D D D D D D D D D D D D D D D D D D D D Specification 1.1 Compliant ACPI 1.0 Compliant PCI Local Bus Specification Revision 2.1/2.2 Compliant PC 98/99 Compliant Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges Fully Compliant with the PCI Bus Power Management Specification for PCI to CardBus Bridges Specification Ultra Zoomed Video Zoomed Video Auto-Detect Advanced filtering on Card Detect Lines Provide 90 Microseconds of Noise Immunity. Programmable D3 Status Pin Internal Ring Oscillator 3.3-V Core Logic with Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards Supports Two PC Card or CardBus Slots With Hot Insertion and Removal Uses Serial Interface to TI TPS2206 Dual Power Switch Supports 132 Mbyte/sec. Burst Transfers to Maximize Data Throughput on Both the PCI Bus and the CardBus Bus Supports Serialized IRQ with PCI Interrupts 8 Programmable Multifunction Pins Interrupt Modes Supported: Serial ISA/Serial PCI, Serial ISA/Parallel PCI, Parallel PCI Only. Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID Supports Zoomed Video with Internal Buffering D Dedicated Pin for PCI CLKRUN D Four General-Purpose Event Registers D Multifunction PCI Device with Separate D D D D D D D D D D D D D D D D D D Configuration Space for each Socket Five PCI Memory Windows and Two I/O Windows Available to each PC Card16 Socket Two I/O Windows and Two Memory Windows Available to each CardBus Socket ExCA-Compatible Registers are Mapped in Memory or I/O Space Supports Distributed DMA and PC/PCI DMA Intel 82365SL-DF Register Compatible Supports 16-bit DMA on Both PC Card Sockets Supports Ring Indicate, SUSPEND, and PCI CLKRUN Advanced Submicron, Low-Power CMOS Technology Provides VGA / Palette Memory and I/O, and Subtractive Decoding Options LED Activity Pins Supports PCI Bus Lock (LOCK) Packaged in a 256-pin BGA or 257-pin Micro-Star BGA OHCI Link Function Designed to IEEE 1394 Open Host Controller Interface (OHCI) Specification Implements PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency Supports Physical Write Posting of up to 3 Outstanding Transactions OHCI Link Function is IEEE 1394-1995 Compliant and Compatible with Proposal 1394a Supports Serial Bus Data Rates of 100, 200, and 400 Mbits/second Provides Bus-Hold Buffers on the PHY-Link I/F for Low-cost Single Capacitor Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names and Terminal Assignments . . . . . . . . . . . . . . . . . . . 5 PCI4450 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PC Card Applications Overview . . . . . . . . . . . . . . . . . . . . . . . . . 28 Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . 35 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . 43 PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . 44 ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . . 82 CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . 106 Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . 114 2 POST OFFICE BOX 655303 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switrching Characteristics for PHY-Link Interface . . . . . . . . . . . . . Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements, (Memory Cycles) . . . . . . . . . . . . . . . . . . . . Timing Requirements, (I/O Cycles) . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics (Miscellaneous) . . . . . . . . . . . . . . . . . . PC Card Parameter Mesasurement Information . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • DALLAS, TEXAS 75265 182 183 185 186 187 188 188 188 189 190 191 192 197 193 193 195 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 description The Texas Instruments PCI4450 is an integrated dual-socket PC Card controller and IEEE 1394 Open HCI host controller. This high-performance integrated solution provides the latest in both PC Card and IEEE 1394 technology. The PCI4450 is a three-function PCI device compliant with PCI Local Bus Specification 2.2. Functions 0 and 1 provide the independent PC Card socket controllers compliant with the 1997 PC Card Standard. The PCI4450 provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI4450 is register compatible with the Intel 82365SL–DF ExCA controller. The PCI4450 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI4450 can be programmed to accept posted writes to improve bus utilization. Function 2 of the PCI4450 is compatible with IEEE1394A and the latest 1394 open host controller interface (OHCI) specifications. The chip provides the IEEE1394 link function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI4450 provides physical write posting and a highly tuned physical data path for SBP-2 performance. Multiple cache line burst transfers, advanced internal arbitration, and bus holding buffers on the PHY/Link interface are other features that make the PCI4450 the best-in-class 1394 Open HCI solution. The PCI4450 provides an internally buffered zoomed video (ZV) path. This reduces the design effort of PC board manufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loading specifications. Various implementation specific functions and general-purpose inputs and outputs are provided through eight multifunction terminals. These terminals present a system with options in PC/PCI DMA, PCI LOCK and parallel interrupts, PC Card activity indicator LEDs, and other platform specific signals. ACPI-complaint general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs. The PCI4450 is compliant with the latest PCI Bus Power Management Specification, and provides several low-power modes which enable the host power system to further reduce power consumption. The PC Card (CardBus) Controller and IEEE 1394 Host Controller Device Class Specifications required for Microsoft OnNowt Power Management are supported. Furthermore, an advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption. Unused PCI4450 inputs must be pulled to a valid logic level using a 43 kΩ resistor. use of symbols in this document Throughout this data sheet the overbar symbol denotes an active-low signal. For example: FRAME denotes that this is an active-low signal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal assignments 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A A ÇÇ ÇÇ A A B A A A C A A A D A A A E A A A F A A A G A A A H A A A J A A A K A A A L A ÇÇ ÇÇ ÇÇ ÇÇ A A M A A A N Z A A P Z Z A R Z Z Z T Z Z Z U Z Z Z Z V Z Z Z Z W Z Z Z Y B B B B B B B B B B B B A A A A A A A B B B B B B B B B B B A A A A A B B B B B B B B B B B B A A A A A B B B B ÇÇ ÇÇ B B B B B B B B B B P P B B B B B ÇÇ ÇÇ B B ÇÇ ÇÇ B A A ÇÇ ÇÇ A B B B B P P ÇÇ ÇÇ A ÇÇ ÇÇ B 1 A Bottom View P P P P P P P P P P P P P P P P P ÇÇ ÇÇ ÇÇ ÇÇ P P P P P ÇÇ ÇÇ T ÇÇ ÇÇ S S S S P P P P P P P T S S S S S P P P P P P P S S S S P A P A P P P Z P P P P P P P PCI Interface A PC Card A B PC Card B Z Zoom Video S 1394 PHY/Link T P S Z Z S ÇÇ T POST OFFICE BOX 655303 Ground (GND) TPS Power Switch Miscellaneous Figure 1. PCI4450 Pin Diagram 4 VCC 3.3 Volt • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 signal names and terminal assignments Signal names and their terminal assignments are shown in Tables 1 and 2 and are sorted alphanumerically by the assigned terminal. Table 1. GFN Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI GFN SIGNAL NAME GFN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 GND A_CAD16//A_A17 A_CAD11//A_OE A_CC/BE0//A_CE1 A_RSVD//A_D14 A_CAD3//A_D5 A_CAD1//A_D4 A_CCD1//A_CD1 B_CAD29//B_D1 B_CCLKRUN//B_WP(IOIS16) B_CSTSCHG//B_BVD1(STSCHG/RI) B_CINT//B_READY(IREQ) B_CAD24//B_A2 B_CAD23//B_A3 B_CAD21//B_A5 B_CAD19//B_A25 B_CC/BE2//B_A12 B_CFRAME//B_A23 B_CGNT//B_WE B_CSTOP//B_A20 A_RSVD//A_A18 A_CAD14//A_A9 A_CAD15//A_IOWR A_CAD10//A_CE2 VCCA A_CAD5//A_D6 A_CAD4//A_D12 A_CAD0//A_D3 B_CAD30//B_D9 B_CCD2//B_CD2 B_CSERR//B_WAIT B_CVS1//B_VS1 VCCB B_CREQ//B_INPACK B_CRST//B_RESET B_CAD18//B_A7 B_CCLK//B_A16 B_CDEVSEL//B_A21 B_CPERR//B_A14 B_CPAR//B_A13 A_CGNT//A_WE A_CPAR//A_A13 A_CC/BE1//A_A8 A_CAD12//A_A11 A_CAD9//A_A10 A_CAD8//A_D15 A_CAD6//A_D13 A_CAD2//A_D11 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 SIGNAL NAME B_RSVD//B_D2 B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR) B_CAD26//B_A0 B_CC/BE3//B_REG B_CAD22//B_A4 B_CVS2//B_VS2 B_CAD17//B_A24 B_CTRDY//B_A22 B_CBLOCK//B_A19 B_RSVD//B_A18 B_CAD14//B_A9 A_CDEVSEL//A_A21 A_CBLOCK//A_A19 A_CPERR//A_A14 GND A_CAD13//A_IORD VCC A_CAD7//A_D7 GND B_CAD31//B_D10 B_CAD28//B_D8 VCC B_CAD25//B_A1 GND B_CAD20//B_A6 VCC B_CIRDY//B_A15 GND B_CC/BE1//B_A8 B_CAD15//B_IOWR B_CAD13//B_IORD A_CIRDY//A_A15 A_CTRDY//A_A22 A_CCLK//A_A16 A_CSTOP//A_A20 B_CAD16//B_A17 B_CAD12//B_A11 VCCB B_CAD9//B_A10 A_CAD17//A_A24 A_CC/BE2//A_A12 VCCA VCC VCC B_CAD11//B_OE B_CC/BE0//B_CE1 B_CAD7//B_D7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GFN SIGNAL NAME G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 A_CVS2//A_VS2 A_CAD19//A_A25 A_CAD18//A_A7 A_CFRAME//A_A23 B_CAD10//B_CE2 B_CAD8//B_D15 B_RSVD//B_D14 B_CAD5//B_D6 A_CAD21//A_A5 A_CRST//A_RESET A_CAD20//A_A6 GND GND B_CAD6//B_D13 B_CAD3//B_D5 B_CAD4//B_D12 A_CC/BE3//A_REG A_CAD23//A_A3 A_CREQ//A_INPACK A_CAD22//A_A4 B_CAD1//B_D4 B_CAD2//B_D11 B_CAD0//B_D3 B_CCD1//B_CD1 A_CAD26//A_A0 A_CAD24//A_A2 A_CAD25//A_A1 VCC PCLK CLKRUN PRST GNT A_CVS1//A_VS1 A_CINT//A_READY(IREQ) A_CSERR//A_WAIT VCCA VCC AD31 AD30 REQ A_CAUDIO//A_BVD2(SPKR) A_CSTSCHG//A_BVD1(STSCHG/RI) A_CCLKRUN//A_WP(IOIS16) A_CCD2//A_CD2 AD26 AD27 AD28 AD29 5 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 signal names and terminal assignments (continued) Table 1. GFN Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI (Continued) GFN N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 6 SIGNAL NAME A_CAD27//A_D0 A_CAD28//A_D8 A_CAD29//A_D1 GND GND C/BE3 AD24 AD25 A_CAD30//A_D9 A_RSVD//A_D2 ZV_HREF ZV_Y1 AD20 AD23 VCCP IDSEL/MFUNC7 A_CAD31//A_D10 ZV_VSYNC ZV_Y2 VCC VCC AD19 AD21 AD22 ZV_Y0 ZV_Y3 ZV_Y5 ZV_UV0 IRDY AD16 AD17 AD18 ZV_Y4 ZV_Y6 ZV_UV2 GND ZV_SDATA VCC GFN U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 SIGNAL NAME PHY_CTL0 GND PHY_DATA6 VCC SUSPEND CLOCK GND AD6 VCC AD12 GND TRDY W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 DEVSEL C/BE2 ZV_Y7 ZV_UV1 ZV_UV3 ZV_LRCLK MFUNC5 PHY_CLK PHY_DATA0 PHY_DATA3 PHY_DATA7 MFUNC3 SPKROUT DATA AD0 VCCP AD7 AD9 AD13 C/BE1 STOP FRAME ZV_UV4 ZV_UV6 ZV_SCLK POST OFFICE BOX 655303 GFN • DALLAS, TEXAS 75265 SIGNAL NAME ZV_MCLK LPS PHY_CTL1 PHY_DATA1 PHY_DATA4 MFUNC4 SCL MFUNC0 LATCH IRQSER AD2 AD4 C/BE0 AD10 AD14 PAR PERR ZV_UV5 ZV_UV7 ZV_PCLK MFUNC6 PHY_LREQ LINKON PHY_DATA2 PHY_DATA5 SDA MFUNC2 MFUNC1 G_RST RI_OUT AD1 AD3 AD5 AD8 AD11 AD15 SERR PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 signal names and terminal assignments (continued) Table 2. GJG Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI NO. SIGNAL NAME NO. A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11 A_CC/BE1//A_A8 GND A_CAD12//A_A11 A_CAD10//A_CE2 A_CAD8//A_D15 A_CAD3//A_D5 A_CAD0//A_D3 B_CAD29//B_D1 B_CSTSCHG//B_BVD1(STSCHG/RI) VCC B_CC/BE3//B_REG B_CREQ//B_INPACK B_CVS2//B_VS2 B_CAD17//B_A24 GND B_CCLK//B_A16 B_CDEVSEL//B_A21 A_CPAR//A_A13 A_RSVD//A_A18 A_CAD16//A_A17 A_CAD15//A_IOWR A_CAD11//A_OE VCCA A_CAD6//A_D13 A_CAD2//A_D11 B_CAD30//B_D9 B_CCLKRUN//B_WP(IOIS16) B_CVS1//B_VS1 VCCB B_CAD22//B_A4 B_CAD20//B_A6 B_CAD18//B_A7 B_CIRDY//B_A15 B_CTRDY//B_A22 B_CGNT//B_WE B_CSTOP//B_A20 GND A_CBLOCK//A_A19 B_CPERR//B_A14 B_CPAR//B_A13 A_CPERR//A_A14 A_CSTOP//A_A20 A_CAD14//A_A9 A_CAD13//A_IORD A_CC/BE0//A_CE1 A_CAD5//A_D6 GND B_RSVD//B_D2 B_CCD2//B_CD2 B_CAD26//B_A0 D12 D13 D14 D15 D16 D18 D19 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E18 E19 F1 F2 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F18 F19 G1 G2 G4 G5 G6 G7 G13 G14 G15 SIGNAL NAME B_CAD24//B_A2 B_CAD23//B_A3 VCC B_CFRAME//B_A23 B_CBLOCK//B_A19 B_RSVD//B_A18 B_CC/BE1//B_A8 VCC A_CCLK//A_A16 A_CGNT//A_WE A_CDEVSEL//A_A21 VCC A_RSVD//A_D14 A_CAD1//A_D4 B_CAD31//B_D10 B_CAD27//B_D0 B_CINT//B_READY(IREQ) B_CAD25//B_A1 B_CAD21//B_A5 B_CAD19//B_A25 B_CC/BE2//B_A12 B_CAD16//B_A17 B_CAD14//B_A9 VCC VCCA A_CFRAME//A_A23 A_CIRDY//A_A15 A_CTRDY//A_A22 A_CAD9//A_A10 A_CAD7//A_D7 A_CCD1//A_CD1 B_CAD28//B_D8 B_CAUDIO//B_BVD2(SPKR) B_CSERR//B_WAIT GND B_CRST//B_RESET B_CAD15//B_IOWR B_CAD12//B_A11 B_CAD13//B_IORD VCCB B_CAD11//B_OE GND A_CAD18//A_A7 A_CAD19//A_A25 A_CAD17//A_A24 A_CC/BE2//A_A12 A_CAD4//A_D12 B_CAD7//B_D7 B_CAD10//B_CE2 B_CAD9//B_A10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NO. SIGNAL NAME G16 G18 G19 H1 H2 H4 H5 H6 H14 H15 H16 H18 H19 J1 J2 J4 J5 J6 J14 J15 J16 J18 J19 K1 K2 K4 K5 K6 K14 K15 K18 K19 L1 L2 L4 L5 L6 L14 L15 L16 L18 L19 M1 M2 M4 M5 M6 M14 M15 M16 B_CC/BE0//B_CE1 B_CAD8//B_D15 GND A_CAD20//A_A6 A_CRST//A_RESET A_CAD21//A_A5 A_CAD22//A_A4 A_CVS2//A_VS2 B_CAD4//B_D12 B_RSVD//B_D14 B_CAD5//B_D6 B_CAD6//B_D13 B_CAD3//B_D5 A_CAD23//A_A3 A_CC/BE3//A_REG A_CREQ//A_INPACK A_CAD24//A_A2 A_CAD25//A_A1 VCC B_CAD1//B_D4 B_CAD2//B_D11 B_CAD0//B_D3 B_CCD1//B_CD1 A_CVS1//A_VS1 A_CINT//A_READY(IREQ) A_CSERR//A_WAIT VCCA A_CAD26//A_A0 GNT PCLK CLKRUN PRST A_CSTSCHG//A_BVD1(STSCHG/RI) A_CCLKRUN//A_WP(IOIS16) A_CCD2//A_CD2 A_CAD27//A_D0 A_CAUDIO//A_BVD2(SPKR) REQ AD31 AD28 AD30 AD29 A_CAD29//A_D1 GND A_CAD30//A_D9 A_RSVD//A_D2 A_CAD28//A_D8 C/BE3 AD27 AD26 7 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 signal names and terminal assignments (continued) Table 2. GJG Terminals Sorted Alphanumerically for CardBus // 16-bit Signals and OHCI (Continued) NO. M18 M19 N1 N2 N4 N5 N6 N7 N13 N14 N15 N16 N18 N19 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P18 P19 R1 R2 R4 R5 8 SIGNAL NAME AD25 AD24 ZV_HREF ZV_VSYNC ZV_Y0 ZV_Y1 ZV_Y2 A_CAD31//A_D10 AD3 AD22 AD23 GND VCCP IDSEL/MFUNC7 VCC ZV_Y3 ZV_Y4 ZV_Y5 ZV_Y6 LINKON PHY_DATA3 MFUNC2 MFUNC1 G_RST IRQSER AD6 AD9 VCC AD19 AD21 AD20 ZV_Y7 ZV_UV0 ZV_UV2 MFUNC6 NO. R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U18 U19 V1 SIGNAL NAME PHY_LREQ PHY_DATA0 PHY_DATA7 MFUNC3 SUSPEND RI_OUT AD2 AD5 AD8 AD16 C/BE2 AD18 AD17 ZV_UV1 ZV_UV4 GND VCC PHY_CLK GND PHY_DATA6 MFUNC4 SPKROUT CLOCK AD1 AD4 C/BE0 AD12 C/BE1 FRAME IRDY ZV_UV3 ZV_UV6 TRDY DEVSEL ZV_UV5 POST OFFICE BOX 655303 NO. V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 • DALLAS, TEXAS 75265 SIGNAL NAME ZV_SCLK ZV_LRCLK ZV_PCLK LPS PHY_CTL1 PHY_DATA1 PHY_DATA5 SCL VCC DATA AD0 VCC GND AD11 AD14 PAR PERR STOP ZV_UV7 ZV_MCLK ZV_SDATA MFUNC5 PHY_CTL0 PHY_DATA2 PHY_DATA4 SDA MFUNC0 LATCH GND VCCP AD7 AD10 AD13 AD15 SERR PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI4450 System Block Diagram Figure 2 shows a simplified system implementation example using the PCI4450. The PCI interface includes all address/data and control signals for PCI protocol. Highlighted in this diagram is the functionality supported by the PCI4450. The PCI4450 supports PC/PCI DMA, PCI Way DMA (distributed DMA), PME wake-up from D3cold through D0, 4 interrupt modes, an integrated zoomed video port, and 12 multifunction pins (8 MFUNC, and 4 GPIO pins) that can be programmed for a wide variety of functions. PCI Bus Activity LED’s Real Time Clock CLKRUN IRQSER PCI4450 Clock TPS2206 Power Switch ZV Enable 2 PC Card Socket A DMA 4 Zoomed Video 68 23 for ZV† PC Card Socket B Embedded Controller PME 23 4 South Bridge 19 Video VGA Controller 14 68 23 for ZV OHCI-PHY Interface PHY 4 Audio Audio Codec Interrupt Routing Options: 1) Serial ISA/Serial PCI 2) Serial ISA/Parallel PCI 1394 Ports † The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals to the VGA controller. Figure 2. PCI4450 System Block Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions This section describes the PCI4450 terminal functions. The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc., for quick reference. The terminal numbers are also listed for convenient reference. Table 3. Power Supply TERMINAL FUNCTION NAME GFN NO. GJG NO. GND A1, D4, D8, D13, D17, H4, H17, N4, N17, U4, U8, U13, U17 A3, A16, C1, D8, F12, G1, G19, M2, N16, T4, T7, V14, W12 Device ground terminals VCC D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 A11, D14, E1, E6, E19, J14, P1, P15, T5, V10, V13 Power supply terminal for core logic (3.3 Vdc) VCCA B5, F3, L4 B6, F1, K5 Clamp voltage for PC Card A interface. Indicates Card A signaling environment. VCCB B13, E19 B12, F18 Clamp voltage for PC Card B interface. Indicates Card B signaling environment. VCCP P19, V14 N18, W13 Clamp voltage for PCI signaling (3.3 Vdc or 5 Vdc) Table 4. PC Card Power Switch TERMINAL NAME 10 GFN NO. GJG NO. I/O TYPE FUNCTION CLOCK U12 T11 I/O 3-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. This terminal defaults as an input which means an external clock source must be used. If the internal ring oscillator is used, then an external CLOCK source is not required. The internal oscillator may be enabled by setting bit 27 of the system control register (PCI offset 80h) to a 1b. A 43 kW pulldown resistor should be tied to this terminal. DATA V12 V11 O 3-line power switch data. DATA is used to serially communicate socket power-control information to the power switch. LATCH W12 W11 O 3-line power switch latch. LATCH is asserted by the PCI4450 to indicate to the PC Card power switch that the data on the DATA line is valid. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 5. PCI System TERMINAL NAME GFN NO. GJG NO. I/O TYPE FUNCTION CLKRUN K18 K18 I/O PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow it down, and the PCI4450 responds accordingly. If CLKRUN is not implemented, then this pin should be tied low. CLKRUN is enabled by default by bit 1 (KEEPCLK) in the system control register. PCLK K17 K15 I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. I PCI reset. When the PCI bus reset is asserted, PRST causes the PCI4450 to place all output buffers in a high-impedance state and reset all internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI4450 is in its default state. When the SUSPEND mode is enabled, the device is protected from the PRST and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. I Global reset. When the global reset is asserted, the G_RST signal causes the PCI4450 to place all output buffers in a high-impedance state and reset all internal registers. When G_RST is asserted, the device is completely in its default state. For systems that require wake-up from D3, G_RST will normally be asserted only during initial boot. PRST should be asserted following initial boot so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, G_RST should be tied to PRST. PRST G_RST K19 Y12 K19 P11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 6. PCI Address and Data TERMINAL NAME GFN NO. GJG NO. AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 L18 L19 M20 M19 M18 M17 N20 N19 P18 R20 R19 P17 R18 T20 T19 T18 Y19 W18 V17 U16 Y18 W17 V16 Y17 V15 U14 Y16 W15 Y15 W14 Y14 V13 L15 L18 L19 L16 M15 M16 M18 M19 N15 N14 P18 P19 P16 R18 R19 R15 W17 V16 W16 T15 V15 W15 P14 R14 W14 P13 R13 T13 N13 R12 T12 V12 C/BE3 C/BE2 C/BE1 C/BE0 N18 U20 V18 W16 M14 R16 T16 T14 PAR 12 W19 V17 I/O TYPE FUNCTION I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. I/O PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). I/O PCI bus parity. In all PCI bus read and write cycles, the PCI4450 calculates even parity across the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI4450 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 7. PCI Interface Control TERMINAL NAME GFN NO. GJG NO. I/O TYPE FUNCTION DEVSEL U19 U19 I/O PCI device select. The PCI4450 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI4450 monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the PCI4450 terminates the cycle with an initiator abort. FRAME V20 T18 I/O PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. GNT K20 K14 I PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI4450 access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. I/O PCI bus lock. MFUNC7/LOCK can be configured as PCI LOCK and used to gain exclusive access downstream. Since this functionality is not typically used, other functions may be accessed through this terminal. MFUNC7/LOCK defaults to and can be configured through the multifunction routing status register. LOCK (MFUNC7) P20 N19 IDSEL/MFUNC7 P20 N19 I Initialization device select. IDSEL selects the PCI4450 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. If the LATCH terminal (W12/W11) has an external pulldown resistor, then this terminal is configurable as MFUNC7 and IDSEL defaults to the AD23 terminal. IRDY T17 T19 I/O PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PERR W20 V18 I/O PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register. REQ L20 L14 O PCI bus request. REQ is asserted by the PCI4450 to request access to the PCI bus as an initiator. SERR Y20 W18 O PCI system error. SERR is an output that is pulsed from the PCI4450 when enabled through the command register, indicating a system error has occurred. The PCI4450 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the bridge control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. STOP V19 V19 I/O PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. I/O PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted. TRDY U18 U18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 8. System Interrupt TERMINAL NAME GFN NO. INTA (MFUNC0) W11 INTB (MFUNC1) GJG NO. I/O TYPE FUNCTION I/O Parallel PCI interrupt. INTA can be mapped to MFUNC0 when parallel PCI interrupts are used. See programmable interrupt subsystem for details on interrupt signaling. MFUNC0/INTA defaults to a general-purpose input. I/O Parallel PCI interrupt. INTB can be mapped to MFUNC1 when parallel PCI interrupts are used. See programmable interrupt subsystem for details on interrupt signaling. MFUNC1/INTB defaults to a general-purpose input. W10 Y11 P10 INTC (MFUNC2) Y10 P9 I/O Parallel PCI interrupt. INTC can be mapped to MFUNC2 when parallel PCI interrupts are used. See programmable interrupt subsystem for details on interrupt signaling. MFUNC2/INTC defaults to a general-purpose input. IRQSER W13 P12 I/O Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme. Serialized PCI interrupts can also be sent in the IRQSER stream. See programmable interrupt subsystem for details on interrupt signaling. MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 MFUNC1 MFUNC0 Y4 V5 W9 V10 Y10 Y11 W11 Interrupt request/secondary functions multiplexed. The primary function of these terminals is to provide programmable options supported by the PCI4450. These interrupt multiplexer outputs can be mapped to various functions. See multifunction routing status register for options. R5 W5 T9 R9 P9 P10 W10 O All of these terminals have secondary functions, such as PCI interrupts, PC/PCI DMA, OHCI LEDs, GPE request/grant, ring indicate output, and zoomed video status, that can be selected with the appropriate programming of this register. When the secondary functions are enabled, the respective terminals are not available for multifunction routing. See the multifunction routing status register for programming options. RI_OUT/PME Y13 R11 O Ring indicate out and power management event output. Terminal provides an output to the system for ring-indicate or PME signals. Alternately, RI_OUT can be routed on MFUNC7. Table 9. PC/PCI DMA TERMINAL NAME PCGNT (MFUNC2) PCGNT (MFUNC3) PCREQ (MFUNC7) PCREQ (MFUNC4) PCREQ (MFUNC0) 14 GFN NO. GJG NO. Y10 P9 I/O TYPE I/O FUNCTION PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI DMA scheme. PCGNT, is available on MFUNC2 or MFUNC3. V10 R9 This terminal is also used for the serial EEPROM interface. P20 N19 W9 T9 PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system supporting the PC/PCI DMA scheme. PCREQ is available on MFUNC7, MFUNC4, or MFUNC0. W11 W10 O This terminal is also used for the serial EEPROM interface. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 10. Zoomed Video TERMINAL I/O AND MEMORY INTERFACE SIGNAL I/O TYPE N1 A10 O Horizontal sync to the zoomed video port R2 N2 A11 O Vertical sync to the zoomed video port ZV_Y7 ZV_Y6 ZV_Y5 ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0 V1 U2 T3 U1 T2 R3 P4 T1 R1 P6 P5 P4 P2 N6 N5 N4 A20 A14 A19 A13 A18 A8 A17 A9 O Video data to the zoomed video port in YV:4:2:2 format ZV_UV7 ZV_UV6 ZV_UV5 ZV_UV4 ZV_UV3 ZV_UV2 ZV_UV1 ZV_UV0 Y2 W2 Y1 W1 V3 U3 V2 T4 W2 U2 V1 T2 U1 R4 T1 R2 A25 A12 A24 A15 A23 A16 A22 A21 O Video data to the zoomed video port in YV:4:2:2 format ZV_SCLK W3 V2 A7 O Audio SCLK PCM ZV_MCLK W4 W3 A6 O Audio MCLK PCM ZV_PCLK Y3 V4 IOIS16 O Pixel clock to the zoomed video port ZV_LRCLK V4 V3 INPACK O Audio LRCLK PCM ZV_SDATA U5 W4 SPKR O Audio SDATA PCM NAME GFN NO. GJG NO. ZV_HREF P3 ZV_VSYNC FUNCTION POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 11. Miscellaneous TERMINAL I/O TYPE FUNCTION W10 I/O Multifunction terminal 0. Defaults as a general-purpose input (GPI0), and can be programmed to perform various functions. Refer to multifunction routing register description. Y11 P10 I/O Multifunction terminal 1. Defaults as a general-purpose input (GPI1), and can be programmed to perform various functions. Refer to multifunction routing register description. MFUNC2 Y10 P9 I/O Multifunction terminal 2. Defaults as a general-purpose input (GPI2), and can be programmed to perform various functions. Refer to multifunction routing register description. MFUNC3 V10 R9 I/O Multifunction terminal 3. Defaults as a general-purpose input (GPI3), and can be programmed to perform various functions. Refer to multifunction routing register description. MFUNC4 W9 T9 I/O Multifunction terminal 4. Defaults as a high–impedance reserved input, and can be programmed to perform various functions. Refer to multifunction routing register description. MFUNC5 V5 W5 I/O Multifunction terminal 5. Defaults as a high–impedance reserved input, and can be programmed to perform various functions. Refer to multifunction routing register description. MFUNC6 Y4 R5 I/O Multifunction terminal 6. Defaults as a high–impedance reserved input, and can be programmed to perform various functions. Refer to multifunction routing register description. IDSEL/MFUNC7 P20 N19 I/O IDSEL and multifunction terminal 7. Defaults as IDSEL, but may be used as a multifunction terminal. Refer to multifunction routing register description and Section 3.4 for details. SCL W10 V9 I/O Serial ROM clock. This terminal provides the SCL serial clock signaling in a two–wire serial ROM implementation, and is sensed at reset for serial ROM detection. SDA Y9 W9 I/O Serial ROM data. This terminal provides the SDA serial data signaling in a two–wire serial ROM implementation. SPKROUT V11 T10 O Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI4450 from the PC Card interface. SPKROUT is driven as the XOR combination of card SPKR//CAUDIO inputs. SUSPEND U11 R10 I Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See suspend mode for details. 16 NAME GFN NO. GJG NO. MFUNC0 W11 MFUNC1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 12. 16-bit PC Card Address and Data (slots A and B) TERMINAL GFN NO. GJG NO. I/O TYPE FUNCTION NAME SLOT A† SLOT B‡ SLOT A† SLOT B‡ A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 G2 F1 G4 E2 D1 E4 D2 B1 A2 E3 E1 D3 C2 F2 C4 C5 B2 C3 G3 H3 H1 J4 J2 K2 K3 K1 A16 C16 A18 C17 B18 A20 C18 C19 E17 B17 D16 B19 B20 A17 E18 E20 C20 D18 B16 D14 A15 C14 A14 A13 D12 C12 G4 G5 F2 F5 E5 D2 C2 B2 B3 E2 F4 D1 B1 G6 A4 F6 D4 A2 G2 H1 H4 H5 J1 J5 J6 K6 E14 A15 D15 B17 A18 B19 D16 D18 E16 A17 B16 C18 C19 E15 F15 G15 E18 D19 B15 B14 E13 B13 D13 D12 E12 D11 O PC Card address. 16-bit PC Card address lines. A25 is the most significant bit. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C6 A5 C7 B7 C8 R1 P1 N2 D7 B6 A6 A7 B8 P2 N3 N1 G18 G19 H18 H20 J18 D9 B9 D10 F20 G20 H19 J17 J19 C9 A9 C10 A6 E7 B7 G7 B8 N7 M4 M6 F7 D7 A7 E8 A8 M5 M1 L5 G18 H15 H18 H14 J16 E9 B9 F9 G13 H16 H19 J15 J18 D9 A9 E10 I/O PC Card data. 16-bit PC Card data lines. D15 is the most significant bit. † Terminal name for slot A is preceded with A_. For example, the full name for terminal G2 is A_A25. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal A16 is B_A25. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 13. 16-bit PC Card Interface Control (slots A and B) TERMINAL GFN NO. NAME BVD1 (STSCHG/RI) SLOT A† M2 SLOT B‡ A11 GJG NO. SLOT A† L1 SLOT B‡ A10 I/O TYPE FUNCTION I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 and BVD2 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register for the enable bits. See ExCA card status-change register and the ExCA interface status register for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. BVD2 (SPKR) M1 C11 L6 F10 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 and BVD1 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register for enable bits. See ExCA card status-change register and the ExCA interface status register for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI4450 and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. CD1 CD2 A8 M4 J20 B10 F8 L4 J19 D10 I PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see ExCA interface status register. CE1 CE2 A4 B4 F19 G17 D6 A5 G16 G14 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation. O I/O read. IORD is asserted by the PCI4450 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI4450 asserts IORD during DMA transfers from the PC Card to host memory. INPACK IORD J3 D5 B14 D20 J4 D5 A13 F16 I/O write. IOWR is driven low by the PCI4450 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. IOWR 18 B3 D19 B4 F14 O DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI4450 asserts IOWR during transfers from host memory to the PC Card. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 13. 16-bit PC Card Interface Control (slots A and B) (continued) TERMINAL GFN NO. NAME SLOT A† SLOT B‡ GJG NO. SLOT A† SLOT B‡ I/O TYPE FUNCTION Output enable. OE is driven low by the PCI4450 to enable 16-bit memory PC Card data output during host memory read cycles. OE READY (IREQ) A3 L2 F18 A12 B5 K2 F19 E11 O I DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI4450 asserts OE to indicate TC for a DMA write operation. Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I /O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG J1 C13 J2 A12 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI4450 asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET H2 B15 H2 F13 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. WAIT L3 B11 K4 F11 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. WE C1 A19 E4 B18 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI4450 asserts WE to indicate TC for a DMA read operation. Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. WP (IOIS16) M3 A10 L2 B10 I I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation. VS1 VS2 L1 G1 B12 C15 K1 H6 B11 A14 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the 16-bit PC Card. † Terminal name for slot A is preceded with A_. For example, the full name for terminal C1 is A_WE. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_WE. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 14. CardBus PC Card Interface System (slots A and B) TERMINAL GFN NO. NAME CCLK CCLKRUN CRST SLOT A† E3 M3 H2 SLOT B‡ B17 A10 B15 GJG NO. SLOT A† E2 L2 H2 SLOT B‡ A17 B10 F13 I/O TYPE FUNCTION O CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, and CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. O CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI4450 to indicate that the CCLK frequency is decreased. CardBus clock run (CCLKRUN) follows the PCI clock run (CLKRUN). I/O CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be placed in a high-impedance state, and the PCI4450 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. † Terminal name for slot A is preceded with A_. For example, the full name for terminal E3 is A_CCLK. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal B17 is B_CCLK. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 15. CardBus PC Card Address and Data (slots A and B) TERMINAL GFN NO. GJG NO. NAME SLOT A† SLOT B‡ SLOT A† SLOT B‡ CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 R1 P1 N3 N2 N1 K1 K3 K2 J2 J4 H1 H3 G2 G3 F1 A2 B3 B2 D5 C4 A3 B4 C5 C6 D7 C7 B6 B7 A6 C8 A7 B8 D9 B9 A9 D10 C10 C12 D12 A13 A14 C14 A15 D14 A16 B16 C16 E17 D19 C20 D20 E18 F18 G17 E20 G18 F20 H18 G20 H20 H19 J18 J17 J19 N7 M4 M1 M6 L5 K6 J6 J5 J1 H5 H4 H1 G4 G2 G5 B3 B4 D4 D5 A4 B5 A5 F6 A6 F7 B7 D7 G7 A7 B8 E8 A8 E9 B9 A9 F9 E10 D11 E12 D12 D13 B13 E13 B14 E14 B15 A15 E16 F14 E18 F16 F15 F19 G14 G15 G18 G13 H18 H16 H14 H19 J16 J15 J18 CC/BE3 CC/BE2 CC/BE1 CC/BE0 CPAR J1 F2 C3 A4 C2 C13 A17 D18 F19 B20 J2 G6 A2 D6 B1 A12 E15 D19 G16 C19 I/O TYPE FUNCTION I/O PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most significant bit. I/O CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24). I/O CardBus parity. In all CardBus read and write cycles, the PCI4450 calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI4450 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion. † Terminal name for slot A is preceded with A_. For example, the full name for terminal C2 is A_CPAR. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal B20 is B_CPAR. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 16. CardBus PC Card Interface Control (slots A and B) TERMINAL GFN NO. GJG NO. I/O TYPE FUNCTION F10 I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI4450 supports the binary audio mode and outputs a binary signal from the card to SPKROUT. C2 D16 I/O J20 B10 F8 L4 J19 D10 I CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with ithCVS1 CVS1 and CVS2 to identif identify card insertion and interrogate cards to determine the operating voltage and card type. D1 B18 E5 A18 I/O CardBus device select. The PCI4450 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI4450 monitors CDEVSEL until a target responds. If no target responds before timeout occurs, then the PCI4450 terminates the cycle with an initiator abort. CFRAME G4 A18 F2 D15 I/O CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. CGNT C1 A19 E4 B18 I CardBus bus grant. CGNT is driven by the PCI4450 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CINT L2 A12 K2 E11 I CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. NAME SLOT A† SLOT B‡ SLOT A† SLOT B‡ CAUDIO M1 C11 L6 CBLOCK D2 C18 CCD1 CCD2 A8 M4 CDEVSEL CardBus lock. CBLOCK is used to gain exclusive access to a target. CIRDY E1 D16 F4 B16 I/O CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. CPERR D3 B19 D1 C18 I/O CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CREQ J3 B14 J4 A13 I CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CSERR L3 B11 K4 F11 I CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI4450 can report CSERR to the system by assertion of SERR on the PCI interface. CSTOP E4 A20 D2 B19 I/O CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CSTSCHG M2 A11 L1 A10 I CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status and is used as a wake-up mechanism. CTRDY E2 C17 F5 B17 I/O CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. CVS1 CVS2 L1 G1 B12 C15 K1 H6 B11 A14 I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type. † Terminal name for slot A is preceded with A_. For example, the full name for terminal M1 is A_CAUDIO. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminal C11 is B_CAUDIO. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 terminal functions (continued) Table 17. IEEE1394 PHY/Link Interface Terminals TERMINAL I/O TYPE FUNCTION I/O Phy–link interface control. These bi-direction signals control passage of information between the PHY and link. The link can only drive these terminals after the PHY has granted permission following a link request (LREQ). R8 T8 V8 W8 P8 W7 V7 R7 I/O Phy–link interface data. These bi-directional signals pass data between the PHY and link. These terminals are driven by the link on transmissions and are driven by the PHY on receptions. Only DATA1–DATA0 are valid for 100 Mbit speed. DATA4–DATA0 are valid for 200 Mbit speed and DATA7–DATA0 are valid for 400 Mbit speed. V6 T6 I System clock. This input in ut provides rovides a 49.152 MHz clock signal for data synchronization. PHY_LREQ Y5 R6 O Link request. This signal is driven by the link to initiate a request for the PHY to perform some service. LINKON Y6 P7 I 1394 link on. This input from the PHY indicates that the link should turn on. LPS W5 V5 O Link power status. LPS indicates that link is powered and fully functional. NAME GFN NO. GJG NO. PHY_CTL1 PHY_CTL0 W6 U7 V6 W6 PHY_DATA7 PHY_DATA6 PHY_DATA5 PHY_DATA4 PHY_DATA3 PHY_DATA2 PHY_DATA1 PHY_DATA0 V9 U9 Y8 W8 V8 Y7 W7 V7 PHY CLK PHY_CLK I/O characteristics Figure 3 shows a 3-state bidirectional buffer illustration for reference. The table, recommended operating conditions provides the electrical characteristics of the inputs and outputs. The PCI4450 meets the ac specifications of the PC Card 95 Standard and the PCI Bus 2.1 specifications. VCCP Tied for Open Drain OE Pad Figure 3. 3-State Bidirectional Buffer clamping voltages The I/O sites can be pulled through a clamping diode to a voltage rail for protection. The 3.3-V core power supply is independent of the clamping voltages. The clamping (protection) diodes are required if the signaling environment on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5.0 Vdc, and the PCI4450 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V buffer with a clamping diode to VCCP. If a system design requires a 5.0-V PCI bus, then the VCCP would be connected to the 5.0-V power supply. A standard die has only one clamping voltage for the sites as shown in Figure 3. After the terminal assignments are fixed, the fabrication facility will support a design by splitting the clamping voltage for customization. The PCI4450 requires five separate clamping voltages since it supports a wide range of features. The five voltages are listed and defined in the table, recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI interface This section describes the PCI interface of the PCI4450, and how the device responds to and participates in PCI bus cycles. The PCI4450 provides all required signals for PCI master/slave devices and may operate in either 5-V or 3.3-V PCI signaling environments by connecting the VCCP terminals to the desired signaling level. PCI bus lock (LOCK) The bus locking protocol defined in the PCI Specification is not highly recommended, but is provided on the PCI4450 as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the terminal function defaults to a general-purpose input (GPI). The use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor). PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions may proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. To avoid confusion with the PCI bus clock, the CardBus signal for this protocol is CBLOCK. An agent may need to do an exclusive operation because a critical memory access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive, real-time data transfer, such as video. The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. The PCI4450 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access as the target until it completes a delayed read. This target characteristic is prohibited by the 2.1 PCI Specification, and the issue is resolved by the PCI master using LOCK. loading the subsystem identification (EEPROM interface) The subsystem vendor ID register and subsystem ID register make up a double word of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register, used for system and option card (mobile dock) identification purposes, is required by some operating systems. Implementation of this unique identifier register is a PC ‘97 requirement. The PCI4450 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but the access mode may be made read/write by clearing the SUBSYSRW bit in the system control register (bit 5 of the system control register, offset 80h). Once this bit is cleared (0), the BIOS may write a subsystem identification value into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of implementing the serial EEPROM. In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier through a serial EEPROM interface. The PCI4450 loads the double-word of data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PRST and G_RST from the entire PCI4450 core, including the serial EEPROM state machine. Refer to suspend mode for details on using SUSPEND. The PCI4450 provides a two-line serial bus interface to the serial EEPROM. The system designer must implement a pulldown resistor on the PCI4450 LATCH terminal to indicate the serial EEPROM mode. Only when this pulldown resistor is present will the PCI4450 attempt to load data through the serial EEPROM interface. The serial EEPROM interface is a two-pin interface with one data signal (SDA) and one clock signal (SCL). Figure 4 illustrates a typical PCI4450 application using the serial EEPROM interface. VCC Serial EEPROM Latch A0 A1 SCL SCL A2 SDA SDA PCI4450 Figure 4. Serial EEPROM Application As stated above, when the PCI4450 is reset by G_RST, the subsystem data is read automatically from the EEPROM. The PCI4450 masters the serial EEPROM bus and reads four bytes as described in Figure 5. Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 R/W# Data Byte 0 M S/P – Start/Stop Condition A S b6 b5 b4 b3 b2 b1 b0 Restart Data Byte 1 M Data Byte 2 A – Slave Acknowledgment M Data Byte 3 1 A R/W# M P M – Master Acknowledgment Figure 5. EEPROM Interface Subsystem Data Collection The EEPROM is addressed at slave address A0h (1010 0000b), as indicated in Figure 5, and the EEPROM word address auto-increments after each byte transfers according to the protocol. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this slave address. Thus, to provide the subsystem register with data AABBCCDDh the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh. The serial EEPROM chip in the sample application circuit, Figure 4, assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. The serial EEPROM interface signals require pullup resistors. The serial EEPROM protocol allows bidirectional transfers. Both the SCL and SDA signals are placed in a high-impedance state and pulled high when the bus is not active. A high-to-low transition of the SDA line defines a start condition (S). A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. Data is valid and stable during the clock high period. Figure 6 illustrates this protocol. SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data Valid Figure 6. Serial EEPROM Start/Stop Conditions and BIt Transfers Each address byte and data transfer is followed by an acknowledge bit, as indicated in Figure 5. When the PCI4450 transmits the addresses, it returns the SDA signal to the high state and places the line in a high-impedance state. The PCI4450 then generates an SCL clock cycle and expects the EEPROM to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a slave acknowledge with the PCI4450 transmitter and the EEPROM receiver. Figure 7 illustrates general acknowledges. During the data byte transfers from the serial EEPROM to the PCI4450, the EEPROM clocks the SCL signal. After the EEPROM transmits the data to the PCI4450, it returns the SDA signal to the high state and places the line in a high-impedance state. The EEPROM then generates an SCL clock cycle and expects the PCI4450 to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM transmitter and the PCI4450 receiver. Figure 7 illustrates general acknowledges. SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 7. Serial EEPROM Protocol – Acknowledge EEPROM interface status information is communicated through the general status register located at PCI offset 85h. The EEDETECT bit in this register indicates whether or not the PCI4450 serial EEPROM circuitry detects the pulldown resistor on LATCH. An error condition, such as a missing acknowledge, results in the DATAERR bit being set. The EEBUSY bit is set while the subsystem ID register is loading (serial EEPROM interface is busy). 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 serial ROM implementation A serial ROM interface exists in both the Open HCI function and the PC Card controller functions. The PCI4450 implementation adds a busy indication between the interfaces to allow the function 2 loading to follow the functions 0 and 1 load. All serial ROM addressing uses slave address 8’hA0. The functions 0 and 1 serial EEPROM state machine is modified to provide a busy indication to function 2 and to start loading registers at word address 8’h20 to allow for some serial ROM format flexibility in function 2. Primarily, the serial ROM is used to preload the PCI4450 registers with data, and only write accessible bits in these registers may be preloaded. Figure 8 illustrates the PCI4450 serial ROM data format, which is an expanded version of both the OHCI-Lynx and PCI1450 serial ROM formats. Slave Address 8’b10100000 Flag byte Word address 32 (20h) SubSys byte 3 Word address 33 Word address 0 SubSys byte 2 Word address 34 SubSys byte 0 Word address 1 SubSys byte 1 Word address 35 SubSys byte 1 Word address 2 SubSys byte 0 Word address 36 SubSys byte 2 Word address 3 SysCtrl byte 0 Word address 37 SubSys byte 3 Word address 4 SysCtrl byte 1 Word address 38 Link_Enh byte 0 Word address 5 SysCtrl byte 2 Word address 39 MiniROM_Addr Word address 6 SysCtrl byte 3 Word address 40 GUIDHi byte 0 MaxLat / MinGnt Word address 7 General control Word address 41 GUIDHi byte 1 Word address 8 GP event enable Word address 42 GUIDHi byte 2 Word address 9 GP output Word address 43 GUIDHi byte 3 Word address 10 MF route byte 0 Word address 44 GUIDLo byte 0 Word address 11 MF route byte 1 Word address 45 GUIDLo byte 1 Word address 12 MF route byte 2 Word address 46 GUIDLo byte 2 Word address 13 MF route byte 3 Word address 47 GUIDLo byte 3 Word address 14 Card Control Word address 48 CheckSum Word address 15 Device control Word address 49 Link_Enh byte 1 Word address 16 Diagnostic Word address 50 PCI misc byte 0 Word address 17 PMC byte 1 Word address 51 PCI misc byte 1 Word address 18 ExCA ID and rev Word address 52 ... AVAIL RSVD Figure 8. Serial ROM Data Format The flag byte at word address 32 indicates to the PCI4450 whether or not the PC Card controller functions loads the data from word address range 33–52. A flag byte set to 8’hFF indicates to stop loading the serial ROM data for functions 0 and 1, but is independent of the function 2 1394 Open HCI controller load from word address range 0–18. An additional change in the serial ROM behavior with respect to Open HCI GUIDROM register access is the MiniROM_Addr. The MiniROM_Addr field in the ROM data is loaded from byte location 6 (EEPROM word address 6) and indicates to function 2 where to begin accessing the serial ROM via the GUID ROM register. The GUIDROM.addrReset bit function changes slightly to reset serial ROM access to the byte location indicated by MiniROM_Addr. A MiniROM_Addr value of zero provides identical operation as the OHCI-Lynx. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PC Card applications overview This section describes the PC Card interfaces of the PCI4450. A discussion on PC Card recognition details the card interrogation procedure. This section discusses the card powering procedure, including the protocol of the P2C power switch interface. The internal ZV buffering provided by the PCI4450 and programming model is detailed in this section. Also, standard PC Card register models are described, as well as a brief discussion of the PC Card software protocol layers. PC Card insertion/removal and recognition The 1995 PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface (16-bit vs. CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four pins in a certain configuration depending on the type of card and the supply voltage. The encoding scheme for this, defined in the 1997 PC Card Standard, is shown in Table 18. Table 18. PC Card – Card Detect and Voltage Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface Voltage Ground Ground Open Open 5V 16-bit PC Card 5V Ground Ground Open Ground 5V 16-bit PC Card 5 V and 3.3 V 16-bit PC Card 5 V, 3.3 V, and X.X V Ground Ground Ground Ground 5V Ground Ground Ground Connect to CVS1 Open Ground LV 16-bit PC Card 3.3 V Open Connect to CCD1 LV CardBus PC Card 3.3 V Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V Y.Y V Ground Ground Ground Open LV 16-bit PC Card Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V LV CardBus PC Card Y.Y V Connect to CVS1 Ground Open Connect to CCD2 Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved P2C power switch interface (TPS2202A/2206) A power switch with a PCMCIA-to-peripheral control (P2C) interface is required for the PC Card powering interface. The TI TPS2206 (or TPS2202A) Dual-Slot PC Card Power-Interface Switch provides the P2C interface to the CLOCK, DATA, and LATCH terminals of the PCI4450. Figure 9 shows the terminal assignments of the TPS2206. Figure 10 illustrates a typical application where the PCI4450 represents the PCMCIA controller. There are two ways to provide a clock source to the power switch interface. The first method is to provide an external clock source such as a 32 kHz real time clock to the CLOCK terminal. The second method is to use the internal ring oscillator. If the internal ring oscillator is used, then the PCI4450 provides its own clock source for the PC Card interrogation logic and the power switch interface. The mode of operation is determined by the setting of bit 27 of the system control register (PCI offset 80h). This bit is encoded as follows: 0 = CLOCK terminal (terminal U12) is an input (default). 1 = CLOCK terminal is an output that utilizes the internal oscillator. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 A 43 kW pulldown resistor should be tied to the CLOCK pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 5V 5V DATA CLOCK LATCH RESET 12V AVPP AVCC AVCC AVCC GND NC RESET 3.3V 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5V NC NC NC NC NC 12V BVPP BVCC BVCC BVCC NC OC 3.3V 3.3V NC – No internal connection Figure 9. TPS2206 Terminal Assignments Power Supply PC Card A TPS2206 12 V 12 V 5V 5V 3.3 V 3.3 V AVPP VPP1 VPP2 AVCC AVCC VCC VCC AVCC Supervisor RESET PC Card B BVPP VPP1 VPP2 BVCC PCI4450 3 Serial I/F BVCC VCC VCC BVCC PC Card Interface (68 pins/socket) Figure 10. TPS2206 Typical Application zoomed video support The zoomed video (ZV) port on the PCI4450 provides an internally buffered 16-bit ZV PC Card data path. This internal routing is programmed through the multimedia control register. Figure 10 summarizes the zoomed video subsystem implemented in the PCI4450, and details the bit functions found in the multimedia control register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 An output port (PORTSEL) is always selected. The PCI4450 defaults to socket 0 (see the multimedia control register). When ZVOUTEN is enabled, the zoomed video output terminals are enabled and allow the PCI4450 to route the zoomed video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is enabled in the multimedia control register. If the PORTSEL maps to a card port that is disabled (ZVEN =0 or ZVEN1 = 0), then the zoomed video port is driven low (i.e., no data is transmitted). Zoomed Video Subsystem Card Output Enable Logic ZVEN0 ZVOUTEN PC Card Socket 0 PC Card I/F ZVSTAT† 23 VGA 19 Video Signals PORTSEL PC Card Socket 1 PC Card I/F 4 Audio Signals Audio Codec ZVEN1 Card Output Enable Logic † ZVSTAT must be enabled through the GPIO Control Register. Figure 11. Zoomed Video Subsystem zoomed video auto detect Zoomed video auto detect, when enabled, allows the PCI4450 to automatically detect zoomed video data by sensing the pixel clock from each socket and/or from a third zoomed video source that may exist on the motherboard. The PCI4450 automatically switches the internal zoomed video MUX to route the zoomed video stream to the PCI4450’s zoomed video output port. This eliminates the need for software to switch the internal MUX using the multimedia control register (PCI offset 84h, bits 6 and 7). The PCI4450 can be programmed to switch a third zoomed video source by programming MFUNC2 or MFUNC3 as a zoomed video pixel clock sense pin and connecting this pin to the pixel clock of the third zoomed video source. ZVSTAT may then be programmed onto MFUNC4, MFUNC1, or MFUNC0 and this signal may switch the zoomed video buffers from the third zoomed video source. To account for the possibility of several zoomed video sources being enabled at the same time, a programmable priority scheme may be enabled. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Zoomed Video Subsystem Card Output Enable Logic 3rd Zoomed Video Source ZVEN0 Pixel Clock Sense Programmed on MFUNC2 or MFUNC3 PC Card I/F PC Card Socket 0 23 Buffers 23 Enable ZVSTAT Pixel Clock Sense 23 23 Auto Z/V Arbiter and Buffer 23 VGA 19 Video Signals ZV Data 23 Pixel Clock Sense 23 PC Card Socket 1 PC Card I/F 4 Audio Signals Audio Codec ZVEN1 Card Output Enable Logic Figure 12. Zoomed Video with Auto Detect Enabled The PCI4450 defaults with zoomed video auto-detect disabled so that it will function exactly like the PCI1250A and PCI1450. To enable zoomed video auto-detect and the programmable priority scheme, the following bits must be set: D Multimedia control register (PCI offset 84h) bit 5: Writing a 1b enables zoomed video auto-detect D Multimedia control register (PCI offset 84h) bits 4–2: Set the programmable priority scheme 000 = Slot A, Slot B, External Source 001 = Slot A, External Source, Slot B 010 = Slot B, Slot A, External Source 011 = Slot B, External Source, Slot A 100 = External Source, Slot A, Slot B 101 = External Source, Slot B, Slot A 110 = External Source, Slot B, Slot A 111 = Reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 If it is desired to switch a third zoomed video source, then the following bits must also be set: D MFUNC routing register (PCI offset 8Ch), bits 14–12 or 10–8: Write 111b to program MFUNC3 or MFUNC2 as a pixel clock input pin. D MFUNC routing register (PCI ofset 8Ch), bits 18–16, 6–4, or 2–0: Write 111b to program MFUNC4, MFUNC1, or MFUNC0 pin. ultra zoomed video Ultra zoomed video is an enhancement to the PCI4450’s DMA engine and is intended to improve the 16-bit bandwidth for MPEG I and MPEG II decoder PC Cards. This enhancement allows the 4450 to fetch 32 bits of data from memory versus the 11XX/12XX 16-bit fetch capability. This enhancement allows a higher sustained throughput to the 16-bit PC Card, because the 4450 prefetches an extra 16 bits (32 bits total) during each PCI read transaction. If the PCI Bus becomes busy, then the 4450 has an extra 16 bits of data to perform back-to-back 16-bit transactions to the PC Card before having to fetch more data. This feature is built into the DMA engine and software is not required to enable this enhancement. NOTE:The 11XX and 12XX series CardBus controllers have enough 16-bit bandwidth to support MPEG II PC Card decoders. But it was decided to improve the bandwidth even more in the 14XX series CardBus controllers. D3_STAT pin Additional functionality added for the 4450 versus the 1250A/1251 series is the D3_STAT (D3 status) pin. This pin is asserted under the following two conditions (both conditions must be true before D3_STAT is asserted): D Function 0 and Function 1 are placed in D3 D PME is enabled on either function The intent of including this feature in the PCI4450 is to use this pin to switch an external VCC/VAUX switch. This feature can be programmed on MFUNC7, MFUNC6, MFUNC2, or MFUNC1 by writing 100b to the appropriate multifunction routing status register bits (PCI offset 8Ch). internal ring oscillator The internal ring oscillator provides an internal clock source for the PCI4450 so that neither the PCI clock nor an external clock is required in order for the PCI4450 to power down a socket or interrogate a PC Card. This internal oscillator operates nominally at 16 kHz and can be enabled by setting bit 27 of the system control register (PCI offset 80h) to a 1b. This function is disabled by default. SPKROUT usage The SPKROUT signal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 pin becomes SPKR. This terminal, also used in CardBus applications, is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI4450. The CardBus CAUDIO signal also can pass a single amplitude, binary waveform. The binary audio signals from the two PC Card sockets are XOR’ed in the PCI4450 to produce SPKROUT. Figure 13 illustrates the SPKROUT connection. Bit 1, Card Control Register (offset 91h) Card A SPKROUT Enable Card A SPKR SPKROUT Bit 1, Card Control Register (offset 91h) Card B SPKROUT Enable Card B SPKR Card A SPKROUT Enable Card B SPKROUT Enable Figure 13. SPKROUT Connection to Speaker Driver 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Speaker Driver PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 The SPKROUT signal is typically driven only by PC modem cards. To verify the SPKROUT on the PCI4450, a sample circuit was constructed, and this simplified schematic is provided below. The PCI1130/1131 required a pullup resistor on the SUSPEND/SPKROUT terminal. Since the PCI4450 does not multiplex any other function on SPKROUT, this terminal does not require a pullup resistor. VCC VCC SPKROUT 3 7 2 6 + – 1 Speaker 8 4 LM386 Figure 14. Simplified Test Schematic LED socket activity indicators The socket activity LEDs indicate when an access is occurring to a PC Card. The LED signals are programmable via the MFUNC register. When configured for LED outputs, these terminals output an active high signal to indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity. The active-high LED signal is driven for 64 ms durations. When the LED is not being driven high, then it is driven to a low state. Either of the two circuits illustrated in Figure 15 can be implemented to provide the LED signaling, and it is left for the board designer to implement the circuit to best fit the application. Current Limiting R ≈ 500 Ω PCI4450 LED ApplicationSpecific Delay Current Limiting R ≈ 500 Ω PCI4450 LED Figure 15. Two Sample LED Circuits As indicated, the LED signals are driven for 64 ms, and this is accomplished by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when either the SUSPEND signal is asserted or when the PCI clock is to be stopped per the CLKRUN protocol. Furthermore, if any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signals will remain driven. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PC Card 16 DMA support The PCI4450 supports both PC/PCI (centralized) DMA and a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. Table 19 provides the DDMA register configuration. Table 19. Distributed DMA Registers TYPE R W Current address Reserved Page Reserved Reserved 00h Base address R W DMA BASE ADDRESS OFFSET REGISTER NAME Current count R N/A W Mode R Multichannel W Mask 04h Base count Reserved N/A Status Request Command N/A Reserved Master Clear 08h 0Ch Reserved CardBus socket register The PCI4450 contains all registers for compatibility with the latest PCI to PCMCIA CardBus Bridge Specification. These registers exist as the CardBus socket registers, and are listed in Table 20. Table 20. CardBus Socket Registers 34 REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket power management 20h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 programmable interrupt subsystem Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI4450. The PCI4450 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based upon various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI4450 is therefore backward compatible with existing interrupt control register definitions, and new registers have been defined where required. The PCI4450 detects PC Card interrupts and events at the PC Card interface and notifies the host controller via one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI4450, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts. The method by which any type of PCI4450 interrupt is communicated to the host interrupt controller varies from system to system. The PCI4450 offers system designers the choice of using parallel PCI interrupt signaling or the serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with serialized IRQs via the multifunction routing register at offset 8Ch. PC Card functional and card status change interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service. They are indicated by asserting specially defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. Card status change (CSC) type interrupts, defined as events at the PC Card interface which are detected by the PCI4450, may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals. Table 21 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent upon the type of card inserted in the PC Card socket. The three types of cards that may be inserted into any PC Card socket are: 16-bit memory card, 16-bit I/O card, and CardBus cards. Functional interrupt events are valid only for 16-bit I/O and CardBus cards, that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal type CSC interrupts are independent of the card type. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 21. PC Card Interrupt Events and Description Card Type Event Type Signal Description CSC BVD1 (STSCHG) // CSTSCHG A transition on the BVD1 signal indicates a change in the PC Card battery conditions. CSC BVD2 (SPKR) // CAUDIO A transition on the BVD2 signal indicates a change in the PC Card battery conditions. Wait states (READY) CSC READY (IREQ) // CINT A transition on the READY signal indicates a change in the ability of the memory PC Card to accept or provide data. Change in card status (STSCHG) CSC BVD1 (STSCHG) // CSTSCHG Interrupt request (IREQ) Functional READY (IREQ) // CINT The assertion of the IREQ signal indicates an interrupt request from the PC Card. Change in card status (CSTSCHG) CSC BVD1 (STSCHG) // CSTSCHG The assertion of the CSTSCHG signal indicates a status change on the PC Card. Interrupt request (CINT) Functional READY (IREQ) // CINT The assertion of the CINT signal indicates an interrupt request from the PC Card. Power cycle complete CSC N/A An interrupt is generated when a PC Card power-up cycle has completed. Card insertion or removal CSC CD1 // CCD1, CD2 // CCD2 A transition on either the CD1//CCD1 signal or the CD2//CCD2 signal indicates an insertion or removal of a 16-bit // CardBus PC Card. Power cycle complete CSC N/A An interrupt is generated when a PC Card power-up cycle has completed. Battery conditions (BVD1, BVD2) 16-bit Memory y 16 bit I/O 16-bit CardBus All PC Cards The assertion of the STSCHG signal indicates a status change on the PC Card. The signal naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well as CardBus. For example, the READY(IREQ)//CINT signal includes the READY signal for 16-bit memory cards, the IREQ signal for 16-bit I/O cards, and the CINT signal for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second enclosed in parentheses. The CardBus signal name follows after a forward double slash (//). The PC Card standard describes the power-up sequence that must be followed by the PCI4450 when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI4450 interrupt scheme may be used to notify the host system, as in indicated in Table 21, denoted by the power cycle complete event. This interrupt source is considered a PCI4450 internal event because it does not depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket. interrupt masks and flags Host software may individually mask, or disable, most of the potential interrupt sources listed in Table 22 by setting the appropriate bits in the PCI4450. By individually masking the interrupt sources listed in these tables, software can control which events will cause a PCI4450 interrupt. Host software has some control over which system interrupt the PCI4450 will assert by programming the appropriate routing registers. The PCI4450 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing is somewhat specific to the interrupt signaling method used. This will be discussed in more detail in the following sections. When an interrupt is signaled by the PCI4450, the interrupt service routine must be able to discern which of the events in Table 22 caused the interrupt. Internal registers in the PCI4450 provide flags which report which of the interrupt sources was the cause of an interrupt. By reading these status bits, the interrupt service routine can determine which action is to be taken. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 22 details the registers and bits associated with masking and reporting potential interrupts. All interrupts may be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts. Table 22. PCI4450 Interrupt Masks and Flags Registers Card Type 16 bit Memory 16-bit Memor 16 bit I/O 16-bit All 16-bit PC Cards CardBus Event Mask Flag Battery conditions (BVD1 BVD2) (BVD1, ExCA Offset Offset05h/45h/805h 05h/45h/805h Bit 1 & 0 Bits ExCA Offset Offset04h/44h/804h 04h/44h/804h Bits Bit 1 & 0 Wait states (READY) ExCA Offset 05h/45h/805h Bit 2 ExCA Offset 04h/44h/804h Bit 2 Change in card status (STSCHG) ExCA Offset 05h/45h/805h Bit 0 ExCA Offset 04h/44h/804h Bit 0 Interrupt request (IREQ) Always enabled PCI Configuration Offset 91h Bit 0 Power cycle complete ExCA Offset 05h/45h/805h Bit 3 ExCA Offset 04h/44h/804h Bit 3 Change in card status (CSTSCHG) Socket mask register Bit 0 Socket event register Bit 0 Interrupt request (CINT) Always enabled PCI Configuration Offset 91h Bit 0 Power cycle complete Socket mask register Bit 3 Socket event register Bit 3 Card insertion or removal Socket mask register Bits 2 & 1 Socket event register Bits 2 & 1 There is no mask bit to stop the PCI4450 from passing PC Card functional interrupts through to the appropriate interrupt scheme. Functional interrupts should not be fired until the PC Card is initialized and powered. There are various methods of clearing the interrupt flag bits listed in Table 22. The flag bits in the ExCA registers (16-bit PC Card related interrupt flags) may be cleared by two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is a reading of the flag bit register. The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the flag cleared on read method. The CardBus related interrupt flags can only be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning. using parallel PCI interrupts Parallel PCI interrupts are available when in pure parallel PCI interrupt mode and are routed on MFUNC0–MFUNC2. The PCI interrupt signaling is dependent upon the interrupt mode and is summarized in Table 23. The interrupt mode is selected in the device control register (92h). Table 23. Interrupt Pin Register Cross Reference INTPIN Function 0 INTPIN Function 1 Parallel PCI interrupts only 0x01 (INTA) 0x02 (INTB) Reserved 0x01 (INTA) 0x02 (INTB) IRQ serialized (IRQSER) & parallel PCI interrupts 0x01 (INTA) 0x01 (INTA) IRQ & PCI serialized (IRQSER) interrupts (default) 0x01 (INTA) 0x02 (INTB) Interrupt Signaling Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 power management overview In addition to the low-power CMOS technology process used for the PCI4450, various features are designed into the device to allow implementation of popular power saving techniques. These features and techniques are discussed in this section. CLKRUN protocol CLKRUN is the primary method of power management on the PCI bus side of the PCI4450. Since some chipsets do not implement CLKRUN, this is not always available to the system designer, and alternate power savings features are provided. If CLKRUN is not implemented, then the CLKRUN pin should be tied low. CLKRUN is enabled by default via bit 1 (KEEPCLK) in the system control register (80h). CardBus PC Card power management The PCI4450 implements its own card power management engine that can turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The CCLK can also be configured as divide by 16 instead of stopped. The CLKRUN protocol is followed on the CardBus interface to control this clock management. PCI bus power management The PCI Bus Power Management Interface Specification (PCIPM) establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software visible power management states, which result in varying levels of power savings. The four power management states of PCI functions are: D0 - Fully On state, D1 and D2 - intermediate states, and D3 - Off state. Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power state of the upstream bridge device. For the operating system to manage the device power states on the PCI bus, the PCI function should support four power management operations. The four operations are: capabilities reporting; power status reporting; setting the power state; and system wake-up. The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1b in bit 4 of the PCI status register (PCI offset 06h). When software determines that the device has a capabilities list by seeing that bit 4 of the PCI status register is set, it will read the capability pointer register at PCI offset 14h. This value in the register points the location in PCI configuration space of the capabilities linked list. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, then the next item pointer should be set to 0. The registers following the next item pointer are specific to the function’s capability. The PCIPM capability implements the following register block: Power Management Register Block Power management capabilities (PMC) Data Next item pointer PMCSR bridge support extensions Capability ID Power management control status (CSR) Offset = 0 Offset = 4 The power management capabilities (PMC) register is a static read-only register that provides information on the capabilities of the function, related to power management. The PMCSR register enables control of power management states and enables/monitors power management events. The data register is an optional register that provides a mechanism for state-dependent power measurements such as power consumed or heat dissipation. 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 CardBus device class power management The PCI Bus Interface Specification for PCI-to-CardBus Bridges was approved by PCMCIA in December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed in the PCI Bus Interface Specification for PCI-to-CardBus Bridges is wake-up from D3hot or D3cold without losing wake-up context (also called PME context). The specific issues addressed by the PCI Bus Interface Specification for PCI-to-CardBus Bridges for D3 wake up are as follows: D Preservation of device context: The PCI Power Management Specification version 1.0 states that PRST D must be asserted when transitioning from D3cold to D0. Some method to preserve wake-up context must be implemented so that PRST does not clear the PME context registers. Power source in D3cold if wake-up support is required from this state. The Texas Instruments PCI4450 addresses these D3 wake-up issues in the following manner: D Preservation of device context: When PRST is asserted, bits required to preserve PME context are not D cleared. To clear all bits in the PCI4450, another reset pin is defined: G_RST (global reset). G_RST is normally only asserted during the initial power-on sequence. After the initial boot, PRST should be asserted so that PME context is retained for D3-to-D0 transitions. Bits cleared by G_RST, but not cleared by PRST (if the PME enable bit is set), are referred to as PME context bits. Please refer to the master list of PME context bits in the next section. Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an auxiliary power source must be switched to the PCI4450 VCC pins. This switch should be a make before break type of switch, so that VCC to the PCI4450 is not interrupted. master list of PME context bits and global reset only bits PME context bit means that the bit is cleared only by the assertion of G_RST when the PME enable bit is set (PCI offset A4h, bit 8). If PME is not enabled, then these bits are cleared when either PRST or G_RST is asserted. Global reset only bits, as the name implies, are only cleared by G_RST. These bits are never cleared by PRST regardless of the setting of the PME enable bit. (PCI offset A4h, bit 8). The G_RST signal is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the G_RST signal internally, thus preserving all register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Global reset only bits: D D D D D D D D D D D D D D D D D Subsystem ID/subsystem vendor ID (PCI offset 40h): bits 31–0 PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31–1 System control register (PCI offset 80h): bits 31–29, 27–24, 22–14, 6–3, 1, 0 Multimedia control register (PCI offset 84h): bits 7–0 General status register (PCI offset 85h): bits 2–0 General-purpose event status register (PCI offset 88h): bits 7, 6, 3–0 General-purpose event enable register (PCI offset 89h): bits 7, 6, 3–0 General-purpose input register (PCI offset 8Ah): bits 3–0 General-purpose output register (PCI offset 8Bh): bits 3–0 MFUNC routing register (PCI offset 8Ch): bits 31–0 Retry status register (PCI offset 90h): bits 7–1 Card control register (PCI offset 91h): bits 7, 6, 2, 1, 0 Device control register (PCI offset 92h): bits 7–0 Diagnostic register (PCI offset 93h): bits 7–0 Socket DMA register 0 (PCI offset 94h): bits 1–0 Socket DMA register 1 (PCI offset 98h): bits 15–0 GPE control/status register (PCI offset A8h): bits 10, 9, 8, 2, 1, 0 PME context bits D D D D D D D D D D 40 Bridge control register (PCI offset 3Eh): bit 6 Power management capabilities register (PCI offset A2h): bit 15 Power management control/status register (PCI offset A4h): bits 15, 8 ExCA power control register (ExCA 802h/842h): bits 7, 4, 3, 1, 0 ExCA interrupt and general control (ExCA 803h/843h): bit 6, 5 ExCA card status change register (ExCA 804h/844h): bits 3–0 ExCA card status change interrupt register (ExCA 805h/845h): bits 3–0 CardBus socket event register (CardBus offset 00h): bits 3–0 CardBus socket mask register (CardBus offset 04h): bits 3–0 CardBus socket control register (CardBus offset 10h): bits 6, 5, 4, 2, 1, 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 system diagram implementing CardBus device class power management PCI Bus Real Time Clock‡ South Bridge PRST G_RST† Clock TPS2206 Power Switch 2 CLKRUN PCI4450 Embedded Controller PME Vcc System Vcc PC Card Socket A 68 D3Status PC Card Socket B Vaux Make before break switch 68 † The system connection to G_RST is implementation specific. G_RST should be applied whenever Vcc is applied to the PCI4450. PRST should be applied for subsequent warm resets. ‡ Not required if internal oscillator is used. Figure 16. System Diagram Implementing CardBus Device Class Power Management suspend mode The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the G_RST (global reset) signal from the PCI4450. Besides gating PRST and G_RST, SUSPEND also gates PCLK inside the PCI4450 in order to minimize power consumption. Gating PCLK does not create any issues with respect to the power switch interface in the PCI4450. This is because the PCI4450 does not depend on the PCI clock to clock the power switch interface. There are two methods to clock the power switch interface in the PCI4450: D Use an external clock to the PCI4450 CLOCK pin D Use the internal oscillator It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt stream, then the PCI clock will have to be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial interrupt state machine. PRST G_RST PCI4450 Core SUSPEND GNT PCLK Figure 17. SUSPEND Functional Illustration POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 requirements for SUSPEND A requirement for implementing suspend mode is that the PCI bus must not be parked on the PCI4450 when SUSPEND is asserted. The PCI4450 responds to SUSPEND being asserted by placing the REQ pin in a high impedance state. The PCI4450 will also gate the internal clock and reset. The GPIOs, MFUNC signals, and RI_OUT signals are all active during SUSPEND, unless they are disabled in the appropriate PCI4450 registers. ring indicate The RI_OUT output is an important feature used in legacy power management. It is used so that a system can go into a suspended mode and wake up on modem rings and other card events. The RI_OUT signal on the PCI4450 may be asserted under any of the following conditions: D A 16-bit PC Card modem in a powered socket asserts RI to indicate an incoming call to the system. D A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up. D A card status change (CSC) event, such as insertion/removal of cards, battery voltage levels, occurs. A CSTSCHG signal from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two RI_OUT events are enabled separately. The following figure details various enable bits for the PCI4450 RI_OUT function; however, it does not illustrate the masking of CSC events. See interrupt masks and flags for a detailed description of CSC interrupt masks and flags. RI_OUT is multiplexed on the same pin with PME. The default is for RI_OUT to be signaled on this pin. In PCI power managed systems, the PME signal should be enabled by setting bit 0 (RI_OUT/PME) in the system control register (80h) and clearing bit 7 (RIENB) in the card control register (91h). RI_OUT Function PC Card Socket 0 Card I/F CSC 16-bit Card Bus RI CBWAKE RIENB RICSC(A) RI_OUT RICSC(B) CSC PC Card Socket 1 Card I/F RI 16-bIt CBWAKE Card Bus Figure 18. RI_OUT Functional Illustration Routing of CSC events to the RI_OUT signal, enabled on a per socket basis, is programmed by the RICSC bit in the card control register. This bit is socket dependent (not shared), as illustrated in Figure 18. 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 The RI signal from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the ExCA interrupt and general control register. This is programmed on a per socket basis, and is only applicable when a 16-bit card is powered in the socket. The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers. PC CARD CONTROLLER PROGRAMMING MODEL This section describes the PCI4450 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI4450 function. As noted below, some bits are global in nature and should be accessed only through function 0. Registers containing one or more global bits are denoted by a “§.” Any bit followed by a “†” is not cleared by the assertion of PRST (refer to CardBus device class power management for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are only cleared by G_RST. If PME is not enabled, then these bits are cleared by G_RST or PRST. These bits are sometimes referred to as PME context bits and are implemented to allow PME context to be preserved when transitioning from D3hot or D3cold to D0. If the PME context PRST functionality is not desired, then the PRST and G_RST signals should be tied together. If a bit is followed by a “‡”, then this bit is only cleared by G_RST in all cases (not conditional on PME being enabled). These bits are intended to maintain device context such as interrupt routing and MFUNC programming during “warm” resets. PCI configuration registers (functions 0 and 1) The PCI4450 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The configuration header, compliant with the PCI Specification as a CardBus bridge header, is PC97/PC98 compliant as well. Table 24 illustrates the PCI configuration header, which includes both the predefined portion of the configuration space and the user definable registers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 24. Functions 0 and 1 PCI Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID Status Command Class code BIST Header type Latency timer 00h 04h Revision ID 08h Cache line size 0Ch CardBus socket registers/ExCA base address Secondary status CardBus latency timer Subordinate bus number 10h Reserved Capability pointer CardBus bus number PCI bus number 1Ch CardBus memory limit register 0 20h CardBus memory base register 1 24h CardBus memory limit register 1 28h CardBus I/O base register 0 2Ch CardBus I/O limit register 0 30h CardBus I/O base register 1 34h Bridge control † 38h Interrupt pin Subsystem ID ‡ Interrupt line Subsystem vendor ID ‡ 3Ch 40h PC Card 16-bit I/F legacy mode base address ‡ 44h Reserved 48h–7Fh System control ‡ 80h Reserved Reserved General status † Multimedia control ‡ GP0 control ‡ GP1 control ‡ GPE enable ‡ GPE status ‡ Multifunction routing † Device control ‡ 84h 88h 8Ch Card control ‡ Retry status ‡ 90h Socket DMA register 0 ‡ 94h Socket DMA register 1 ‡ 98h Reserved Power management capabilities † Data (Reserved) 18h CardBus memory base register 0 CardBus I/O limit register 1 Diagnostic ‡ 14h 9Ch Next pointer item PMCSR bridge support extensions Capability ID A0h Power management control/status † A4h GPE control/status ‡ A8h Reserved † One or more bits in the register are PME context bits and can only be cleared by the assertion of G_RST when PME is enabled. If PME is not enabled, then these bits are cleared by the assertion of PRST or G_RST. ‡ One or more bits in this register are only cleared by the assertion G_RST. 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 vendor ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 1 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 1 0 0 1 1 0 0 Vendor ID Register: Type: Offset: Default: Description: Vendor ID Read-only 00h (Functions 0, 1) 104Ch This 16-bit register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. device ID register Bit 15 14 13 12 11 10 9 8 Type R R R R R R R R Default 1 0 1 0 1 1 0 0 Name 7 6 5 4 3 2 1 0 R R R R R R R R 0 1 0 0 0 0 0 0 Device ID Register: Type: Offset: Default: Description: Device ID Read-only 02h (Functions 0, 1) AC40h This 16-bit register contains a value assigned to the PCI4450 by Texas Instruments. The device identification for the PCI4450 is AC40. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 command register Bit 15 14 13 12 11 10 9 8 Type R R R R R R R R/W Default 0 0 0 0 0 0 0 0 Name 7 6 5 4 3 2 1 0 R R/W R/W R R R/W R/W R/W 0 0 0 0 0 0 0 0 Command Register: Type: Offset: Default: Description: Command Read-only, Read/Write 04h 0000h The command register provides control over the PCI4450 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, see Table 25. None of the bit functions in this register are shared between the two PCI4450 PCI functions. Two command registers exist in the PCI4450, one for each function. Software manipulates the two PCI4450 functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the two functions, and these control bits appear separate per function to software. Table 25. PCI Command Register Description BIT TYPE 15–10 R Reserved. These bits return 0s when read. Writes have no effect. 9 R Fast back-to-back enable. The PCI4450 will not generate fast back-to-back transactions; therefore, this bit is read-only. This bit returns a 0 when read. 8 R/W System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set for the PCI4450 to report address parity errors. 0 = Disables the SERR output driver (default). 1 = Enables the SERR output driver. 7 R Address/data stepping control. The PCI4450 does not support address/data stepping, and this bit is hardwired to 0. Writes to this bit have no effect. 6 R/W Parity error response enable. This bit controls the PCI4450’s response to parity errors through the PERR signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by asserting SERR. 0 = PCI4450 ignores detected parity error (default). 1 = PCI4450 responds to detected parity errors. 5 R/W VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI4450does not respond to palette register writes and snoops the data). When the bit is 0, the PCI4450 will treat all palette accesses like all other accesses. 4 R Memory write and invalidate enable. This bit controls whether a PCI initiator device can generate memory write and invalidate commands. The PCI4450 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns 0 when read. Writes to this bit have no effect. 3 R Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI4450 does not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns 0 when read. Writes to this bit have no effect. 2 R/W Bus master control. This bit controls whether or not the PCI4450 can act as a PCI bus initiator (master). The PCI4450 can take control of the PCI bus only when this bit is set. 0 = Disables the PCI4450’s ability to generate PCI bus accesses (default). 1 = Enables the PCI4450’s ability to generate PCI bus accesses. 1 R/W Memory space enable. This bit controls whether or not the PCI4450 may claim cycles in PCI memory space. 0 = Disables the PCI4450’s response to memory space accesses (default). 1 = Enables the PCI4450’s response to memory space accesses. 0 R/W I/O space control. This bit controls whether or not the PCI4450 may claim cycles in PCI I/O space. 0 = Disables the PCI4450 from responding to I/O space accesses (default). 1 = Enables the PCI4450 to respond to I/O space accesses. 46 FUNCTION POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 status register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R R R/W R R R R R R R R 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Name Type Default Status Register: Type: Offset: Default: Description: Status Read-only, Read/Write 06h (Functions 0, 1) 0210h The status register provides device information to the host system. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown through each function. Table 26. Status Register Description BIT TYPE FUNCTION 15 R/W PAR_ERR. Detected parity error. This bit is set when a parity error is detected, either address or data parity errors. Write a 1 to clear this bit. 14 R/W SYS_ERR. Signaled system error. This bit is set when SERR is enabled and the PCI4450 signaled a system error to the host. Write a 1 to clear this bit. 13 R/W MABORT. Received master abort. This bit is set when a cycle initiated by the PCI4450 on the PCI bus has been terminated by a master abort. Write a 1 to clear this bit. 12 R/W TABT_REC. Received target abort. This bit is set when a cycle initiated by the PCI4450 on the PCI bus was terminated by a target abort. Write a 1 to clear this bit. 11 R/W TABT_SIG. Signaled target abort. This bit is set by the PCI4450 when it terminates a transaction on the PCI bus with a target abort. Write a 1 to clear this bit. 10–9 R PCI_SPEED. DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the PCI4450 asserts this signal at a medium speed on nonconfiguration cycle accesses. DATAPAR. Data parity error detected. Write a 1 to clear this bit. 0 = The conditions for setting this bit have not been met. 1 = A data parity error occurred and the following conditions were met: a. PERR was asserted by any PCI device including the PCI4450. b. The PCI4450 was the bus master during the data parity error. c. The parity error response bit is set in the command register. 8 R/W 7 R FBB_CAP. Fast back-to-back capable. The PCI4450 cannot accept fast back-to-back transactions; thus, this bit is hardwired to 0. 6 R UDF. UDF supported. The PCI4450 does not support the user definable features; therefore, this bit is hardwired to 0. 5 R 66 MHz capable. The PCI4450 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is hardwired to 0. 4 R Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power management capabilities is implemented in this function. 3–0 R Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 class code and revision ID register Bit 31 30 29 28 27 26 Type R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 Bit 15 14 13 12 11 10 9 8 7 Name 25 24 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 1 1 1 6 5 4 3 2 1 0 Class code and revision ID Name Class code and revision ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Class code and revision ID Read-only 08h (Functions 0, 1) 0607 0000h This register recognizes the PCI4450 functions 0 and 1 as a bridge device (06h) and CardBus bridge device (07h) with a 00h programming interface. Furthermore, the TI chip revision is indicated in the lower byte (00h). cache line size register Bit 7 6 5 4 R/W R/W R/W 0 0 0 Name Type Default 2 1 0 R/W R/W R/W R/W R/W 0 0 0 0 0 Cache line size Register: Type: Offset: Default: Description: 48 3 Cache line size Read/Write 0Ch (Functions 0, 1) 00h This register is programmed by host software to indicate the system cache line size. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 latency timer register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 Name Type Latency timer Default Register: Type: Offset: Default: Description: Latency timer Read/Write 0Dh 00h This register specifies the latency timer for the PCI4450, in units of PCI clock cycles. When the PCI4450 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI4450 transaction has terminated, then the PCI4450 terminates the transaction when its GNT is deasserted. header type register Bit 7 6 5 4 Name 3 2 1 0 Header type Type R R R R R R R R Default 1 0 0 0 0 0 1 0 Register: Type: Offset: Default: Description: Header type Read-only 0Eh (Functions 0, 1) 82h This register returns 82h when read, indicating that the PCI4450 functions 0 and 1 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and 80h–FFh is user definable extension registers. BIST register Bit 7 6 5 4 Name 3 2 1 0 BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: BIST Read-only 0Fh (Functions 0, 1) 00h Since the PCI4450 does not support a built-in self-test (BIST), this register returns the value of 00h when read. This register returns 0s for the two PCI4450 functions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 CardBus socket registers / ExCA registers base address register Bit 31 30 29 28 27 26 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 Name Type Default 24 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 5 4 3 2 1 0 CardBus socket registers/ExCA base address Name Type 25 CardBus socket registers/ExCA base address R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: CardBus socket registers/ExCA base address Read-only, Read/Write 10h 0000 0000h This register is programmed with a base address referencing the CardBus socket registers and the memory mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11–0 are read-only, returning 0s when read. When software writes all ones to this register, the value read back will be FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory mapped ExCA registers begin at offset 800h. This register is not shared by functions 0 and 1, mapping each socket control register separately. capability pointer register Bit 7 6 5 4 Type R R R R Default 1 0 1 0 Name 2 1 0 R R R R 0 0 0 0 Capability pointer Register: Type: Offset: Default: Description: 50 3 Capability pointer Read-only 14h A0h This register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register is read-only and returns A0h when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 secondary status register Bit 15 14 13 12 11 10 9 R/WC R/WC R/WC R/WC R/WC R R R/WC 0 0 0 0 0 0 1 0 Name Type Default 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Secondary status Register: Type: Offset: Default: Description: Secondary status Read-only, Read/Write to Clear 16h 0200h This register is compatible with the PCI-PCI bridge secondary status register. It indicates CardBus related device information to the host system. This register is very similar to the PCI status register (offset 06h), and status bits are cleared by a writing a 1. This register is not shared by the two socket functions, but is accessed on a per socket basis. Table 27. Secondary Status Register Description BIT TYPE FUNCTION 15 R/WC CBPARITY. Detected parity error. This bit is set when a CardBus parity error is detected, either address or data parity errors. Write a 1 to clear this bit. 14 R/WC CBSERR. Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI4450 does not assert the CSERR signal. Write a 1 to clear this bit. 13 R/WC CBMABORT. Received master abort. This bit is set when a cycle initiated by the PCI4450 on the CardBus bus has been terminated by a master abort. Write a 1 to clear this bit. 12 R/WC REC_CBTA. Received target abort. This bit is set when a cycle initiated by the PCI4450 on the CardBus bus was terminated by a target abort. Write a 1 to clear this bit. 11 R/WC SIG_CBTA. Signaled target abort. This bit is set by the PCI4450 when it terminates a transaction on the CardBus bus with a target abort. Write a 1 to clear this bit. 10–9 R CB_SPEED. CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the PCI4450 asserts this signal at a medium speed. CB_DPAR. CardBus data parity error detected. Write a 1 to clear this bit. 0 = The conditions for setting this bit have not been met. 1 = A data parity error occurred and the following conditions were met: a. CPERR was asserted on the CardBus interface. b. The PCI4450 was the bus master during the data parity error. c. The parity error response bit is set in the bridge control register. 8 R/WC 7 R CBFBB_CAP. Fast back-to-back capable. The PCI4450 cannot accept fast back-to-back transactions; therefore, this bit is hardwired to 0. 6 R CB_UDF. User definable feature support. The PCI4450 does not support the user definable features; therefore, this bit is hardwired to 0. 5 R CB66MHZ. 66 MHz capable. The PCI4450 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, this bit is hardwired to 0. 4–0 R Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI bus number register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 PCI bus number Register: Type: Offset: Default: Description: PCI bus number Read/Write 18h (Functions 0, 1) 00h This register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI4450 is connected. The PCI4450 uses this register, in conjunction with the CardBus bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to its secondary buses. CardBus bus number register Bit 7 6 5 Name Type Default 4 3 2 1 0 CardBus bus number R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: CardBus bus number Read/Write 19h 00h This register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI4450 is connected. The PCI4450 uses this register, in conjunction with the PCI bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI4450 controller function. subordinate bus number register Bit 7 6 5 Name Type Default 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: 52 4 Subordinate bus number Subordinate bus number Read/Write 1Ah 00h This register is programmed by the host system to indicate the highest numbered bus below the CardBus bus. The PCI4450 uses this register, in conjunction with the PCI bus number and CardBus bus number registers, to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each CardBus controller function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 CardBus latency timer register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CardBus latency timer Type Default Register: Type: Offset: Default: Description: CardBus latency timer Read/Write 1Bh (Functions 0, 1) 00h This register is programmed by the host system to specify the latency timer for the PCI4450 CardBus interface, in units of CCLK cycles. When the PCI4450 is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI4450 transaction has terminated, then the PCI4450 terminates the transaction at the end of the next data phase. A recommended minimum value for this register of 20h allows most transactions to be completed. memory base registers 0, 1 Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Memory base registers 0, 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Type Default Memory base registers 0, 1 Register: Type: Offset: Default: Description: Memory base registers 0, 1 Read-only, Read/Write 1Ch, 24h 0000 0000h These registers indicate the lower address of a PCI memory address range. They are used by the PCI4450 to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero in order for the PCI4450 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of memory to CardBus). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 memory limit registers 0, 1 Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Memory limit registers 0, 1 Name Type 24 Memory limit registers 0, 1 R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Memory limit registers 0, 1 Read-only, Read/Write 20h, 28h 0000 0000h These registers indicate the upper address of a PCI memory address range. They are used by the PCI4450 to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero in order for the PCI4450 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of memory to CardBus). I/O base registers 0, 1 Bit 31 30 29 28 27 26 25 R R R R R R R R Name Type 24 23 22 21 20 19 18 17 16 R R R R R R R R I/O base registers 0, 1 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default I/O base registers 0, 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: I/O base registers 0, 1 Read-only, Read/Write 2Ch, 34h 0000 0000h These registers indicate the lower address of a PCI I/O address range. They are used by the PCI4450 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page, and the upper 16 bits (31–16) are all 0s which locate this 64-Kbyte page in the first page of the 32-bit PCI I/O address space. Bits 31–16 and bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary in the first 64-Kbyte page of PCI I/O address space. These I/O windows are enabled when either the I/O base register or the I/O limit register are nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus. Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions. 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 I/O limit registers 0, 1 Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Default 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 I/O limit registers 0, 1 Name Type 24 I/O limit registers 0, 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: I/O limit registers 0, 1 Read-only, Read/Write 30h, 38h 0000 0000h These registers indicate the upper address of a PCI I/O address range. They are used by the PCI4450 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16 of the appropriate I/O base register) on doubleword boundaries. Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to read-only bits have no effect. The PCI4450 assumes that the lower two bits of the limit address are ones. These I/O windows are enabled when either the I/O base register or the I/O limit register are nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus. Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions. interrupt line register Bit 7 6 5 4 Name Type Default 3 2 1 0 Interrupt line R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Register: Type: Offset: Default: Description: Interrupt line Read/Write 3Ch FFh This register communicates interrupt line routing information to the host system. This register is not used by the PCI4450, since there are many programmable interrupt signaling options. This register is considered reserved; however, host software may read and write to this register. Each PCI4450 function has an interrupt line register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 interrupt pin register PCI function 0 Bit 7 6 5 4 Name 3 2 1 0 Interrupt pin – PCI function 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 0 0 0 0 0 0 1 0 PCI function 1 Bit Name Interrupt pin – PCI function 1 Register: Type: Offset: Default: Description: Interrupt pin Read-only 3Dh The default depends on the interrupt signaling mode. The value read from this register is function dependent. The value depends on two interrupt tie bits (INTRTIE and TIEALL) in the system control register. INTRTIE is compatible with other TI CardBus controllers and ties INTA to INTB internally. The TIEALL bit ties INTA, INTB, and INTC together internally. The internal interrupt connections set by INTRTIE and TIEALL are communicated to host software through this standard register interface. Refer to Table 28 for a complete description of the register contents. Table 28. Interrupt Pin Register Cross Reference INTRTIE Bit TIEALL Bit INTPIN Function 0 INTPIN Function 1 INTPIN Function 2 0 0 0x01 (INTA) 0x02 (INTB) 0x03 (INTC) 1 0 0x01 (INTA) 0x01 (INTA) 0x03 (INTC) x 1 0x01 (INTA) 0x01 (INTA) 0x01 (INTA) bridge control register Bit 15 14 13 12 11 10 9 Type R R R R R R/W R/W R/W Default 0 0 0 0 0 0 1 1 Name 7 6† 5 4 3 2 1 0 R/W R/W R/W R R/W R/W R/W R/W 0 1 0 0 0 0 0 0 Bridge control Register: Type: Offset: Default: Description: 56 8 Bridge control Read-only, Read/Write 3Eh (Function 0, 1) 0340h This register provides control over various PCI4450 bridging functions. Some bits in this register are global in nature and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 29. Bridge Control Register Description BIT TYPE 15–11 R FUNCTION Reserved. These bits return 0s when read. R/W POSTEN. Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables posting of write data on burst cycles. Operating with write posting disabled will inhibit performance on burst cycles. Note that bursted write data can be posted, but various write transactions may not. This bit is socket dependent and is not shared between functions 0 and 1. R/W PREFETCH1. Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. This bit is encoded as: 0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default). 8 R/W PREFETCH0. Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is encoded as: 0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default). 7 R/W PCI Interrupt – IREQ routing enable. This bit is used to select whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers. 0 = Functional interrupts are routed to PCI interrupts (default). 1 = Functional interrupts are routed by ExCA registers. R/W CRST. CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST signal may also be asserted by passing a PRST assertion to CardBus. 0 = CRST is deasserted. 1 = CRST is asserted (default). This bit will not be cleared by the assertion of PRST. It will only be cleared by the assertion of G_RST. 5§ R/W MABTMODE. Master abort mode. This bit controls how the PCI4450 responds to a master abort when the PCI4450 is an initiator on the CardBus interface. This bit is common between each socket. 0 = Master aborts not reported (default). 1 = Signal target abort on PCI and signal SERR, if enabled. 4 R 3 R/W VGAEN. VGA enable. This bit affects how the PCI4450 responds to VGA addresses. When this bit is set, accesses to VGA addresses will be forwarded. 2 R/W ISAEN. ISA mode enable. This bit affects how the PCI4450 passes I/O cycles within the 64-Kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI4450 will not forward the last 768 bytes of each 1K I/O range to CardBus. 1 R/W CSERREN. CSERR enable. This bit controls the response of the PCI4450 to CSERR signals on the CardBus bus. This bit is separate for each socket. 0 = CSERR is not forwarded to PCI SERR. 1 = CSERR is forwarded to PCI SERR. R/W CPERREN. CardBus parity error response enable. This bit controls the response of the PCI4450 to CardBus parity errors. This bit is separate for each socket. 0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR. 10 9 6† 0 Reserved. This bit returns 0 when read. † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. § These bits are global in nature and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 subsystem vendor ID register Bit 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8‡ 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ R R R R R R R R 0 0 0 0 0 0 0 0 Subsystem vendor ID ‡ This bit is cleared only by the assertion of G_RST. Register: Type: Offset: Default: Description: Subsystem vendor ID Read-only, Read/Write (when bit 5 in the system control register is 0.) 40h (Functions 0, 1) 0000h This register, used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. subsystem ID register Bit 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ Name 8‡ 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ Subsystem ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ‡ This bit is cleared only by the assertion of G_RST. Register: Type: Offset: Default: Description: Subsystem ID Read-only, Read/Write (when bit 5 in the system control register is 0.) 42h (Functions 0, 1) 0000h This register, used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. If an EEPROM is present, then the subsystem ID and subsystem vendor ID will be loaded from EEPROM after a reset. 58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PC Card 16-bit I/F legacy mode base address register Bit 31‡ 30‡ 29‡ 28‡ 27‡ 26‡ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ 8‡ 7‡ 6‡ Name Type Default Bit Default 24‡ 23‡ 22‡ 21‡ 20‡ 19‡ 18‡ 17‡ 16‡ R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 5‡ 4‡ 3‡ 2‡ 1‡ 0 PC Card 16-bit I/F legacy mode base address Name Type 25‡ PC Card 16-bit I/F legacy mode base address R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ‡ This bit is cleared only by the assertion of G_RST. Register: Type: Offset: Default: Description: PC Card 16-bit I/F legacy mode base address Read-only, Read/Write 44h (Functions 0, 1) 0000 0001h The PCI4450 supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An address written to this register is the address for the index register and the address+1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only returning 1 when read. As specified in the Yenta specification, this register is shared by functions 0 and 1. Refer to the ExCA register set description for register offsets. system control register Bit 31‡ 30‡ 29‡ 28 27‡ 26‡ 25‡ Name Type Default Bit Default 23 22‡ 21‡ 20‡ 19‡ 18‡ 17‡ 16‡ R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15‡ 14‡ 13 12 11 10 9 8 7 6‡ 5‡ 4‡ 3‡ 2 1‡ 0‡ R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Name Type 24‡ System control System control ‡ This bit is cleared only by the assertion of G_RST. Register: Type: Offset: Default: Description: System control Read-only, Read/Write 80h (Functions 0, 1) 0000 0020h System level initializations are performed through programming this doubleword register. Some of the bits are global in nature and should be accessed only through function 0. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 30. System Control Register Description BIT TYPE FUNCTION R/W SER_STEP. Serialized PCI interrupt routing step. These bits are used to configure the serialized PCI interrupt stream signaling and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. These bits are global to both PCI4450 functions. 00 = INTA/INTB/INTC signal in INTA/INTB/INTC slots (default) 01 = INTA/INTB/INTC signal in INTB/INTC/INTD slots 10 = INTA/INTB/INTC signal in INTC/INTD/INTA slots 11 = INTA/INTB/INTC signal in INTD/INTA/INTB slots 29‡§ R/W INTRTIE. Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally and are signaled as INTA. INTA may then be shifted by using the SER_STEP bits. This bit is global to both PCI4450 functions. This bit has no effect on INTC. 0 = INTA and INTB are not tied together internally (default). 1 = INTA and INTB are tied together internally. 28 R/W TIEALL. This bit ties INTA, INTB, and INTC internally (to INTA) and reports this through the interrupt pin register. R/W P2CCLK. P2C power switch CLOCK. This bit determines whether the CLOCK terminal (terminal U12) is an input that requires an external clock source or if this terminal is an output that uses the internal oscillator. 0 = CLOCK terminal (terminal U12) is an input (default) (disabled). 1 = CLOCK terminal is an output, the PCI4450 generated CLOCK. A 43kW pulldown resistor should be tied to this terminal. R/W SMIROUTE. SMI interrupt routing. This bit is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket. 0 = PC Card power change interrupts routed to IRQ2 (default). 1 = A CSC interrupt is generated on PC Card power changes. R/W SMISTATUS. SMI interrupt status. This socket dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to this bit clears the status. 0 = SMI interrupt is signaled. 1 = SMI interrupt is not signaled. 24‡§ R/W SMIENB. SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled). 0 = SMI interrupt mode is disabled (default). 1 = SMI interrupt mode is enabled. 23 R 31–30‡§ 27‡§ 26‡§ 25‡ 22‡ R/W 21‡ R/W 20‡ R/W 19‡ 18–16‡ Reserved CBRSVD. CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals will be driven low when a CardBus card is inserted. When this bit is low, as default, these signals are placed in a high-impedance state. 0 = Place the CardBus RSVD terminals in a high-impedance state 1 = Drive the Cardbus RSVD terminals low (default). VCCPROT. VCC protection enable. This bit is socket dependent. 0 = VCC protection is enabled for 16-bit cards (default). 1 = VCC protection is disabled for 16-bit cards. Reduced zoomed video enable. When this bit is enabled, A25–22 of the card interface for PC Card 16 cards is placed in the high impedance state. This bit is encoded as: 0 = Reduced zoomed video is disabled (default). 1 = Reduced zoomed video is enabled. R/W CDREQEN. PC/PCI DMA card enable. When this bit is set, the PCI4450 allows 16-bit PC Cards to request PC/PCI DMA using the DREQ signaling. DREQ is selected through the socket DMA register 0. 0 = Ignore DREQ signaling from PC Cards (default). 1 = Signal DMA request on DREQ. R/W CDMACHAN. PC/PCI DMA channel assignment. These bits are encoded as: 0–3 = 8-bit DMA channels 4 = PCI master; not used (default) 5–7 = 16-bit DMA channels § These bits are global in nature and should be accessed only through function 0. ‡ This bit is cleared only by the assertion of G_RST. 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 30. System Control Register Description (continued) BIT TYPE FUNCTION 15‡§ R/W MRBURSTDN. Memory read burst enable downstream. When this bit is set, memory read transactions are allowed to burst downstream. 0 = MRBURSTDN downstream is disabled. 1 = MRBURSTDN downstream is enabled (default). R/W MRBURSTUP. Memory read burst enable upstream. When this bit is set, the PCI4450 allows memory read transactions to burst upstream. 0 = MRBURSTUP upstream is disabled (default). 1 = MRBURSTUP upstream is enabled. 13 R SOCACTIVE. Socket activity status. When set, this bit indicates access has been performed to or from a PC Card, and is cleared upon read of this status bit. This bit is socket dependent. 0 = No socket activity (default) 1 = Socket activity 12 R Reserved. This bit returns 1 when read. This is the power rail bit in functions 0 and 1. R PWRSTREAM. Power stream in progress status bit. When set, this bit indicates that a power stream to the power switch is in progress and a powering change has been requested. When this bit is clear, it indicates that the power stream is complete. 0 = Power stream is complete, delay has expired. 1 = Power stream is in progress. R DELAYUP. Power-up delay in progress status bit. When set, this bit indicates that a power-up stream has been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up delay has expired. 0 = Power-up delay has expired. 1 = Power-up stream sent to switch. Power might not be stable. R DELAYDOWN. Power-down delay in progress status bit. When set, this bit indicates that a power-down stream has been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-down delay has expired. 0 = Power-down delay has expired. 1 = Power-down stream sent to switch. Power might not be stable. 8 R INTERROGATE. Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when the interrogation completes. This bit is socket dependent. 0 = Interrogation not in progress (default) 1 = Interrogation in progress 7 R Reserved. This bit returns 0 when read. 14‡§ 11 10 9 R/W PWRSAVINGS. Power savings mode enable. When this bit is set, the PCI4450 will consume less power with no performance loss. This bit is shared between the two PCI4450 functions. 0 = Power savings mode disabled 1 = Power savings mode enabled (default) 5‡§ R/W SUBSYSRW. Subsystem ID (SS ID), subsystem vendor ID (SS VID), and the ExCA identification and revision registers read/write enable. This bit is shared by functions 0 and 1. This bit does not control read/write of function 2, subsystem ID register. 0 = Subsystem ID, subsystem vendor ID, and the ExCA identification and revision registers are read/write. 1 = Subsystem ID, subsystem vendor ID, and the ExCA identification and revision registers are read-only (default). 4‡§ R/W CB_DPAR. CardBus data parity SERR signaling enable. 0 = CardBus data parity not signaled on PCI SERR signal (default) 1 = CardBus data parity signaled on PCI SERR signal 3‡§ R/W CDMA_EN. PC/PCI DMA enable. Enables PC/PCI DMA when set. When PC/PCI DMA is enabled, PCREQ and PCGNT should be routed to a multifunction routing terminal. See multifunction routing status register for options. 0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled 2 R 6‡§ Reserved. This bit returns 0 when read. § These bits are global in nature and should be accessed only through function 0. ‡ This bit is cleared only by the assertion of G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 30. System Control Register Description (continued) BIT 1‡§ 0‡§ TYPE FUNCTION R/W KEEPCLK. Keep clock. When this bit is set, the PCI4450 will always follow CLKRUN protocol to maintain the system PCLK and the CCLK (CardBus clock). This bit is global to the PCI4450 functions. 0 = Allow system PCLK and CCLK to stop (default) 1 = Never allow system PCLK or CCLK clock to stop Note that the functionality of this bit has changed versus the PCI12XX series of TI CardBus controllers. In these CardBus controllers, setting this bit would only maintain the PCI clock, not the CCLK. In the PCI4450, setting this bit will maintain both the PCI clock and the CCLK. R/W PME/RI_OUT select bit. When this bit is 1, the PME signal is routed on to pin Y13 (PME/RI_OUT pin). When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal is routed on to pin Y13 (GFN) or pin R11 (GJG). If this bit is 0 and bit 7 (RIENB) of the card control register is 0, then the output (Y13 or R11) will be placed in a high-impedance state. This pin is encoded as: 0 = RI_OUT signal is routed to pin Y13 (GFN) or pin R11 (GJG) if bit 7 of the card control register is 1*. (default) 1 = PME signal is routed on pin Y13 (GFN) or pin R11 (GJG) of the PCI4450 controller. NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register is 0, then the output on pin Y13 (GFN) or pin R11 (GJG) is placed in a high-impedance state. § These bits are global in nature and should be accessed only through function 0. ‡ This bit is cleared only by the assertion of G_RST. 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 multimedia control register Bit 7‡ 6‡ 5‡ 4‡ R/W R/W R/W R/W 0 0 0 0 Name Type 3‡ 2‡ 1‡ 0‡ R/W R/W R/W R/W 0 0 0 0 Multimedia control Default Register: Type: Offset: Default: Description: Multimedia control Read/Write 84h (Functions 0, 1) 00h This register provides port mapping for the PCI4450 zoomed video/data ports. See zoomed video support for details on the PCI4450 zoomed video support. Access this register only through function 0. Table 31. Multimedia Control Register Description BIT TYPE FUNCTION R/W ZVOUTEN. ZV output enable. This bit enables the output for the PCI4450 outsourcing ZV terminals. When this bit is reset, ‘0’, these terminals are in a high impedance state. 0 = PCI4450 ZV output terminals disabled (default) 1 = PCI4450 ZV output terminals enabled 6‡ R/W PORTSEL. ZV port select. This bit controls the multiplexing control over which PC Card ZV port data will be driven to the outsourcing PCI4450 ZV port. 0 = Output card 0 ZV if enabled (default) 1 = Output card 1 ZV if enabled 5‡ R/W Zoomed video auto-detect. This bit enables the zoomed video auto-detect feature. This bit is encoded as: 0 = Zoomed video auto detect disabled (default) 1 = Zoomed video auto detect enabled R/W Auto-detect priority encoding. These bits have meaning only if zoomed video auto-detect is enabled in bit 5 of this register. If auto-detect is enabled, then bits 4–2 are encoded as follows: 000 = Slot A, Slot B, External Source 001 = Slot A, External Source, Slot B 010 = Slot B, Slot A, External Source 011 = Slot B, External Source, Slot A 100 = External Source, Slot A, Slot B 101 = External Source, Slot B, Slot A 110 = Reserved 111 = Reserved R/W ZVEN1. PC Card 1 ZV mode enable. Enables the zoomed video mode for socket 1. When set, the PCI4450 inputs ZV data from the PC Card interface, and disables output drivers on ZV terminals. 0 = PC Card 1 ZV disabled (default) 1 = PC Card 1 ZV enabled R/W ZVEN0. PC Card 0 ZV mode enable. Enables the zoomed video mode for socket 0. When set, the PCI4450 inputs ZV data from the PC Card interface, and disables output drivers on ZV terminals. 0 = PC Card 0 ZV disabled (default) 1 = PC Card 0 ZV enabled 7‡ 4–2‡ 1‡ 0‡ ‡ This bit is cleared only by the assertion of G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 general status register Bit 7 6 5 4 3 2‡ 1‡ 0‡ R/U R R R 0 0 0 R R/U R R 0 0 X 0 0 Name General status Type Default Register: Type: Offset: Default: Description: General status Read/Update 85h (Functions 0) 00h This register provides the general device status information. The status of the serial EEPROM interface is provided through this register. Table 32. General Status Register Description BIT TYPE 7 R/U 6–3 R 2‡§ R/U EEDETECT. Serial EEPROM detect. Serial EEPROM is detected by sampling a logic high on SCL on PRST. When this bit is set, the serial ROM is detected. This status bit is encoded as: 0 = EEPROM not detected (default) 1 = EEPROM detected 1‡§ R DATAERR. Serial EEPROM data error status. This bit indicates when a data error occurs on the serial EEPROM interface. This bit may be set due to a missing acknowledge. This bit is cleared by a writing a 1. 0 = No error detected. (default) 1 = Data error detected. R EEBUSY. Serial EEPROM busy status. This bit indicates the status of the PCI4450 serial EEPROM circuitry. This bit is set during the loading of the subsystem ID value. 0 = Serial EEPROM circuitry is not busy (default). 1 = Serial EEPROM circuitry is busy. 0‡§ FUNCTION IDSEL_DET. When this bit is set, the IDSEL/MFUNC7 terminal functions as an IDSEL input. Reserved. These bits return 0s when read. § This bit is global in nature and should only be accessed through function 0. ‡ This bit is cleared only by the assertion of G_RST. 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 general control register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 Name General control Register: Type: Offset: Default: Description: General control Read-Only, Read/Write 86h 00h This register provides top level PCI arbitration control. Table 33. General Control Register Description BIT TYPE 7–4 R 3 R/W DISABLE_OHCI. When this bit is set, the open HCI 1394 controller function is completely nonaccessible and nonfunctional. 2 R/W GP2IIC. When this bit is set, the GPO0 and GPO1 signals are routed to SDA and SCL, respectively. R/W ARB_CTRL. Controls top level PCI arbitration. 00 = 1394 open HCI priority 01 = CardBus priority 10 = Fair round robin 11 = Reserved (fair round robin) 1–0 FUNCTION Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 general-purpose event status register Bit 7‡ 6‡ 5 RCU RCU R R 0 0 0 0 Name Type 4 3‡ 2‡ 1‡ 0‡ RCU RCU RCU RCU 0 0 0 0 General-purpose event status Default Register: Type: Offset: Default: Description: General-purpose event status Read/Clear/Update 88h 00h This register contains status bits that are set when general events occur and may be programmed to generate general-purpose event signalling through GPE. Table 34. General-Purpose Event Status Register Description BIT TYPE 7‡ RCU PWR_STS. Power change status. This bit is set when software changes the VCC or VPP power state of either socket. FUNCTION 6‡ RCU VPP12_STS. 12V VPP request status. This bit is set when software has changed the requested VPP level to or from 12 V for either socket. 5–4 R 3‡ RCU GP3_STS. GPI3 status. This bit is set on a change in status of the MFUNC3 terminal input level if configured as a general-purpose input, GPI3. 2‡ RCU GP2_STS. GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a general-purpose input, GPI2. 1‡ RCU GP1_STS. GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a general-purpose input, GPI1. 0‡ RCU GP0_STS. GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a general-purpose input, GPI0. Reserved. This bit returns 0 when read. A write has no effect. ‡ This bit is cleared only by the assertion of G_RST. 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 general-purpose event enable register Bit 7‡ 6‡ 5 R/W R/W R R 0 0 0 0 Name 4 3‡ 2‡ 1‡ 0‡ R/W R/W R/W R/W 0 0 0 0 General-purpose event enable Type Default Register: Type: Offset: Default: Description: General-purpose event enable Read-only, Read/Write 89h 00h This register contains bits that are set to enable GPE signals. Table 35. General-Purpose Event Enable Register Description BIT TYPE 7‡ R/W PWR_EN. Power change GPE enable. When this bit is set, GPE is signaled on PWR_STS events. FUNCTION 6‡ R/W VPP12_EN. 12-Volt VPP GPE enable. When this bit is set, GPE is signaled on VPP12_STS events. 5–4 R 3‡ R/W Reserved. This bit returns 0 when read. A write has no effect. GP3_EN. GPI3 GPE enable. When this bit is set, GPE is signaled on GP3_STS events. 2‡ R/W GP2_EN. GPI2 GPE enable. When this bit is set, GPE is signaled on GP2_STS events. 1‡ R/W GP1_EN. GPI1 GPE enable. When this bit is set, GPE is signaled on GP1_STS events. 0‡ R/W GP0_EN. GPI0 GPE enable. When this bit is set, GPE is signaled on GP0_STS events. ‡ This bit is cleared only by the assertion of G_RST. general-purpose input register Bit 7 6 5 Name 4 3‡ 2‡ 1‡ 0‡ General-purpose input Type R R R R RU RU RU RU Default 0 0 0 0 x x x x Register: Type: Offset: Default: Description: General-purpose input Read/Update 8Ah 00h This register contains GPI terminal status. Table 36. General-Purpose Input Register Description BIT TYPE FUNCTION 7–4 R 3‡ RU Reserved. These bits return 0s when read. Writes have no effect. GPI3_DATA. GPI3 data input. This bit represents the logical value of the data input from GPI3. 2‡ RU GPI2_DATA. GPI2 data input. This bit represents the logical value of the data input from GPI2. 1‡ RU GPI1_DATA. GPI1 data input. This bit represents the logical value of the data input from GPI1. 0‡ RU GPI0_DATA. GPI0 data input. This bit represents the logical value of the data input from GPI0. ‡ This bit is cleared only by the assertion of G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 67 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 general-purpose output register Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 4 3‡ 2‡ 1‡ 0‡ R/W R/W R/W R/W 0 0 0 0 General-purpose output Register: Type: Offset: Default: Description: General-purpose output Read-only, Read/Write 8Bh 00h This register is used to drive the GPO3–GPO0 outputs. Table 37. General-Purpose Output Register Description BIT TYPE 7–4 R FUNCTION 3‡ R/W GPO3_DATA. This bit represents the logical value of the data driven to GPO3. 2‡ R/W GPO2_DATA. This bit represents the logical value of the data driven to GPO2. 1‡ R/W GPO1_DATA. This bit represents the logical value of the data driven to GPO1. Reserved. These bits return 0s when read. Writes have no effect. 0‡ R/W GPO0_DATA. This bit represents the logical value of the data driven to GPO0. ‡ This bit is cleared only by the assertion of G_RST. 68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 multifunction routing status register Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Multifunction routing status Name Type 24 Multifunction routing status R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Multifunction routing status Read/Write 8Ch 0000 0000h This register is used to configure MFUNC7–MFUNC0 terminals. These terminals may be configured for various functions. This register is intended to be programmed once at power-on initialization. The default value for this register may also be loaded through a serial ROM. Table 38. Multifunction Routing Status Register Description BIT TYPE 31 R 30–28 R/W 27 R 26–24 R/W 23 R 22–20 R/W 19 R 18–16 R/W 15 R 14–12 R/W FUNCTION Reserved. This bit returns 0 when read. Writes have no effect. MFUNC7_SEL. MFUNC7 select. These bits control the mapping of MFUNC7 as follows: 000 = IDSEL 100 = D3_STAT 001 = RI_OUT 101 = LOCK 010 = OHCI_LED 110 = RSVD 011 = PCREQ 111 = RSVD Reserved. This bit returns 0 when read. Writes have no effect. MFUNC6_SEL. MFUNC6 select. These bits control the mapping of MFUNC6 as follows: 000 = RSVD 100 = D3_STAT 001 = RSVD 101 = RSVD 010 = OHCI_LED 110 = CAUDPWM 011 = RSVD 111 = RSVD Reserved. This bit returns 0 when read. Writes have no effect. MFUNC5_SEL. MFUNC5 select. These bits control the mapping of MFUNC5 as follows: 000 = RSVD 100 = RSVD 001 = RSVD 101 = GPE 010 = OHCI_LED 110 = CAUDPWM 011 = RSVD 111 = RSVD Reserved. This bit returns 0 when read. Writes have no effect. MFUNC4_SEL. MFUNC4 select. These bits control the mapping of MFUNC4 as follows: 000 = RSVD 100 = RSVD 001 = RSVD 101 = GPE 010 = LEDA1 110 = RSVD 011 = PCREQ 111 = ZV_STAT Reserved. This bit returns 0 when read. Writes have no effect. MFUNC3_SEL. MFUNC3 select. These bits control the mapping of MFUNC3 as follows: 000 = GPI3 100 = RSVD 001 = GPO3 101 = LOCK 010 = LEDA2 110 = RSVD 011 = PCGNT 111 = C_ZVCLK POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 69 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 38. Multifunction Routing Status Register Description (continued) BIT TYPE 11 R 10–8 R/W 7 R 6–4 R/W 3 R 2–0 70 R/W FUNCTION Reserved. This bit returns 0 when read. Writes have no effect. MFUNC2_SEL. MFUNC2 select. These bits control the mapping of MFUNC2 as follows: 000 = GPI2 100 = D3_STAT 001 = GPO2 101 = RSVD 010 = INTC 110 = RSVD 011 = PCGNT 111 = C_ZVCLK Reserved. This bit returns 0 when read. Writes have no effect. MFUNC1_SEL. MFUNC1 select. These bits control the mapping of MFUNC1 as follows: 000 = GPI1 100 = D3_STAT 001 = GPO1 101 = LOCK 010 = INTB 110 = CAUDPWM 011 = TEST_MUX 111 = ZV_STAT Reserved. This bit returns 0 when read. Writes have no effect. MFUNC0_SEL. MFUNC0 select. These bits control the mapping of MFUNC0 as follows: 000 = GPI0 100 = RSVD 001 = GPO0 101 = GPE 010 = INTA 110 = RSVD 011 = PCREQ 111 = ZV_STAT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 retry status register Bit 7‡ 6‡ 5‡ 4 3‡ 2 1‡ 0 R/W R/W R/WC R 1 1 0 R/WC R R/WC R 0 0 0 0 0 Name Type Retry status Default Register: Type: Offset: Default: Description: Retry status Read-only, Read/Write 90h (Functions 0, 1) C0h The contents of this register enable the retry time-out counters and display the retry expiration status. The flags are set when the PCI4450 retries a PCI or CardBus master request, and the master does not return within 215 PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI command register, PCI status register, and bridge control register by the PCI SIG. Access this register only through function 0. Table 39. Retry Status Register Description BIT TYPE FUNCTION 7‡ R/W PCIRETRY. PCI retry time-out counter enable. This bit is encoded as: 0 = PCI retry counter disabled 1 = PCI retry counter enabled (default) 6‡§ R/W CBRETRY. CardBus retry time-out counter enable. This bit is encoded as: 0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default) 5‡ R/WC 4 R 3‡§ R/WC 2 R 1‡ R/WC 0 R TEXP_CBB. CardBus target B retry expired. Write a 1 to clear this bit. 0 = Inactive (default) 1 = Retry has expired. Reserved. This bit returns 0 when read. TEXP_CBA. CardBus target A retry expired. Write a 1 to clear this bit. 0 = Inactive (default) 1 = Retry has expired. Reserved. This bit returns 0 when read. TEXP_PCI. PCI target retry expired. Write a 1 to clear this bit. 0 = Inactive (default) 1 = Retry has expired. Reserved. This bit returns 0 when read. § These bits are global in nature and should be accessed only through function 0. ‡ This bit is cleared only by the assertion of G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 71 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 card control register Bit 7‡ 6‡ 5 4 3 2‡ 1‡ 0‡ R/W R/W R/W R 0 0 0 R R/W R/W R/W 0 0 0 0 0 Name Type Card control Default Register: Type: Offset: Default: Description: Card control Read-only, Read/Write 91h 00h This register is provided for PCI1130 compatibility. The contents provide the PC Card function interrupt flag (IFG) and an alias for the ZVEN0 and ZVEN1 bits found in the PCI4450 multimedia control register. When this register is accessed by function 0, the ZVEN0 bit will alias with ZVENABLE. When this register is accessed by function 1, the ZVEN1 bit will alias with ZVENABLE. Setting ZVENABLE only places the PC Card socket interface ZV terminals in a high impedance state, but does not enable the PCI4450 to drive ZV data onto the ZV terminals. The RI_OUT signal is enabled through this register, and the enable bit is shared between functions 0 and 1. Table 40. Card Control Register Description BIT TYPE FUNCTION 7‡§ R/W RIENB. Ring indicate enable. When this bit is 1, the RI_OUT output is enabled. This bit is global in nature and should be accessed only through function 0. This bit defaults to 0. 6‡ R/W ZVENABLE. Compatibility ZV mode enable. When this bit is 1, the corresponding PC Card socket interface ZV terminals will enter a high impedance state. This bit defaults to 0. 5 R/W Reserved. 4–3 R 2‡ 1‡ 0‡ Reserved. These bits default to 0. R/W AUD2MUX. CardBus Audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal must be routed through an MFUNC terminal. If this bit is set for both functions, then function 0 gets routed. 0 = CAUDIO set to CAUDPWM on MFUNC pin (default) 1 = CAUDIO is not routed. R/W SPKROUTEN. Speaker output enable. When this bit is 1, it enables SPKR on the PC Card and routes it to SPKROUT on the PCI bus. The SPKR signal from socket 0 is XOR’ed with the SPKR signal from socket 1 and sent to SPKROUT. The SPKROUT terminal only drives data then either functions SPKROUTEN bit is set. This bit is encoded as: 0 = SPKR to SPKROUT not enabled (default) 1 = SPKR to SPKROUT enabled R/W IFG. Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when a functional interrupt is signaled from a PC Card interface, and is socket dependent (i.e., not global). Write back a ‘1’ to clear this bit. 0 = No PC Card functional interrupt detected (default) 1 = PC Card functional interrupt detected § These bits are global in nature and should be accessed only through function 0. ‡ This bit is cleared only by the assertion of G_RST. 72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 device control register Bit 7‡ 6‡ 5‡ 4 3‡ 2‡ 1‡ 0‡ R/W R/W R/W R 0 1 1 R/W R/W R/W R/W 0 0 1 1 0 Name Type Device control Default Register: Type: Offset: Default: Description: Device control Read-only, Read/Write 92h (Functions 0, 1) 66h This register is provided for PCI1130 compatibility. It contains bits which are shared between functions 0 and 1. The interrupt mode select is programmed through this register. The socket capable force bits are also programmed through this register. Table 41. Device Control Register Description BIT TYPE FUNCTION 7‡ R/W Socket power lock bit. When this bit is set to 1, software will not be able to power down the PC Card socket while in D3. This may be necessary to support Wake on LAN or RING if the operating system is programmed to power down a socket when the CardBus controller is placed in the D3 state. 6‡§ R/W 3VCAPABLE. 3-V socket capable force bit. 0 = Not 3-V capable 1 = 3-V capable (default) 5‡ R/W IO16R2. Diagnostic bit. This bit defaults to 1. 4 R 3‡§ R/W TEST. TI test bit. Write only 0 to this bit. This bit can be set to shorten the interrogation counter. 2–1‡§ R/W INTMODE. Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded: 00 = Parallel PCI interrupts only 01 = Reserved 10 = IRQ serialized interrupts & parallel PCI interrupts INTA and INTB 11 = IRQ & PCI serialized interrupts (default) 0‡§ R/W Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI4450, and it tests only the pins that are inputs or I/Os. Any output only terminal on the PCI4450 is excluded from the NAND tree test. Reserved. This bit returns 0 when read. A write has no effect. § These bits are global in nature and should be accessed only through function 0. ‡ This bit is cleared only by the assertion of G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 73 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 diagnostic register Bit 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ R/W R/W R/W R/W 0 1 1 R/W R/W R/W R/W 0 0 0 0 1 Name Type Diagnostic Default Register: Type: Offset: Default: Description: Diagnostic Read/Write 93h (Functions 0, 1) 61h This register is provided for internal Texas Instruments test purposes. Table 42. Diagnostic Register Description BIT TYPE FUNCTION 7‡§ R/W This bit defaults to 0. This bit is encoded as: 0 = Reads true values in PCI vendor ID and PCI device ID registers (default). 1 = Reads all ones in reads to the PCI vendor ID and PCI device ID registers. 6‡ R/W Reserved. 5‡ R/W CSC interrupt routing control 0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1. 1 = CSC Interrupts routed to PCI if ExCA 805 bits 7–4 = 0000b. (Default) In this case, the setting of ExCA 803 bit 4 is a “don’t care.” 4‡§ R/W DIAG. Diagnostic RETRY_DIS. Delayed transaction disable. 3‡§ R/W 2‡§ R/W DIAG. Diagnostic RETRY_EXT. Extends the latency from 16 to 64. DIAG. Diagnostic DISCARD_TIM_SEL_CB. Set = 210, Reset = 215 1‡§ R/W DIAG. Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, Reset = 215 0‡§ R/W ASYNC_CSC. Asynchronous interrupt generation. 0 = CSC interrupt not generated asynchronously 1 = CSC interrupt is generated asynchronously (default) § These bits are global in nature and should be accessed only through function 0. ‡ This bit is cleared only by the assertion of G_RST. 74 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 socket DMA register 0 Bit 31 30 29 28 27 26 25 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name 24 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 0 0 0 6 5 4 3 2 1‡ 0‡ Socket DMA register 0 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: DMA socket register 0 Read-only, Read/Write 94h (Functions 0, 1) 0000 0000h This register provides control over the PC Card DREQ (DMA request) signaling. Table 43. Socket DMA Register 0 Description BIT TYPE 31–2 R 1–0‡ R/W FUNCTION Reserved. These bits return 0s when read. DREQPIN. DMA request (DREQ) pin. These bits indicate which pin on the 16-bit PC Card interface will as the DREQ signal during DMA transfers. This field is encoded as: 00 = Socket not configured for DMA (default) 01 = DREQ uses SPKR 10 = DREQ uses IOIS16 11 = DREQ uses INPACK ‡ This bit is cleared only by the assertion of G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 75 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 socket DMA register 1 Bit 31 30 29 28 27 26 25 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ 8‡ 7‡ Name Bit Default 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 0 0 0 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ Socket DMA register 1 Name Type 24 Socket DMA register 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: DMA socket register 1 Read-only, Read/Write 98h (Functions 0, 1) 0000 0000h The contents of this register provide control over the distributed DMA (DDMA) registers and the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI I/O address space. Note that 32-bit transfers to the 16-bit PC Card interface are not supported; the maximum transfer possible to the PC Card interface is 16-bits. However, 32 bits of data are prefetched from the PCI bus, thus allowing back-to-back 16-bit transfers to the PC Card interface. Table 44. Socket DMA Register 1 Description BIT TYPE 31–16 R 15–4‡ R/W 3‡ R 2–1‡ 0‡ FUNCTION Reserved. These bits return 0s when read. DMABASE. DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K bytes of I/O address space. The lower four bits are hardwired to 0, and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary EXTMODE. Extended addressing. This feature is not supported by the PCI4450, and always returns a 0. R/W XFERSIZE. Transfer size. These bits specify the width of the DMA transfer on the PC Card interface, and are encoded as: 00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved R/W DDMAEN. DDMA registers decode enable. Enables the decoding of the distributed DMA registers based upon the value of DMABASE. 0 = Disabled (default) 1 = Enabled ‡ This bit is cleared only by the assertion of G_RST. 76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 capability ID register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 1 Name Capability ID Register: Type: Offset: Default: Description: Capability ID Read-only A0h 01h This register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. next item pointer register Bit 7 6 5 Name 4 3 2 1 0 Next item pointer Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Next item pointer Read-only A1h 00h The contents of this register indicate the next item in the linked list of the PCI power management capabilities. Since the PCI4450 functions only include one capabilities item, this register returns 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 77 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 power management capabilities register Bit 15† 14 13 12 11 10 R/W R R R R R R R R 1 1 1 1 1 1 1 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R R R R R 0 0 1 0 0 0 1 Power management capabilities Register: Type: Offset: Default: Description: Power management capabilities Read-only, Read/Write A2h (Functions 0, 1) FE11h This register contains information on the capabilities of the PC Card function related to power management. Both PCI4450 CardBus bridge functions support D0, D1, D2, and D3 power states. Table 45. Power Management Capabilities Register Description BIT TYPE FUNCTION PME support. This 5-bit field indicates the power states from which the PCI4450 device functions may assert PME. A 0b (zero) for any bit indicates that the function cannot assert the PME signal while in that power state. These five bits return 0Fh when read. Each of these bits is described below: Bit 15 – defaults to a 1 indicating the PME signal can be asserted from the D3cold state. This bit is read/write because wake-up support from D3cold is contingent on the system providing an auxiliary power source to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC terminals for D3cold wake-up support, then BIOS should write a 0 to this bit. Bit 14 – contains the value 1 to indicate that the PME signal can be asserted from the D3hot state. Bit 13 – contains the value 1 to indicate that the PME signal can be asserted from the D2 state. Bit 12 – contains the value 1 to indicate that the PME signal can be asserted from the D1 state. Bit 11 – contains the value 1 to indicate that the PME signal can be asserted from the D0 state. 15† R/W 14–11 R 10 R D2_Support. This bit returns a 1 when read, indicating that the function supports the D2 device power state. 9 R D1_Support. This bit returns a 1 when read, indicating that the function supports the D1 device power state. 8–6 R Reserved. These bits return 000b when read. 5 R DSI. Device specific initialization. This bit returns 0 when read. R AUX_PWR. Auxiliary power source. This bit is meaningful only if bit 15 (D3cold supporting PME) is set. When this bit is set, it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. A 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source. If the function does not support PME while in the D3cold state (bit 15=0), then this field must always return 0. 4 3 R PMECLK. When this bit is 1, it indicates that the function relies on the presence of the PCI clock for PME operation. When this bit is 0, it indicates that no PCI clock is required for the function to generate PME. Functions that do not support PME generation in any state must return 0 for this field. 2–0 R Version. These 3 bits return 001b when read, indicating that there are 4 bytes of general-purpose power management (PM) registers as described in the draft revision 1.0 PCI Bus Power Management Interface Specification. † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. 78 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 power management control/status register Bit 15† 14 13 12 11 10 R/WC R R R R R R R/W R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8† 7 6 5 4 3 2 1 0 R R R R R R/W R/W 0 0 0 0 0 0 0 Power management control/status Register: Type: Offset: Default: Description: Power management control/status Read-only, Read/Write, Read/Write to Clear A4h (Functions 0, 1) 000000h This register determines and changes the current power state of the PCI4450 CardBus function. The contents of this register are not affected by the internally generated reset caused by the transition from the D3hot to D0 state. All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3hot-to-D0 state transition, with the exception of the PME context bits (if PME is enabled) and the G_RST only bits. Table 46. Power Management Control/Status Register Description BIT TYPE FUNCTION 15† R/WC PMESTAT. PME status. This bit is set when the CardBus function would normally assert the PME signal, independent of the state of the PME_EN bit. This bit is cleared by a write back of 1, and this also clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect. 14–13 R DATASCALE. This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data, as indicated by the DYN_DATA bit. 12–9 R DATASEL. Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data, as indicated by the DYN_DATA bit. 8† R/W PME enable. This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This bit will not be cleared by the assertion of PRST. It will only be cleared by the assertion of G_RST. 7–2 R 1–0 R/W Reserved. These bits return 0s when read. PWRSTATE. Power state. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. This field is encoded as: 00 = D0 01 = D1 10 = D2 11 = D3hot † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 79 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 power management control/status register bridge support extensions Bit 7 6 Type R R R R R Default 1 1 0 0 0 Name 5 4 3 2 1 0 R R R 0 0 0 Power management control/status register bridge support extensions Register: Type: Offset: Default: Description: Power management control/status register bridge support extensions Read-only A6h (Functions 0, 1) C0h This register supports PCI bridge specific functionality. It is required for all PCI-to-PCI bridges. Table 47. PMCSR_BSE Bridge Support Extensions BIT TYPE FUNCTION R BPCC_Enable. Bus power/clock control enable. This bit returns 1 when read. This bit is encoded as: 0 = Bus power/clock control is disabled. 1 = Bus power/clock control is enabled (default). A 0 indicates that the bus power/clock control policies defined in the PCI Power Management specification are disabled. When the bus power/clock control enable mechanism is disabled, the bridge’s PMCSR powerstate field cannot be used by the system software to control the power or the clock of the bridge’s secondary bus. A 1 indicates that the bus power/clock control mechanism is enabled. When bus power/clock control is disabled, the bridge’s PMCSR power state field cannot be used by the system software to control power or the clock of the bridge’s secondary bus. 6 R B2_B3. B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot. This bit is only meaningful if bit 7 (BPCC_Enable) is a 1. This bit is encoded as: 0 = when the bridge is programmed to D3hot, its secondary bus will have its power removed (B3). 1 = when the bridge function is programmed to D3hot, its secondary bus’s PCI clock will be stopped (B2). (Default) 5–0 R Reserved. These bits return 0s when read. 7 80 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 GPE control/status register Bit 15 14 13 12 11 10‡ 9‡ Type R R R R R R/WC R/WC R/WC Default 0 0 0 0 0 0 0 0 Name 8‡ 7 6 5 4 3 2‡ 1‡ 0‡ R R R R R R/W R/W R/W 0 0 0 0 0 0 0 0 GPE control/status Register: Type: Offset: Default: Description: GPE control/status Read-only, Read/Write, Read/Write to Clear A8h 0001h If the GPE (general-purpose event) function is programmed onto the MFUNC5 pin by writing 101b to bits 22–20 of the multifunction routing register (PCI offset 8Ch), then this register may be used to program which events will cause GPE to be asserted and report the status. Table 48. GPE Control/Status Register Description BIT TYPE 15–11 R FUNCTION 10‡ R/WC ZV1_STS. PC Card socket 1 status. This bit is set on a change in status of the ZVENABLE bit in function 1. 9‡ R/WC ZV0_STS. PC Card socket 0 status. This bit is set on a change in status of the ZVENABLE bit in function 0. 8‡ R/WC VPP12_STS. 12-volt VPP request status. This bit is set when software has changed the requested VPP level to or from 12 volts from either socket. 7–3 R 2‡ R/W ZV1_EN. PC Card socket 1 zoomed video event enable. When this bit is set, GPE is signaled on a change in status of the ZVENABLE bit in function 1 of the PC Card controller. 1‡ R/W ZV0_EN. PC Card socket 0 zoomed video event enable. When this bit is set, GPE is signaled on a change in status of the ZVENABLE bit in function 0 of the PC Card controller. 0‡ R/W VPP12_EN. 12 Volt VPP request event enable. When this bit is set, a GPE is signaled when software has changed the requested VPP level to or from 12 Volts for either socket. Reserved. These bits return 0s when read. Reserved. These bits return 0s when read. ‡ This bit is cleared only by the assertion of G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 81 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA compatibility registers (functions 0 and 1) The ExCA (exchangeable card architecture) registers implemented in the PCI4450 are register-compatible with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base), and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy mode base address register, which is shared by both card sockets. The offsets from this base address run contiguous from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. Refer to Figure 19 for an ExCA I/O mapping illustration. Table 49 identifies each ExCA register and its respective ExCA offset. The TI PCI4450 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus socket registers/ExCA registers base address register (PCI register 10h) at memory offset 800h. Each socket has a separate base address programmable by function. Refer to Figure 20 for an ExCA memory mapping illustration. Note that memory offsets are 800h–844h for both functions 0 and 1. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K window at memory offset 0h. The interrupt registers, as defined by the 82365SL Specification, in the ExCA register set control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI4450 to ensure that all possible PCI4450 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h. Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity. Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. Memory windows have 4K byte granularity. A bit location followed by a ‡ means that this bit is not cleared by the assertion of PRST. This bit will only be cleared by the assertion of G_RST. This is necessary to retain device context when transitioning from D3 to D0. 82 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Offset Host I/O Space PCI4450 Configuration Registers 00h Card Bus Socket / ExCA Base Address 10h PC Card A ExCA Registers Index Data 16–bit Legacy Mode Base Address 3Fh 40h 44h PC Card B ExCA Registers 7Fh Note: The 16–bit legacy mode base address register is shared by function 0 and 1 as indicated by the shading. Offset of desired register is placed in the Index register and the data from that location is returned in the data register. Figure 19. ExCA Register Access Through I/O Host Memory Space PCI1450 Configuration Registers Offset . .. Host Memory Space Offset Offset 00h CardBus Socket/ExCA Base Address 10h CardBus Socket A Registers 20h . . 00h 16-bit Legacy-Mode Base Address 44h . .. ExCA Registers Card A 800h CardBus Socket B Registers 20h 844h 800h ExCA Registers Card B Note: The CardBus Socket/ExCA Base Address Mode Register is separate for functions 0 and 1. 844h Offsets are from the CardBus socket/ExCA base Address register’s base address Figure 20. ExCA Register Access Through Memory POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 83 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 49. ExCA Registers and Offsets PCI MEMORY ADDRESS OFFSET ExCA OFFSET (CARD A) ExCA OFFSET (CARD B) 800 00 40 Interface status 801 01 41 Power control † 802† 02 42 Interrupt and general control † 803† 03 43 Card status change † 804† 04 44 Card status change interrupt configuration † 805† 05 45 Address window enable 806 06 46 I / O window control 807 07 47 I / O window 0 start-address low-byte 808 08 48 REGISTER NAME Identification and revision I / O window 0 start-address high-byte 809 09 49 I / O window 0 end-address low-byte 80A 0A 4A I / O window 0 end-address high-byte 80B 0B 4B I / O window 1 start-address low-byte 80C 0C 4C I / O window 1 start-address high-byte 80D 0D 4D I / O window 1 end-address low-byte 80E 0E 4E I / O window 1 end-address high-byte 80F 0F 4F Memory window 0 start-address low-byte 810 10 50 Memory window 0 start-address high-byte 811 11 51 Memory window 0 end-address low-byte 812 12 52 Memory window 0 end-address high-byte 813 13 53 Memory window 0 offset-address low-byte 814 14 54 Memory window 0 offset-address high-byte 815 15 55 Card detect and general control 816 16 56 Reserved 817 17 57 Memory window 1 start-address low-byte 818 18 58 Memory window 1 start-address high-byte 819 19 59 Memory window 1 end-address low-byte 81A 1A 5A Memory window 1 end-address high-byte 81B 1B 5B Memory window 1 offset-address low-byte 81C 1C 5C Memory window 1 offset-address high-byte 81D 1D 5D Global control 81E 1E 5E Reserved 81F 1F 5F Memory window 2 start-address low-byte 820 20 60 Memory window 2 start-address high-byte 821 21 61 Memory window 2 end-address low-byte 822 22 62 Memory window 2 end-address high-byte 823 23 63 Memory window 2 offset-address low-byte 824 24 64 Memory window 2 offset-address high-byte 825 25 65 Reserved 826 26 66 Reserved 827 27 67 † One or more bits in this register are cleared only by the assertion of G_RST when PME is enabled. If PME is NOT enabled, then this bit is cleared by the assertion of PRST or G_RST. 84 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 49. ExCA Registers and Offsets (continued) REGISTER NAME Memory window 3 start-address low-byte PCI MEMORY ADDRESS OFFSET ExCA OFFSET (CARD A) ExCA OFFSET (CARD B) 828 28 68 Memory window 3 start-address high-byte 829 29 69 Memory window 3 end-address low-byte 82A 2A 6A Memory window 3 end-address high-byte 82B 2B 6B Memory window 3 offset-address low-byte 82C 2C 6C Memory window 3 offset-address high-byte 82D 2D 6D Reserved 82E 2E 6E Reserved 82F 2F 6F Memory window 4 start-address low-byte 830 30 70 Memory window 4 start-address high-byte 831 31 71 Memory window 4 end-address low-byte 832 32 72 Memory window 4 end-address high-byte 833 33 73 Memory window 4 offset-address low-byte 834 34 74 Memory window 4 offset-address high-byte 835 35 75 I/O window 0 offset-address low-byte 836 36 76 I/O window 0 offset-address high-byte 837 37 77 I/O window 1 offset-address low-byte 838 38 78 I/O window 1 offset-address high-byte 839 39 79 Reserved 83A 3A 7A Reserved 83B 3B 7B Reserved 83C 3C 7C Reserved 83D 3D 7D Reserved 83E 3E 7E Reserved 83F 3F 7F Memory window page register 0 840 - - Memory window page register 1 841 - - Memory window page register 2 842 - - Memory window page register 3 843 - - Memory window page register 4 844 - - POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 85 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA identification and revision register (Index 00h) Bit 7 6 5 R/W R/W R/W R/W 1 0 0 0 Name Type 4 3 2 1 0 R/W R/W R/W R/W 0 1 0 0 ExCA identification and revision Default Register: Type: Offset: ExCA identification and revision Read/Write CardBus Socket Address + 800h: Card A ExCA Offset 00h Card B ExCA Offset 40h Default: 84h Description: This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. NOTE: If bit 5 (SUBSYRW) in the system control register is 1, then this register is read-only. Table 50. ExCA Identification and Revision Register Description BIT 86 TYPE FUNCTION 7–6 R/W IFTYPE. Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the PCI4450. The PCI4450 supports both I/O and memory 16-bit PC Cards. 5–4 R/W Reserved. These bits can be used for 82365SL emulation. 3–0 R/W 365REV. 82365SL revision. This field stores the 82365SL revision supported by the PCI4450. Host software may read this field to determine compatibility to the 82365SL register set. This field defaults to 0100b upon reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA interface status register (Index 01h) Bit 7 6 5 Type R R R R Default 0 0 x x Name 4 3 2 1 0 R R R R x x x x ExCA interface status Register: Type: Offset: ExCA interface status Read-only CardBus Socket Address + 801h: Card A ExCA Offset 01h Card B ExCA Offset 41h Default: 00XX XXXXb Description: This register provides information on current status of the PC Card interface. An x in the default bit values indicates that the value of the bit after reset depends on the state of the PC Card interface. Table 51. ExCA Interface Status Register Description BIT TYPE 7 R Reserved. This bit returns 0 when read. A write has no effect. 6 R CARDPWR. Card power. This bit indicates the current power status of the PC Card socket. This bit reflects how the ExCA power control register has been programmed. The bit is encoded as: 0 = VCC and VPP to the socket is turned off (default). 1 = VCC and VPP to the socket is turned on. 5 R READY. This bit indicates the current status of the READY signal at the PC Card interface. 0 = PC Card is not ready for a data transfer. 1 = PC Card is ready for a data transfer. R CARDWP. Card write protect. This bit indicates the current status of the WP signal at the PC Card interface. This signal reports to the PCI4450 whether or not the memory card is write protected. Further, write protection for an entire PCI4450 16-bit memory window is available by setting the appropriate bit in the ExCA memory window offset-address high byte register. 0 = WP signal is 0. PC Card is R/W. 1 = WP signal is 1. PC Card is read-only. R CDETECT2. Card detect 2. This bit indicates the status of the CD2 signal at the PC Card interface. Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket. 0 = CD2 signal is 1. No PC Card inserted. 1 = CD2 signal is 0. PC Card at least partially inserted. R CDETECT1. Card detect 1. This bit indicates the status of the CD1 signal at the PC Card interface. Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket. 0 = CD1 signal is 1. No PC Card inserted. 1 = CD1 signal is 0. PC Card at least partially inserted. R BVDSTAT. Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 0 reflects the BVD1 status, and bit 1 reflects BVD2. 00 = Battery is dead. 01 = Battery is dead. 10 = Battery is low; warning. 11 = Battery is good. When a 16-bit I/O card is inserted, this field indicates the status of the SPKR (bit 1) signal and the STSCHG (bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs. 4 3 2 1–0 FUNCTION POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 87 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA power control register (Index 02h) Bit 7 6 5 4† R/W R R R/W 0 0 0 0 Name 3† 2 1† 0† R/W R R/W R/W 0 0 0 0 ExCA power control Type Default Register: Type: Offset: ExCA power control Read-only, Read/Write CardBus Socket Address + 802h: Card A ExCA Offset 02h Card B ExCA Offset 42h Default: 00h Description: This register provides PC Card power control. Bit 7 of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit PC Card applications. Table 52. ExCA Power Control Register Description BIT TYPE 7† R/W 6–5 R 4–3† R/W 2 R 1–0† R/W FUNCTION COE. Card output enable. This bit controls the state of all of the 16-bit outputs on the PCI4450. This bit is encoded as: 0 = 16-bit PC Card outputs are disabled (default). 1 = 16-bit PC Card outputs are enabled. Reserved. These bits return 0s when read. Writes have no effect. EXCAVCC. VCC. These bits are used to request changes to card VCC. This field is encoded as: 00 = 0 V (default) 01 = 0 V Reserved 10 = 5 V 11 = 3 V Reserved. This bit returns 0 when read. A write has no effect. EXCAVPP. VPP. These bits are used to request changes to card VPP. The PCI4450 ignores this field unless VCC to the socket is enabled (i.e., 5 Vdc or 3.3 Vdc). This field is encoded as: 00 = 0 V (default) 01 = VCC 10 = 12 V 11 = 0 V Reserved † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. 88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA interrupt and general control register (Index 03h) Bit 7 6† 5† R/W R/W R/W R/W 0 0 0 0 Name Type 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA interrupt and general control Default Register: Type: Offset: ExCA interrupt and general control Read/Write CardBus Socket Address + 803h: Card A ExCA Offset 03h Card B ExCA Offset 43h Default: 00h Description: This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. Table 53. ExCA Interrupt and General Control Register Description BIT TYPE 7 R/W RINGEN. Card ring indicate enable. Enables the ring indicate function of the BVD1/RI pins. This bit is encoded as: 0 = Ring indicate disabled (default) 1 = Ring indicate enabled 6† R/W Card reset. This bit controls the 16-bit PC Card RESET signal, and allows host software to force a card reset. This bit affects 16-bit cards only. This bit is encoded as: 0 = RESET signal asserted (default) 1 = RESET signal deasserted. 5† R/W CARDTYPE. Card type. This bit indicates the PC Card type. This bit is encoded as: 0 = Memory PC Card is installed (default) 1 = I/O PC Card is installed R/W CSCROUTE. PCI interrupt – CSC routing enable bit. This bit has meaning only if the CSC interrupt routing control bit (PCI offset 93h, bit 5) is 0b. In this case, when this bit is set (high), the card status change interrupts are routed to PCI interrupts. When low the card status change interrupts are routed, using bits 7–4 in the ExCA card status change interrupt configuration register. This bit is encoded as: 0 = CSC interrupts routed by ExCA registers (default) 1 = CSC interrupts routed to PCI interrupts If the CSC interrupt routing control bit (PCI offset 93h, bit 5) is set to 1b, this bit has no meaning which is the default case. R/W INTSELECT. Card interrupt select for I/O PC Card functional interrupts. These bits select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as: 0000 = No ISA interrupt routing (default). CSC interrupts routed to PCI Interrupts. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 4 3–0 FUNCTION † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 89 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA card status-change register (Index 04h) Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 4 3† 2† 1† 0† R R R R 0 0 0 0 ExCA card status-change Register: Type: Offset: ExCA card status-change Read-only CardBus Socket Address + 804h: Card A ExCA Offset 04h Card B ExCA Offset 44h Default: 00h Description: This register reflects the status of PC Card CSC interrupt sources. The ExCA card status change interrupt configuration register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads as 0. When an interrupt source is enabled and that particular event occurs, the corresponding bit in this register is set to indicate the interrupt source. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register, as well. Resetting a bit is accomplished by one of two methods: a read of this register, or an explicit write back of 1 to the status bit. The choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the ExCA global control register. Table 54. ExCA Card Status-Change Register Description BIT TYPE 7–4 R Reserved. These bits return 0s when read. Writes have no effect. R CDCHANGE. Card detect change. This bit indicates whether a change on the CD1 or CD2 signals occurred at the PC Card interface. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as: 0 = No change detected on either CD1 or CD2 1 = A change was detected on either CD1 or CD2 R READYCHANGE. Ready change. When a 16-bit memory is installed in the socket, this bit includes whether the source of a PCI4450 interrupt was due to a change on the READY signal at the PC Card interface indicating that PC Card is now ready to accept new data. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as: 0 = No low-to-high transition detected on READY (default) 1 = Detected a low-to-high transition on READY When a 16-bit I/O card is installed, this bit is always 0. R BATWARN. Battery warning change. When a 16-bit memory card is installed in the socket, this bit indicates whether the source of a PCI4450 interrupt was due to a battery low warning condition. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as: 0 = No battery warning condition (default) 1 = Detected a battery warning condition When a 16-bit I/O card is installed, this bit is always 0. R BATDEAD. Battery dead or status change. When a 16-bit memory card is installed in the socket, this bit indicates whether the source of a PCI4450 interrupt was due to a battery dead condition. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as: 0 = STSCHG deasserted (default) 1 = STSCHG asserted Ring indicate. When the PCI4450 is configured for ring indicate operation this bit indicates the status of the RI pin. 3† 2† 1† 0† FUNCTION † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. 90 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA card status-change interrupt configuration register (Index 05h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type 4 3† 2† 1† 0† R/W R/W R/W 0 0 0 ExCA card status-change interrupt configuration Default Register: Type: Offset: ExCA card status-change interrupt configuration Read/Write CardBus Socket Address + 805h: Card A ExCA Offset 05h Card B ExCA Offset 45h Default: 00h Description: This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. Table 55. ExCA Card Status-Change Interrupt Register Description BIT TYPE FUNCTION 7–4 R/W CSCSELECT. Interrupt select for card status change. These bits select the interrupt routing for card status change interrupts. This field is encoded as: 0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) is set to 1b. In this case bit 4 of ExCA 803 is a “don’t care.” This is the default setting. 0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI offset 93h) is set to 0b. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h to 1b 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 3† R/W CDEN. Card detect enable. Enables interrupts on CD1 or CD2 changes. This bit is encoded as: 0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enable interrupts on CD1 or CD2 line changes 2† R/W READYEN. Ready enable. This bit enables/disables a low-to-high transition on the PC Card READY signal to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation 1† R/W BATWARNEN. Battery warning enable. This bit enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation 0† R/W BATDEADEN. Battery dead enable. This bit enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt. 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 91 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA address window enable register (Index 06h) Bit 7 6 5 R/W R/W R R/W 0 0 0 0 Name 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA address window enable Type Default Register: Type: Offset: ExCA address window enable Read-only, Read/Write CardBus Socket Address + 806h: Card A ExCA Offset 06h Card B ExCA Offset 46h Default: 00h Description: This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI4450 will not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the ExCA memory and I/O window start/end/offset address registers. Table 56. ExCA Address Window Enable Register Description BIT TYPE 7 R/W IOWIN1EN. I/O window 1 enable. This bit enables/disables I/O window 1 for the card. This bit is encoded as: 0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled 6 R/W IOWIN0EN. I/O window 0 enable. This bit enables/disables I/O window 0 for the card. This bit is encoded as: 0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled 5 R 4 R/W MEMWIN4EN. Memory window 4 enable. This bit enables/disables memory window 4 for the card. This bit is encoded as: 0 = memory window 4 disabled (default) 1 = memory window 4 enabled 3 R/W MEMWIN3EN. Memory window 3 enable. This bit enables/disables memory window 3 for the card. This bit is encoded as: 0 = memory window 3 disabled (default) 1 = memory window 3 enabled 2 R/W MEMWIN2EN. Memory window 2 enable. This bit enables/disables memory window 2 for the card. This bit is encoded as: 0 = memory window 2 disabled (default) 1 = memory window 2 enable R/W MEMWIN1EN. Memory window 1 enable. This bit enables/disables memory window 1 for the PC Card. This bit is encoded as: 0 = memory window 1 disabled (default) 1 = memory window 1 enabled R/W MEMWIN0EN. Memory window 0 enable. This bit enables/disables memory window 0 for the PC Card. This bit is encoded as: 0 = memory window 0 disabled (default) 1 = memory window 0 enabled 1 0 92 FUNCTION Reserved. This bit returns 0 when read. A write has no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA I/O window control register (Index 07h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA I/O window control Default Register: Type: Offset: ExCA I/O window control Read/Write CardBus Socket Address + 807h: Card A ExCA Offset 07h Card B ExCA Offset 47h Default: 00h Description: This register contains parameters related to I/O window sizing and cycle timing. Table 57. ExCA I/O Window Control Register Description BIT 7 6 5 4 3 2 1 0 TYPE FUNCTION R/W WAITSTATE1. I/O window 1 wait-state. This bit controls the I/O window 1 wait-state for 16-bit I/O accesses. This bit has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default) 1 = 16-bit cycles extended by one equivalent ISA wait state R/W ZEROWS1. I/O window 1 zero wait-state. This bit controls the I/O window 1 wait-state for 8-bit I/O accesses. NOTE: This bit has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF. 0 = 8-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three ISA cycles R/W IOSIS16W1. I/O window 1 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used the IOIS16 signal from the PC Card to determine the data width of the I/O data transfer. 0 = Data width determined by DATASIZE1, bit 4 (default) 1 = Window data width determined by IOIS16 R/W DATASIZE1. I/O window 1 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window 1 IOIS16 source bit (bit 5) is set. This bit is encoded as: 0 = Window data width is 8 bits (default) 1 = Window data width is 16 bits R/W WAITSTATE0. I/O window 0 wait-state. This bit controls the I/O window 0 wait-state for 16-bit I/O accesses. This bit has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default) 1 = 16-bit cycles extended by one equivalent ISA wait state R/W ZEROWS0. I/O window 0 zero wait-state. This bit controls the I/O window 0 wait-state for 8-bit I/O accesses. NOTE: This bit has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF. 0 = 8-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three ISA cycles R/W IOIS16W0. I/O window 0 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used the IOIS16 signal from the PC Card to determine the data width of the I/O data transfer. 0 = Data width determined by DATASIZE0, bit 0 (default) 1 = Window data width determined by IOIS16 R/W DATASIZE0. I/O window 0 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window 1 IOIS16 Source bit (bit 1) is set. This bit is encoded as: 0 = Window data width is 8 bits (default) 1 = Window data width is 16 bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 93 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA I/O window 0 & 1 start-address low-byte register (Index 08h, 0Ch) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA I/O window 0 & 1 start-address low-byte Register: Offset: ExCA I/O window 0 start-address low-byte CardBus Socket Address + 808h: Card A ExCA Offset 08h Card B ExCA Offset 48h Register: ExCA I/O window 1 start-address low-byte Offset: CardBus Socket Address + 80Ch: Card A ExCA Offset 0Ch Card B ExCA Offset 4Ch Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. ExCA I/O window 0 & 1 start-address high-byte register (Index 09h, ODh) Bit 7 6 5 Name Type Default 4 3 2 1 0 ExCA I/O window 0 & 1 start-address high-byte R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Offset: ExCA I/O window 0 start-address high-byte CardBus Socket Address + 809h: Card A ExCA Offset 09h Card B ExCA Offset 49h Register: ExCA I/O window 1 start-address high-byte Offset: CardBus Socket Address + 80Dh: Card A ExCA Offset 0Dh Card B ExCA Offset 4Dh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the start address. 94 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA I/O window 0 & 1 end-address low-byte register (Index 0Ah, 0Eh) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA I/O window 0 & 1 end-address low-byte Register: Offset: ExCA I/O window 0 end-address low-byte CardBus Socket Address + 80Ah: Card A ExCA Offset 0Ah Card B ExCA Offset 4Ah Register: ExCA I/O window 1 end-address low-byte Offset: CardBus Socket Address + 80Eh: Card A ExCA Offset 0Eh Card B ExCA Offset 4Eh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. ExCA I/O window 0 & 1 end-address high-byte register (Index 0Bh, 0Fh) Bit 7 6 5 Name Type Default 4 3 2 1 0 ExCA I/O window 0 & 1 end-address high-byte R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Offset: ExCA I/O window 0 end-address high-byte CardBus Socket Address + 80Bh: Card A ExCA Offset 0Bh Card B ExCA Offset 4Bh Register: ExCA I/O window 1 end-address high-byte Offset: CardBus Socket Address + 80Fh: Card A ExCA Offset 0Fh Card B ExCA Offset 4Fh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 95 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA memory window 0–4 start-address low-byte register (Index 10h/18h/20h/28h/30h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 start-address low-byte Register: Offset: ExCA memory window 0 start-address low-byte CardBus Socket Address + 810h: Card A ExCA Offset 10h Card B ExCA Offset 50h Register: ExCA memory window 1 start-address low-byte Offset: CardBus Socket Address + 818h: Card A ExCA Offset 18h Card B ExCA Offset 58h Register: ExCA memory window 2 start-address low-byte Offset: CardBus Socket Address + 820h: Card A ExCA Offset 20h Card B ExCA Offset 60h Register: ExCA memory window 3 start-address low-byte Offset: CardBus Socket Address + 828h: Card A ExCA Offset 28h Card B ExCA Offset 68h Register: ExCA memory window 4 start-address low-byte Offset: CardBus Socket Address + 830h: Card A ExCA Offset 30h Card B ExCA Offset 70h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of the start address. 96 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA memory window 0–4 start-address high-byte register (Index 11h/19h/21h/29h/31h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 start-address high-byte Default Register: Offset: ExCA memory window 0 start-address high-byte CardBus Socket Address + 811h: Card A ExCA Offset 11h Card B ExCA Offset 51h Register: ExCA memory window 1 start-address high-byte Offset: CardBus Socket Address + 819h: Card A ExCA Offset 19h Card B ExCA Offset 59h Register: ExCA memory window 2 start-address high-byte Offset: CardBus Socket Address + 821h: Card A ExCA Offset 21h Card B ExCA Offset 61h Register: ExCA memory window 3 start-address high-byte Offset: CardBus Socket Address + 829h: Card A ExCA Offset 29h Card B ExCA Offset 69h Register: ExCA memory window 4 start-address high-byte Offset: CardBus Socket Address + 831h: Card A ExCA Offset 31h Card B ExCA Offset 71h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory window data width and wait states are set in this register. Table 58. ExCA Memory Window 0–4 Start-Address High-Byte Register Description BIT TYPE FUNCTION 7 R/W DATASIZE. This bit controls the memory window data width. This bit is encoded as: 0 = Window data width is 8 bits (default) 1 = Window data width is 16 bits 6 R/W ZEROWAIT. Zero wait-state. This bit controls the memory window wait state for 8- and 16-bit accesses. This wait state timing emulates the ISA wait-state used by the 82365SL-DF. This bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three ISA cycles 16-bit cycles reduce to the equivalent of two ISA cycles. 5–4 R/W SCRATCH. Scratch pad bits. These bits have no effect on memory window operation. 3–0 R/W STAHN. Start address high-nibble. These bits represent the upper address bits A23–A20 of the memory window start address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 97 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA memory window 0–4 end-address low-byte register (Index 12h/1Ah/22h/2Ah/32h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 end-address low-byte Register: Offset: ExCA memory window 0 end-address low-byte CardBus Socket Address + 812h: Card A ExCA Offset 12h Card B ExCA Offset 52h Register: ExCA memory window 1 end-address low-byte Offset: CardBus Socket Address + 81Ah: Card A ExCA Offset 1Ah Card B ExCA Offset 5Ah Register: ExCA memory window 2 end-address low-byte Offset: CardBus Socket Address + 822h: Card A ExCA Offset 22h Card B ExCA Offset 62h Register: ExCA memory window 3 end-address low-byte Offset: CardBus Socket Address + 82Ah: Card A ExCA Offset 2Ah Card B ExCA Offset 68h Register: ExCA memory window 4 end-address low-byte Offset: CardBus Socket Address + 832h: Card A ExCA Offset 32h Card B ExCA Offset 72h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of the end address. 98 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA memory window 0–4 end-address high-byte register (Index 13h/1Bh/23h/2Bh/33h) Bit 7 6 5 R/W R/W R R R/W 0 0 0 0 0 Name 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 end-address high-byte Type Default Register: Offset: ExCA memory window 0 end-address high-byte CardBus Socket Address + 813h: Card A ExCA Offset 13h Card B ExCA Offset 53h Register: ExCA memory window 1 end-address high-byte Offset: CardBus Socket Address + 81Bh: Card A ExCA Offset 1Bh Card B ExCA Offset 5Bh Register: ExCA memory window 2 end-address high-byte Offset: CardBus Socket Address + 823h: Card A ExCA Offset 23h Card B ExCA Offset 63h Register: ExCA memory window 3 end-address high-byte Offset: CardBus Socket Address + 82Bh: Card A ExCA Offset 2Bh Card B ExCA Offset 6Bh Register: ExCA Memory window 4 end-address high-byte Offset: CardBus Socket Address + 833h: Card A ExCA Offset 33h Card B ExCA Offset 73h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory window wait states are set in this register. Table 59. ExCA Memory Window 0–4 End-Address High-Byte Register Description BIT TYPE FUNCTION 7–6 R/W MEMWS. Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits. 5–4 R 3–0 R/W Reserved. These bits return 0s when read. Writes have no effect. ENDHN. End address high-nibble. These bits represent the upper address bits A23–A20 of the memory window and address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 99 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA memory window 0–4 offset-address low-byte register (Index 14h/1Ch/24h/2Ch/34h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 offset-address low-byte Register: Offset: ExCA memory window 0 offset-address low-byte CardBus Socket Address + 814h: Card A ExCA Offset 14h Card B ExCA Offset 54h Register: ExCA memory window 1 offset-address low-byte Offset: CardBus Socket Address + 81Ch: Card A ExCA Offset 1Ch Card B ExCA Offset 5Ch Register: ExCA memory window 2 offset-address low-byte Offset: CardBus Socket Address + 824h: Card A ExCA Offset 24h Card B ExCA Offset 64h Register: ExCA memory window 3 offset-address low-byte Offset: CardBus Socket Address + 82Ch: Card A ExCA Offset 2Ch Card B ExCA Offset 6Ch Register: ExCA memory window 4 offset-address low-byte Offset: CardBus Socket Address + 834h: Card A ExCA Offset 34h Card B ExCA Offset 74h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of the offset address. 100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA memory window 0–4 offset-address high-byte register (15h/1Dh/25h/2Dh/35h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 offset-address high-byte Default Register: Offset: ExCA memory window 0 offset-address high-byte CardBus Socket Address + 815h: Card A ExCA Offset 15h Card B ExCA Offset 55h Register: ExCA memory window 1 offset-address high-byte Offset: CardBus Socket Address + 81Dh: Card A ExCA Offset 1Dh Card B ExCA Offset 5Dh Register: ExCA memory window 2 offset-address high-byte Offset: CardBus Socket Address + 825h: Card A ExCA Offset 25h Card B ExCA Offset 65h Register: ExCA memory window 3 offset-address high-byte Offset: CardBus Socket Address + 82Dh: Card A ExCA Offset 2Dh Card B ExCA Offset 6Dh Register: ExCA memory window 4 offset-address high-byte Offset: CardBus Socket Address + 835h: Card A ExCA Offset 35h Card B ExCA Offset 75h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The lower 6 bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. Table 60. ExCA Memory Window 0–4 Offset-Address High-Byte Register Description BIT TYPE FUNCTION 7 R/W WINWP. Write protect. This bit specifies whether write operations to this memory window are enabled. This bit is encoded as: 0 = Write operations are allowed (default) 1 = Write operations are not allowed 6 R/W REG. This bit specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as: 0 = Memory window is mapped to common memory (default) 1 = Memory window is mapped to attribute memory 5–0 R/W OFFHB. Offset address high-byte. These bits represent the upper address bits A25–A20 of the memory window offset address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 101 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA I/O window 0 & 1 offset-address low-byte register (Index 36h, 38h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA I/O window 0 & 1 offset-address low-byte Register: Offset: ExCA I/O window 0 offset-address low-byte CardBus Socket Address + 836h: Card A ExCA Offset 36h Card B ExCA Offset 76h Register: ExCA memory window 1 offset-address low-byte Offset: CardBus Socket Address + 838h: Card A ExCA Offset 38h Card B ExCA Offset 78h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0. ExCA I/O window 0 & 1 offset-address high-byte register (Index 37h, 39h) Bit 7 6 5 Name Type Default 4 3 2 1 0 ExCA I/O window 0 & 1 offset-address high-byte R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Offset: ExCA I/O window 0 offset-address high-byte CardBus Socket Address + 837h: Card A ExCA Offset 37h Card B ExCA Offset 77h Register: ExCA memory window 1 offset-address high-byte Offset: CardBus Socket Address + 839h: Card A ExCA Offset 39h Card B ExCA Offset 79h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the offset address. 102 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA card detect and general control register (Index 16h) Bit 7 6 5 Type R R W R/W Default X X 0 0 Name 4 3 2 1 0 R R R/W R 0 0 0 0 ExCA card detect and general control Register: Type: Offset: ExCA card detect and general control Read-only, Write-only, Read/Write CardBus Socket Address + 816h: Card A ExCA Offset 16h Card B ExCA Offset 56h Default: XX00 0000b Description: This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the VS1 and VS2 signals at the PC Card interface. Table 61 describes each bit in the ExCA card detect and general control register. Table 61. ExCA Card Detect and General Control Register Description BIT TYPE FUNCTION 7 R VS2STAT. VS2. This bit reports the current state of the VS2 signal at the PC Card interface, and, therefore, does not have a default value. 0 = VS2 is low 1 = VS2 is high 6 R VS1STAT. VS1. This bit reports the current state of the VS1 signal at the PC Card interface, and, therefore, does not have a default value. 0 = VS1 is low 1 = VS1 is high W SWCSC. Software card detect interrupt. If the card detect enable bit in the ExCA card status change interrupt configuration register is set, then writing a 1 to this bit causes a card detect card status change interrupt for the associated card socket. If the card detect enable bit is cleared to 0 in the ExCA card status change interrupt configuration register, then writing a 1 to the software card detect interrupt bit has no effect. This bit is write-only. A read operation of this bit always returns 0. Writing a 1 to this bit also clears it. If bit 2 of the ExCA global control register is set and a 1 is written to clear bit 3 of the ExCA card status change interrupt register, then this bit also gets cleared. 4 R/W CDRESUME. Card detect resume enable. If this bit is set to 1 and once a card detect change has been detected on the CD1 and CD2 inputs, then the RI_OUT output will go from high to low. The RI_OUT remains low until the card status change bit in the ExCA card status change register is cleared. If this bit is a 0, then the card detect resume functionality is disabled. 0 = Card detect resume disabled (default) 1 = Card detect resume enabled 3–2 R 5 1 R/W 0 R Reserved. These bits return 0s when read. Writes have no effect. REGCONFIG. Register configuration upon card removal. This bit controls how the ExCA registers for the socket react to a card removal event. This bit is encoded as: 0 = No change to ExCA registers upon card removal (default) 1 = Reset ExCA registers upon card removal Reserved. This bit returns 0 when read. A write has no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 103 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA global control register (Index 1Eh) Bit 7 6 5 4 Type R R R R/W Default 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA global control Register: Type: Offset: ExCA global control Read-only, Read/Write CardBus Socket Address + 81Eh: Card A ExCA Offset 1Eh Card B ExCA Offset 5Eh Default: 00h Description: This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in this register are retained for 82365SL compatibility. Table 62. ExCA Global Control Register Description BIT TYPE 7–5 R Reserved. These bits return 0s when read. Writes have no effect. R/W INTMODEB. Level/edge interrupt mode select – card B. This bit selects the signaling mode for the PCI4450 host interrupt for Card B interrupts. This bit is encoded as: 0 = Host interrupt is edge mode (default) 1 = Host interrupt is level mode R/W INTMODEA. Level/edge interrupt mode select – card A. This bit selects the signaling mode for the PCI4450 host interrupt for card A interrupts. This bit is encoded as: 0 = Host interrupt is edge mode (default) 1 = Host interrupt is level mode 2 R/W IFCMODE. Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA card status change register. This bit is encoded as: 0 = Interrupt flags cleared by read of CSC register (default) 1 = Interrupt flags cleared by explicit write back of 1 1 R/W 4 3 0 104 FUNCTION R/W CSCMODE. Card status change level/edge mode select. This bit selects the signaling mode for the PCI4450 host interrupt for card status changes. This bit is encoded as: 0 = Host interrupt is edge mode (default) 1 = Host interrupt is level mode PWRDWN. PWRDWN mode select. When the bit is set to 1, the PCI4450 is in power-down mode. In power-down mode the PCI4450 card outputs are placed in a high-impedance state until an active cycle is executed on the card interface. Followingan active cycle the outputs are again placed in a high-impedance state. The PCI4450 still receives DMA requests, functional interrupts and/or card status change interrupts; however, an actual card access is required to “wake up” the interface. This bit is encoded as: 0 = Power-down mode disabled (default) 1 = Power-down mode enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ExCA memory window 0–4 page register (Index 40h, 41h, 42h, 43h, 44h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA memory window 0–4 page Register: Type: Offset: Default: Description: ExCA memory window 0–4 page Read/Write CardBus Socket Address + 840h, 841h, 842h, 843h, 844h 00h The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software may locate 16-bit memory windows in any one of 256 16M-byte regions in the 4 Gigabyte PCI address space. These registers are only accessible when the ExCA registers are memory mapped, that is, these registers may not be accessed using the index/data I/O scheme. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 105 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 CardBus socket registers (functions 0 and 1) The PCMCIA CardBus Specification requires a CardBus socket controller to provide five 32-bit registers which report and control the socket-specific functions. The PCI4450 provides the CardBus socket/ExCA base address register (PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each socket has a separate base address register for accessing the CardBus socket registers, see Figure 21 below. Table 63 illustrates the location of the socket registers in relation to the CardBus socket/ExCA base address. Table 63. CardBus Socket Registers REGISTER NAME OFFSET Socket event † 00h Socket mask † 04h Socket present state † 08h Socket force event 0Ch Socket control † 10h Reserved 14h Reserved 18h Reserved 1Ch Socket power management 20h † One or more bits in this register are cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. Host Memory Space PCI1450 Configuration Registers Offset . .. Offset 00h CardBus Socket/ExCA Base Address 10h CardBus Socket A Registers . . 16-bit Legacy-Mode Base Address Host Memory Space 20h 00h 44h . .. ExCA Registers Card A 800h CardBus Socket B Registers 20h 844h 800h ExCA Registers Card B Note: The CardBus Socket/ExCA Base Address Mode Register is separate for functions 0 and 1. Figure 21. Accessing CardBus Socket Registers Through PCI Memory 106 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 844h PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 socket event register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3† 2† 1† 0† Socket event Name Socket event Type R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: R/WC R/WC R/WC R/WC 0 0 0 0 Socket event Read-only, Read/Write to Clear CardBus Socket Address + 00h 0000 0000h This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They may be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software needs to clear this register before enabling interrupts. If it is not cleared and interrupts are enabled, then an interrupt is generated based on any bit set and not masked. Table 64. Socket Event Register Description BIT TYPE 31–4 R FUNCTION 3† R/WC PWREVENT. Power cycle. This bit is set when the PCI4450 detects that the PWRCYCLE bit in the socket present state register has changed. This bit is cleared by writing a 1. 2† R/WC CD2EVENT. CCD2. This bit is set when the PCI4450 detects that the CDETECT2 field in the socket present state register has changed. This bit is cleared by writing a 1. 1† R/WC CD1EVENT. CCD1. This bit is set when the PCI4450 detects that the CDETECT1 field in the socket present state register has changed. This bit is cleared by writing a 1. 0† R/WC CSTSEVENT. CSTSCHG. This bit is set when the CARDSTS field in the socket present state register has changed state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG signal. For 16-bit PC Cards, this bit is set on both transitions of the CSTSCHG signal. This bit is reset by writing a 1. Reserved. These bits return 0s when read. † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 107 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 socket mask register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3† 2† 1† 0† Socket mask Name Socket mask Type R R R R R R R R R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket mask Read-only, Read/Write CardBus Socket Address + 04h 0000 0000h This register allows software to control the CardBus card events which generate a status change interrupt. Table 65 below describes each bit in this register. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register. Table 65. Socket Mask Register Description BIT TYPE 31–4 R 3† R/W PWRMASK. Power cycle. This bit masks the PWRCYCLE bit in the socket present state register from causing a status change interrupt. 0 = PWRCYCLE event will not cause a CSC interrupt (default) 1 = PWRCYCLE event will cause a CSC interrupt R/W CDMASK. Card detect mask. These bits mask the CDETECT1 and CDETECT2 bits in the socket present state register from causing a CSC interrupt. 00 = Insertion/removal will not cause CSC interrupt (default) 01 = Reserved (undefined) 10 = Reserved (undefined) 11 = Insertion/removal will cause CSC interrupt R/W CSTSMASK. CSTSCHG mask. This bit masks the CARDSTS field in the socket present state register from causing a CSC interrupt. 0 = CARDSTS event will not cause CSC interrupt (default) 1 = CARDSTS event will cause CSC interrupt 2–1† 0† FUNCTION Reserved. These bits return 0s when read. † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. 108 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 socket present state register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 1 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket present state Name Socket present state Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X Register: Type: Offset: Default: Description: Socket present state Read-only CardBus Socket Address + 08h 3000 00XXh This register reports information about the socket interface. Writes to the socket force event register are reflected here as well as general socket interface status. Information about PC Card VCC support and card type is only updated at each insertion. Also note that the PCI4450 uses the CCD1 and CCD2 signals during card identification, and changes on these signals during this operation are not reflected in this register. Table 66. Socket Present State Register Description BIT TYPE FUNCTION 31 R YVSOCKET. YV socket. This bit indicates whether or not the socket can supply VCC = Y.YV to PC Cards. The PCI4450 does not support Y.YV VCC; therefore, this bit is always reset unless overridden by the socket force event register. This bit is hardwired to 0. 30 R XVSOCKET. XV socket. This bit indicates whether or not the socket can supply VCC = X.XV to PC Cards. The PCI4450 does not support X.XV VCC; therefore, this bit is always reset unless overridden by the socket force event register. This bit is hardwired to 0. 29 R 3VSOCKET. 3-V socket. This bit indicates whether or not the socket can supply VCC = 3.3 Vdc to PC Cards. The PCI4450 does support 3.3 V VCC; therefore, this bit is always set unless overridden by the socket force event register. 28 R 5VSOCKET. 5-V socket. This bit indicates whether or not the socket can supply VCC = 5.0 Vdc to PC Cards. The PCI4450 does support 5.0 V VCC; therefore, this bit is always 1 unless overridden by the device control register (bit 6). 27–14 R Reserved. These bits return 0s when read. 13 R YVCARD. YV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y Vdc. This bit can be set by writing to the corresponding bit in the socket force event register. 12 R XVCARD. XV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = X.X Vdc. This bit can be set by writing to the corresponding bit in the socket force event register. 11 R 3VCARD. 3-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 Vdc. This bit can be set by writing to the corresponding bit in the socket force event register. 10 R 5VCARD. 5-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 5.0 Vdc. R BADVCCREQ. Bad VCC request. This bit indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 109 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 66. Socket Present State Register Description (continued) BIT TYPE FUNCTION 8 R DATALOST. Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI4450. 0 = Normal operation (default) 1 = Potential data loss due to card removal R NOTACARD. Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not updated until a valid PC Card is inserted into the socket. 0 = Normal operation (default) 1 = Unrecognizable PC Card detected 6 R IREQCINT. READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC Card interface. 0 = READY(IREQ)//CINT is low 1 = READY(IREQ)//CINT is high 5 R CBCARD. CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 4 R 16BITCARD. 16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 3 R PWRCYCLE. Power cycle. This bit indicates that the status of each card powering request. This bit is encoded as: 0 = Socket is powered down (default) 1 = Socket is powered up 2 R CDETECT2. CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD2 is low (PC Card may be present) 1 = CCD2 is high (PC Card not present) 1 R CDETECT1. CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD1 is low (PC Card may be present) 1 = CCD1 is high (PC Card not present) 0 R CARDSTS. CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface. 0 = CSTSCHG is low 1 = CSTSCHG is high 7 110 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 socket force event register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket force event Name Socket force event Type R W W W W W W W W R W W W W W W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket force event Read-only, Write-only CardBus Socket Address + 0Ch 0000 XXXXh This register is used to force changes to the socket event register and the socket present state register. The CVSTEST bit in this register must be written when forcing changes that require card interrogation. Table 67. Socket Force Event Register Description BIT TYPE 31–15 R Reserved. These bits return 0s when read. FUNCTION 14 W CVSTEST. Card VS test. When this bit is set, the PCI4450 reinterrogates the PC Card, updates the socket present state register, and re-enables the socket power control. 13 W FYVCARD. Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 12 W FXVCARD. Force XV card. Writes to this bit cause the XVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 11 W F3VCARD. Force 3-V card. Writes to this bit cause the 3VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 10 W F5VCARD. Force 5-V card. Writes to this bit cause the 5VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 9 W FBADVCCREQ. Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register can be made by writing this bit. 8 W FDATALOST. Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register to be written. 7 W FNOTACARD. Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register to be written. 6 R Reserved. This bit returns 0 when read. 5 W FCBCARD. Force CardBus card. Writes to this bit cause the CBCARD bit in the socket present state register to be written. 4 W F16BITCARD. Force 16-bit card. Writes to this bit cause the 16BITCARD bit in the socket present state register to be written. 3 W FPWRCYCLE. Force power cycle. Writes to this bit cause the PWREVENT bit in the socket event register to be written, and the PWRCYCLE bit in the socket present state register is unaffected. 2 W FCDETECT2. Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register to be written, and the CDETECT2 bit in the socket present state register is unaffected. 1 W FCDETECT1. Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register to be written, and the CDETECT1 bit in the socket present state register is unaffected. 0 W FCARDSTS. Force CSTSCHG. Writes to this bit cause the CSTSEVENT bit in the socket event register to be written. The CARDSTS bit in the socket present state register is unaffected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 111 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 socket control register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6† 5† 4† 3 2† 1† 0† Socket control Name Socket control Type R R R R R R R R R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket control Read-only, Read/Write CardBus Socket Address + 10h 0000 0000h This register provides control of the voltages applied to the socket’s VPP and VCC. The PCI4450 ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. Table 68. Socket Control Register Description BIT TYPE 31–8 R FUNCTION Reserved. These bits return 0s when read. R/W STOPCLK. This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock to the CardBus Card: 0 = The PCI4450 Clock run master will try to stop the clock to the CardBus Card under the following two conditions: The CardBus interface is idle for 8 clocks and There is a request from the PCI master to stop the PCI clock. 1 = The PCI4450 clock run master will try to stop the clock to the CardBus card under the following condition: The CardBus interface is idle for 8 clocks. In summary, if this bit is set to1, then the CardBus controller will try to stop the clock to the CardBus card independent of the PCI clock run signal. The only condition that has to be satisfied in this case is the CardBus interface sampled idle for 8 clocks. 6–4† R/W VCCCTRL. VCC control. These bits are used to request card VCC changes. 000 = Request power off (default) 001 = Reserved 010 = Request VCC = 5.0 V 011 = Request VCC = 3.3 V 100 = Request VCC = X.XV 101 = Request VCC = Y.YV 110 = Reserved 111 = Reserved 3 R 7 2–0† R/W Reserved. This bit returns 0 when read. VPPCTRL. VPP control. These bits are used to request card VPP changes. 000 = Request power off (default) 001 = Request VPP = 12.0 V 010 = Request VPP = 5.0 V 011 = Request VPP = 3.3 V 100 = Request VPP = X.XV 101 = Request VPP = Y.YV 110 = Reserved 111 = Reserved † This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST. 112 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 socket power management register Bit 31 30 29 28 27 26 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name 25 24 23 22 21 20 19 18 17 16 R R R R R R R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Socket power management Name Socket power management Type R R R R R R R R R R R R R R R R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket power management Read-only, Read/Write CardBus Socket Address + 20h 0000 0000h This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. Table 69. Socket Power Management Register Description BIT TYPE 31–26 R Reserved. These bits return 0s when read. 25 R SKTACCES. Socket access status. This bit provides information on when a socket access has occurred. This bit is cleared by a read access. 0 = No PC Card access has occurred (default) 1 = PC Card has been accessed 24 R SKTMODE. Socket mode status. This bit provides clock mode information. 0 = Normal clock operation 1 = Clock frequency has changed 23–17 R Reserved. These bits return 0s when read. 16 R/W 15–1 R 0 R/W FUNCTION CLKCTRLEN. CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL). 0 = Clock control disabled (default) 1 = Clock control enabled Reserved. These bits return 0s when read. This bit determines whether the CardBus clock run master stops the CCLK or slows the clock when it detects idle activity on the CardBus interface. 0 = Stop the CardBus clock using the clock run protocol when there is no activity on the CardBus interface (default). 1 = Divide PCI clock by 16 using the clock run protocol when there is no activity on the CardBus interface. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 113 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 distributed DMA (DDMA) registers The DMA base address, programmable in PCI configuration space at offset 98h, points to a 16-byte region in PCI I/O space where the DDMA registers reside. Table 70 summarizes the names and locations of these registers. These registers are identical in function, but different in location from the Intel 8237 DMA controller. The similarity between the register models retains some level of compatibility with legacy DMA and simplifies the translation required by the master DMA device when forwarding legacy DMA writes to DMA channels. These PCI4450 DMA register definitions are identical to those registers of the same name in the 8237 DMA controller; however, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment. In such cases, the PCI4450 will implement these obsolete register bits as nonfunctional, read-only bits. The reserved registers shown in Table 70 are implemented as read-only, and return 0s when read. Writes to reserved registers have no effect. Table 70. Distributed DMA Registers TYPE R W Current address Reser ed Reserved Page Reser ed Reserved Reser ed Reserved 114 00h Base address R W DMA BASE ADDRESS OFFSET REGISTER NAME Current count R N/A W Mode R Multichannel W Mask Reser ed Reserved Reserved 04h Base count N/A Status Request Command N/A Master clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Reserved 08h 0Ch PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 DMA current address / base address register Bit 15 14 13 R/W R/W R/W R/W Default 0 0 0 0 Bit 7 6 5 4 Name Type Default 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 DMA current address/base address Name Type 12 DMA current address/base address R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Size: Description: DMA current address/base address Read/Write DMA Base Address + 00h 00 0000h Two bytes This register is used to set the starting (base) memory address of a DMA transfer. Reads from this register indicate the current memory address of a direct memory transfer. For the 8-bit DMA transfer mode, the DMA current address register contents are presented on AD15–0 of the PCI bus during the address phase. Bits 7–0 of the DMA page register are presented on AD23–AD16 of the PCI bus during the address phase. For the 16-bit DMA transfer mode, the DMA current address register contents are presented on AD16–AD1 of the PCI bus during the address phase, and AD0 is driven to logic ‘0’. Bits 7–1 of the DMA page register are presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored. DMA page register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Name Type Default DMA page Register: Type: Offset: Default: Size: Description: DMA page Read/Write DMA Base Address + 02h 0000h One byte This register is used to set the upper byte of the address of a DMA transfer. Details of the address represented by this register are explained in the DMA current address/base address register, above. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 115 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 DMA current count / base count register Bit 15 14 13 R/W R/W R/W R/W Default 0 0 0 0 Bit 7 6 5 4 Name 12 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 DMA current count/base count Type Name DMA current count/base count Type R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Default Register: Type: Offset: Default: Size: Description: DMA current count/base count Read/Write DMA Base Address + 04h 0000h Two bytes This register is used to set the total transfer count, in bytes, of a direct memory transfer. Reads from this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after each transfer. Likewise, the count is decremented by 2 in 16-bit transfer mode. DMA command register Bit 7 6 5 4 Type R R R Default 0 0 0 Name 3 2 1 0 R R R/W R R 0 0 0 0 0 DMA command Register: Type: Offset: Default: Size: Description: DMA command Read-only, Read/Write DMA Base Address + 08h 0000h One byte This register is used to enable and disable the controller; all other bits are reserved. Table 71. DDMA Command Register Description BIT TYPE 7–3 R 2 R/W 1–0 R 116 FUNCTION Reserved. These bits return 0s when read. DMA controller enable. This bit enables and disables the distributed DMA slave controller in the PCI4450, and defaults to the enabled state. 0 = DMA controller enabled (default) 1 = DMA controller disabled Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 DMA status register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 0 Name DMA status Register: Type: Offset: Default: Size: Description: DMA status Read-only DMA Base Address + 08h 0000h One byte This register indicates the terminal count and DMA request (DREQ) status. Table 72. DMA Status Register Description BIT TYPE FUNCTION 7–4 R DREQSTAT. Channel request. In the 8237, these bits indicate the status of the DREQ signal of each DMA channel. In the PCI4450, these bits indicate the DREQ status of the single socket being serviced by this register. All four bits are set when the PC Card asserts its DREQ signal, and are reset when DREQ is deasserted. The status of the mask bit in the DMAmultichannel mask register has no effect on these bits. 3–0 R TC. Channel terminal count. The 8327 uses these bits to indicate the TC status of each of its four DMA channels. In the PCI4450, these bits report information about just a single DMA channel; therefore, all four of these register bits indicate the TC status of the single socket being serviced by this register. All four bits are set when the terminal count (TC) is reached by the DMA channel. These bits are reset when read or when the DMA channel is reset DMA request register Bit 7 6 5 4 Name 3 2 1 0 DMA request Type W W W W W W W W Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Size: Description: DMA request Write-only DMA Base Address + 09h 0000h One byte This register is used to request a DDMA transfer through software. Any write to this register enables software requests. This register is to be used in block mode only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 117 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 DMA mode register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R 0 0 0 0 0 Name DMA mode Type Default Register: Type: Offset: Default: Size: Description: DMA mode Read-only, Read/Write DMA Base Address + 0Bh 0000h One byte This register is used to set the DMA transfer mode. Table 73. DDMA Mode Register Description BIT TYPE FUNCTION R/W DMAMODE. Mode select bits. The PCI4450 uses these bits to determine the transfer mode. 00 = Demand mode select (default) 01 = Single mode select 10 = Block mode select 11 = Reserved 5 R/W INCDEC. Address increment/decrement. The PCI4450 uses this register bit to select the memory address in the DMA current address/base address register to increment or decrement after each data transfer. This is in accordance with the 8237 use of this register bit, and is encoded as follows: 0 = Addresses increment (default) 1 = Addresses decrement 4 R/W AUTOINIT. Auto-initialization bit. 0 = Auto-initialization disabled (default) 1 = Auto-initialization enabled 3–2 R/W XFERTYPE. Transfer type. These bits select the type of direct memory transfer to be performed. A memory write transfer moves data from the PCI4450 PC Card interface to memory, and a memory read transfer moves data from memory to the PCI4450 PC Card interface. The field is encoded as: 00 = No transfer selected (default) 01 = Write transfer 10 = Read transfer 11 = Reserved 1–0 R 7–6 118 Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 DMA master clear register Bit 7 6 5 4 Type W W W W Default 0 0 0 0 Name 3 2 1 0 W W W W 0 0 0 0 DMA master clear Register: Type: Offset: Default: Size: Description: DMA master clear Write-only DMA Base Address + 0Dh 0000h One byte This register is used to reset the DDMA controller, and resets all DDMA registers. DMA multichannel mask register Bit 7 6 5 Name 4 3 2 1 0 DMA multichannel mask Type R R R R R R R R/W Default 0 0 0 0 0 0 0 1 Register: Type: Offset: Default: Size: Description: DMA multichannel mask Read-only, Read/Write DMA Base Address + 0Fh 0000h One byte The PCI4450 uses only the least significant bit of this register to mask the PC Card DMA channel. The PCI4450 sets the mask bit when the PC Card is removed. Host software is responsible for either resetting the socket’s DMA controller or re-enabling the mask bit. Table 74. DDMA MultiChannel Mask Register Description BIT TYPE 7–1 R 0 R/W FUNCTION Reserved. These bits return 0s when read. MASKBIT. Mask select bit. This bit masks incoming DREQ signals from the PC Card. When set, the socket ignores DMA requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced normally. 0 = DDMA service provided on card DREQ 1 = Socket DREQ signal ignored (default) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 119 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 OHCI-Lynx controller programming model This section describes the internal registers used to program the link function, including both PCI configuration registers and Open HCI registers. All registers are detailed in the same format. A brief description is provided for each register, followed by the register offset and a bit-table describing the reset state for each register. A bit description table is typically included that indicates bit field names, a detailed field description, and field access tags. Table 75 describes the field access tags. Table 75. Bit Field Access Tag Descriptions ACCESS TAG NAME R Read Field may be read by software. W Write Field may be written by software to any value. S Set C Clear U Update MEANING Field may be set by a write of 1. Writes of 0 have no effect. Field may be cleared by a write of 1. Writes of 0 have no effect. Field may be autonomously updated by the PCI4450. PCI configuration registers The PCI4450 link function configuration header is compliant with the PCI Specification as a standard header. Table 76 illustrates the PCI configuration header which includes both the predefined portion of the configuration space and the user definable registers. The registers that are labeled Reserved are read-only returning 0 when read and are not applicable to the link function or have been reserved by the PCI specification for future use. Table 76. PCI Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID Status 00h Command Class code BIST Header type Latency timer 04h Revision ID 08h Cache line size 0Ch Open HCI registers base address 10h TI extension registers base address 14h Reserved 18h Reserved 1Ch Reserved 20h Reserved 24h Reserved 28h Subsystem ID Subsystem vendor ID Reserved 30h Reserved Capabilites pointer 34h Interrupt pin Interrupt line 3Ch Next item pointer Capability ID Reserved Max latency 38h Min grant PCI OHCI control Power management capabilities PM data 120 40h PMCSR_BSE Power management CSR 44h 48h Reserved 4C–ECh PCI miscellaneous configuration F0h Link_enhancements F4h Subsystem ID alias GPIO3 2Ch Subsystem vendor ID alias GPIO2 GPIO1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GPIO0 F8h FCh PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 vendor ID register Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Type: Offset: Default: Description: Vender ID Read-only 00h 104Ch This 16-bit read-only register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. device ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 1 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 1 0 0 0 1 Device ID Register: Type: Offset: Default: Description: Device ID register Read-only 02h 8011h This 16-bit read-only register contains a value assigned to the PCI4450 by Texas Instruments. The device identification for the PCI4450 OHCI controller function is 8011h. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 121 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI command register Bit 15 14 13 12 11 10 9 Type R R R R R R R R/W Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R/W R R/W R R/W R/W R 0 0 0 0 0 0 0 0 PCI command Register: Type: Offset: Default: Description: PCI command Read-only, Read/Write 04h 0000h The command register provides control over the PCI4450 link interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Table 77. PCI Command Register Description BIT 15–10 122 FIELD NAME TYPE DESCRIPTION RSVD R Reserved. These bits return 0s when read. 9 FBB_ENB R Fast back-to-back enable. The PCI4450 will not generate fast back to back transactions, thus this bit returns 0 when read. 8 SERR_ENB R/W SERR enable. When set, the PCI4450 SERR driver is enabled. SERR can be asserted after detecting an address parity error on the PCI bus. 7 STEP_ENB R Address/data stepping control. The PCI4450 does not support address/data stepping, and this bit is hardwired to 0. 6 PERR_ENB R/W Parity error enable. When set, the PCI4450 is enabled to drive PERR response to parity errors through the PERR signal. 5 VGA_ENB R VGA palette snoop enable. The PCI4450 does not feature VGA palette snooping. This bit returns 0 when read. 4 MWI_ENB R/W Memory write and invalidate enable. When set, the PCI4450 is enabled to generate MWI PCI bus commands. If reset, the PCI4450 will generate memory write commands instead. 3 SPECIAL R Special cycle enable. The PCI4450 function does not respond to special cycle transactions. This bit returns 0 when read. 2 MASTER_ENB R/W Bus master enable. When set, the PCI4450 is enabled to initiate cycles on the PCI bus. 1 MEMORY_ENB R/W Memory response enable. Setting this bit enables the PCI4450 to respond to memory cycles on the PCI bus. This bit must be set to access OHCI registers. 0 IO_ENB R I/O space enable. The PCI4450 link does not implement any I/O mapped functionality; thus, this bit returns 0 when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI status register Bit 15 14 13 12 11 10 9 8 RCU RCU RCU RCU RCU R R RCU 0 0 0 0 0 0 1 0 Name Type Default 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 1 0 0 0 0 PCI status Register: Type: Offset: Default: Description: PCI status Read-only, Read/Clear/Update 06h 0210h PCI Bus Specification, as seen in the bit descriptions. Table 78. PCI Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PAR_ERR RCU Detected parity error. This bit is set when a parity error is detected, either address or data parity errors. 14 SYS_ERR RCU Signaled system error. This bit is set when SERR is enabled and the PCI4450 signaled a system error to the host. 13 MABORT RCU Received master abort. This bit is set when a cycle initiated by the PCI4450 on the PCI bus has been terminated by a master abort. 12 TABORT_REC RCU Received target abort. This bit is set when a cycle initiated by the PCI4450 on the PCI bus was terminated by a target abort. 11 TABORT_SIG RCU Signaled target abort. This bit is set by the PCI4450 when it terminates a transaction on the PCI bus with a target abort. R DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b indicating that the PCI4450 asserts this signal at a medium speed on non-configuration cycle accesses. 10–9 PCI_SPEED 8 DATAPAR RCU 7 FBB_CAP R Fast back-to-back capable. The PCI4450 cannot accept fast back-to-back transactions; thus, this bit is hardwired to 0. 6 UDF R UDF supported. The PCI4450 does not support the user definable features; thus, this bit is hardwired to 0. 5 66MHZ R 66 MHz capable. The PCI4450 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is hardwired to 0. 4 CAPLIST R Capabilities list. This bit returns 1 when read, and indicates that capabilities additional to standard PCI are implemented. The linked list of PCI power management capabilities is implemented in this function. RSVD R Reserved. These bits return 0s when read. 3–0 Data parity error detected. This bit is set when the following conditions have been met: a. PERR was asserted by any PCI device including the PCI4450 b. The PCI4450 was the bus master during the data parity error c. The parity error response bit is set in the command register POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 123 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 class code and revision ID register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Class code and revision ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Class code and revision ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 X Register: Type: Offset: Default: Description: Class code and revision ID Read-only 08h 0C00 100Xh This read-only register categorizes the PCI4450 as a serial bus controller (0Ch), controlling an IEEE1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the lower byte. Table 79. Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31–24 BASECLASS R Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus controller. 23–16 SUBCLASS R Sub class. This field returns 00h when read, which specifically classifies the function as controlling a IEEE1394 serial bus. 15–8 PGMIF R Programming interface. This field returns 10h when read, which indicates that the programming model is compliant with the 1394 OHCI specification. 7–0 CHIPREV R Silicon revision. This field returns the silicon revision of the PCI4450. 124 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 latency timer and class cache line size register Bit 15 14 13 12 11 10 R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Latency timer and class cache line size Register: Type: Offset: Default: Description: Latency timer and class cache line size Read/Write 0Ch 0000h This register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the PCI4450. Table 80. Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION 15–8 LATENCY_TIMER R/W PCI latency timer. The value in this register specifies the latency timer for the PCI4450, in units of PCI clock cycles. When the PCI4450 is a PCI bus initiator and asserts FRAME, the latency timer will begin counting from zero. If the latency timer expires before the PCI4450 transaction has terminated, then the PCI4450 will terminate the transaction when its GNT is deasserted. 7–0 CACHELINE_SZ R/W Cache line size. This value is used by the PCI4450 during memory write and invalidate, memory read line, and memory read multiple transactions. header type and BIST register Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Header type and BIST Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Header type and BIST Read-only 0Eh 0000h This register indicates that this function is part of a multifunction device and has a standard PCI header type and indicates no built-in self-test. Table 81. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15–8 BIST R Built-in self-test. The PCI4450 does not include a built-in self-test, and this field returns 00h when read. 7–0 HEADER_TYPE R PCI header type. The PCI4450 includes the standard PCI header, and this is communicated by returning 00h when this field is read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 open HCI registers base address register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Open HCI registers base address R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Open HCI registers base address R/W R/W R/W R/W R/W R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Open HCI registers base address Read-only, Read/Write 10h 0000 0000h This register is programmed with a base address referencing the memory mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2 Kbytes of memory address space are required for the OHCI registers. Table 82. Open HCI Registers Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31–11 OHCIREG_PTR R/W Open HCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI register base address. 10–4 OHCI_SZ R Open HCI register size. This field returns 0s when read, and indicates that the OHCI registers require a 2-Kbyte region of memory. 3 OHCI_PF R OHCI register prefetch. This bit returns 0, indicating the OHCI registers are nonprefetchable. 2–1 OHCI_MEMTYPE R Open HCI memory type. This field returns 0s when read, and indicates that the base register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 OHCI_MEM R OHCI memory indicator. This bit returns 0, indicating the OHCI registers are mapped into system memory space. 126 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 TI extension base address register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 TI extension base address Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name TI extension base address Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: TI extension base address Read-only 14h 0000 0000h This register is programmed with a base address referencing the memory mapped TI extension registers. Table 83. TI Extension Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31–11 TI_EXTREG_PTR R/W TI extension register pointer. Specifies the upper 20 bits of the 32-bit TI extension register base address. 10–4 TI_SZ R TI extension register size. This field returns 0s when read, and indicates that the TI extension registers require a 2-Kbyte region of memory. 3 TI_PF R TI extension register prefetch. This bit returns 0, indicating the TI extension registers are nonprefetchable. 2–1 TI_MEMTYPE R TI memory type. This field returns 0s when read, and indicates that the base register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 TI_MEM R TI memory indicator. This bit returns 0, indicating the TI extension registers are mapped into system memory space. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 127 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI subsystem identification register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 PCI subsystem identification RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default PCI subsystem identification RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: PCI subsystem identification Read/Update 2Ch 0000 0000h This register is used for subsystem and option card identification purposes. This register can be initialized from the serial EEPROM or can be written using the subsystem access register. Table 84. PCI Subsystem Identification Register Description BIT FIELD NAME TYPE DESCRIPTION 31–16 OHCI_SSID RU Subsystem device ID. This field indicates the subsystem device ID. 15–0 OHCI_SSVID RU Subsystem vendor ID. This field indicates the subsystem vendor ID. PCI power management capabilities pointer register Bit 7 6 5 Name 4 3 2 1 0 PCI power management capabilities pointer Type R R R R R R R R Default 0 1 0 0 0 1 0 0 Register: Type: Offset: Default: Description: 128 PCI power management capabilities pointer Read-only 34h 44h This register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI4450 configuration header double-words at 44h and 48h provide the power management registers. This register is read-only and returns 44h when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 interrupt line and pin registers Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Interrupt line and pin Register: Type: Offset: Default: Description: Interrupt line and pin Read-only, Read/Write 3Ch 0000h This register is used to communicate interrupt line routing information. Table 85. Interrupt Line and Pin Registers Description BIT FIELD NAME TYPE DESCRIPTION 15–8 INTR_PIN R Interrupt pin register. This register returns 01h, 02h, or 03h when read, indicating that the PCI4450 link function signals interrupts on INTA, INTB, or INTC pin. 7–0 INTR_LINE R/W Interrupt line register. This register is programmed by the system and indicates to the software which interrupt line the PCI4450 INTA is connected. MIN_GNT and MAX_LAT registers Bit 15 14 13 12 11 10 9 RU RU RU RU RU RU RU RU RU 0 0 0 0 0 0 1 0 0 Name Type Default 8 7 6 5 4 3 2 1 0 RU RU RU RU RU RU RU 0 0 0 0 0 1 0 MIN_GNT and MAX_LAT Register: Type: Offset: Default: Description: MIN_GNT and MAX_LAT Read/Update 3Eh 0202h This register is used to communicate to the system the desired setting of the latency timer register. If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset. If no serial ROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4. Table 86. MIN_GNT and MAX_LAT Registers Description BIT FIELD NAME TYPE DESCRIPTION 15–8 MAX_LAT RU Maximum latency. The contents of this register may be used by host BIOS to assign an arbitration priority-level to the PCI4450. The default for this register indicates that the PCI4450 may need to access the PCI bus as often as every 1/4 µs; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial ROM. 7–0 MIN_GNT RU Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer register value to the PCI4450. The default for this register indicates that the PCI4450 may need to sustain burst transfers for nearly 64 µs; thus, requesting a large value be programmed in the PCI4450 latency timer register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 129 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI OHCI control register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 PCI OHCI control Register: Type: Offset: Default: Description: PCI OHCI control Read-only 40h 0000h This register contains IEEE1394 Open HCI specific control bits. All bits in this register are read-only and return 0s, since no OHCI specific control bits have been implemented. capability ID and next item pointer registers Bit 15 14 13 12 11 10 Name 9 8 7 6 5 4 3 2 1 0 Capability ID and next item pointer Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: Type: Offset: Default: Description: Capability ID and next item pointer Read-only 44h 0001h This register identifies the linked list capability item, and provides a pointer to the next capability item. Table 87. Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TYPE DESCRIPTION 15–8 NEXT_ITEM R Next item pointer. The PCI4450 supports only one additional capability that is communicated to the system through the extended capabilities list; thus, this field returns 00h when read. 7–0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power management capability. 130 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 power management capabilities register Bit 15 14 13 12 11 10 RU RU RU RU RU R R R R 0 1 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R R R R R 0 0 0 0 0 0 1 Power management capabilities Register: Type: Offset: Default: Description: Power management capabilities Read/Update 46h 4001h This register indicates the capabilities of the PCI4450 related to PCI power management. In summary, the D0, D2, and D3hot device states are supported. Table 88. Power Management Capabilities Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_D3COLD RU PME support from D3cold. When set, PCI4450 generates a PME wake event from D3cold. This bit state is dependent upon PCI4450 Vaux implementation and may be configured by host software using the PCI miscellaneous configuration register. 14–11 PME_SUPPORT RU PME support. This four-bit field indicates the power states from which the PCI4450 may assert PME. These four bits return a value of 4’b1100 by default, indicating that PME may be asserted from the D3hot and D2 power states. Bit 13 may be modified by host software using the PCI miscellaneous configuration register. 10 D2_SUPPORT R D2 support. This bit returns a 1 when read, indicating that the PCI4450 supports the D2 power state. 9 D1_SUPPORT R D1 support. This bit returns a 0 when read, indicating that the PCI4450 does not support the D1 power state. 8 DYN_DATA R Dynamic data support. This bit returns a 0 when read, indicating that the PCI4450 does not report dynamic power consumption data. 7–6 RSVD R Reserved. These bits return 0s when read. 5 DSI R Device specific initialization. This bit returns 0 when read, indicating that the PCI4450 does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. 4 AUX_PWR R Auxiliary power source. Since the PCI4450 supports PME generation in the D3cold device state and requires Vaux, this bit returns 1 when read. 3 PME_CLK R PME clock. This bit returns 0 when read indicating that no host bus clock is required for the PCI4450 to generate PME. 2–0 PM_VERSION R Power management version. This field returns 001b when read, indicating that the PCI4450 is compatible with the registers described in the revision 1.0 PCI Bus Power Management Specification. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 131 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 power management control and status register Bit 15 14 13 12 11 10 RC R R R R R R R/W R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R R R R/W R/W 0 0 0 0 0 0 0 Power management control and status Register: Type: Offset: Default: Description: Power management control and status Read-only, Read/Write, Read/Clear 48h 0000h This register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. Table 89. Power Management Control and Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_STS RC This bit is set when the PCI4450 would normally be asserting the PME signal, independent of the state of the PME_ENB bit. This bit is cleared by a write back of 0, and this also clears the PME signal driven by the PCI4450. Writing a 0 to this bit has no effect. 14–9 DYN_CTRL R Dynamic data control. This bit field returns 0s when read since the PCI4450 does not report dynamic data. 8 PME_ENB R/W PME enable. This bit enables the function to assert PME. If the bit is cleared assertion of PME is disabled. 7–5 RSVD R Reserved. These bits return 0s when read. 4 DYN_DATA R Dynamic data. This bit returns 0 when read since the PCI4450 does not report dynamic data. Reserved. These bits return 0s when read. 3–2 RSVD R 1–0 PWR_STATE R/W 132 Power state. This two-bit field is used to set the PCI4450 device power state, and is encoded as follows: 00 = Current power state is D0 01 = Current power state is D1 10 = Current power state is D2 11 = Current power state is D3hot POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 power management extension register Bit 15 14 13 12 11 10 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Name 9 8 7 6 5 4 3 2 1 0 R R R R R R R 0 0 0 0 0 0 0 Power management extension Register: Type: Offset: Default: Description: Power management extension Read-only 4Ah 0000h This register provides extended power management features not applicable to the PCI4450, thus it is read-only and returns 0 when read. Table 90. Power Management Extension Register Description BIT FIELD NAME TYPE DESCRIPTION 15–8 PM_DATA R Power management data. This bit field returns 0s when read since the PCI4450 does not report dynamic data. 7–0 PMCSR_BSE R Power management CSR – bridge support extensions. This field returns 0s since the PCI4450 does not provide P2P bridging. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 133 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI miscellaneous configuration register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 PCI miscellaneous configuration Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default PCI miscellaneous configuration R/W R R/W R R R/W R R R R R R R/W R/W R/W R/W 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: PCI miscellaneous configuration Read-only, Read/Write F0h 0000 2400h This register provides miscellaneous PCI-related configuration. Table 91. PCI Miscellaneous Configuration Register Description BIT FIELD NAME TYPE 31–16 RSVD R 15 PME_D3COLD R/W 14 RSVD R 13 PME_SUPPORT_D2 R/W DESCRIPTION Reserved. These bits return 0s when read. PME support from D3cold. This bit is used to program the corresponding read-only value read from power management capabilities. This bit retains state through PCI reset and D3 – D0 transitions. Reserved. This bit returns 0 when read. PME support. This bit is used to program the corresponding read-only value read from power management capabilities. If wake from the D2 power state implemented in PCI4450 is not desired, then this bit may be cleared to indicate to power management software that wake–up from D2 is not supported. This bit retains state through PCI reset and D3 – D0 transitions. 12–11 RSVD R 10 D2_SUPPORT R/W 9–4 RSVD R 3 RSVD R/W Reserved. This bit defaults to 0. 2 DISABLE_SCLKGATE R/W When set, the internal SCLK runs identically with the chip input. 1 DISABLE_PCIGATE R/W When set, the internal PCI clock runs identically with the chip input. 0 KEEP_PCLK R/W When set, the PCI clock is always kept running through the CLKRUN protocol. When cleared, the PCI clock may be stopped using CLKRUN. 134 Reserved. These bits return 0s when read. D2 support. This bit is used to program the corresponding read-only value read from power management capabilities. If the D2 power state implemented in PCI4450 is not desired, then this bit may be cleared to indicate to power management software that D2 is not supported. This bit retains state through PCI reset and D3 – D0 transitions. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 link enhancement control register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Link enhancement control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Link enhancement control Type R R R/W R/W R R R/W R/W R/W R R R R R/W R/W R Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Link enhancement control Read-only, Read/Write F4h 0000 1000h This register implements TI proprietary bits that are initialized by software or by a serial EEPROM if present. After these bits are set, their functionality is enabled only if the aPhyEnhanceEnable bit in the HCControl register is set. Table 92. Link Enhancement Control Register Description BIT FIELD NAME TYPE 31–14 RSVD R 13–12 atx_thresh R/W DESCRIPTION Reserved. These bits return 0s when read. This bit field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When PCI4450 retries the packet, it uses a 2K-byte threshold resulting in store-and-forward operation. 00 = Threshold ~ 2 Kbytes resulting in store-and-forward operation 01 = Threshold ~ 1.7 Kbytes (default) 10 = Threshold ~ 1 K 11 = Threshold ~ 512 bytes 11–10 RSVD R 9 enab_audio_ts R/W Reserved. This bit returns 0 when read. Enable audio/music CIP timestamp enhancement. When this bit is set, the enhancement is enabled for audio/music CIP transmit streams (FMT = 6’h10). 8 enab_dv_ts R/W Enable DV CIP timestamp enhancement. When this bit is set, the enhancement is enabled for DV CIP transmit streams (FMT = 6’h00). 7 enab_unfair R/W Enable asynchronous priority requests. OHCILynx (TSB12LV22) compatible. 6 RSVD R This reserved field will not be assigned in PCI4450 follow–on products since this bit location loaded by the serial ROM from the enhancements field corresponds to HCControl.programPhyEnable in Open HCI register space. 5–3 RSVD R Reserved. These bits return 0s when read. 2 enab_insert_idle R/W Enable insert idle. OHCILynx (TSB12LV22) compatible. 1 enab_accel R/W Enable acceleration enhancements. OHCILynx (TSB12LV22) compatible. 0 RSVD R Reserved. This bit returns 0 when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 135 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 subsystem access register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Subsystem access identification R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Subsystem access identification R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Subsystem access identification Read/Write F8h 0000 0000h This register is used for system and option card identification purposes. The contents of this register are aliased to subsystem identification register at address 2Ch. Table 93. Subsystem Access Identification Register Description BIT FIELD NAME TYPE 31–16 SUBDEV_ID R/W Subsystem device ID. This field indicates the subsystem device ID. 15–0 SUBVEN_ID R/W Subsystem vendor ID. This field indicates the subsystem vendor ID. 136 DESCRIPTION POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 GPIO control register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 GPIO control Type R R R/W R/W R R R R/W R R R/W R/W R R R R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default GPIO control R/W R R/W R/W R R R R/W R/W R R/W R/W R R R R/W 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 Register: Type: Offset: Default: Description: GPIO control Read-only, Read/Write FCh 0000 1010h This register has the control and status bits for GPIO0, GPIO1, GPIO2 and GPIO3 ports. Upon reset, GPIO0 and GPIO1 default to bus manager contender (BMC) and link power status terminals, respectively. The BMC terminal can be configured as GPIO0 by setting the disable_BMC bit to 1. The LPS terminal can be configured as GPIO1 by setting the disable_LPS bit to 1. Table 94. General-Purpose Input/Output Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31–30 RSVD R 29 GPIO_INV3 R/W Reserved. These bits return 0s when read. GPIO3 polarity invert. This bit controls the input/output polarity control of GPIO3. 0 = noninverted (default) 1 = inverted 28 GPIO_ENB3 R/W GPIO3 enable control. This bit controls the output enable for GPIO3 0 = high-impedance output (default) 1 = output enabled 27–25 RSVD R 24 GPIO_DATA3 R/W Reserved. These bits return 0s when read. 23–22 RSVD R 21 GPIO_INV2 R/W GPIO2 polarity invert. This bit controls the input/output polarity control of GPIO2. 0 = noninverted (default) 1 = inverted 20 GPIO_ENB2 R/W GPIO2 enable control. This bit controls the output enable for GPIO2. 0 = high-impedance output (default) 1 = output enabled GPIO3 data. When GPIO3 output is enabled, the value written to this bit represents the logical data driven to the GPIO3 terminal. Reserved. These bits return 0s when read. 19–17 RSVD R 16 GPIO_DATA2 R/W Reserved. These bits return 0s when read. GPIO2 data. When GPIO2 output is enabled, the value written to this bit represents the logical data driven to the GPIO2 terminal. 15 DISABLE_LPS R/W Disable link power status (LPS). This bit configures this terminal as 0 = LPS (default) 1 = GPIO1 14 RSVD R Reserved. This bit returns 0 when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 137 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 94. General-Purpose Input/Output Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 13 GPIO_INV1 R/W GPIO1 polarity invert. When DISABLE_LPS bit is set to 1, this bit controls the input output polarity control of GPIO1 0 = noninverted (default) 1 = inverted 12 GPIO_ENB1 R/W GPIO1 enable control. When DISABLE_LPS bit is set to 1, this bit controls the output enable for GPIO1 0 = high-impedance output 1 = output enabled (default) 11–9 RSVD R 8 GPIO_DATA1 R/W GPIO1 data. When DISABLE_LPS bit is set to 1 and GPIO1 output is enabled, the value written to this bit represents the logical data driven to the GPIO1 terminal. 7 DISABLE_BMC R/W Disable bus manager contender (BMC). This bit configures this terminals as bus master contender or GPIO. 0 = BMC (default) 1 = GPIO0 6 RSVD R 5 GPIO_INV0 R/W GPIO0 polarity invert. When DISABLE_BMC bit is set to 1, this bit controls the input output polarity control of for GPIO0 0 = non-inverted (default) 1 = inverted 4 GPIO_ENB0 R/W GPIO0 enable control. When DISABLE_BMC bit is set to 1, this bit controls the output enable for GPIO0 0 = high-impedance output 1 = output enabled (default) 3–1 RSVD R 0 GPIO_DATA0 R/W 138 Reserved. These bits return 0s when read. Reserved. This bit returns 0 when read. Reserved. These bits return 0s when read. GPIO0 data. When DISABLE_BMC bit is set to 1 and GPIO0 output is enabled, the value written to this bit represents the logical data driven to the GPIO0 terminal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 link timer adjustment register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Link timer adjustment Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Link timer adjustment Type R R R R R R R R R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Link timer adjustment Read-only, Read/Write C10h 0000 0000h This register is used to control the link rollover value, and should be programmed with a non–zero value only when PCI4450 is the 1394 cycle master. Table 95. Link Timer Adjustment Register Description BIT FIELD NAME TYPE DESCRIPTION 31–8 RSVD R Reserved. These bits return 0s when read. 7 TIMER_ADJ_REQ R This bit indicates that the timer adjust request is active, but not completed. This bit is set whenever the timer adjust field is written, and is cleared when the actual adjustment is made. 6–4 RSVD R Reserved. These bits return 0s when read. 3–0 TIMER_ADJ_VAL R/W Cycle timer adjustment value. This four bit signed value is used to adjust the PCI4450 cycleTimer. The cycle timer offset field may be adjusted from +7 to –8 using this register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 139 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 open HCI registers The open HCI registers defined by the IEEE1394 Open HCI Specification are memory mapped into a 2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space. These registers are the primary interface for controlling the PCI4450 IEEE1394 link function. This section provides the register interface and bit descriptions. There are several set and clear register pairs in this programming model, which are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 96 for an illustration. A 1 written to RegisterSet causes the corresponding bit in the set/clear register to be set, while a 0 leaves the corresponding bit unaffected. A 1 written to RegisterClear causes the corresponding bit in the set/clear register to be reset, while a 0 leaves the corresponding bit in the set/clear register unaffected. Typically, a read from either RegisterSet or RegisterClear returns the value of the set/clear register. However, sometimes reading the RegisterClear will provide a masked version of the set/clear register. The interrupt event register is an example of this behavior. Table 96. Open HCI Register Map DMA CONTEXT — 140 REGISTER NAME ABBREVIATION OFFSET OHCI version Version 00h Global unique ID ROM GUID_ROM 04h Asynchronous transmit retries ATRetries 08h CSR data CSRData 0Ch CSR compare data CSRCompareData 10h CSR control CSRControl 14h Configuration ROM header ConfigROMhdr 18h Bus identification BusID 1Ch Bus options BusOptions 20h Global unique ID high GUIDHi 24h Global unique ID low GUIDLo 28h Reserved — 2Ch Reserved — 30h Configuration ROM map ConfigROMmap 34h Posted write address low PostedWriteAddressLo 38h Posted write address high PostedWriteAddressHi 3Ch Vendor identification VendorID 40h Reserved — POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 44h – 4Ch PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 96. Open HCI Register Map (Continued) DMA CONTEXT REGISTER NAME — Host controller control Self ID ABBREVIATION OFFSET HCControlSet 50h HCControlClr 54h Reserved — 58h Reserved — 5Ch Reserved — 60h Self ID buffer SelfIDBuffer 64h Self ID count SelfIDCount 68h Reserved — 6Ch IRChannelMaskHiSet 70h IRChannelMaskHiClear 74h — Isochronous receive channel mask high Isochronous receive channel mask low Interrupt event Interrupt mask Isochronous transmit interrupt event Isochronous transmit interrupt mask — Isochronous receive interrupt event Isochronous receive interrupt mask IRChannelMaskLoSet 78h IRChannelMaskLoClear 7Ch IntEventSet 80h IntEventClear 84h IntMaskSet 88h IntMaskClear 8Ch IsoXmitIntEventSet 90h IsoXmitIntEventClear 94h IsoXmitIntMaskSet 98h IsoXmitIntMaskClear 9Ch IsoRecvIntEventSet A0h IsoRecvIntEventClear A4h IsoRecvIntMaskSet A8h IsoRecvIntMaskClear ACh Reserved B0–D8h Fairness control FairnessControl DCh LinkControlSet E0h LinkControlClear E4h Node identification NodeID E8h Phy layer control PhyControl ECh Isochronous cycle timer IsoCycleTimer Reserved — Link control Asynchronous request filter high Asynchronous request filter low Physical request filter high Physical request filter low AsyncRequestFilterHiSet 100h AsyncRequestFilterHiClear 104h AsyncRequestFilterLoSet 108h AsyncRequestFilterloClear 10Ch PhysicalRequestFilterHiSet 110h PhysicalRequestFilterHiClear 114h PhysicalRequestFilterLoSet 118h PhysicalRequestFilterloClear 11Ch Physical upper bound PhysicalUpperBound Reserved — POST OFFICE BOX 655303 F0h F4h – FCh • DALLAS, TEXAS 75265 120h 124h – 17Ch 141 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 96. Open HCI Register Map (Continued) DMA CONTEXT Asychronous request transmit [ ATRQ ] Asychronous res onse transmit response [ ATRS ] Asychronous request receive [ ARRQ ] Asychronous response res onse receive [ ARRS ] Isochronous transmit context n n = 0, 1, 2, 3, … 7 Isochronous receive context n n = 0, 1, 2, 3, 4 142 REGISTER NAME Context control ABBREVIATION OFFSET ContextControlSet 180h ContextControlClear 184h Reserved — 188h Command pointer CommandPtr 18Ch Reserved — 190h – 19Ch ContextControlSet 1A0h ContextControlClear 1A4h Reserved — 1A8h Command pointer CommandPtr Reserved — Context control 1ACh 1B0h – 1BCh ContextControlSet 1C0h ContextControlClear 1C4h Reserved — 1C8h Command pointer CommandPtr Reserved — Context control Context control 1CCh 1D0h – 1DCh ContextControlSet 1E0h ContextControlClear 1E4h Reserved — 1E8h Command pointer CommandPtr 1ECh Reserved — 1F0h – 1FCh ContextControlSet 200h + 16*n ContextControlClear 204h + 16*n Context control Reserved — 208h + 16*n Command pointer CommandPtr 20Ch + 16*n ContextControlSet 400h + 32*n ContextControlClear 404h + 32*n Reserved — 408h + 32*n Command pointer CommandPtr 40Ch + 32*n Context match ContextMatch 410h + 32*n Context control POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 OHCI version register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 OHCI version Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name OHCI version Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: OHCI version Read-only 00h 0X01 0000h This register indicates the OHCI version support, and whether or not the serial ROM is present. Table 97. OHCI Version Register Description BIT FIELD NAME TYPE DESCRIPTION 31–25 RSVD R Reserved. These bits return 0s when read. 24 GUID_ROM R The PCI4450 sets this bit if the serial ROM is detected. If the serial ROM is present, then the Bus_Info_Block will be automatically loaded on hardware reset. 23–16 version R Major version of the Open HCI. The PCI4450 is compliant with the OHCI specification version 1.00; thus, this field reads 8’h01. 15–8 RSVD R Reserved. These bits return 0s when read. 7–0 revision R Minor version of the Open HCI. The PCI4450 is compliant with the OHCI specification version 1.00; thus, this field reads 8’h00. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 143 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 GUID ROM register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 GUID ROM RSU R R R R R RSU R RU RU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GUID ROM Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: GUID ROM Read-only, Read/Set/Update, Read/Update 04h 00XX 0000h This register is used to access the serial ROM, and is only applicable if the Version.GUID_ROM bit is set. Table 98. GUID ROM Register Description BIT FIELD NAME TYPE DESCRIPTION 31 addrReset RSU Software sets this bit to reset the GUID ROM address to 0. When the PCI4450 completes the reset, it clears this bit. The PCI4450 does not automatically fill rdData with the 0th byte. 30–26 RSVD R 25 rdStart RSU 24 RSVD R 23–16 rdData RU 15–0 RSVD R 144 Reserved. These bits return 0s when read. A read of the currently addressed byte is started when this bit is set. This bit is automatically cleared when the PCI4450 completes the read of the currently addressed GUID ROM byte. Reserved. ThIs bit returns 0 when read. This field represents the data read from the GUID ROM. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 asynchronous transmit retries register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Asynchronous transmit retries Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Asynchronous transmit retries Type R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Asynchronous transmit retries Read-only, Read/Write 08h 0000 0000h This register indicates the number of times the PCI4450 will attempt a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. Table 99. Asynchronous Transmit Retries Register Description BIT FIELD NAME TYPE DESCRIPTION 31–29 secondLimit R The second limit field returns 0s when read, since outbound dual-phase retry is not implemented. 28–16 cycleLimit R The cycle limit field returns 0s when read, since outbound dual-phase retry is not implemeted. 15–12 RSVD R Reserved. These bits return 0s when read. 11–8 maxPhysRespRetries R/W The maxPhysRespRetries field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 7–4 maxATRespRetries R/W The maxATRespRetries field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 3–0 maxATReqRetries R/W The maxATReqRetries field tells the asynchronous transmit DMA request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 145 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 CSR data register Bit 31 30 29 28 27 26 25 24 Name 23 22 21 20 19 18 17 16 CSR data Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CSR data Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: CSR data Read-only 0Ch XXXX XXXXh This register is used to access the bus management CSR registers from the host through compare-swap operations. This register contains the data to be stored in a CSR if the compare is successful. CSR compare register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 CSR compare Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name CSR compare Register: Type: Offset: Default: Description: 146 CSR compare Read-only 10h XXXX XXXXh This register is used to access the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 CSR control register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 CSR control RU R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CSR control Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X Register: Type: Offset: Default: Description: CSR control Read-only, Read/Update, Read/Write 14h 0000 0000h This register is used to access the bus management CSR registers from the host through compare-swap operations. This register is used to control the compare-swap operation and select the CSR resource. Table 100. CSR Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 csrDone RU This bit is set by the PCI4450 when a compare-swap operation is complete. It is reset whenever this register is written. 30–2 RSVD R 1–0 csrSel R/W Reserved. These bits return 0s when read. This field selects the CSR resource as follows: 00 = BUS_MANAGER_ID 01 = BANDWIDTH_AVAILABLE 10 = CHANNELS_AVAILABLE_HI 11 = CHANNELS_AVAILABLE_LO POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 147 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 configuration ROM header register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Configuration ROM header R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Configuration ROM header R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X X X X X X X X X Register: Type: Offset: Default: Description: Configuration ROM header Read/Write 18h 0000 XXXXh This register externally maps to the first quadlet of the 1394 configuration ROM, offset 48’hFFFF_F000_0400. Table 101. Configuration ROM Header Register Description BIT FIELD NAME TYPE DESCRIPTION 31–24 info_length R/W IEEE1394 bus mgmt field. Must be valid when HCControl.linkEnable bit is set. 23–16 crc_length R/W IEEE1394 bus mgmt field. Must be valid when HCControl.linkEnable bit is set. 15–0 rom_crc_value R/W IEEE1394 bus management field. Must be valid at any time the HCControl.linkEnable bit is set. The reset value is undefined if no serial ROM is present. If a serial ROM is present, then this field is loaded from the serial ROM. bus identification register Bit 31 30 29 28 27 26 25 R R R R R R R R Name Type 24 23 22 21 20 19 18 17 16 R R R R R R R R Bus identification Default 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Bus identification Type R R R R R R R R R R R R R R R R Default 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 0 Register: Type: Offset: Default: Description: 148 Bus identification Read-only 1Ch 3133 3934h This register externally maps to the first quadlet in the Bus_Info_Block, and contains the constant 32’h31333934, which is the ASCII value of 1394. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 bus options register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Bus options R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X 0 0 0 0 X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Bus options R/W R/W R/W R/W R R R R R/W R/W R R R R R R 1 0 1 0 0 0 0 0 X X 0 0 0 0 1 0 Register: Type: Offset: Default: Description: Bus options Read-only, Read/Write 20h X0XX A0X2h This register externally maps to the second quadlet of the Bus_Info_Block. Table 102. Bus Options Register Description BIT FIELD NAME TYPE DESCRIPTION 31 irmc R/W Isochronous resource manager capable. IEEE1394 bus management field. Must be valid when HCControl.linkEnable bit is set. 30 cmc R/W Cycle master capable. IEEE1394 bus management field. Must be valid when HCControl.linkEnable bit is set. 29 isc R/W Isochronous support capable. HCControl.linkEnable bit is set. 28 bmc R/W Bus manager capable. IEEE1394 bus management field. Must be valid when HCControl.linkEnable bit is set. IEEE1394 bus management field. Must be valid when HCControl.linkEnable bit is set. IEEE1394 bus management field. Must be valid when 27 pmc R/W 26–24 RSVD R 23–16 cyc_clk_acc R/W Cycle master clock accuracy. (accuracy in parts per million) IEEE1394 bus management field. Must be valid when HCControl.linkEnable bit is set. 15–12 max_rec R/W IEEE 1394 bus management field. Hardware shall initialize max_rec to indicate the maximum number of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes must be 512 greater, and is calculated by 2^(max_rec + 1). Software may change max_rec, however this field must be valid at any time the HCControl.linkEnable bit is set. A received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a soft reset, and defaults to value indicating 2048 bytes on hard reset. 11–8 RSVD R 7–6 g R/W 5–3 RSVD R Reserved. These bits return 0s when read. 2–0 Lnk_spd R Link speed. This field returns 010, indicating that the link speeds of 100, 200 and 400 Mbits/s are supported. Reserved. These bits return 0s when read. Reserved. These bits return 0s when read. Generation counter. This field shall be incremented is any portion the configuration ROM has incremented since the prior bus reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 149 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 GUID high register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 GUID high Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GUID high Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: GUID high Read-only 24h 0000 0000h This register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset. At that point, the contents of this register cannot be changed. If no serial ROM is detected, then this register may be written once to set the value of this register. At that point, the contents of this register cannot be changed. GUID low register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 GUID low Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name GUID low Register: Type: Offset: Default: Description: 150 GUID low Read-only 28h 0000 0000h This register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo in the Bus_Info_Block. This register initializes to 0s on a hardware reset, and behaves identical to the GUID high register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 configuration ROM mapping register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Configuration ROM mapping R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Configuration ROM mapping R/W R/W R/W R/W R/W R/W R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Configuration ROM mapping Read-only, Read/Write 34h 0000 0000h This register contains the start address within system memory that will map to the start address of 1394 configuration ROM for this node. Table 103. Configuration ROM Mapping Register Description BIT FIELD NAME TYPE DESCRIPTION 31–10 configROMaddr R/W If a quadlet read request to 1394 offset 48’hFFFF_F000_0400 through offset 48’hFFFF_F000_07FF is received, then the low order 10 bits of the offset are added to this register to determine the host memory address of the read request. 9–0 RSVD R Reserved. These bits return 0s when read. posted write address low register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Posted write address low RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Posted write address low RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU X X X X X X X X X X X X X X X X Register: Type: Offset: Default: Description: Posted write address low Read/Update 38h XXXX XXXXh This register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. Table 104. Posted Write Address Low Register Description BIT FIELD NAME TYPE 31–0 offsetLo RU DESCRIPTION The lower 32 bits of the 1394 destination offset of the write request that failed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 151 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 posted write address high register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Posted write address high RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Posted write address high RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU X X X X X X X X X X X X X X X X Register: Type: Offset: Default: Description: Posted write address high Read/Update 3Ch XXXX XXXXh This register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. Table 105. Posted Write Address High Register Description BIT FIELD NAME TYPE DESCRIPTION 31–16 sourceID RU This bus and node number of the node that issued the write request that failed. 15–0 offsetHi RU The upper 16 bits of the 1394 destination offset of the write request that failed. vendor ID register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: 152 Vendor ID Read-only 40h 0000 0000h The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The PCI4450 does not implement Texas Instruments unique behavior with regards to Open HCI. Thus this register is read-only and returns 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 host controller control register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Host controller control RSC R R R R R R R RC RSC R R RSC RSC RSC RSCU Default 0 X 0 0 0 0 0 0 0 0 0 0 0 X 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Host controller control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Host controller control Read/Set/Clear/Update 50h set register 54h clear register Default: X00X 0000h Description: This set/clear register pair provides flags for controlling the PCI4450 link function. Table 106. Host Controller Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 RSVD R 30 noByteSwapData RSC Reserved. These bits return 0s when read. 29–24 RSVD R 23 programPhyEnable RC This bit informs upper level software that lower level software has consistently configured the p1394a enhancements in the Link and PHY. When 1 generic software such as the OHCI driver is responsible for configuring p1394a enhancements in the PHY and the aPhyEnhanceEnable bit in the PCI4450. When 0, the generic software may not modify the p1394a enhancements in the PCI4450 or PHY and cannot interpret the setting of aPhyEnhanceEnable. This bit can be initialized from serial EEPROM. 22 aPhyEnhanceEnable RSC When the programPhyenable is 1 and link enable is 1, the OHCI driver can set this bit to use all p1394a enhancements. When programPhyEnable is set 0, the software shall not change PHY enhancements or the aPhyEnhanceEnable bit. 21–20 RSVD R 19 LPS RSC This bit is used to control the link power status. Software must set LPS to 1 to permit the link-PHY communication. A 0 prevents link-PHY communication. 18 postedWriteEnable RSC This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only when linkEnable is 0. 17 linkEnable RSC This bit is cleared to 0 by a hardware reset or software reset. Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready. When this bit is clear the PCI4450 is logically and immediately disconnected from the 1394 bus, no packets will be received or processed nor will packets be transmitted. 16 SoftReset RSCU When set to 1, all PCI4450 state is reset, all FIFO’s are flushed, and all OHCI registers are set to their hardware reset values unless otherwise specified. PCI registers are not affected by this bit. This bit remains set to 1 while the softReset is in progress and reverts back to 0 when the reset has completed. 15–0 RSVD R This bit is used to control whether physical accesses to locations outside the PCI4450 itself as well as any other DMA data accesses should be swapped. Reserved. These bits return 0s when read. Reserved. These bits return 0s when read. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 153 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 self ID buffer pointer register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Self ID buffer pointer R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Self ID buffer pointer R/W R/W R/W R/W R/W R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Self ID buffer pointer Read-only, Read/Write 64h XXXX XX00h This register points to the 2-Kbyte aligned base address of the buffer in host memory where the self ID packets will be stored during bus initialization. Bits 31–11 are read/write accessible. self ID count register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Self ID count RU R R R R R R R RU RU RU RU RU RU RU RU Default X 0 0 0 0 0 0 0 X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R R R R R RU RU RU RU RU RU RU RU RU R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Self ID count Register: Type: Offset: Default: Description: Self ID count Read/Update 68h X0XX 0000h This register keeps a count of the number of times the bus self ID process has occurred, flags self ID packet errors, and keeps a count of the amount of self ID data in the self ID buffer. Table 107. Self ID Count Register Description BIT FIELD NAME TYPE DESCRIPTION 31 selfIDError RU When this bit is 1, an error was detected during the most recent self ID packet reception. The contents of the self ID buffer are undefined. This bit is cleared after a self ID reception in which no errors are detected. Note that an error can be a hardware error or a host bus write error. 30–24 RSVD R 23–16 selfIDGeneration RU 15–11 RSVD R 10–2 selfIDSize RU 1–0 RSVD R 154 Reserved. These bits return 0s when read. The value in this field increments each time a bus reset is detected. This field rolls over to 0 after reaching 255. Reserved. These bits return 0s when read. This field indicates the number of quadlets that have been written into the self ID buffer for the current selfIDGeneration. This includes the header quadlet and the self ID data. This field is cleared to 0 when the self ID reception begins. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ISO receive channel mask high register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 ISO receive channel mask high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default ISO receive channel mask high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC X X X X X X X X X X X X X X X X Register: Type: Offset: ISO receive channel mask high Read/Set/Clear 70h set register 74h clear register Default: XXXX XXXXh Description: This set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the value of the IRChannelMaskHi register. Table 108. ISO Receive Channel Mask High Register Description BIT FIELD NAME TYPE DESCRIPTION 31 isoChannel63 RSC When set, the PCI4450 is enabled to receive from iso channel number 63. 30 isoChannel62 RSC When set, the PCI4450 is enabled to receive from iso channel number 62. 29 isoChannel61 RSC When set, the PCI4450 is enabled to receive from iso channel number 61. 28 isoChannel60 RSC When set, the PCI4450 is enabled to receive from iso channel number 60. 27 isoChannel59 RSC When set, the PCI4450 is enabled to receive from iso channel number 59. 26 isoChannel58 RSC When set, the PCI4450 is enabled to receive from iso channel number 58. 25 isoChannel57 RSC When set, the PCI4450 is enabled to receive from iso channel number 57. 24 isoChannel56 RSC When set, the PCI4450 is enabled to receive from iso channel number 56. 23 isoChannel55 RSC When set, the PCI4450 is enabled to receive from iso channel number 55. 22 isoChannel54 RSC When set, the PCI4450 is enabled to receive from iso channel number 54. 21 isoChannel53 RSC When set, the PCI4450 is enabled to receive from iso channel number 53. 20 isoChannel52 RSC When set, the PCI4450 is enabled to receive from iso channel number 52. 19 isoChannel51 RSC When set, the PCI4450 is enabled to receive from iso channel number 51. 18 isoChannel50 RSC When set, the PCI4450 is enabled to receive from iso channel number 50. 17 isoChannel49 RSC When set, the PCI4450 is enabled to receive from iso channel number 49. 16 isoChannel48 RSC When set, the PCI4450 is enabled to receive from iso channel number 48. 15 isoChannel47 RSC When set, the PCI4450 is enabled to receive from iso channel number 47. 14 isoChannel46 RSC When set, the PCI4450 is enabled to receive from iso channel number 46. 13 isoChannel45 RSC When set, the PCI4450 is enabled to receive from iso channel number 45. 12 isoChannel44 RSC When set, the PCI4450 is enabled to receive from iso channel number 44. 11 isoChannel43 RSC When set, the PCI4450 is enabled to receive from iso channel number 43. 10 isoChannel42 RSC When set, the PCI4450 is enabled to receive from iso channel number 42. 9 isoChannel41 RSC When set, the PCI4450 is enabled to receive from iso channel number 41. 8 isoChannel40 RSC When set, the PCI4450 is enabled to receive from iso channel number 40. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 155 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 108. ISO Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE 7 isoChannel39 RSC When set, the PCI4450 is enabled to receive from iso channel number 39. DESCRIPTION 6 isoChannel38 RSC When set, the PCI4450 is enabled to receive from iso channel number 38. 5 isoChannel37 RSC When set, the PCI4450 is enabled to receive from iso channel number 37. 4 isoChannel36 RSC When set, the PCI4450 is enabled to receive from iso channel number 36. 3 isoChannel35 RSC When set, the PCI4450 is enabled to receive from iso channel number 35. 2 isoChannel34 RSC When set, the PCI4450 is enabled to receive from iso channel number 34. 1 isoChannel33 RSC When set, the PCI4450 is enabled to receive from iso channel number 33. 0 isoChannel32 RSC When set, the PCI4450 is enabled to receive from iso channel number 32. ISO receive channel mask low register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 ISO receive channel mask low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC X X X X X X X X X X X X X X X X Name Type Default ISO receive channel mask low Register: Type: Offset: ISO receive channel mask low Read/Set/Clear 78h set register 7Ch clear register Default: XXXX XXXXh Description: This set/clear register is used to enable packet receives from the lower 32 isochronous data channels. Table 109. ISO Receive Channel Mask Low Register Descriptions BIT FIELD NAME TYPE 31 isoChannel31 RSC When set, the PCI4450 is enabled to receive from iso channel number 31. 30 isoChannel30 RSC When set, the PCI4450 is enabled to receive from iso channel number 30. L L L 1 isoChannel1 RSC When set, the PCI4450 is enabled to receive from iso channel number 1. 0 isoChannel0 RSC When set, the PCI4450 is enabled to receive from iso channel number 0. 156 DESCRIPTION Bits 29 through 2 follow the same pattern POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 interrupt event register Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Interrupt event Type R R R R R Default 0 X 0 0 0 RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU X X Bit 15 14 13 12 11 10 9 Name R RSCU RSCU X X X X X X 0 X X 8 7 6 5 4 3 2 1 0 Interrupt event Type R R R R R R Default 0 0 0 0 0 0 RSCU RSCU X X RU RU X X RSCU RSCU RSCU RSCU RSCU RSCU X X X X X X Register: Type: Offset: Interrupt event Read/Set/Clear/Update 80h set register 84h clear register [returns IntEvent and IntMask when read] Default: XXXX 0XXXh Description: This set/clear register reflects the state of the various PCI4450 interrupt sources. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. Table 110. Interrupt Event Register Description BIT FIELD NAME TYPE DESCRIPTION 31 RSVD R Reserved. This bit returns 0 when read. 30 vendorSpecific R Vendor defined. 29–27 RSVD R Reserved. These bits return 0s when read. 26 phyRegRcvd RSCU The PCI4450 has received a PHY register data byte which can be read from the PHY control register. 25 cycleTooLong RSCU If LinkControl.cycleMaster is set, this indicated that over 125 µs elapsed between the start of sending a cycle start packet and the end of a subaction gap. LinkControl.cycleMaster is cleared by this event. 24 unrecoverableError RSCU This event occurs when the PCI4450 encounters any error that forces it to stop operations on any or all of its subunits. For example, when a DMA context sets its dead bit. While unrecoverableError is set, all normal interrupts for the context(s) that caused this interrupt will be blocked from being set. 23 cycleInconsistent RSCU A cycle start was received that had an isochronous cycleTimer.seconds and isochronous cycleTimer.count different from the value in the CycleTimer register. 22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent/received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start. CycleLost may be set either when it occurs or when logic predicts that it will occur. 21 cycle64Seconds RSCU Indicates that the 7th bit of the cycle second counter has changed. 20 cycleSynch RSCU Indicates that a new isochronous cycle has started and is set when the low order bit of the cycle count toggles. 19 phy RSCU Indicates the PHY requests an interrupt through a status transfer. 18 RSVD R 17 busReset RSCU Reserved. These bits return 0s when read. Indicates that the PHY chip has entered bus reset mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 157 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 110. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 16 selfDcomplete RSCU A selfID packet stream has been received. It will be generated at the end of the bus initialization process. This bit is turned off simultaneously when IntEvent.busReset is turned on. 15–10 RSVD R 9 lockRespErr RSCU Indicates that the PCI4450 sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. 8 postedWriteErr RSCU Indicates that a host bus error occurred while the PCI4450 was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. 7 isochRx RU Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have generated and interrupt. This is not a latched event, it is the OR’ing of all bits in (isoRecvIntEvent and isoRecvIntMask). The isoRecvIntEvent register indicates which contexts have interrupted. 6 iscohTx RU Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have generated and interrupt. This is not a latched event, it is the OR’ing of all bits in (isoXmitIntEvent and isoXmitIntMask). The isoXmitIntEvent register indicates which contexts have interrupted. 5 RSPkt RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor’s xferStatus and resCount fields have been updated. 4 RQPkt RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor’s xferStatus and resCount fields have been updated. 3 ARRS RSCU Async receive response DMA interrupt. This bit is conditionally set upon completion of an ARRS context command descriptor. 2 ARRQ RSCU Async receive request DMA interrupt. This bit is conditionally set upon completion of an ARRQ DMA context command descriptor. 1 respTxComplete RSCU Asynchronous response transmit DMA interrupt. This bit is conditionally set upon completion of an ATRS DMA command. 0 reqTxComplete RSCU Asynchronous request transmit DMA interrupt. This bit is conditionally set upon completion of an ATRQ DMA command. 158 Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 interrupt mask register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Interrupt mask RSC R R R R Default 0 X 0 0 0 RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU X X Bit 15 14 13 12 11 10 9 Name R RSCU RSCU X X X X X X 0 X X 8 7 6 5 4 3 2 1 0 Interrupt mask Type R R R R R R Default 0 0 0 0 0 0 RSCU RSCU X X RU RU X X RSCU RSCU RSCU RSCU RSCU RSCU X X X X X X Register: Type: Offset: Interrupt mask Read/Set/Clear 88h set register 8Ch clear register Default: XXXX 0XXXh Description: This set/clear register is used to enable the various PCI4450 interrupt sources. Reads from either the set register or the clear register always return IntMask. In all cases except masterIntEnable (bit 31), the enables for each interrupt event align with the event register bits detailed in Table 110. Table 111. Interrupt Mask Register Description BIT FIELD NAME TYPE DESCRIPTION 31 masterIntEnable RSC When set, external interrupts will be generated in accordance with the IntMask register. If clear, no external interrupts will be generated. 30–0 See Table 110 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 159 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 isochronous transmit interrupt event register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous transmit interrupt event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous transmit interrupt event Type R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 X X X X X X X X Register: Type: Offset: Isochronous transmit interrupt event Read/Set/Clear 90h set register 84h clear register [returns IsoXmitEvent and IsoXmitMask when read] Default: 0000 00XXh Description: This set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST command completes and its interrupt bits are set. Upon determining that the IntEvent.isochTx interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. Table 112. Isochronous Transmit Interrupt Event Register Description BIT FIELD NAME TYPE DESCRIPTION 31–8 RSVD R 7 isoXmit7 RSC Isochronous transmit channel 7 caused the isochTx interrupt. 6 isoXmit6 RSC Isochronous transmit channel 6 caused the isochTx interrupt. 5 isoXmit5 RSC Isochronous transmit channel 5 caused the isochTx interrupt. 4 isoXmit4 RSC Isochronous transmit channel 4 caused the isochTx interrupt. 3 isoXmit3 RSC Isochronous transmit channel 3 caused the isochTx interrupt. 2 isoXmit2 RSC Isochronous transmit channel 2 caused the isochTx interrupt. 1 isoXmit1 RSC Isochronous transmit channel 1 caused the isochTx interrupt. 0 isoXmit0 RSC Isochronous transmit channel 0 caused the isochTx interrupt. 160 Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 isochronous transmit interrupt mask register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous transmit interrupt mask Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous transmit interrupt mask Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 X X X X X X X X Register: Type: Offset: Isochronous transmit interrupt mask Read/Set/Clear 98h set register 9Ch clear register Default: 0000 00XXh Description: This set/clear register is used to enable the isochTx interrupt source on a per channel basis. Reads from either the set register or the clear register always return IsoXmitIntMask. In all cases the enables for each interrupt event align with the event register bits detailed in Table 112. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 161 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 isochronous receive interrupt event register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous receive interrupt event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous receive interrupt event Type R R R R R R R R R R R R RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 X X X X Register: Type: Offset: Isochronous receive interrupt event Read/Set/Clear A0h set register A4h clear register [returns IsoRecvEvent and IsoRecvMask when read] Default: 0000 000Xh Description: This set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set. Upon determining that the IntEvent.isochRx interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. Table 113. Isochronous Receive Interrupt Event Register Description BIT FIELD NAME TYPE DESCRIPTION 31–4 RSVD R 3 isoRecv3 RSC Isochronous receive channel 3 caused the isochRx interrupt. 2 isoRecv2 RSC Isochronous receive channel 2 caused the isochRx interrupt. 1 isoRecv1 RSC Isochronous receive channel 1 caused the isochRx interrupt. 0 isoRecv0 RSC Isochronous receive channel 0 caused the isochRx interrupt. 162 Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 isochronous receive interrupt mask register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous receive interrupt mask Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous receive interrupt mask Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 X X X X Register: Type: Offset: Isochronous receive interrupt mask Read/Set/Clear A8h set register ACh clear register Default: 0000 000Xh Description: This set/clear register is used to enable the isochRx interrupt source on a per channel basis. Reads from either the set register or the clear register always return IsoRecvIntMask. In all cases the enables for each interrupt event align with the event register bits detailed in Table 113. fairness control register (optional register) Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Fairness control Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R R R R R R R R R R R R R R R R Default X X X X X X X X 0 0 0 0 0 0 0 0 Name Fairness control Register: Type: Offset: Default: Description: Fairness control Read-only DCh XXXX XX00h This register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. Table 114. Link Control Register Description BIT FIELD NAME TYPE 31–8 RSVD R Reserved. DESCRIPTION 7–0 pri_req R This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY during fairness interval. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 163 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 link control register Bit 31 30 29 28 27 26 25 24 Name 23 22 21 20 19 18 17 16 Link control Type R R R R R R R R R RSC RSCU RSC R R R R Default 0 0 0 0 0 0 0 0 0 X X X 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Link control Type R R R R R RSC RSC R R R R R R R R R Default 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Link control Read/Set/Clear/Update E0h set register E4h clear register Default: 00X0 0X00h Description: This set/clear register provides the control flags that enable and configure the link core protocol portions of the PCI4450. It contains controls for the receiver and cycle timer. Table 115. Link Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31–23 RSVD R 22 cycleSource RSC When 1, the cycle timer will use an external source (CYCLEIN) to determine when to roll over the cycle timer. When 0, the cycle timer rolls over when the timer reaches 3072 cycles of the 24.576 MHz clock (125 µs). 21 cycleMaster RSCU When set, and the PHY has notified the PCI4450 that it is root, the PCI4450 will generate a cycle start packet every time the cycle timer rolls over, based on the setting of the cycleSource bit. When 0, the OHICLynx will accept received cycle start packets to maintain synchronization with the node which is sending them. This bit is automatically reset when the cycleTooLong event occurs and cannot be set until the IntEvent.cycleTooLong bit is cleared. 20 CycleTimerEnable RSC When 1, the cycle timer offset will count cycles of the 24.576 MHz clock and roll over at the appropriate time based on the settings of the above bits. When 0, the cycle timer offset will not count. 19–11 RSVD R 10 RcvPhyPkt RSC When 1, the receiver will accept incoming PHY packets into the AR request context if the AR request context is enabled. This does not control receipt of self-identification packets. 9 RcvSelfID RSC When 1, the receiver will accept incoming self-identification packets. Before setting this bit to 1, software must ensure that the self ID buffer pointer register contains a valid address. 8–0 RSVD R 164 Reserved. These bits return 0s when read. Reserved. These bits return 0s when read. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 node identification register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Node identification RU RU R R RU R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Node identification RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RU RU RU RU RU RU 1 1 1 1 1 1 1 1 1 1 X X X X X X Register: Type: Offset: Default: Description: Node identification Read/Write/Update E8h 0000 11XXh This register contains the address of the node on which the OHICLynx chip resides, and indicates the valid node number status. The 16-bit combination of busNumber and NodeNumber is referred to as the node ID. Table 116. Node Identification Register Description BIT FIELD NAME TYPE DESCRIPTION 31 iDValid RU This bit indicates whether or not the PCI4450 has a valid node number. It is cleared when a 1394 bus reset is detected and set when the PCI4450 receives a new node number from the PHY. 30 root RU This bit is set during the bus reset process if the attached PHY is root. 29–28 RSVD R Reserved. These bits return 0s when read. 27 CPS RU 26–16 RSVD R Set if the PHY is reporting that cable power status is OK (VP 8V). 15–6 busNumber RWU This number is used to identify the specific 1394 bus the PCI4450 belongs to when multiple 1394-compatiable buses are connected via a bridge. 5–0 NodeNumber RU This number is the physical node number established by the PHY during self-identification. It is automatically set to the value received from the PHY after the self-identification phase. If the PHY sets the nodeNumber to 63, software should not set ContextControl.run for either of the AT DMA contexts. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 165 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PHY control register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 PHY control RU R R R RU RU RU RU RU RU RU RU RU RU RU RU Default X 0 0 0 X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default PHY control RWU RWU R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 X X X X X X X X X X X X Register: Type: Offset: Default: Description: PHY control Read/Write/Update ECh XXXX 0XXXh This register is used to read or write a PHY register. Table 117. PHY Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 rdDone RU This bit is cleared to 0 by the PCI4450 when either rdReg or wrReg is set to 1. This bit is set to 1 when a register transfer is received from the PHY. 30–28 RSVD R 27–24 rdAddr RU Reserved. These bits return 0s when read. This is the address of the register most recently received from the PHY. 23–16 rdData RU This field is the contents of a PHY register which has been read. 15 rdReg RWU This bit is set by software to initiate a read request to a PHY register, and is cleared by hardware when the request has been sent. The wrReg and rdReg bits must be used exclusively. 14 wrReg RWU This bit is set by software to initiate a write request to a PHY register, and is cleared by hardware when the request has been sent. The wrReg and rdReg bits must be used exclusively. 13–12 RSVD R 11–8 regAddr R/W This field is the address of the PHY register to be written or read. 7–0 wrData R/W This field is the data to be written to a PHY register, and is ignored for reads. 166 Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 isochronous cycle timer register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Isochronous cycle timer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Isochronous cycle timer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU X X X X X X X X X X X X X X X X Register: Type: Offset: Default: Description: Isochronous cycle timer Read/Write/Update F0h XXXX XXXXh This read/write register indicates the current cycle number and offset. When the PCI4450 is cycle master, this register is transmitted with the cycle start message. When the PCI4450 is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. Table 118. Isochronous Cycle Timer Register Description BIT FIELD NAME TYPE DESCRIPTION 31–25 cycleSeconds RWU This field counts seconds (cycleCount rollovers) modulo 128. 24–12 cycleCount RWU This field counts cycles (cycleOffset rollovers) modulo 8000. 11–0 cycleOffset RWU This field counts 24.576 MHz clocks modulo 3072, i.e., 125 µs. If an external 8 kHz clock configuration is being used, then cycleOffset must be set to 0 at each tick of the external clock. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 167 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 asynchronous request filter high register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Asynchronous request filter high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Asynchronous request filter high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Asynchronous request filter high Read/Set/Clear 100h set register 104h clear register Default: 0000 0000h Description: This set/clear register is used to enable asynchronous receive requests on a per node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this register, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same bus as the PCI4450. All nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set. Table 119. Asynchronous Request Filter High Register Description BIT FIELD NAME TYPE DESCRIPTION 31 asynReqAllBuses RSC If set to 1, all asynchronous requests received by the PCI4450 from nonlocal bus nodes will be accepted. 30 asynReqResource62 RSC If set to 1 for local bus node number 62, asynchronous requests received by the PCI4450 from that node will be accepted. 29 asynReqResource61 RSC If set to 1 for local bus node number 61, asynchronous requests received by the PCI4450 from that node will be accepted. 28 asynReqResource60 RSC If set to 1 for local bus node number 60, asynchronous requests received by the PCI4450 from that node will be accepted. 27 asynReqResource59 RSC If set to 1 for local bus node number 59, asynchronous requests received by the PCI4450 from that node will be accepted. 26 asynReqResource58 RSC If set to 1 for local bus node number 58, asynchronous requests received by the PCI4450 from that node will be accepted. 25 asynReqResource57 RSC If set to 1 for local bus node number 57, asynchronous requests received by the PCI4450 from that node will be accepted. 24 asynReqResource56 RSC If set to 1 for local bus node number 56, asynchronous requests received by the PCI4450 from that node will be accepted. 23 asynReqResource55 RSC If set to 1 for local bus node number 55, asynchronous requests received by the PCI4450 from that node will be accepted. 22 asynReqResource54 RSC If set to 1 for local bus node number 54, asynchronous requests received by the PCI4450 from that node will be accepted. 21 asynReqResource53 RSC If set to 1 for local bus node number 53, asynchronous requests received by the PCI4450 from that node will be accepted. 20 asynReqResource52 RSC If set to 1 for local bus node number 52, asynchronous requests received by the PCI4450 from that node will be accepted. 168 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 119. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 19 asynReqResource51 RSC If set to 1 for local bus node number 51, asynchronous requests received by the PCI4450 from that node will be accepted. 18 asynReqResource50 RSC If set to 1 for local bus node number 50, asynchronous requests received by the PCI4450 from that node will be accepted. 17 asynReqResource49 RSC If set to 1 for local bus node number 49, asynchronous requests received by the PCI4450 from that node will be accepted. 16 asynReqResource48 RSC If set to 1 for local bus node number 48, asynchronous requests received by the PCI4450 from that node will be accepted. 15 asynReqResource47 RSC If set to 1 for local bus node number 47, asynchronous requests received by the PCI4450 from that node will be accepted. 14 asynReqResource46 RSC If set to 1 for local bus node number 46, asynchronous requests received by the PCI4450 from that node will be accepted. 13 asynReqResource45 RSC If set to 1 for local bus node number 45, asynchronous requests received by the PCI4450 from that node will be accepted. 12 asynReqResource44 RSC If set to 1 for local bus node number 44, asynchronous requests received by the PCI4450 from that node will be accepted. 11 asynReqResource43 RSC If set to 1 for local bus node number 43, asynchronous requests received by the PCI4450 from that node will be accepted. 10 asynReqResource42 RSC If set to 1 for local bus node number 42, asynchronous requests received by the PCI4450 from that node will be accepted. 9 asynReqResource41 RSC If set to 1 for local bus node number 41, asynchronous requests received by the PCI4450 from that node will be accepted. 8 asynReqResource40 RSC If set to 1 for local bus node number 40, asynchronous requests received by the PCI4450 from that node will be accepted. 7 asynReqResource39 RSC If set to 1 for local bus node number 39, asynchronous requests received by the PCI4450 from that node will be accepted. 6 asynReqResource38 RSC If set to 1 for local bus node number 38, asynchronous requests received by the PCI4450 from that node will be accepted. 5 asynReqResource37 RSC If set to 1 for local bus node number 37, asynchronous requests received by the PCI4450 from that node will be accepted. 4 asynReqResource36 RSC If set to 1 for local bus node number 36, asynchronous requests received by the PCI4450 from that node will be accepted. 3 asynReqResource35 RSC If set to 1 for local bus node number 35, asynchronous requests received by the PCI4450 from that node will be accepted. 2 asynReqResource34 RSC If set to 1 for local bus node number 34, asynchronous requests received by the PCI4450 from that node will be accepted. 1 asynReqResource33 RSC If set to 1 for local bus node number 33, asynchronous requests received by the PCI4450 from that node will be accepted. 0 asynReqResource32 RSC If set to 1 for local bus node number 32, asynchronous requests received by the PCI4450 from that node will be accepted. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 169 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 asynchronous request filter low register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Asynchronous request filter low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Asynchronous request filter low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Asynchronous request filter low Read/Set/Clear 108h set register 10Ch clear register Default: 0000 0000h Description: This set/clear register is used to enable asynchronous receive requests on a per node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identical to the asynchronous request filter high register. Table 120. Asynchronous Request Filter Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 asynReqResource31 RSC If set to 1 for local bus node number 31, asynchronous requests received by the PCI4450 from that node will be accepted. 30 asynReqResource30 RSC If set to 1 for local bus node number 30, asynchronous requests received by the PCI4450 from that node will be accepted. 170 L L L 1 asynReqResource1 RSC If set to 1 for local bus node number 1, asynchronous requests received by the PCI4450 from that node will be accepted. 0 asynReqResource0 RSC If set to 1 for local bus node number 0, asynchronous requests received by the PCI4450 from that node will be accepted. Bits 29 through 2 follow the same pattern. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 physical request filter high register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Physical request filter high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Physical request filter high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Physical request filter high Read/Set/Clear 110h set register 114h clear register Default: 0000 0000h Description: This set/clear register is used to enable physical receive requests on a per node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set in this register, then the request will be handled by the ARRQ context instead of the physical request context. Table 121. Physical Request Filter High Register Description BIT FIELD NAME TYPE DESCRIPTION 31 physReqAllBusses RSC If set to 1, then all asynchronous requests received by the PCI4450 from nonlocal bus nodes will be accepted. 30 physReqResource62 RSC If set to 1 for local bus node number 62, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 29 physReqResource61 RSC If set to 1 for local bus node number 61, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 28 physReqResource60 RSC If set to 1 for local bus node number 60, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 27 physReqResource59 RSC If set to 1 for local bus node number 59, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 26 physReqResource58 RSC If set to 1 for local bus node number 58, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 25 physReqResource57 RSC If set to 1 for local bus node number 57, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 24 physReqResource56 RSC If set to 1 for local bus node number 56, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 23 physReqResource55 RSC If set to 1 for local bus node number 55, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 22 physReqResource54 RSC If set to 1 for local bus node number 54, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 21 physReqResource53 RSC If set to 1 for local bus node number 53, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 20 physReqResource52 RSC If set to 1 for local bus node number 52, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 19 physReqResource51 RSC If set to 1 for local bus node number 51, then physical requests received by the PCI4450 from that node will be handled through the physical request context. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 171 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 121. Physical Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 physReqResource50 RSC If set to 1 for local bus node number 50, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 17 physReqResource49 RSC If set to 1 for local bus node number 49, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 16 physReqResource48 RSC If set to 1 for local bus node number 48, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 15 physReqResource47 RSC If set to 1 for local bus node number 47, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 14 physReqResource46 RSC If set to 1 for local bus node number 46, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 13 physReqResource45 RSC If set to 1 for local bus node number 45, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 12 physReqResource44 RSC If set to 1 for local bus node number 44, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 11 physReqResource43 RSC If set to 1 for local bus node number 43, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 10 physReqResource42 RSC If set to 1 for local bus node number 42, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 9 physReqResource41 RSC If set to 1 for local bus node number 41, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 8 physReqResource40 RSC If set to 1 for local bus node number 40, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 7 physReqResource39 RSC If set to 1 for local bus node number 39, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 6 physReqResource38 RSC If set to 1 for local bus node number 38, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 5 physReqResource37 RSC If set to 1 for local bus node number 37, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 4 physReqResource36 RSC If set to 1 for local bus node number 36, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 3 physReqResource35 RSC If set to 1 for local bus node number 35, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 2 physReqResource34 RSC If set to 1 for local bus node number 34, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 1 physReqResource33 RSC If set to 1 for local bus node number 33, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 0 physReqResource32 RSC If set to 1 for local bus node number 32, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 172 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 physical request filter low register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Physical request filter low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Physical request filter low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Physical request filter low Read/Set/Clear 118h set register 11Ch clear register Default: 0000 0000h Description: This set/clear register is used to enable physical receive requests on a per node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register. If the bit corresponding to the node ID is not set in this register, then the request will be handled by the asynchronous request context instead of the physical request context. Table 122. Physical Request Filter Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 physReqResource31 RSC If set to 1 for local bus node number 31, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 30 physReqResource30 RSC If set to 1 for local bus node number 30, then physical requests received by the PCI4450 from that node will be handled through the physical request context. L L L 1 physReqResource1 RSC If set to 1 for local bus node number 1, then physical requests received by the PCI4450 from that node will be handled through the physical request context. 0 physReqResource0 RSC If set to 1 for local bus node number 0, then physical requests received by the PCI4450 from that node will be handled through the physical request context. Bits 29 through 2 follow the same pattern. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 173 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 physical upper bound register (optional register) Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Physical upper bound Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Physical upper bound Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: 174 Physical upper bound Read-only 120h 0000 0000h This register is an optional register and is not implemented. This register is read-only and returns all 0s. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 asynchronous context control register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Asynchronous context control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Asynchronous context control RSCU R R RSU RU RU R R RU RU RU RU RU RU RU RU 0 0 0 X 0 0 0 0 X X X X X X X X Register: Type: Offset: Asynchronous context control Read/Set/Clear/Update 180h set register [ATRQ] 184h clear register [ATRQ] 1A0h set register [ATRS] 1A4h clear register [ATRS] 1C0h set register [ARRQ] 1C4h clear register [ARRQ] 1E0h set register [ATRS] 1E4h clear register [ATRS] Default: 0000 X0XXh Description: This set/clear register controls the state and indicates status of the DMA context. Table 123. Asynchronous Context Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31–16 RSVD R 15 run RSCU 14–13 RSVD R 12 wake RSU Software sets this bit to cause the PCI4450 to continue or resume descriptor processing. The PCI4450 will clear this bit on every descriptor fetch. Reserved. These bits return 0s when read. This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The PCI4450 will only change this bit on a hardware or software reset. Reserved. These bits return 0s when read. 11 dead RU The PCI4450 sets this bit when it encounters a fatal error and clears the bit when software resets the run bit. 10 active RU The PCI4450 sets this bit to 1 when it is processing descriptors. 9–8 RSVD R 7–5 spd RU This field indicates the speed at which a packet was received or transmitted, and only contains meaningful information for receive contexts. This field is encoded as: 000b = 100 Mbits/sec, 001b = 200 Mbits/sec, 010b = 400 Mbits/sec, and all other values are reserved. 4–0 eventcode RU This field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 175 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 asynchronous context command pointer register Bit 31 30 29 28 27 Name Type 26 25 24 23 22 21 20 19 18 17 16 Asynchronous context command pointer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Asynchronous context command pointer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU X X X X X X X X X X X X X X X X Register: Type: Offset: Asynchronous context command pointer Read/Write/Update 19Ch [ATRQ] 1ACh [ATRS] 1CCh [ATRQ] 1ECh [ATRS] Default: XXXX XXXXh Description: This register contains a pointer to the address of the first descriptor block that the PCI4450 will access when software enables the context by setting the ContextControl.run bit. Table 124. Asynchronous Context Command Pointer Register Description BIT FIELD NAME TYPE 31–4 descriptorAddress RWU Contains the upper 28 bits of the address of a 16-byte aligned descriptor block. 3–0 Z RWU Indicates the number of contiguous descriptors at the address pointed to by the descriptor address. If Z is 0, it indicates that the descriptorAddress is not valid. 176 DESCRIPTION POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 isochronous transmit context control register Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Isochronous transmit context control RSCU RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Isochronous transmit context control RSC R R RSU RU RU R R RU RU RU RU RU RU RU RU 0 0 0 X 0 0 0 0 X X X X X X X X Register: Type: Offset: Isochronous transmit context control Read/Set/Clear/Update 200h + (16 * n) set register 204h + (16 * n) clear register Default: XXXX X0XXh Description: This set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …). Table 125. Isochronous Transmit Context Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 cycleMatchEnable RSCU When set to 1, processing will occur such that the packet described by the context’s first descriptor block will be transmitted in the cycle whose number is specified in the cycleMatch field of this register. The 13-bit cycleMatch field must match the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. 30–16 cycleMatch RSC Contains a 15-bit value, corresponding to the lower order 2 bits of cycleSeconds and 13-bit cycleCount field. If cycleMatchEnable is set, then this IT DMA context will become enabled for transmits when the bus cycleCount value equals the cycleMatch value. 15 run RSC This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The PCI4450 will only change this bit on a hardware or software reset. 14–13 RSVD R 12 wake RSU Software sets this bit to cause the PCI4450 to continue or resume descriptor processing. The PCI4450 will clear this bit on every descriptor fetch. 11 dead RU The PCI4450 sets this bit when it encounters a fatal error, and clears the bit when software resets the run bit. 10 active RU The PCI4450 sets this bit to 1 when it is processing descriptors. 9–8 RSVD R 7–5 spd RU This field in not meaningful for isochronous transmit contexts. 4–0 event code RU Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown. Reserved. These bits return 0s when read. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 177 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 isochronous transmit context command pointer register Bit 31 30 29 28 27 Name 26 25 24 23 22 21 20 19 18 17 16 Isochronous transmit context command pointer Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous transmit context command pointer Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Register: Type: Offset: Default: Description: 178 Isochronous transmit context command pointer Read-only 20Ch + (16 * n) XXXX XXXXh This register contains a pointer to the address of the first descriptor block that the PCI4450 will access when software enables an ISO transmit context by setting the ContextControl.run bit. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 ischronous receive context control register Bit 31 30 29 28 27 Name Type 26 25 24 23 22 21 20 19 18 17 16 Ischronous receive context control RSC RSC RSCU RSC R R R R R R R R R R R R Default X X X X 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Ischronous receive context control RSCU R R RSU RU RU R R RU RU RU RU RU RU RU RU 0 0 0 X 0 0 0 0 X X X X X X X X Register: Type: Offset: Ischronous receive context control Read/Set/Clear/Update 400h + (32 * n) set register 404h + (32 * n) clear register Default: X000 X0XXh Description: This set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …). Table 126. Isochronous Receive Context Control BIT FIELD NAME TYPE DESCRIPTION 31 bufferFill RSC When set, received packets are placed back-to-back to completely fill each receive buffer. When clear, each received packet is placed in a single buffer. If the multiChanMode bit is set to 1, this bit must also be set to 1. The value of bufferFill must not be changed while active or run are set. 30 isochHeader RSC When set to 1, received isochronous packets will include the complete 4-byte isochronous packet header seen by the link layer. The end of the packet will be marked with a xferStatus in the first doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet. When clear, the packet header is stripped off of received isochronous packets. The packet header, if received, immediately precedes the packet payload. The value of isochHeader must not be changed while active or run are set. 29 cycleMatchEnable RSCU When set, the context will begin running only when the 13-bit cycleMatch field in the contextMatch register matches the 13-bit cycleCount in the cycleStart packet. The effects of this bit, however, are impacted by the values of other bits in this register. Once the context has become active, hardware clears the cycleMatchEnable bit. The value of cycleMatchEnable must not be changed while active or run are set. 28 multiChanMode RSC When set, the corresponding isochronous receive DMA context will receive packets for all isochronous channels enabled in the IRChannelMaskHi and IRChannelMaskLo registers. The isochronous channel number specified in the IRDMA context match register is ignored. When 0, the IRDMA context will receive packets for that single channel. Only one IRDMA context may use the IRChannelMask registers. If more that one IRDMA context control register has the multiChanMode bit set, results are undefined. The value of multiChanMode must not be changed while active or run are set. 27–16 RSVD R 15 run RSCU 14–13 RSVD R 12 wake RSU Software sets this bit to cause the PCI4450 to continue or resume descriptor processing. The PCI4450 will clear this bit on every descriptor fetch. 11 dead RU The PCI4450 sets this bit when it encounters a fatal error, and clears the bit when software resets the run bit. 10 active RU The PCI4450 sets this bit to 1 when it is processing descriptors. Reserved. These bits return 0s when read. This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The PCI4450 will only change this bit on a hardware or software reset. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 179 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 126. Isochronous Receive Context Control (Continued) 9–8 RSVD R Reserved. These bits return 0s when read. 7–5 spd RU This field indicates the speed at which the packet was received. 3’b000 = 100 Mbits/sec, 3’b001 = 200 Mbits/sec, and 3’b010 = 400 Mbits/sec. All other values are reserved. 4–0 event code RU Following and INPUT* command, the error code is indicated in this field. isochronous receive context command pointer register Bit 31 30 29 28 27 R R R R R Name Type 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive context command pointer R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous receive context command pointer Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Register: Type: Offset: Default: Description: 180 Isochronous receive context command pointer Read-only 40Ch + (32 * n) XXXX XXXXh This register contains a pointer to the address of the first descriptor block that the PCI4450 will access when software enables an ISO receive context by setting the ContextControl.run bit. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 isochronous receive context match register Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous receive context match Type R R R R R R R R R R R R R R R R Default X X X X 0 0 0 X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous receive context match Type R R R R R R R R R R R R R R R R Default X X X X X X X X 0 X X X X X X X Register: Type: Offset: Default: Description: Isochronous receive context match Read/Write 410Ch + (32 * n) XXXX XXXXh This register is used to start an isochronous receive context running on a specified cycle number, to filter incoming isochronous packets based on tag values, and to wait for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …). Table 127. Isochronous Receive Context Match Register Description BIT FIELD NAME TYPE DESCRIPTION 31 tag3 R/W If set, this context will match on iso receive packets with a tag field of 2’b11. 30 tag2 R/W If set, this context will match on iso receive packets with a tag field of 2’b10. 29 tag1 R/W If set, this context will match on iso receive packets with a tag field of 2’b01. 28 tag0 R/W If set, this context will match on iso receive packets with a tag field of 2’b00. 27–25 RSVD R 24–12 cycleMatch R/W Reserved. These bits return 0s when read. Contains a 13-bit value, corresponding to the 13-bit cycleCount field in the cycleStart packet. If cycleMatchEnable is set, then this context is enabled for receives when the bus cycleCount value equals the cycleMatch value. 11–8 sync R/W This field contains the 4-bit field which is compared to the sync field of each iso packet for this channel when the command descriptor’s w field is set to 2’b11. 7 RSVD R 6 tag1SyncFilter R/W Reserved. These bits return 0s when read. If set and the tag1 bit is set , then packets with tag2b01 shall be accepted into the context if the two most significant bits of the packets sync field are 2’b00. Packets with tag values other than 2’b01 are filtered according to tag0, tag2 and tag3 without any additional restrictions. If clear, this context will match on isochronous receive packets as specified in the tag0–3 bits with no additional restrictions. 5–0 channelNumber R/W This 6-bit field indicates the isochronous channel number for which this IR DMA context will accept packets. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 181 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 GPIO interface The GPIO interface consists of four general-purpose input output ports. On power reset, GPIO0 and GPIO1 are enabled and are configured as bus manager contender (BMC) and link power status (LPS) , respectively. BMC and LPS outputs can be configured via the GPIO control register in PCI Configuration space, as GPIO0 and GPIO1. Figure 3 shows the schematic for GPIO0 and GPIO implementation. GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register. Figure 4 shows the schematic for GPIO2 and GPIO3 implementation. GPIO Read Data GPIO Write Data D GPIO Port Q BMC GPIO_Invert Disable BMC GPIO Enable Figure 22. BMC/LINKON/GPIO0 GPIO Read Data GPIO Write Data D GPIO Port Q LPS GPIO_Invert Disable LPS GPIO Enable Figure 23. LPS/GPIO1 182 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 GPIO Read Data GPIO Write Data D GPIO Port Q GPIO_Invert GPIO Enable Figure 24. GPIO2 and GPIO3 serial EEPROM serial bus interface The PCI4450 provides a serial bus interface to initiallize the 1394 Global Unique ID register and a few PCI configuration registers through a serial EEPROM. The PCI4450 communicates with the serial EEPROM via the 2-wire serial interface. After power-up the serial interface initializes the locations listed in Table 128. While the PCI4450 is accessing the serial ROM , all incoming PCI Slave accesses are terminated with retry status. Table 129 shows the serial ROM memory map required for initializing the PCI4450 registers. Table 128. Registers and Bits Loadable through Serial EEPROM OFFSET REGISTER BITS LOADED FROM EEPROM OHCI Register (24h) 1394 GlobalUniqueIDHi 31–0 OHCI Register(28h) 1394 GlobalUniqueIDLo 31–0 OHCI Register (50h) Host Control Register PCI Register (2Ch) PCI Subsytem ID 15–0 PCI Register (2Dh) PCI Vendor ID 15–0 PCI Register (3Eh) PCI Maximum Latency, PCI Minimum Grant 15–0 PCI Register (F4h) Link Enhancements Control Register 7, 2, 1 POST OFFICE BOX 655303 23 • DALLAS, TEXAS 75265 183 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 129. Serial EEPROM Map BYTE ADDRESS 00 BYTE DESCRIPTION PCI maximum latency (4’h0) PCI_Minimum grant (4’h0) 01 PCI vendor ID 02 PCI vendor ID (ms byte) 03 PCI subsytem ID (ls byte) 04 05 184 PCI subsytem ID [7] Link_enhancementControl.enab_unfair [6] HCControl. ProgramPhy Enable [5] RSVD [4] RSVD [3] RSVD [2] Link_enhancementControl.enab_ insert_idle 06 Reserved 07 1394 GlobalUniqueIDHi (ls byte 0) 08 1394 GlobalUniqueIDHi (byte 1) 09 1394 GlobalUniqueIDHi (byte 2) 0A 1394 GlobalUniqueIDHi (ms byte 3) 0B 1394 GlobalUniqueIDLo (ls byte 0) 0C 1394 GlobalUniqueIDLo (byte 1) 0D 1394 GlobalUniqueIDLo (byte 2) 0E 1394 GlobalUniqueIDLo (ms byte 3) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 [1] Link_enhancementControl.enab_accel [0] RSVD PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 absolute maximum ratings over operating temperature ranges (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Clamping voltage range, VCCP, VCCA, VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCA + 0.5 V Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCB + 0.5 V ZV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Miscellaneous and Phy I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCC + 0.5 V Output voltage range, VO: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCA + 0.5 V Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCB + 0.5 V ZV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Miscellaneous and Phy I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCA or VCCB. ZV terminals and TTL signals are measured with respect to VCC. The limit specified applies for a dc condition. 2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCA or VCCB. ZV terminals and TTL signals are measured with respect to VCC. The limit specified applies for a dc condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 185 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 recommended operating conditions (see Note 3) VCC Core voltage Commercial VCCP PCI I/O voltage, voltage ZV Port I/O voltage Commercial VCCA/B PC Card I/O voltage OPERATION MIN NOM MAX UNIT 3.3 V 3 3.3 3.6 V 3.3 V 3 3.3 3.6 5V 4.5 5 5.5 3.3 V 3 3.3 3.6 5V 4.75 5 5.25 3.3 V 0.5 VCCP 5V 2 3.3 V 0.475 VCCA/B 5V 2.4 Commercial PCI VIH† PC Card High-level Hi h l l Input I t voltage lt PHY I/F TTL‡ 2 2 Fail safe§ PCI VIL† PC Card Low-level L l l input i t voltage lt 2.4 VI PC Card VO¶ Output Out ut voltage VCCA/B VCCA/B V VCC VCC V V V 0 0 0.8 3.3 V 0 0.325 VCCA/B 5V 0 0.8 0 0.8 V 0 0.8 V V 0 0.8 3.3 V 0 5V 0 VCCP VCCA/B 0 VCC VCC 0 Fail safe§ PCI V 5V PHY I/F TTL‡ In Input ut voltage VCCP VCCP 3.3 V Fail safe§ PC Card V VCC 0.3 VCCP PHY I/F TTL‡ PCI V 0 3.3 V 0 5V 0 V V V VCC VCC VCC VCC PHY I/F TTL‡ 0 Fail safe§ 0 VCC VCC PCI and PC Card 1 4 TTL and fail safe 0 6 0 V V tt Input transition times (tr and tf) ns TA TJ# Operating ambient temperature range 0 25 70 _C Virtual junction temperature 0 25 115 _C † Applies to external inputs and bidirectional buffers without hysteresis ‡ TTL 4 mA pins are A_CVS1//A_VS1, A_CVS2//A_VS2, B_CVS1//B_VS1, B_CVS2//B_VS2, CLOCK, DATA, LATCH, SPKROUT, MFUNC4–MFUNC0, SCL, SDA, ZV_UVx, ZV_PCLK, ZV_SDATA, ZV_LRCLK, ZV_MCLK, ZV_VSYNC, ZV_HREF, ZV_SCLK, ZV_Yx, SUSPEND, LPS, PHY_LREQ. TTL 8 mA pins are MFUNC6, MFUNC5, PHY_CTL0, PHY_CTL1, PHY_DATAx, and LINKON. § Fail-safe pin is RI_OUT (open drain). ¶ Applies to external output buffers # These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. 186 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER PINS OPERATION 3.3 V PCI PC Card VOH High le el output High-level o tp t voltage oltage (see Note 4) PHY I/F 5V VOL 5V IOH = –0.15 mA 2.4 3.3 V IOH = –4 mA 2.8 3.3 V IOL = –8 mA VCC–0.6 IOH = –4 mA VCC–0.6 IOH = –8 mA VCC–0.6 5V 0.1 VCC 0.55 3.3 V IOL = 0.7 mA 0.1 VCC 5V IOL = 0.7 mA 0.55 IOL = 4 mA 0.5 3.3 V IOL = 8 mA 0.5 IOL = 4 mA 0.5 IOL = 8 mA 0.5 IOL = 8 mA 0.5 VI = VCC VI = VCC –1 VI = VCC† VI = VCC† 10 Input pins VI = GND –1 I/O pins VI = GND –10 Latch VI = GND VI = VCC‡ –2 VI = VCC‡ VI = VCC‡ 20 VI = VCC‡ VI = VCC 25 PHY I/F SERR 3.6 V IOZL 3-state out output, ut, high-impedance high-im edance state current (see Note 4) Output pins IOZH 3-state out output, ut, high-impedance high-im edance state current Output pins 5.25 V 3.6 V 5.25 V 3.6 V Input pins IIH IOL = 6 mA V 3.3 V Low-level output voltage g Low-level input current IOL = 1.5 mA High-level input current (see Note 5) 5.25 V 3.6 V I/O pins Fail-safe pins 5.25 V –1 25 V V V V µA A µA A µA µ 10 10 µA 10 † For PCI pins, VI = VCCP. For PC Card pins, VI = VCC(A/B). For ZV pins, VI = VCC. For miscellaneous pins, VI = VCC. ‡ For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. NOTES: 4. VOH and IOL are not tested on SERR (GFN pin Y20, GJG pin W18)and RI_OUT (GFN pin Y13, GJG pin R11) because they are open-drain outputs. 5. IIH is not tested on LATCH (GFN pin W12, GJG pin W11) because it is pulled up with an internal resistor. POST OFFICE BOX 655303 3.6 V UNIT 2.4 0.9 VCC TTL IIL IOH = –2 mA MAX 0.9 VCC IOH = –0.15 mA 3.3 V PC Card IOH = –0.5 mA MIN 3.3 V TTL PCI TEST CONDITIONS • DALLAS, TEXAS 75265 187 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 26 and Figure 27) ALTERNATE SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT tc Cycle time, PCLK tcyc 30 ns twH Pulse duration, PCLK high thigh 11 ns twL Pulse duration, PCLK low tlow 11 ns ∆v/∆t Slew rate, PCLK tr, tf 1 tw Pulse duration, RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN 100 ms trst-clk 4 V/ns PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 7, Figure 25, and Figure 28) ALTERNATE SYMBOL PARAMETER tpd Pro agation delay time, Propagation See Note 6 PCLK-to-shared signal valid delay time tval PCLK-to-shared signal invalid delay time tinv ten tdis Enable time, high impedance-to-active delay time from PCLK tsu th Setup time before PCLK valid Disable time, active-to-high impedance delay time from PCLK Hold time after PCLK high TEST CONDITIONS MIN MAX UNIT 11 CL = 50 pF, F, See Note 7 ns 2 ton toff 2 ns tsu th 7 ns 0 ns 28 ns NOTES: 6. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR. 7. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. Switching characteristics for PHY-Link interface PARAMETER MEASURED MIN tsu Setup time, Dn, CTLn, LREQ to PHY_CLK –50% to 50% 6 th Hold time, Dn, CTLn, LREQ before PHY_CLK –50% to 50% 1 td Delay time, PHY_CLK to Dn, CTLn –50% to 50% 2 188 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP MAX UNIT ns 11 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PARAMETER MEASUREMENT INFORMATION LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD† (pF) IOL (mA) IOH (mA) VLOAD‡ (V) 50 8 –8 0 3 50 8 –8 1.5 50 8 –8 ‡ IOL Test Point From Output Under Test VLOAD CLOAD † CLOAD includes the typical load-circuit distributed capacitance. IOH ‡ VLOAD – VOL = 50 Ω, where V OL = 0.6 V, IOL = 8 mA IOL LOAD CIRCUIT VCC Timing Input (see Note A) 50% VCC High-Level Input 0V th tsu 90% VCC Data Input 10% VCC 50% VCC 50% VCC Low-Level Input 0V tf VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES Output Control (low-level enabling) 50% VCC tPLZ tpd 50% VCC tpd 50% VCC VOH 50% VCC VOL tpd Waveform 1 (see Notes B and C) VOH 50% VCC VOL Waveform 2 (see Notes B and C) 50% VCC tPHZ tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 50% VCC 0V 0V In-Phase Output VCC 50% VCC 0V VCC tPZL 50% VCC tpd Out-of-Phase Output 50% VCC VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC VCC 50% VCC 0V tw VCC tr Input (see Note A) 50% VCC 50% VCC VCC ≅ 50% VCC VOL + 0.3 V VOL VOH VOH – 0.3 V ≅ 50% VCC 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the following characteristics: PRR = 1 MHz, ZO = 50 Ω, tr = 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ, VOL and VOH are measured values. Figure 25. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 189 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PCI BUS PARAMETER MEASUREMENT INFORMATION thigh tlow 2V 2 V MIN Peak-to-Peak 0.8 V tf tr tcyc Figure 26. PCLK Timing Waveform PCLK trst RSTIN tsrst-clk Figure 27. RSTIN Timing Waveforms PCLK 1.5 V tval PCI Output tinv Valid 1.5 V ton toff PCI Input Valid tsu th Figure 28. Shared Signals Timing Waveforms 190 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PC Card cycle timing The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL-DF timing as possible, while always slightly exceeding the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. The PC Card address setup and hold times are a function of the wait-state bits. Table 130 shows address setup time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 131 and Table 132 show command active time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 133 shows address hold time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 130. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles TS1 – 0 = 01 (PCLK/ns) WAIT-STATE BITS I/O 3/90 Memory WS1 0 2/60 Memory WS1 1 4/120 Table 131. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles WAIT-STATE BITS ZWS TS1 – 0 = 01 (PCLK/ns) 0 0 19/570 1 X 23/690 0 1 7/210 00 0 19/570 01 X 23/690 10 X 23/690 11 X 23/690 00 1 7/210 WS I/O Memory Table 132. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles WAIT-STATE BITS I/O Memory y WS ZWS TS1 – 0 = 01 (PCLK/ns) 0 0 7/210 1 X 11/330 0 1 N/A 00 0 9/270 01 X 13/390 10 X 17/510 11 X 23/630 00 1 5/150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 191 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 Table 133. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles TS1 – 0 = 01 (PCLK/ns) WAIT-STATE BITS I/O 2/60 Memory WS1 0 2/60 Memory WS1 1 3/90 timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see Note 8 and Figure 29) ALTERNATE SYMBOL MIN MAX UNIT tsu tsu Setup time, CE1 and CE2 before WE/OE low T1 60 ns Setup time, CA25–CA0 before WE/OE low T2 ns tsu tpd Setup time, REG before WE/OE low T3 tsu(A)+2PCLK 90 Propagation delay time, WE/OE low to WAIT low T4 tw th Pulse duration, WE/OE low T5 Hold time, WE/OE low after WAIT high T6 th tsu Hold time, CE1 and CE2 after WE/OE high T7 Setup time (read), CDATA15–CDATA0 valid before OE high T8 th th Hold time (read), CDATA15–CDATA0 valid after OE high T9 0 ns Hold time, CA25–CA0 and REG after WE/OE high T10 ns tsu th Setup time (write), CDATA15–CDATA0 valid before WE low T11 th(A)+1PCLK 60 Hold time (write), CDATA15–CDATA0 valid after WE low T12 240 ns ns ns 200 ns ns 120 ns ns ns NOTE 8: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock. timing requirements over recommended ranges of supply voltage and operating free-air temperature, I/O cycles (see Figure 30) ALTERNATE SYMBOL MIN MAX UNIT tsu tsu Setup time, REG before IORD/IOWR low T13 Setup time, CE1 and CE2 before IORD/IOWR low tsu tpd Setup time, CA25–CA0 valid before IORD/IOWR low Propagation delay time, IOIS16 low after CA25–CA0 valid T16 tpd tw Propagation delay time, IORD low to WAIT low T17 35 ns Pulse duration, IORD/IOWR low T18 TcA ns th th Hold time, IORD low after WAIT high T19 Hold time, REG low after IORD high T20 th th Hold time, CE1 and CE2 after IORD/IOWR high Hold time, CA25–CA0 after IORD/IOWR high tsu th Setup time (read), CDATA15–CDATA0 valid before IORD high T23 Hold time (read), CDATA15–CDATA0 valid after IORD high tsu th Setup time (write), CDATA15–CDATA0 valid before IOWR low Hold time (write), CDATA15–CDATA0 valid after IOWR high 192 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 60 ns T14 60 ns T15 tsu(A)+2PCLK ns 35 ns ns 0 ns T21 120 ns T22 th(A)+1PCLK 10 ns T24 0 ns T25 90 ns T26 90 ns ns PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see Figure 31) ALTERNATE SYMBOL PARAMETER BVD2 low to SPKROUT low tpd d MAX UNIT 30 BVD2 high to SPKROUT high Propagation delay time MIN IREQ to IRQ15–IRQ3 T27 30 30 T28 STSCHG to IRQ15–IRQ3 ns 30 PC Card PARAMETER MEASUREMENT INFORMATION CA25–CA0 T10 REG CE1, CE2 T1 WE, OE T5 T7 T3 T2 T6 T4 WAIT T12 T11 CDATA15–CDATA0 (write) T8 T9 CDATA15–CDATA0 (read) With no wait state With wait state Figure 29. PC Card Memory Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 193 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 PC Card PARAMETER MEASUREMENT INFORMATION CA25–CA0 T16 T22 IOIS16 REG T20 CE1, CE2 T14 IORD, IOWR T13 T15 T18 T21 T19 T17 WAIT T26 T25 CDATA15–CDATA0 (write) T23 T24 CDATA15–CDATA0 (read) With no wait state With wait state Figure 30. PC Card I/O Cycle BVD2 T27 SPKROUT IREQ T28 IRQ15–IRQ3 Figure 31. Miscellaneous PC Card Delay Times 194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 MECHANICAL DATA GFN (S-PBGA-N256) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 24,70 SQ 24,00 24,13 TYP 1,27 0,635 0,635 1,27 Y W V U T R P N M L K J H G F E D C B A 1 3 2 2,32 1,92 5 4 7 6 9 8 10 11 13 15 17 19 12 14 16 18 20 0,40 0,30 Seating Plane 0,70 0,50 0,80 0,60 0,10 M 0,15 4040185-2/B 11/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 195 PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 MECHANICAL DATA GJG (S-PBGA-N257) PLASTIC BALL GRID ARRAY 16,10 SQ 15,90 14,40 TYP 0,80 W V U T R P N M L K J H G F E D C B A 0,80 1 3 2 0,95 0,85 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4173511/A 08/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration Micro Star is a trademark of Texas Instruments Incorporated. 196 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated