PCKEP14 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver Rev. 01 — 30 October 2002 Product data 1. Description The PCKEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the PCKEP14 is operating under PECL conditions. The PCKEP14 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device, and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 Ω resistors, even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The common enable (EN) is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled, as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. The PCKEP14, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the PCKEP14 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ 100 ps device-to-device skew 25 ps within device skew 400 ps typical propagation delay Maximum frequency > 2 GHz (typical) Contains temperature compensation PECL and HSTL mode: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL mode: VCC = 0 V with VEE = −2.375 V to −3.8 V LVDS input compatible Open input default state. PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 3. Pinning information 3.1 Pinning 20 VCC Q0 1 20 VCC Q0 2 19 EN Q0 2 19 EN Q1 3 18 VCC Q1 3 18 VCC Q1 4 17 CLK1 Q1 4 17 CLK1 Q2 5 16 CLK1 Q2 5 Q2 6 15 VBB Q2 6 Q3 7 14 CLK0 Q3 7 Q3 8 13 CLK0 Q3 8 13 CLK0 Q4 9 12 CLK_SEL Q4 9 12 CLK_SEL 11 VEE Q4 10 11 VEE Q4 10 002aaa354 PCKEP14PW 1 PCKEP14D Q0 16 CLK1 15 VBB 14 CLK0 002aaa221 Fig 1. SO20 pin configuration. Fig 2. TSSOP20 pin configuration. 3.2 Pin description Table 1: 3.2.1 Pin description Symbol Pin Description Q0-Q4 1, 3, 5, 7, 9 Positive ECL/PECL output Q0-Q4 2, 4, 6, 8, 10 Negative ECL/PECL output VEE 11 Negative supply CLK_SEL 12 ECL/PECL active clock select input. Pin will default LOW when left open. CLK0, CLK1 13, 16 ECL/PECL/HSTL CLK input. Pins will default LOW when left open. CLK0, CLK1 14, 17 ECL/PECL/HSTL CLK input. Pins will default to VCC/2 when left open. VBB 15 Reference voltage output VCC 18, 20 Positive supply EN 19 ECL synchronous enable Power supply connection CAUTION All VCC and VEE pins must be connected to power supply to guarantee proper operation. MSC895 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 2 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 4. Ordering information Table 2: Ordering information Type number Package Name Description Version PCKEP14D SO20 plastic small outline package 8 leads; body width 7.5 mm SOT163-1 PCKEP14PW TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 5. Logic diagram Q0 Q0 Q1 1 20 2 19 3 18 17 4 Q1 D VCC EN VCC CLK1 Q 16 5 Q2 6 Q2 1 15 CLK1 VBB 0 7 Q3 8 Q3 Q4 Q4 14 13 9 12 10 11 CLK0 CLK0 CLK_SEL VEE 002aaa222 Fig 3. Logic diagram. CAUTION All VCC and VEE pins must be connected to power supply to guarantee proper operation. MSC895 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 3 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 6. Function table Table 3: Function table CLK0 CLK1 CLK_SEL EN Q L X L L L H X L L H X L H L L X H H L H X X X H L[1] [1] On next negative transition of CLK0 or CLK1. 7. Attributes Table 4: Attributes Characteristic Value internal input pull-down resistor 75 kΩ internal input pull-up resistor 37.5 kΩ ESD protection Human Body Model > 2.5 kV Machine Model > 100 V Charged Device Model > 1 kV moisture sensitivity, indefinite time out of drypack Level 1 flammability rating UL-94 code V-0 A 1/8” Meets or exceeds JEDEC Specification EIA/JEDS78 IC latch-up test. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 4 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC PECL mode power supply VEE = 0 V - 4.1 V VEE NECL mode power supply VCC = 0 V - −4.1 V VI PECL mode input voltage VEE = 0 V; VI ≤ VCC - 4.1 V NECL mode input voltage VCC = 0 V; VI ≥ VEE - −4.1 V Iout output current continuous - 50 mA - 100 mA IBB VBB source current 0 0.1 mA Tamb operating ambient temperature −40 +85 °C Tstg storage temperature range −65 +150 °C Rth(j-a) thermal resistance from junction to ambient surge 0 LFPM - 140 °C/W 500 LFPM - 100 °C/W Rth(j-c) thermal resistance from junction to case 23 41 °C/W Tsld soldering temperature - 265 °C 9. Static characteristics Table 6: PECL DC characteristics[1] VCC = 2.5 V; VEE = 0 V [2] Symbol Parameter Tamb = −40 °C Conditions Min power supply current IEE 45 VOH HIGH-level output voltage [3] VOL LOW-level output voltage [3] VIH HIGH-level input voltage single-ended VIL LOW-level input voltage single-ended VIHCMR HIGH-level input voltage, common mode range (differential) IIH HIGH-level input current IIL LOW-level input current output reference voltage VBB [1] [2] [3] [4] Typ 60 Tamb = +25 °C Max 75 Min 45 Typ 60 Tamb = +85 °C Max 75 Min 45 Typ 60 Unit Max 75 mA 1355 1480 1605 1355 1500 1605 1355 1510 1605 mV 555 720 805 555 700 805 555 710 805 mV 1335 - 1620 1335 - 1620 1275 - 1620 mV 555 - 875 555 - 875 555 - 875 mV 1.2 - 2.5 1.2 - 2.5 1.2 - 2.5 V - - 150 - - 150 - - 150 µA CLK 0.5 - - 0.5 - - 0.5 - - µA CLK −150 - - −150 - - −150 - - µA [4] 1075 1165 1265 1065 1165 1265 1085 1180 1270 mV Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V. All loading with 50 Ω to VCC − 2 V. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 5 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver Table 7: PECL DC characteristics[1] VCC = 3.3 V; VEE = 0 V [2] Symbol Parameter IEE power supply current Tamb = −40 °C Conditions Min 45 VOH HIGH-level output voltage [3] VOL LOW-level output voltage [3] VIH HIGH-level input voltage VIL LOW-level input voltage single-ended single-ended VBB output reference voltage [4] VIHCMR HIGH-level input voltage, common mode range (differential) [5] IIH HIGH-level input current IIL LOW-level input current CLK CLK [1] [2] [3] [4] [5] Typ 60 Tamb = +25 °C Max 75 Min 45 Typ 60 Tamb = +85 °C Max 75 Min 45 Typ 60 Unit Max 75 mA 2155 2280 2405 2155 2300 2405 2155 2310 2405 mV 1355 1515 1605 1355 1500 1605 1355 1500 1605 mV 2135 - 2420 2135 - 2420 2135 - 2420 mV 1355 - 1675 1355 - 1675 1355 - 1675 mV 1875 1965 2065 1865 1965 2065 1885 1980 2070 mV 1.2 - 3.3 1.2 - 3.3 1.2 - 3.3 V - - 150 - - 150 - - 150 µA 0.5 - - 0.5 - - 0.5 - - µA −150 - - −150 - - −150 - - µA Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. All loading with 50 Ω to VCC − 2 V. Single-ended input operation is limited to VCC ≥ 3.0 V in PECL mode. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 6 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver Table 8: NECL DC characteristics[1] VCC = 0 V; VEE = −3.8 V to −2.375 V [2] Symbol Parameter Tamb = −40 °C Conditions Min Typ Max 75 Min 45 Typ 60 Max 75 Min Typ HIGH-level output voltage [3] −1145 −1020 −895 VOL LOW-level output voltage [3] −1945 −1785 −1695 −1945 −1800 −1695 −1945 −1800 −1695 mV VIH HIGH-level input voltage single-ended −1165 - −880 VIL LOW-level input voltage single-ended −1945 - −1625 −1945 - VBB output reference voltage [4] VIHCMR HIGH-level input voltage, common mode range (differential) [5] IIH HIGH-level input current IIL LOW-level input current −1165 - −880 60 Max VOH −1145 −1000 −895 45 Unit power supply current [2] [3] [4] [5] 60 Tamb = +85 °C IEE [1] 45 Tamb = +25 °C −1145 −990 −1165 - 95 mA −895 mV −880 −1625 −1945 - mV −1625 mV −1425 −1335 −1235 −1435 −1335 −1235 −1415 −1320 −1230 mV VEE+1.2 0 VEE+1.2 0 VEE+1.2 0 V - - 150 - - 150 - - 150 µA CLK 0.5 - - 0.5 - - 0.5 - - µA CLK −150 - - −150 - - −150 - - µA Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. All loading with 50 Ω to VCC − 2 V. Single-ended input operation is limited to VEE ≤ 3.0 V in NECL mode. VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 9: HSTL DC characteristics VCC = 2.375 V to 3.8 V; VEE = 0 V. Symbol Parameter Tamb = −40 °C Conditions Min Typ Tamb = +25 °C Max Min Typ Tamb = +85 °C Max Min Typ Unit Max VIH HIGH-level input voltage 1200 - - 1200 - - 1200 - - mV VIL LOW-level input voltage - - 400 - - 400 - - 400 mV © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 7 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 10. Dynamic characteristics Table 10: AC characteristics (VCC = 0 V; VEE = −2.375 V to −3.8 V) or (VCC = 2.375 V to 3.8 V; VEE = 0 V) [1] Symbol Parameter Tamb = −40 °C Conditions fmax(PECL/ maximum toggle frequency see Figure 4 Tamb = +25 °C Tamb = +85 °C Unit Min Typ Max Min Typ Max Min Typ Max - >2 - - >2 - - >2 - 250 345 425 275 360 475 300 430 525 ps - 10 25 - 15 25 - 15 25 ps GHz HSTL) tPLH, tPHL propagation delay to output differential tSKEW skew time within-device [2] - 100 125 - 150 175 - 200 225 ps - 0.2 <1 - 0.2 <1 - 0.2 <1 ps EN set-up time 100 50 - 100 50 - 100 50 - ps th EN hold time 200 140 - 200 140 - 200 140 - ps Vi(p-p) minimum input swing 150 800 1200 150 800 1200 150 800 1200 mV tr/tf output rise/fall times 125 205 250 125 200 250 125 200 275 part-to-part tJITTER cycle-to-cycle jitter tsu [1] [2] see Figure 4 (20% - 80%) ps Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC − 2.0 V. Skew is measured between outputs under identical transitions. 002aaa223 900 9 800 8 700 7 600 6 500 5 400 4 300 3 200 2 100 1 VOUT(p-p) (mV) 0 0 1000 2000 3000 0 4000 FREQUENCY (MHz) Fig 4. fmax. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 8 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 11. Application information Q D DRIVER DEVICE RECEIVER DEVICE Q D 50 Ω 50 Ω VTT 002aaa220 VTT = VCC − 2.0 V. Fig 5. Typical termination for output driver and device evaluation. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 9 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 Fig 6. SO20 package outline (SOT163-1). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 10 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-153 Fig 7. TSSOP20 package outline (SOT360-1). © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 11 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C small/thin packages. 13.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 12 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 13.5 Package related soldering information Table 11: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method Reflow[2] Wave BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[3] suitable PLCC[4], SO, SOJ suitable suitable recommended[4][5] LQFP, QFP, TQFP not SSOP, TSSOP, VSO not recommended[6] [1] [2] [3] [4] [5] [6] suitable suitable For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 14. Revision history Table 12: Revision history Rev Date 01 20021030 CPCN Description - Product data (9397 750 09565) Engineering Change Notice 853-2373 28877 (date: 20020909) © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Product data Rev. 01 — 30 October 2002 13 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver 15. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09565 Rev. 01 — 30 October 2002 14 of 15 PCKEP14 Philips Semiconductors 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver Contents 1 2 3 3.1 3.2 3.2.1 4 5 6 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power supply connection . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 12 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 13 Package related soldering information . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 © Koninklijke Philips Electronics N.V. 2002. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 30 October 2002 Document order number: 9397 750 09565