PCK940L Low voltage 1 : 18 clock distribution chip Rev. 01 — 4 April 2006 Product data sheet 1. General description The PCK940L is a 1 : 18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS compatible and feature the drive strength to drive 50 Ω series or parallel terminated transmission lines. With output-to-output skews of 150 ps, the PCK940L is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5 V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. With a low output impedance of approximately 20 Ω, in both the HIGH and LOW logic states, the output buffers of the PCK940L are ideal for driving series terminated transmission lines. With an output impedance of 20 Ω, the PCK940L has the capability of driving two series terminated transmission lines from each output. This gives the PCK940L an effective fan-out of 1 : 36. If a lower output impedance is desired, please see the PCK942C data sheet. The differential LVPECL inputs of the PCK940L allow the device to interface directly with a LVPECL fan-out buffer like the PCKEP111 to build very wide clock fan-out trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLKSEL pin will select the LVCMOS level clock input. All inputs of the PCK940L have internal pull-up/pull-down resistors so they can be left open if unused. The PCK940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3 V core and 3.3 V output, a 3.3 V core and 2.5 V outputs, as well as a 2.5 V core and 2.5 V outputs. The 32-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead LQFP package has a 7 mm × 7 mm body size with a conservative 0.8 mm pin spacing. 2. Features n n n n n LVPECL or LVCMOS clock input 2.5 V LVCMOS outputs for Pentium II microprocessor support 150 ps maximum output-to-output skew Maximum output frequency of 250 MHz at 3.3 V VCC 32-lead LQFP packaging PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip n Dual or single supply voltage: u Dual VCC supply voltage, 3.3 V core and 2.5 V output u Single 3.3 V VCC supply voltage for 3.3 V outputs u Single 2.5 V VCC supply voltage for 2.5 V I/O 3. Ordering information Table 1. Ordering information Type number PCK940LBD Package Name Description Version LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1 4. Functional diagram PCK940L PECL_CLK PECL_CLK 0 Q0 LVCMOS_CLK 1 16 LVCMOS_CLKSEL (internal pull-down) Q1 to Q16 Q17 002aab887 Fig 1. Functional diagram of PCK940L PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 2 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip 5. Pinning information 25 GND1 26 Q5 27 Q4 28 Q3 29 VCC1 30 Q2 31 Q1 32 Q0 5.1 Pinning GND1 1 24 Q6 GND2 2 23 Q7 LVCMOS_CLK 3 22 Q8 LVCMOS_CLKSEL 4 PECL_CLK 5 PECL_CLK 6 19 Q10 VCC2 7 18 Q11 VCC1 8 17 GND2 21 VCC2 VCC1 16 20 Q9 Q12 15 Q13 14 Q14 13 GND1 12 Q15 11 9 Q17 Q16 10 PCK940LBD 002aab888 Fig 2. Pin configuration for LQFP32 5.2 Pin description Table 2. Pin description Symbol Pin I/O Description PECL_CLK 5 input LVPECL reference clock input PECL_CLK 6 input LVPECL reference clock input (active LOW) LVCMOS_CLK 3 input LVCMOS alternative reference clock input LVCMOS_CLKSEL 4 input LVCMOS clock source select Q0 to Q17 32, 31, 30, 28, 27, 26, 24, 23, 22, 20, 19, 18, 15, 14, 11, 10, 9 output LVCMOS clock outputs GND1 1, 12, 25 - supply output negative power supply GND2 2, 17 - supply core negative power supply VCC1 8, 16, 29 - supply output positive power supply VCC2 7, 21 - supply core positive power supply PCK940L_1 Product data sheet Type © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 3 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip 6. Functional description Refer to Figure 1 “Functional diagram of PCK940L”. 6.1 Function table Table 3. Function table LVCMOS_CLKSEL Input 0 PECL_CLK 1 LVCMOS_CLK Table 4. Power supply voltage Supply pin Voltage level VCC2 2.5 V or 3.3 V ± 5 % VCC1 2.5 V or 3.3 V ± 5 % 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VCC supply voltage Conditions −0.3 +3.6 V VI input voltage −0.3 VDD + 0.3 V II input current - ±20 mA Tstg storage temperature −40 +125 °C 8. Static characteristics Table 6. Static characteristics (3.3 V VCC, 3.3 V outputs) Tamb = 0 °C to 70 °C; VCC2 = 3.3 V ± 5 %; VCC1 = 3.3 V ± 5 % Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage LVCMOS_CLK 2.4 - VCC2 V VIL LOW-level input voltage LVCMOS_CLK - - 0.8 V Vi(p-p) peak-to-peak input voltage PECL_CLK 500 - 1000 mV VICR common mode input voltage range PECL_CLK VCC − 1.4 - VCC − 0.6 V VOH HIGH-level output voltage IOH = −20 mA 2.4 - - V IOH = 20 mA VOL LOW-level output voltage - - 0.5 V II input current - - ±200 µA Ci input capacitance - 4.0 - pF CPD power dissipation capacitance - 10 - pF Zo output impedance 18 23 28 Ω ICC(max) maximum supply current - 0.5 1.0 mA per output PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 4 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip Table 7. Static characteristics (3.3 V VCC, 2.5 V outputs) Tamb = 0 °C to 70 °C; VCC2 = 3.3 V ± 5 %; VCC1 = 2.5 V ± 5 % Symbol Parameter Conditions VIH HIGH-level input voltage LVCMOS_CLK 2.4 - VCC2 V VIL LOW-level input voltage LVCMOS_CLK - - 0.8 V Vi(p-p) peak-to-peak input voltage PECL_CLK 500 - 1000 mV VICR common mode input voltage range PECL_CLK VCC − 1.4 - VCC − 0.6 V VOH HIGH-level output voltage IOH = −20 mA 1.8 - - V VOL LOW-level output voltage IOH = 20 mA - - 0.5 V II input current - - ±200 µA Ci input capacitance - 4.0 - pF CPD power dissipation capacitance - 10 - pF Zo output impedance - 23 - Ω ICC(max) maximum supply current - 0.5 1.0 mA per output Min Typ Max Unit Table 8. Static characteristics (2.5 V VCC, 2.5 V output) Tamb = 0 °C to 70 °C; VCC2 = 2.5 V ± 5 %; VCC1 = 2.5 V ± 5 % Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage LVCMOS_CLK 2.0 - VCC2 V VIL LOW-level input voltage LVCMOS_CLK - - 0.8 V Vi(p-p) peak-to-peak input voltage PECL_CLK 500 - 1000 mV VICR common mode input voltage range PECL_CLK VCC − 1.0 - VCC − 0.6 V VOH HIGH-level output voltage IOH = −20 mA 1.8 - - V VOL LOW-level output voltage IOH = 20 mA - - 0.5 V II input current - - ±200 µA Ci input capacitance - 4.0 - pF CPD power dissipation capacitance - 10 - pF Zo output impedance 18 23 28 Ω ICC(max) maximum supply current - 0.5 1.0 mA per output PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 5 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip 9. Dynamic characteristics Table 9. Dynamic characteristics (3.3 V VCC, 3.3 V output) Tamb = 0 °C to 70 °C; VCC2 = 3.3 V ± 5 %; VCC1 = 3.3 V ± 5 % Symbol Parameter foper(max) maximum operating frequency LOW-to-HIGH propagation delay tPLH tsk(o) tsk(pr) δo output skew time process skew time output duty cycle Conditions Min Typ Max Unit - - 250 MHz PECL_CLK ≤ 150 MHz [1] 2.0 2.7 3.8 ns LVCMOS_CLK ≤ 150 MHz [1] 1.8 2.5 3.0 ns PECL_CLK > 150 MHz 2.0 2.9 3.7 ns LVCMOS_CLK > 150 MHz 1.8 2.4 3.2 ns output-to-output PECL_CLK [1] - - 200 ps LVCMOS_CLK [1] - - 150 ps PECL_CLK < 150 MHz [1][2] - - 1.4 ns LVCMOS_CLK < 150 MHz [1][2] - - 1.2 ns PECL_CLK > 150 MHz [1][2] - - 1.7 ns LVCMOS_CLK > 150 MHz [1][2] - - 1.4 ns PECL_CLK [1][3] - - 850 ps LVCMOS_CLK [1][3] - - 750 ps fclk < 134 MHz 45 50 55 % fclk ≤ 250 MHz 40 50 60 % fclk < 134 MHz 35 50 65 % fclk ≤ 250 MHz 40 50 60 % part-to-part LCVMOS_CLK; input δ = 50 % PECL_CLK; input δ = 50 % tr rise time output; from 0.5 V to 2.4 V 0.3 - 1.1 ns tf fall time output; from 2.4 V to 0.5 V 0.3 - 1.1 ns [1] Tested using standard input levels, production tested at 150 MHz. [2] Across temperature and voltage ranges, includes output skew. [3] For a specific temperature and voltage, includes output skew. PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 6 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip Table 10. Dynamic characteristics (3.3 V VCC, 2.5 V output) Tamb = 0 °C to 70 °C; VCC2 = 3.3 V ± 5 %; VCC1 = 2.5 V ± 5 % Symbol Parameter foper(max) maximum operating frequency tPLH LOW-to-HIGH propagation delay tsk(o) tsk(pr) δo output skew time process skew time output duty cycle Conditions Min Typ Max Unit - - 250 MHz PECL_CLK ≤ 150 MHz [1] 2.0 2.8 4.0 ns LVCMOS_CLK ≤ 150 MHz [1] 1.7 2.5 3.0 ns PECL_CLK > 150 MHz 2.0 2.9 4.0 ns LVCMOS_CLK > 150 MHz 1.8 2.5 3.3 ns output-to-output PECL_CLK [1] - - 300 ps LVCMOS_CLK [1] - - 150 ps PECL_CLK < 150 MHz [1][2] - - 1.5 ns LVCMOS_CLK < 150 MHz [1][2] - - 1.3 ns PECL_CLK > 150 MHz [1][2] - - 1.8 ns LVCMOS_CLK > 150 MHz [1][2] - - 1.5 ns PECL_CLK [1][3] - - 850 ps LVCMOS_CLK [1][3] - - 750 ps part-to-part LCVMOS_CLK; input δ = 50 % fclk < 134 MHz 45 50 55 % fclk ≤ 250 MHz 40 50 60 % fclk < 134 MHz 35 50 65 % fclk ≤ 250 MHz PECL_CLK; input δ = 50 % 40 50 60 % tr rise time output; from 0.5 V to 1.8 V 0.3 - 1.2 ns tf fall time output; from 1.8 V to 0.5 V 0.3 - 1.2 ns [1] Tested using standard input levels, production tested at 150 MHz. [2] Across temperature and voltage ranges, includes output skew. [3] For a specific temperature and voltage, includes output skew. PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 7 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip Table 11. Dynamic characteristics (2.5 V VCC, 2.5 V output) Tamb = 0 °C to 70 °C; VCC2 = 2.5 V ± 5 %; VCC1 = 2.5 V ± 5 % Symbol Parameter foper(max) maximum operating frequency tPLH LOW-to-HIGH propagation delay tsk(o) tsk(pr) δo output skew time process skew time output duty cycle Conditions Min Typ Max Unit - - 200 MHz PECL_CLK ≤ 150 MHz [1] 2.6 4.0 5.2 ns LVCMOS_CLK ≤ 150 MHz [1] 2.3 3.1 4.0 ns PECL_CLK > 150 MHz 2.8 3.8 5.0 ns LVCMOS_CLK > 150 MHz 2.3 3.1 4.0 ns output-to-output PECL_CLK [1] - - 300 ps LVCMOS_CLK [1] - - 200 ps PECL_CLK < 150 MHz [1][2] - - 2.6 ns LVCMOS_CLK < 150 MHz [1][2] - - 1.7 ns PECL_CLK > 150 MHz [1][2] - - 2.2 ns LVCMOS_CLK > 150 MHz [1][2] - - 1.7 ns PECL_CLK [1][3] - - 1.2 ns LVCMOS_CLK [1][3] - - 1.0 ns part-to-part LCVMOS_CLK; input δ = 50 % fclk < 134 MHz 45 50 55 % fclk ≤ 250 MHz 40 50 60 % fclk < 134 MHz 35 50 65 % fclk ≤ 250 MHz PECL_CLK; input δ = 50 % 40 50 60 % tr rise time output; from 0.5 V to 1.8 V 0.3 - 1.2 ns tf fall time output; from 1.8 V to 0.5 V 0.3 - 1.2 ns [1] Tested using standard input levels, production tested at 150 MHz. [2] Across temperature and voltage ranges, includes output skew. [3] For a specific temperature and voltage, includes output skew. PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 8 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip 9.1 Timing diagrams PECL_CLK PECL_CLK VCC VICR Vi(p-p) LVCMOS_CLK 0.5VCC GND tPD tPD VCC Qn VCC 0.5VCC Qn 0.5VCC GND GND 002aab893 002aab892 Fig 3. Propagation delay (tPD) test reference Fig 4. LVCMOS_CLK propagation delay (tPD) test reference VCC 0.5VCC GND VCC tsk(o) 0.5VCC VCC GND tp 0.5VCC To δo = (tp ÷ To × 100 %) GND 002aab291 002aab891 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Fig 5. Output duty cycle The pin-to-pin skew is defined as the worst-case difference in propagation delay between any two similar delay paths within a single device. Fig 6. Output-to-output skew (1) (2) tf tr 002aab292 (1) output 2.4 V; input 2.0 V (VCC = 3.3 V) output 1.8 V; input 1.7 V (VCC = 2.5 V) (2) output 0.55 V; input 0.8 V (VCC = 3.3 V) output 0.6 V; input 0.7 V (VCC = 2.5 V) Fig 7. Transition time test reference PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 9 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip 10. Test information PCK940L D.U.T. DIFFERENTIAL PULSE GENERATOR Z = 50 Ω Zo = 50 Ω Zo = 50 Ω RT = 50 Ω RT = 50 Ω VT VT 002aab889 Fig 8. LVCMOS_CLK PCK940L AC test reference for VCC = 3.3 V and VCC = 2.5 V DIFFERENTIAL PULSE GENERATOR Z = 50 Ω Zo = 50 Ω RT = 50 Ω VT PCK940L D.U.T. Zo = 50 Ω RT = 50 Ω VT 002aab890 Fig 9. PECL_CLK PCK940L AC test reference for VCC = 3.3 V and VCC = 2.5 V PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 10 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip 11. Package outline LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1 c y X 24 A 17 16 25 ZE e E HE A A2 A 1 (A 3) wM θ bp Lp pin 1 index L 32 9 detail X 1 8 e ZD v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.4 0.3 0.18 0.12 7.1 6.9 7.1 6.9 0.8 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.25 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 θ o 7 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT358 -1 136E03 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 03-02-25 05-11-09 Fig 10. Package outline SOT358-1 (LQFP32) PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 11 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip 12. Soldering 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 12.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 260 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 12 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 12.5 Package related soldering information Table 12. Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method Wave Reflow[2] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[4] suitable PLCC[5], SO, SOJ suitable suitable not recommended[5][6] suitable SSOP, TSSOP, VSO, VSSOP not recommended[7] suitable CWQCCN..L[8], PMFP[9], WQCCN..L[8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. PCK940L_1 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 13 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 13. Abbreviations Table 13. Abbreviations Acronym Description LVCMOS Low Voltage Complementary Metal Oxide Semiconductor LVPECL Low Voltage Positive Emitter Coupled Logic PLL Phase-Locked Loop 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes PCK940L_1 20060404 Product data sheet - - PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 14 of 16 PCK940L Philips Semiconductors Low voltage 1 : 18 clock distribution chip 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] PCK940L_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 4 April 2006 15 of 16 Philips Semiconductors PCK940L Low voltage 1 : 18 clock distribution chip 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 9.1 10 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 12 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 13 Package related soldering information . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: [email protected]. Date of release: 4 April 2006 Document identifier: PCK940L_1