TI PCM1602KY

PCM1602
PCM
160
2
www.ti.com
24-Bit, 192kHz Sampling, 6-Channel,
Enhanced Multilevel, Delta-Sigma
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● 24-BIT RESOLUTION
● INTEGRATED A/V RECEIVERS
● ANALOG PERFORMANCE:
Dynamic Range: 100dB typ (PCM1602Y)
105dB typ (PCM1602KY)
SNR: 100dB typ (PCM1602Y)
105dB typ (PCM1602KY)
THD+N: 0.003% typ (PCM1602Y)
0.002% typ (PCM1602KY)
Full-Scale Output: 3.1Vp-p typ
● DVD MOVIE AND AUDIO PLAYERS
● 4x/8x OVERSAMPLING INTERPOLATION
FILTER:
Stopband Attenuation: –55dB
Passband Ripple: ±0.03dB
● SAMPLING FREQUENCY:
5kHz to 200kHz (Channels 1 and 2)
5kHz to 100kHz (Channels 3, 4, 5, and 6)
DESCRIPTION
● HDTV RECEIVERS
● CAR AUDIO SYSTEMS
● DVD ADD-ON CARDS FOR HIGH-END PCs
● DIGITAL AUDIO WORKSTATIONS
● OTHER MULTICHANNEL AUDIO SYSTEMS
● ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO DATA
● DATA FORMATS: Standard, I2S, and Left-Justified
● SYSTEM CLOCK: 128, 192, 256, 384, 512, or 768fS
● USER-PROGRAMMABLE FUNCTIONS:
Digital Attenuation: 0dB to –63dB, 0.5dB/Step
Soft Mute
Zero Flags May Be Used As GeneralPurpose Logic Output
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
The PCM1602 is a CMOS monolithic integrated circuit
that features six 24-bit audio Digital-to-Analog Converters (DACs) and support circuitry in a small LQFP-48
package. The DACs utilize Texas Instrument’s enhanced
multilevel, delta-sigma architecture that employs fourthorder noise shaping and 8-level amplitude quantization
to achieve excellent signal-to-noise performance and a
high tolerance to clock jitter.
The PCM1602 accepts industry-standard audio data
formats with 16- to 24-bit audio data. Sampling rates up
to 200kHz (channels 1 and 2) or 100kHz (channels 3, 4,
5, and 6) are supported. A full set of user-programmable
functions are accessible through a 4-wire serial control
port that supports register write and read functions.
● DUAL-SUPPLY OPERATION:
+5V Analog, +3.3V Digital
● +5V TOLERANT DIGITAL LOGIC INPUTS
● PACKAGE: LQFP-48
Copyright © 2000, Texas Instruments Incorporated
SBAS163
Printed in U.S.A. December, 2000
SPECIFICATIONS
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit data, unless otherwise noted.
PCM1602Y
PCM1602KY
PARAMETER
CONDITIONS
MIN
RESOLUTION
DATA FORMAT
Audio Data Interface Formats
Audio Data Bit Length
Audio Data Format
Sampling Frequency (fS)
DYNAMIC PERFORMANCE(3) (4)
PCM1602Y
THD+N at VOUT = 0dB
THD+N at VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
Level Linearity Error
PCM1602KY
THD+N at VOUT = 0dB
THD+N at VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
Level Linearity Error
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
2
MAX
24
VOUT 1, 2
VOUT 3, 4, 5, 6
System Clock Frequency
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level
VIH
VIL
Input Logic Current
IIH(1)
IIL(1)
IIH(2)
IIL(2)
Output Logic Level
VOH
VOL
TYP
UNITS
Bits
Standard, I2S, Left-Justified
16, 18, 20, 24-Bits Selectable
MSB-First, Binary Two’s Complement
5
200
5
100
128, 192, 256, 384, 512, 768fS
kHz
kHz
TTL-Compatible
2.0
VIN = VDD
VIN = 0V
VIN = VDD
VIN = 0V
IOH = –4mA
IOL = +4mA
fS = 44.1kHz
fS = 96kHz
fS = 192Hz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
VOUT = –90dB
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
EIAJ, A-Weighted, fS = 44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
VOUT = –90dB
65
VDC
VDC
10
–10
100
–10
µA
µA
µA
µA
1.0
VDC
VDC
2.4
94
94
91
99
99
96
VOUT = 0.5VCC at Bipolar Zero
Full Scale (–0dB)
AC Load
0.8
0.003
0.005
0.006
1.25
1.40
1.65
100
99
98
100
99
98
98
97
96
±0.5
0.009
%
%
%
%
%
%
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0.002
0.004
0.005
0.7
0.9
1.0
105
103
102
105
103
102
103
101
100
±0.5
0.007
%
%
%
%
%
%
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
±1.0
±1.0
±30
±6
±3
±60
% of FSR
% of FSR
mV
62% of VCC
50% VCC
5
Vp-p
VDC
kΩ
PCM1602
SBAS163
SPECIFICATIONS (Cont.)
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit data, unless otherwise noted.
PCM1602Y
PCM1602KY
PARAMETER
CONDITIONS
DIGITAL FILTER PERFORMANCE
Filter Characteristics 1, Sharp Roll-Off
Passband
Passband
Stopband
Passband Ripple
Stopband Attenuation
Stopband Attenuation
Filter Characteristics 2, Slow Roll-Off
Passband
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
De-Emphasis Error
TYP
±0.03dB
–3dB
Stopband = 0.546fS
Stopband = 0.567fS
±0.03
–50
–55
±0.5dB
–3dB
+3.0
+4.5
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
ICC
Power Dissipation
±0.5
20/fS
±0.1
–0.03
–0.20
dB
dB
+3.3
+5.0
11
24
19
27
28
28
171
219
203
–25
θJA
LQFP-48
dB
dB
dB
dB
dB
sec
dB
–40
f = 20kHz
f = 44kHz
POWER-SUPPLY REQUIREMENTS(4)
Voltage Range, VDD
VCC
Supply Current, IDD(5)
UNITS
0.198fS
0.390fS
0.884fS
Stopband = 0.884fS
MAX
0.454fS
0.487fS
0.546fS
ANALOG FILTER PERFORMANCE
Frequency Response
TEMPERATURE RANGE
Operation Temperature
Thermal Resistance
MIN
+3.6
+5.5
15
38
240
+85
100
VDC
VDC
mA
mA
mA
mA
mA
mA
mW
mW
mW
°C
°C/W
NOTES: (1) Pins 38, 40, 41, 45-47 (SCKI, BCK, LRCK, DATA1, DATA2, DATA3). (2) Pins 34-37 (MDI, MC, ML, RST). (3) Analog performance specifications
are tested with a Shibasoku #725 THD Meter with 400Hz HPF on, 30kHz LPF on, average mode with 20kHz bandwidth limiting. The load connected to the analog
output is 5kΩ, or larger, via capacitive loading. (4) Conditions in 192kHz operation are: system clock = 128fS, DAC3 through DAC6 disabled in Register 8, and
oversampling rate = 64fS in Register 12. (5) CLKO is disabled.
PCM1602
SBAS163
3
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Power Supply Voltage, VDD .............................................................. +4.0V
VCC .............................................................. +6.5V
Ground Voltage Differences .............................................................. ±0.1V
Digital Input Voltage ................................................ –0.3V to (6.5V + 0.3V)
Input Current (except power supply) ............................................... ±10mA
Operating Temperature Under Bias ................................ –40°C to +125°C
Storage Temperature ...................................................... –55°C to +150°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR reflow, 10s) .......................................... +235°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM1602Y
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PCM1602Y
PCM1602Y/2K
PCM1602KY
PCM1602KY/2K
250-Piece Tray
Tape and Reel
250-Piece Tray
Tape and Reel
LQFP-48
340
–25°C to +85°C
PCM1602Y
"
"
"
"
"
PCM1602KY
LQFP-48
340
–25°C to +85°C
PCM1602KY
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM1602Y/2K” will yield a single 2000-piece Tape and Reel.
4
PCM1602
SBAS163
BLOCK DIAGRAM
BCK
Output Amp and
DAC
LRCK
DATA1 (1,2)
DATA2 (3,4)
Serial
Input
I/F
Output Amp and
DAC
DATA3 (5,6)
4x/8x
Oversampling
Digital Filter
with
Function
Controller
TEST
Output Amp and
DAC
MC
Function
Control
I/F
DAC
MDI
Output Amp and
VCOM
Low-Pass Filter
VOUT4
Output Amp and
VOUT5
Low-Pass Filter
Output Amp and
DAC
MDO
VOUT3
Low-Pass Filter
RST
ML
VOUT2
Low-Pass Filter
DAC
Enhanced
Multilevel
Delta-Sigma
Modulator
VOUT1
Low-Pass Filter
VOUT6
Low-Pass Filter
System Clock
VCC1-5
VDD
ZERO6/GPO6
ZERO5/GPO5
ZERO4/GPO4
ZERO3/GPO3
ZERO2/GPO2
ZERO1/GPO1
ZEROA
AGND1-6
Power Supply
Zero Detect
DGND
System Clock
Manager
SCKO
SCKI
PCM1602
SBAS163
MDO
NC
NC
NC
NC
34
33
32
31
30
29
28
27
26
LQFP
AGND2
MDI
35
VCC2
MC
36
VCC1
ML
Top View
AGND1
PIN CONFIGURATION
25
RST 37
24
VCC3
SCKI 38
23
AGND3
SCKO 39
22
VCC4
BCK 40
21
AGND4
LRCK 41
20
NC
TEST 42
19
AGND6
VDD 43
18
VCC5
DGND 44
17
AGND5
DATA1 45
16
NC
DATA2 46
15
VCOM
DATA3 47
14
VOUT1
ZEROA 48
13
VOUT2
1
2
3
4
5
6
7
8
9
10
11
12
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
VOUT6
VOUT5
VOUT4
VOUT3
PCM1602
5
PIN ASSIGNMENTS
PIN
NAME
I/O
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
VCOM
NC
AGND5
VCC5
AGND6
NC
AGND4
VCC4
AGND3
VCC3
AGND2
VCC2
AGND1
VCC1
NC
NC
NC
NC
MDO
MDI
MC
ML
RST
SCKI
SCKO
BCK
LRCK
TEST
VDD
DGND
DATA1
DATA2
DATA3
ZEROA
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
I
I
I
I
I
O
I
I
—
—
—
I
I
I
O
Zero Data Flag for VOUT1. Can also be used as GPO pin.
Zero Data Flag for VOUT2. Can also be used as GPO pin.
Zero Data Flag for VOUT3. Can also be used as GPO pin.
Zero Data Flag for VOUT4. Can also be used as GPO pin.
Zero Data Flag for VOUT5. Can also be used as GPO pin.
Zero Data Flag for VOUT6. Can also be used as GPO pin.
No Connection
No Connection
Voltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DATA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA1. Up to 192kHz.
Common Voltage Output. This pin should be bypassed with a 10µF capacitor to AGND.
No Connection
Analog Ground
Analog Power Supply, +5V
Analog Ground
No Connection
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
Analog Ground
Analog Power Supply, +5V
No Connection
No Connection
No Connection
No Connection
Serial Data Output for Serial Control Port(3)
Serial Data Input for Serial Control Port(1)
Shift Clock for Serial Control Port(1)
Latch Enable for Serial Control Port(1)
System Reset, Active LOW(1)
System Clock Input. Input frequency is 128, 192, 256, 384, 512, or 768fS.(2)
Buffered Clock Output. Output frequency is 128, 192, 256, 384, 512, or 768fS, or one-half of 128, 192, 256, 384, 512, or 768fS.
Shift Clock Input for Serial Audio Data. Clock must be 32, 48, or 64fS.(2)
Left and Right Clock Input. This clock is equal to the sampling rate, fS.(2)
Test Pin. This pin should be connected to DGND.(1)
Digital Power Supply, +3.3V
Digital Ground
Serial Audio Data Input for VOUT1 and VOUT2(2)
Serial Audio Data Input for VOUT3 and VOUT4(2)
Serial Audio Data Input for VOUT5 and VOUT6(2)
Zero Data Flag. Logical “AND” of ZERO1 through ZERO6.
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.
6
PCM1602
SBAS163
TYPICAL PERFORMANCE CURVES
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, fS = 44.1kHz)
FREQUENCY RESPONSE PASSBAND
(Sharp Roll-Off)
FREQUENCY RESPONSE (Sharp Roll-Off)
0
0.05
0.04
–20
0.03
0.02
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
0.01
0
–0.01
–0.02
–0.03
–120
–0.04
–0.05
–140
0
1
2
3
0
4
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
FREQUENCY RESPONSE (Slow Roll-Off)
TRANSITION CHARACTERISTICS (Slow Roll-Off)
0
5
4
–20
3
2
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
1
0
–1
–2
–3
–120
–4
–5
–140
0
1
2
3
0
4
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
De-Emphasis and De-Emphasis Error
DE-EMPHASIS ERROR (fS = 32kHz)
0.5
–1.0
0.4
–2.0
0.3
–3.0
0.2
–4.0
0.1
Error (dB)
Level (dB)
DE-EMPHASIS (fS = 32kHz)
0.0
–5.0
–6.0
0.0
–0.1
–7.0
–0.2
–8.0
–0.3
–9.0
–0.4
–10.0
–0.5
0
2
4
6
8
Frequency (kHz)
PCM1602
SBAS163
10
12
14
0
2
4
6
8
10
12
14
Frequency (kHz)
7
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, system clock = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
De-Emphasis and De-Emphasis Error (Cont.)
DE-EMPHASIS ERROR (fS = 44.1kHz)
0.5
–1.0
0.4
–2.0
0.3
–3.0
0.2
–4.0
0.1
Error (dB)
Level (dB)
DE-EMPHASIS (fS = 44.1kHz)
0.0
–5.0
–6.0
0.0
–0.1
–7.0
–0.2
–8.0
–0.3
–9.0
–0.4
–10.0
–0.5
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
Frequency (kHz)
10
12
14
16
18
20
18
22
DE-EMPHASIS ERROR (fS = 48kHz)
DE-EMPHASIS (fS = 48kHz)
0.0
0.5
–1.0
0.4
–2.0
0.3
–3.0
0.2
–4.0
0.1
Error (dB)
Level (dB)
8
Frequency (kHz)
–5.0
–6.0
0.0
–0.1
–7.0
–0.2
–8.0
–0.3
–9.0
–0.4
–0.5
–10.0
0
2
4
6
8
10
12
14
16
18
0
22
2
4
6
8
10
12
14
16
Frequency (kHz)
Frequency (kHz)
ANALOG DYNAMIC PERFORMANCE
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, and 24-bit input data, unless otherwise noted. Conditions in 192kHz operation are: system clock = 128fS,
DAC3 through DAC6 = disable of Register 8, and oversampling rate = 64fS of Register 12.
Supply-Voltage Characteristics
THD+N vs VCC (VDD = 3.3V)
10
DYNAMIC RANGE vs VCC (VDD = 3.3V)
110
–60dB/192kHz, 384fS
–60dB/96kHz, 384fS
108
Dynamic Range (dB)
THD+N (%)
1
–60dB/44.1kHz, 384fS
0.1
0dB/192kHz, 384fS
0.01
0dB/96kHz, 384fS
0.001
96kHz, 384fS
104
102
192kHz, 384fS
100
98
0dB/44.1kHz, 384fS
0.0001
96
4
4.5
5
VCC (V)
8
44.1kHz, 384fS
106
5.5
6
4
4.5
5
5.5
6
VCC (V)
PCM1602
SBAS163
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at TA = +25°C, VCC = 5.0V, VDD = 3.3V, and 24-bit input data, unless otherwise noted. Conditions in 192kHz operation are: system clock = 128fS,
DAC3 through DAC6 = disable of Register 8, and oversampling rate = 64fS of Register 12.
Supply-Voltage Characteristics (Cont.)
CHANNEL SEPARATION vs VCC (VDD = 3.3V)
SNR vs VCC (VDD = 3.3V)
110
108
108
44.1kHz, 384fS
106
SNR (dB)
Channel Separation (dB)
110
96kHz, 384fS
104
102
192kHz, 384fS
100
106
44.1kHz, 384fS
104
96kHz, 384fS
102
100
192kHz, 384fS
98
98
96
96
4
4.5
5
5.5
4
6
4.5
5
5.5
6
VCC (V)
VCC (V)
Temperature Characteristics
DYNAMIC RANGE vs TA
THD+N vs TA
110
10
–60dB/192kHz, 384fS
–60dB/96kHz, 384fS
108
Dynamic Range (dB)
THD+N (%)
1
–60dB/44.1kHz, 384fS
0.1
0dB/192kHz, 384fS
0dB/96kHz, 384fS
0.01
106
44.1kHz, 384fS
104
96kHz, 384fS
102
192kHz, 384fS
100
0.001
98
0dB/44.1kHz, 384fS
96
0.0001
–50
–25
0
25
50
75
–50
100
–25
0
108
108
44.1kHz, 384fS
104
96kHz, 384fS
102
192kHz, 384fS
100
50
75
100
75
100
CHANNEL SEPARATION vs TA
110
Channel Separation (dB)
SNR (dB)
SNR vs TA
110
106
25
Temperature (°C)
Temperature (°C)
98
106
104
44.1kHz, 384fS
102
96kHz, 384fS
100
192kHz, 384fS
98
96
96
–50
–25
0
25
Temperature (°C)
PCM1602
SBAS163
50
75
100
–50
–25
0
25
50
Temperature (°C)
9
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at
the SCKO output (pin 39). SCKO can operate at either full
(fSCKI) or half (fSCKI/2) rate. The SCKO output frequency
may be programmed using the CLKD bit of Register 9. The
SCKO output pin can also be enabled or disabled using the
CLKE bit of Register 9. If the SCKO output is not required,
it is recommended to disable it using the CLKE bit. The
default is SCKO enabled.
SYSTEM CLOCK INPUT
The PCM1602 requires a system clock for operating the
digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCKI input (pin 38).
Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. The PLL1700 multiclock generator from Texas Instruments is an excellent choice
for providing the PCM1602 system clock.
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1602 includes a power-on reset function, as shown
in Figure 2. With the system clock active, and VDD > 2.0V
(typical, 1.6V to 2.4V), the power-on reset function will be
enabled. The initialization sequence requires 1024 system
clocks from the time VDD > 2.0V. After the initialization
period, the PCM1602 will be set to its reset default state, as
described in the Mode Control Register section of this data
sheet.
The 192kHz sampling frequency operation is available on
DATA1 for VOUT1 and VOUT2. It is recommended that
VOUT3, VOUT4, VOUT5, and VOUT6 be forced to the bipolar
zero level using the DAC3, DAC4, DAC5, and DAC6 bits
of Register 9 when operating at 192kHz.
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
SAMPLING
FREQUENCY
128fS
192fS
256fS
384fS
512fS
768fS
8kHz
16kHz
32kHz
44.1kHz
48kHz
96kHz
192kHz
—
—
—
—
—
—
24.5760
—
—
—
—
—
—
36.8640
2.0480
4.0960
8.1920
11.2896
12.2880
24.5760
(2)
3.0720
6.1440
12.2880
16.9344
18.4320
36.8640
(2)
4.0960
8.1920
16.3840
22.5792
24.5760
49.1520
(2)
6.1440
12.2880
24.5760
33.8688
36.8640
(1)
(2)
NOTES: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock is not supported for the given sampling frequency.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
tSCKH
2.0V
System Clock
0.8V
tSCKL
System Clock Pulse
Cycle Time(1)
System Clock Pulse Width HIGH tSCKH: 7ns (min)
System Clock Pulse Width LOW tSCKL: 7ns (min)
NOTE: (1) 1/128fS, 1/256fS, 1/384fS, 1/512fS, and 1/768fS.
FIGURE 1. System Clock Timing.
2.4V
VDD
2.0V
1.6V
0V
Reset
Reset Removal
Internal Reset
Don’t Care
1024 System Clocks
System Clock
FIGURE 2. Power-On Reset Timing.
10
PCM1602
SBAS163
The PCM1602 also includes an external reset capability
using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1602 to
initialize to its reset default state. For normal operation,
RST should be set to a logic “1”.
The external reset operation and timing is shown in Figure 3.
The RST pin is set to logic “0” for a minimum of 20ns.
After the initialization sequence is completed, the PCM1602
will be set to its reset default state, as described in the
Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog
outputs are forced to the bipolar zero level (or VCC/2).
After the reset period, the internal registers are initialized
in the next 1/fS period and, if SCKI, BCK, and LRCK are
provided continuously, the PCM1602 provides proper analog output with unit-group delay, as specified in this data
sheet.
The external reset is especially useful in applications
where there is a delay between PCM1602 power-up and
system clock activation. In this case, the RST pin should
be held at a logic “0” level until the system clock has been
activated.
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1602 is comprised of
a 5-wire synchronous serial port. It includes LRCK (pin 41),
BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), and
DATA3 (pin 47). BCK is the serial audio bit clock, and is
used to clock the serial data present on DATA1, DATA2,
and DATA3 into the audio interface’s serial shift register.
Serial data is clocked into the PCM1602 on the rising edge
of BCK. LRCK is the serial audio left/right clock. It is used
to latch serial data into the serial audio interface’s internal
registers.
Both LRCK and BCK must be synchronous to the system
clock. Ideally, it is recommended that LRCK and BCK be
derived from the system clock input, SCKI. LRCK is
operated at the sampling frequency (fS). BCK may be operated at 32, 48, or 64 times the sampling frequency (I2S format
does not support BCK = 32fS).
Internal operation of the PCM1602 is synchronized with
LRCK. Accordingly, it is held when the sampling rate clock
of LRCK is changed, or SCKI and/or BCK is broken at least
for one clock cycle. If SCKI, BCK, and LRCK are provided
continuously after this hold condition, the internal operation
will be resynchronized automatically, less than 3/fS period. In
this resynchronize period, and following 3/fS, the analog
outputs are forced to the bipolar zone level (or VCC/2).
External resettling is not required.
AUDIO DATA FORMATS AND TIMING
The PCM1602 supports industry-standard audio data formats,
including Standard, I2S, and Left-Justified (see Figure 4).
Data formats are selected using the format bits, FMT[2:0], in
Register 9. The default data format is 24-bit Standard. All
formats require Binary Two’s Complement, MSB-first audio
data. See Figure 5 for a detailed timing diagram of the serial
audio interface.
DATA1, DATA2, and DATA3 each carry two audio channels, designated as the Left and Right channels. The Left
channel data always precedes the Right channel data in the
serial data stream for all data formats. Table II shows the
mapping of the digital input data to the analog output pins.
DATA INPUT
CHANNEL
ANALOG OUTPUT
DATA1
Left
VOUT1(1)
DATA1
Right
VOUT2(1)
DATA2
Left
VOUT3(2)
DATA2
Right
VOUT4(2)
DATA3
Left
VOUT5(2)
DATA3
Right
VOUT6(2)
NOTES: (1) Up to 192kHz. (2) Up to 96kHz.
TABLE II. Audio Input Data to Analog Output Mapping.
RST
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
FIGURE 3. External Reset Timing.
PCM1602
SBAS163
11
SERIAL CONTROL INTERFACE
The serial control interface is a 4-wire synchronous serial
port that operates asynchronously to the serial audio interface. The serial control interface is utilized to program and
read the on-chip mode registers. The control interface includes MDO (pin 33), MDI (pin 34), MC (pin 35), and ML
(pin 36). MDO is the serial data output, used to read back the
values of the mode registers; MDI is the serial data input,
used to program the mode registers; MC is the serial bit
clock, used to shift data in and out of the control port; and
ML is the control port latch clock.
(1) Standard Data Format: L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
R-Channel
L-Channel
BCK
(= 32fS, 48fS or 64fS)
16-Bit Right-Justified, BCK = 48fS or 64fS
DATA
14 15 16
1
14 15 16
3
MSB
16-Bit Right-Justified, BCK = 32fS
DATA
2
1
2
3
14 15 16
1
LSB
14 15 16
MSB
3
14 15 16
MSB
1
LSB
2
2
3
LSB
14 15 16
MSB
LSB
18-Bit Right-Justified
DATA
16 17 18
1
2
3
MSB
16 17 18
1
LSB
2
17 18
MSB
LSB
20-Bit Right-Justified
DATA
18 19 20
1
2
3
18 19 20
MSB
24-Bit Right-Justified
DATA
22 23 24
1
2
1
LSB
3
22 23 24
MSB
3
18 19 20
MSB
1
LSB
2
2
LSB
3
22 23 24
MSB
LSB
(2) I2S Data Format: L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 48fS or 64fS)
DATA
1
2
N-2 N-1 N
3
MSB
1
LSB
(3) Left-Justified Data Format: L-Channel = HIGH, R-Channel = LOW
2
N-2 N-1 N
3
MSB
1
2
1
2
LSB
1/fS
L-Channel
LRCK
R-Channel
BCK
(= 32fS, 48fS or 64fS)
DATA
1
2
3
MSB
N-2 N-1 N
LSB
1
MSB
2
3
N-2 N-1 N
LSB
FIGURE 4. Audio Data Input Formats.
12
PCM1602
SBAS163
LRCK
50% of VDD
tBCH
tBCL
tLB
BCK
50% of VDD
tBCY
tBL
DATA1,DATA2,
DATA3, DATA4
50% of VDD
tDS
SYMBOL
tDH
PARAMETER
MIN
BCK Pulse Cycle Time
BCK High Level Time
BCK Low Level Time
BCK Rising Edge to LRCK Edge
LRCK Falling Edge to BCK Rising Edge
DATA Set Up Time
DATA Hold Time
tBCY
tBCH
tBCL
tBL
tLB
tDS
tDH
MAX
32, 48, or
UNITS
64fS(1)
35
35
10
10
10
10
ns
ns
ns
ns
ns
ns
NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
FIGURE 5. Audio Interface Timing.
REGISTER WRITE OPERATION
All Write operations for the serial control port use 16-bit
data words. Figure 6 shows the control data word format.
The most significant bit is the Read/Write (R/W) bit. When
set to “0”, this bit indicates a Write operation. There are
seven bits, labeled IDX[6:0], that set the register index (or
address) for the Write operation. The least significant eight
bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
Figure 7 shows the functional timing diagram for writing the
serial control port. ML is held at a logic “1” state until a
register needs to be written. To start the register write cycle,
ML is set to logic “0”. Sixteen clocks are then provided on
MC, corresponding to the 16-bits of the control data word on
MDI. After the sixteenth clock cycle has completed, ML is
set to logic “1” to latch the data into the indexed mode
control register.
SINGLE REGISTER READ OPERATION
Read operations utilize the 16-bit control word format shown
in Figure 6. For Read operations, the R/W bit is set to “1”.
Read operations ignore the index bits, IDX[6:0], of the
control data word. Instead, the REG[6:0] bits in Control
Register 11 are used to set the index of the register that is to
be read during the Read operation. Bits IDX[6:0] should be
set to 00H for Read operations.
MSB
R/W
LSB
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
D5
Register Index (or Address)
D4
D3
D2
D1
D0
D1
D0
X
Register Data
Read/Write Operation
0 = Write Operation
1 = Read Operation (register index is ignored)
FIGURE 6. Control Data Word Format for MDI.
ML
MC
MDI
X
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7
D6
D5
D4
D3
D2
X
RW IDX6
FIGURE 7. Write Operation Timing.
PCM1602
SBAS163
13
AUTO-INCREMENT READ OPERATION
The Auto-Increment Read function allows for multiple registers to be read sequentially. The Auto-Increment Read function is enabled by setting the INC bit of Control Register 11
to “1”. The sequence always starts with Register 1, and ends
with the register indexed by the REG[6:0] bits in Control
Register 11.
Figure 8 shows the timing of the Auto-Increment Read
operation. The operation begins by writing Control Register 11, setting INC to “1”, and setting REG[6:0] to the last
register to be read in the sequence. The actual Read operation starts on the next HIGH to LOW transition of the ML
pin.
The details of the Read operation are shown in Figure 8. First,
Control Register 11 must be written with the index of the
register to be read back. Additionally, the INC bit must be set
to logic “0” in order to disable the Auto-Increment Read
function. The Read cycle is then initiated by setting ML to
logic “0” and setting the R/W bit of the control data word to
logic “1”, indicating a Read operation. MDO remains at a
high-impedance state until the last eight bits of the 16-bit read
cycle, which corresponds to the eight data bits of the register
indexed by the REG[6:0] bits of Control Register 11. The
Read cycle is completed when ML is set to “1”, immediately
after the MC clock cycle for the least significant bit of
indexed control register has completed.
INC = 1 (Auto-Increment Read)
ML
MC
MDI
1
0
0
MDO
0
0
0
0
0
High Impedance
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
INDEX “1”
ML
MC
MDI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MDO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
High Impedance
INDEX “N”
INDEX “N – 1”
INC = 0 (Single Register Read)
ML
MC
MDI
1
0
MDO
0
0
0
0
High Impedance
0
0
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
INDEX “N”
NOTES: (1) X = Don’t care. (2) Index which it begins to read in the read mode can set by REG[6:0] in Register 11, data from Register 1 to Register 12 can
be read by setting it as “INC = 1” in Register 11. For example, set REG[6:0] = “0001001” to read from Register 9. (INC = “0” or “1”.)
FIGURE 8. Read Operation Timing.
14
PCM1602
SBAS163
The Read cycle starts by setting the R/W bit of the control
word to “1”, and setting all of the IDX[6:0] bits to “0”.
All subsequent bits input on the MDI are ignored while ML
is set to “0”. For the first eight clocks of the Read cycle,
MDO is set to a high-impedance state. This is followed by
a sequence of 8-bit words, each corresponding the data
contained in Control Registers 1 through N, where N is
defined by the REG[6:0] bits in Control Register 11. The
Read cycle is completed when ML is set to “1”, immediately
after the MC clock cycle for the least significant bit of
Control Register N has completed.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 9 shows a detailed timing diagram for the Serial
Control interface. Pay special attention to the setup and hold
times, as well as tMLS and tMLH, which define minimum delays
between edges of the ML and MC clocks. These timing
parameters are critical for proper control port operation.
tMHH
50% of VDD
ML
tMCH
tMLS
tMCL
tMLH
50% of VDD
MC
tMCY
LSB
MDI
50% of VDD
tMOS
tMDS
tMCH
LSB
50% of VDD
MDO
SYMBOL
tMCY
tMCL
tMCH
tMHH
tMLS
tMLH
tMDH
tMDS
tMOS
PARAMETER
MIN
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
ML High Level Time
ML Falling Edge to MC Rising Edge
ML Hold Time(1)
MDI Hold Time
MDL Set Up Time
MC Falling Edge to MDSO Stable
100
50
50
300
20
20
15
20
MAX
UNITS
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: (1) MC rising edge for LSB to ML rising edge.
FIGURE 9. Control Interface Timing.
PCM1602
SBAS163
15
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The PCM1602 includes a number of user-programmable
functions that are accessed via control registers. The registers are programmed using the Serial Control Interface that
was previously discussed in this data sheet. Table III lists the
available mode control functions, along with their reset
default conditions and associated register index.
FUNCTION
The mode control register map is shown in Table IV. Each
register includes a R/W bit that determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Each register also includes an index (or address)
indicated by the IDX[6:0] bits.
Reserved Registers
Registers 0 and 12 are reserved for factory use. To ensure proper
operation, the user should not write or read these registers.
RESET DEFAULT
CONTROL REGISTER
INDEX, IDX[6:0]
0dB, No Attenuation
1 through 6
Mute Disabled
DAC 1-6 Enabled
24-Bit Standard Format
Sharp Roll-Off
Full Rate (= fSCKI)
SCKO Enabled
De-Emphasis All Channel Disabled
44.1kHz
Normal Phase
High
REG[6:0] = 01H
Auto-Increment Disabled
Zero Flag Enabled
Disabled
64x
7
8
9
9
9
9
10
10
10
10
11
11
12
12
12
AT1[7:0], AT2[7:0]
AT3[7:0], AT4[7:0]
AT5[7:0], AT6[7:0]
MUT[6:1]
DAC[6:1]
FMT[2:0]
FLT
CLKD
CLKE
DMC
DMF[1:0]
DREV
ZREV
REG[6:0]
INC
GPOE
GPO[6:1]
OVER
Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps
Soft Mute Control
DAC 1-6 Operation Control
Audio Data Format Control
Digital Filter Roll-Off Control
SCKO Frequency Selection
SCKO Output Enable
De-Emphasis All Channel Function Control
De-Emphasis All Channel Sample Rate Selection
Output Phase Select
Zero Flag Polarity Select
Read Register Index Control
Read Auto-Increment Control
General-Purpose Output Enable
General-Purpose Output Bits (GPO1-GPO6)
Oversampling Rate Control
Register Map
TABLE III. User-Programmable Mode Controls.
IDX
(B8-B14) REGISTER
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
Register0
Register1
Register2
Register3
Register4
Register5
Register6
Register7
Register8
Register9
Register10
Register11
Register12
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX6
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX5
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX4
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX3
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX2
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX1
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
IDX0
N/A(1)
AT17
AT27
AT37
AT47
AT57
AT67
RSV(2)
RSV(2)
RSV(2)
RSV(2)
INC
OVER
N/A(1)
AT16
AT26
AT36
AT46
AT56
AT66
RSV(2)
RSV(2)
RSV(2)
ZREV
REG6
GPOE
N/A(1)
AT15
AT25
AT35
AT45
AT55
AT65
MUT6
DAC6
FLT
DREV
REG5
GPO6
N/A(1)
AT14
AT24
AT34
AT44
AT54
AT64
MUT5
DAC5
CLKD
DMF1
REG4
GPO5
N/A(1)
AT13
AT23
AT33
AT43
AT53
AT63
MUT4
DAC4
CLKE
DMF0
REG3
GPO4
N/A(1)
AT12
AT22
AT32
AT42
AT52
AT62
MUT3
DAC3
FMT2
DMC
REG2
GPO3
N/A(1)
AT11
AT21
AT31
AT41
AT51
AT61
MUT2
DAC2
FMT1
DMC
REG1
GPO2
N/A(1)
AT10
AT20
AT30
AT40
AT50
AT60
MUT1
DAC1
FMT0
DMC
REG0
GPO1
NOTES: (1) N/A = not assigned. No operation even if setting any data. (2) RSV = reserved for test operation. It should be set “0” during regular operation.
TABLE IV. Mode Control Register Map.
16
PCM1602
SBAS163
REGISTER DEFINITIONS
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 1
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
Register 2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
Register 3
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
Register 4
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT47
AT46
AT45
AT44
AT43
AT42
AT41
AT40
Register 5
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT57
AT56
AT55
AT54
AT53
AT52
AT51
AT50
Register 6
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT67
AT66
AT65
AT64
AT63
AT62
AT61
AT60
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
ATx[7:0]
Digital Attenuation Level Setting
where x = 1 through 6, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 1111 1111B
Each DAC output, VOUT1 through VOUT6, has a digital attenuator associated with it. The attenuator may be
set from 0dB to –63dB, in 0.5dB steps. Changes in attenuator levels are made by incrementing or
decrementing, by one step (0.5dB), for every 8/fS time interval until the programmed attenuator setting is
reached. Alternatively, the attenuator may be set to infinite attenuation (or mute).
The attenuation level may be set using the formula below.
Attenuation Level (dB) = 0.5 (ATx[7:0]DEC – 255)
where: ATx[7:0]DEC = 0 through 255
for: ATx[7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings.
ATx[7:0]
Decimal Value
Attenuator Level Setting
1111 1111B
1111 1110B
1111 1101B
•
•
•
1000 0010B
1000 0001B
1000 0000B
•
•
•
0000 0000B
255
254
253
•
•
•
130
129
128
•
•
•
0
0dB, No Attenuation (default)
–0.5dB
–1.0dB
•
•
•
–62.5dB
–63.0dB
Mute
•
•
•
Mute
PCM1602
SBAS163
17
Register 7
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
MUT6
MUT5
MUT4
MUT3
B1
B0
MUT2 MUT1
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
MUTx
Soft Mute Control
Where x = 1 through 6, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 0
MUTx = 0
MUTx = 1
Mute Disabled (default)
Mute Enabled
The mute bits, MUT1 through MUT6, are used to enable or disable the Soft Mute function for the
corresponding DAC outputs, VOUT1 through V OUT6. The Soft Mute function is incorporated into the digital
attenuators. When Mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When Mute
is enabled by setting MUTx = 1, the digital attenuator for the corresponding output will be decreased from
the current setting to the infinite attenuation setting one attenuator step (0.5dB) at a time. This provides a
quiet, pop-free muting of the DAC output. Upon returning from Soft Mute, by setting MUTx = 0, the
attenuator will be increased one step at a time to the previously programmed attenuator level.
REGISTER 8
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
DAC6
DAC5
DAC4
DAC3
B1
B0
DAC2 DAC1
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
DACx
DAC Operation Control
where x = 1 through 6, corresponding to the DAC output VOUTx.
These bits are Read/Write.
Default Value: 0
DACx = 0
DACx = 1
DAC Operation Enabled (default)
DAC Operation Disabled
The DAC operation controls are used to enable and disable the DAC outputs, VOUT1 through VOUT6. When
DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier
input is switched to the DC common-mode voltage (VCOM), equal to VCC/2.
18
PCM1602
SBAS163
REGISTER 9
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
RSV
FLT
CLKD
CLKE
FMT2
FMT1
FMT0
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
FLT
Digital Filter Roll-Off Control
These bits are Read/Write.
Default Value: 0
FLT = 0
FLT = 1
Sharp Roll-Off (default)
Slow Roll-Off
The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Two
filter roll-off sections are available: Sharp or Slow. The filter responses for these selections are shown in
the Typical Performance Curves section of this data sheet.
CLKD
SCKO Frequency Selection
This bit is Read/Write.
Default Value: 0
CLKD = 0
CLKD = 1
Full Rate, fSCKO = fSCKI (default)
Half Rate, fSCKO = fSCKL/2
The CLKD bit is used to determine the clock frequency at the system clock output pin, SCKO.
CLKE
SCKO Output Enable
This bit is Read/Write.
Default Value: 0
CLKE = 0
CLKE = 1
SCKO Enabled (default)
SCKO Disabled
The CLKE bit is used to enable or disable the system clock output pin, SCKO. When SCKO is enabled, it will
output either a full or half rate clock, based upon the setting of the CLKD bit. When SCKO is disabled, it is set
to a LOW level.
FMT[2:0]
Audio Interface Data Format
These bits are Read/Write.
Default Value: 000B
FMT[2:0]
000
001
010
011
100
101
110
111
Audio Data Format Selection
24-Bit Standard Format, Right-Justified
20-Bit Standard Format, Right-Justified
18-Bit Standard Format, Right-Justified
16-Bit Standard Format, Right-Justified
I2S Format, 16- to 24-bits
Left-Justified Format, 16- to 24-Bits
Reserved
Reserved
Data (default)
Data
Data
Data
The FMT[2:0] bits are used to select the data format for the serial audio interface.
PCM1602
SBAS163
19
REGISTER 10
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
ZREV
DREV
DMF1
DMF0
DMC
DMC
DMC
R/W
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
DMF[1:0]
Sampling Frequency Selection for the De-Emphasis Function
These bits are Read/Write.
Default Value: 00B
DMF[1:0]
00
01
10
11
De-Emphasis Same Rate Selection
44.1kHz (default)
48kHz
32kHz
Reserved
The DMF[1:0] bits are used to select the sampling frequency used for the Digital De-Emphasis function when
it is enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet.
The table below shows the available sampling frequencies.
DMC
Digital De-Emphasis, All Channels Function Control
This bit is Read/Write.
Default Value: 0
DMC = 0
DMC = 1
De-Emphasis Disabled for All Channels (default)
De-Emphasis Enabled for All Channels
The DMC bit is used to enable or disable the De-Emphasis function for all channels. To select more than one
of three DMC bits, enable or disable the De-Emphasis function.
DREV
Output Phase Select
Default Value: 0
DREV = 0
DREV = 1
Normal Output (default)
Inverted Output
The DREV bit is the output analog signal phase control.
ZREV
Zero Flag Polarity Select
Default Value: 0
ZREV = 0
ZREV = 1
Zero Flag Pins HIGH at a Zero Detect (default)
Zero Flag Pins LOW at a Zero Detect
The ZREV bit allows the user to select the polarity of the Zero Flag pins.
20
PCM1602
SBAS163
REGISTER 11
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
INC
REG6
REG5
REG4
REG3
REG2
B1
B0
REG1 REG0
Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default Value: 0
INC
Auto-Increment Read Control
This bit is Read/Write.
Default Value: 0
INC = 0
INC = 1
Auto-Increment Read Disabled (default)
Auto-Increment Read Enabled
The INC bit is used to enable or disable the Auto-Increment Read feature of the Serial Control Interface. Refer
to the Serial Control Interface section of this data sheet for details regarding Auto-Increment Read operation.
REG[6:0]
REGISTER 12
GPOx
Read Register Index
These bits are Read/Write.
Default Value: 01H
The REG[6:0] bits are used to set the index of the register to be read when performing the Single Register Read
operation. In the case of an Auto-Increment Read operation, the REG[6:0] bits indicate the index of the last
register to be read in the Auto-Increment Read sequence. For example, if Registers 1 through 6 are to be read
during an Auto-Increment Read operation, the REG[6:0] bits would be set to 06H. Refer to the Serial Control
Interface section of this data sheet for details regarding the Single Register and Auto-Increment Read operations.
B15
B14
B13
B12
B11
B10
B9
B8
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
B7
B6
OVER GPOE
B5
B4
B3
B2
GPO6
GPO5
GPO4
GPO3
B1
B0
GPO2 GPO1
General-Purpose Logic Output
Where: x = 1 through 6, corresponding pins GPO1 through GPO6.
These bits are Read/Write.
Default Value: 0
GPOx = 0
GPOx = 1
Set GPOx to “0”
Set GPOx to “1”
The general-purpose output pins, GPO1 through GPO6, are enabled by setting GPOE = 1. These pins are used
as general-purpose outputs for controlling user-defined logic functions. When general-purpose outputs are
disabled (GPOE = 0), they default to the zero-flag function, ZERO1 through ZERO6.
GPOE
General-Purpose Output Enable
This bit is Read/Write.
Default Value: 0
GPOE = 0
GPOE = 1
PCM1602
SBAS163
General-Purpose Outputs Disabled
Pins default to zero-flag function (ZERO1 through ZERO6).
General-Purpose Outputs Enabled
Data written to GPO1 through GPO6 will appear at the corresponding pins.
21
Register 12
OVER
(Cont.)
Oversampling Rate Control
This bit is Read/Write.
Default Value: 0
System Clock Rate = 256, 384, 512, or 768fS:
OVER = 0
OVER = 1
64x Oversampling (default)
128x Oversampling
System Clock Rate = 128 or 192fS:
OVER = 0
OVER = 1
32x Oversampling (default)
64x Oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma DACs. The OVER = 1 setting is
recommended when the oversampling rate is 192kHz (system clock rate is 128 or 192fS).
ANALOG OUTPUTS
The PCM1602 includes six independent output channels,
VOUT1 through VOUT6. These are unbalanced outputs, each
capable of driving 3.1Vp-p typical into a 5kΩ AC load with
VCC = +5V. The internal output amplifiers for VOUT1 through
VOUT6 are DC biased to the common-mode (or bipolar zero)
voltage, equal to VCC/2.
The output amplifiers include an RC continuous-time filter,
which helps to reduce the out-of-band noise energy present
at the DAC outputs due to the noise-shaping characteristics
of the PCM1602’s delta-sigma DACs. The frequency response of this filter is shown in Figure 10. By itself, this
filter is not enough to attenuate the out-of-band noise to an
acceptable level for most applications. An external low-pass
filter is required to provide sufficient out-of-band noise
rejection. Further discussion of DAC post-filter circuits is
provided in the Applications Information section of this data
sheet.
VCOM OUTPUT
One unbuffered, common-mode voltage output pin, VCOM
(pin 15), is brought out for decoupling purposes. This pin is
nominally biased to a DC voltage level equal to VCC/2. If
this pin is to be used to bias external circuitry, a voltage
follower is required for buffering purposes. Figure 11 shows
an example of using the VCOM pin for external biasing
applications.
20
Level (dB)
0
PCM1602
–20
4
1
–40
VCOM
–60
3 OPA337
15
+
VBIAS ≈
VCC
2
10µF
–80
–100
1
10
100
1k
10k
100k
1M
Log Frequency (Hz)
10M
FIGURE 11. Biasing External Circuits Using the VCOM Pin.
FIGURE 10. Output Filter Frequency Response.
22
PCM1602
SBAS163
ZERO FLAG
Zero Flag pins can be used to operate external mute circuits,
or used as status indicators for a microcontroller, audio signal
processor, or other digitally controlled functions.
Zero Detect Condition
Zero Detection for each output channel is independent from
the others. If the data for a given channel remains at a “0”
level for 1024 sample periods (or LRCK clock periods), a
Zero Detect condition exists for that channel.
The active polarity of zero flag output can be inverted by
setting the ZREV bit of Control Register 10 to “1”. The reset
default is active high output, or ZREV = 0.
Zero Output Flags
APPLICATIONS INFORMATION
Given that a Zero Detect condition exists for one or more
channels, the Zero Flag pins for those channels will be set to
a logic “1” state. There are Zero Flag pins for each channel,
ZERO1 through ZERO6 (pins 1 through 6). In addition, all six
Zero Flags are logically “AND”ed together, and the result
provided at the ZEROA pin (pin 48), which is set to a logic “1”
state when all channels indicate a Zero Detect condition. The
CONNECTION DIAGRAMS
A basic connection diagram with the necessary power-supply
bypassing and decoupling components is shown in Figure 12.
Texas Instruments recommends using the component values
shown in Figure 12 for all designs.
ML
PLL1700
Micro Controller
MC
SCKO3
MD
+5V
Power Supply
10µF
RST
37
RST
38
SCKI
39
SCKO
BCK
40
BCK
LRCK
41
42
43
VDD
44
DATA1
31
30
29
MDO
NC
NC
NC
NC
28
27
26
25
AGND2
32
VCC2
33
VCC1
34
AGND1
35
MC
ML
36
MDI
Regulator
VCC3
24
AGND3
23
VCC4
22
AGND4
21
LRCK
NC
20
TEST
AGND6
19
VCC5
18
DGND
AGND5
17
45
DATA1
NC
16
DATA2
46
DATA2
VCOM
15
DATA3
47
DATA3
VOUT1
14
LPF
VOUT1
13
LPF
VOUT2
LPF
VOUT3
LPF
VOUT4
LPF
VOUT5
LPF
VOUT6
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
VOUT6
VOUT5
VOUT4
VOUT3
48
ZEROA
ZERO3/GPO3
ZEROA
ZERO2/GPO2
10µF
ZERO1/GPO1
PCM1602
1
2
3
4
5
6
7
8
9
10
11
12
ZERO1–6
10µF
VOUT2
FIGURE 12. Basic Connection Diagram.
PCM1602
SBAS163
23
RS
RS
RS
RS
RS
NOTES: (1) Serial Control and Reset functions
may be provided by DSP/Decoder GPIO pins.
(2) Actual clock output used is determined by
the application. (3) RS = 22Ω to 100Ω. (4) See
Applications Information section of this data
sheet for more information.
Audio DSP
or
Decoder
27MHz
Master Clock
SCKO3(2)
RS(3)
+3.3V
+
48
47
46
45
44
43
42
41
40
39
Zero Flag or
General-Purpose
Outputs
for Mute Circuits,
microcontroller, or
DSP/Decoder.
C10
10µF
C11
10µF
37
38
1
ZEROA
DATA3
DATA2
DATA1
DGND
VDD
TEST
LRCK
BCK
SCKO
SCKI
RST
34
MDI
ZERO3/GPO3
MC
ZERO2/GPO2
ML
ZERO1/GPO1
3
MDO
ZERO4/GPO4
2
4
33
5
32
31
30
NC
29
6
7
8
PCM1602
NC
ZERO5/GPO5
XT1
Buffer
35
NC
ZERO6/GPO6
PLL1700
36
NC
NC
µC/µP(1)
9
28
26
25
10
11
12
VCC1
VOUT6
27
AGND1
VOUT5
ANALOG SECTION
VCC2
VOUT4
DIGITAL SECTION
VCC3
0.1µF
VOUT2
VOUT1
VCOM
NC
AGND6
VCC6
AGND5
NC
AGND4
VCC4
AGND3
AGND2
VOUT3
24
NC
13
14
15
16
17
18
19
20
21
22
23
24
10µF
+
+
+
+
+
+
+
+
10µF
10µF
10µF
10µF
10µF
10µF
10µF
+5V Analog
Output
Low-Pass
Filters(4)
REG1117
+3.3V
+3.3V
LF
SUB
CTR
RS
LS
RF
A typical application diagram is shown in Figure 13. The
REG1117-3.3 from Texas Instruments is used to generate
+3.3V for VDD from the +5V analog power supply. The
PLL1700E from Texas Instruments is used to generate the
system clock input at SCKI, as well as generating the clock
for the audio signal processor.
Series resistors (22Ω to 100Ω) are recommended for SCKI,
LRCK, BCK, DATA1, DATA2, and DATA3. The series
resistor combines with the stray PCB and device input capacitance to form a low-pass filter which removes high-frequency
noise from the digital signal, thus reducing high-frequency
emission.
FIGURE 13. Typical Application Diagram.
PCM1602
SBAS163
POWER SUPPLIES AND GROUNDING
The PCM1602 requires a +5V analog supply and a +3.3V
digital supply. The +5V supply is used to power the DAC
analog and output filter circuitry, while the +3.3V supply is
used to power the digital filter and serial interface circuitry.
For best performance, the +3.3V supply should be derived
from the +5V supply using a linear regulator (see Figure 13).
Two capacitors are required for supply bypassing (see Figure 12). These capacitors should be located as close as
possible to the PCM1602 package. The 10µF capacitors
should be tantalum or aluminum electrolytic, while the
0.1µF capacitors are ceramic (X7R type is recommended
for surface-mount applications).
Multiple FeedBack (MFB) circuit arrangement, that reduces
sensitivity to passive component variations over frequency and
temperature. For more information regarding MFB active filter
design, please refer to the Texas Instruments Applications
Bulletin AB-034, available from our web site (www.ti.com), or
your local Texas Instruments sales office.
Since the overall system performance is defined by the quality
of the DACs and their associated analog output circuitry,
high-quality audio op amps are recommended for the active
filters. The OPA2134 and OPA2353 dual op amps from
Texas Instruments are shown in Figures 14 and 15, and are
recommended for use with the PCM1602.
DAC OUTPUT FILTER CIRCUITS
Delta-sigma DACs utilize noise-shaping techniques to improve in-band Signal-to-Noise Ratio (SNR) performance at
the expense of generating increased out-of-band noise above
the Nyquist Frequency, or fS/2. The out-of-band noise must
be low-pass filtered in order to provide the optimal converter
performance. This is accomplished by a combination of
on-chip and external low-pass filtering.
Figures 14 and 15 show the recommended external low-pass
active filter circuits for dual- and single-supply applications.
These circuits are second-order Butterworth filters using the
AV ≈ –
R2
R1
C1
R3
2
VIN
1
3
C2
AV ≈ –
OPA2134
R4
VOUT
R2
R1
FIGURE 14. Dual Supply Filter Circuit.
R2
R1
R2
C1
R1
R3
VIN
2
1
C2
3
R4
OPA2134
VOUT
PCM1602
VCOM
+
C2
10µF
OPA337
To Additional
Low-Pass Filter
Circuits
FIGURE 15. Single-Supply Filter Circuit.
PCM1602
SBAS163
25
PCB LAYOUT GUIDELINES
Separate power supplies are recommended for the digital and
analog sections of the board. This prevents the switching noise
present on the digital supply from contaminating the analog
power supply and degrading the dynamic performance of the
DACs. In cases where a common +5V supply must be used for
the analog and digital sections, an inductance (RF choke,
ferrite bead) should be placed between the analog and digital
+5V supply connections to avoid coupling of the digital
switching noise into the analog circuitry. Figure 17 shows the
recommended approach for single-supply applications.
A typical PCB floor plan for the PCM1602 is shown in
Figure 16. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a
split or cut in the circuit board. The PCM1602 should be
oriented with the digital I/O pins facing the ground plane
split/cut to allow for short, direct connections to the digital
audio interface and control signals originating from the
digital section of the board.
Analog Power
Digital Power
+VD
DGND
AGND +5VA
+VS –VS
REG
VCC
VDD
Digital Logic
and
Audio
Processor
Output
Circuits
DGND
PCM1602
Digital
Ground
AGND
DIGITAL SECTION
Analog
Ground
ANALOG SECTION
Return Path for Digital Signals
FIGURE 16. Recommended PCB Layout.
Power Supplies
RF Choke or Ferrite Bead
+5V
GND
+VS –VS
REG
VCC
VDD
Digital Logic
and
Audio
Processor
VDD
DGND
Output
Circuits
PCM1602
AGND
Common
Ground
DIGITAL SECTION
ANALOG SECTION
FIGURE 17. Single-Supply PCB Layout.
26
PCM1602
SBAS163
The DAC section of the PCM1602 is based on a multi-bit
delta-sigma architecture. This architecture utilizes a fourthorder noise shaper and an 8-level amplitude quantizer, followed by an analog low-pass filter. A block diagram of the
delta-sigma modulator is shown in Figure 19. This architecture has the advantage of stability and improved jitter tolerance, when compared to traditional 1-bit (2-level) deltasigma designs.
The combined oversampling rate of the digital interpolation
filter and the delta-sigma modulator is 32, 64, or 128fS. The
total oversampling rate is determined by the desired sampling frequency. If fS ≤ 96kHz, then the OVER bit in
Register 12 may be set to an oversampling rate of 64 or
128fS. If fS > 96kHz, then the OVER bit may be used to set
the oversampling rate to 32 or 64fS. Figure 20 shows the
out-of-band quantization noise plots for both the 64x and
128x oversampling scenarios. Notice that the 128x
oversampling plot shows significantly improved out-of-band
noise performance, allowing for a simplified low-pass filter
to be used at the output of the DAC.
Figure 18 illustrates the simulated jitter sensitivity of the
PCM1602. To achieve best performance, the system clock
jitter should be less than 300 picoseconds. This is easily
achieved using a quality clock generation IC, like the PLL1700
from Texas Instruments.
JITTER DEPENDENCE (x 64 Over Sampling)
125
120
Dynamic Range (dB)
THEORY OF OPERATION
115
110
105
100
95
90
0
100
200
300
400
500
600
Jitter (ps)
FIGURE 18. Jitter Sensitivity.
–
+
8fS
Z–1
+
Z–1
+
Z–1
+
Z–1
+
+
8-Level Quantizer
64fS
FIGURE 19. Eight-Level Delta-Sigma Modulator.
QUANTIZATION NOISE SPECTRUM
(128x Oversampling)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
QUANTIZATION NOISE SPECTRUM
(64x Oversampling)
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
–180
0
1
2
3
4
5
Frequency (fS)
6
7
8
0
1
2
3
4
5
6
7
8
Frequency (fS)
FIGURE 20. Quantization Noise Spectrum.
PCM1602
SBAS163
27
KEY PERFORMANCE PARAMETERS
AND MEASUREMENT
This section provides information on how to measure key
dynamic performance parameters for the PCM1602. In all
cases, an Audio Precision System Two Cascade or equivalent audio measurement system is utilized to perform the
testing.
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion + Noise (THD+N) is a significant
figure of merit for audio DACs, since it takes into account
both harmonic distortion and all noise sources within a
specified measurement bandwidth. The true rms value of the
distortion and noise is referred to as THD+N. The test setup
for THD+N measurements is shown in Figure 21.
For the PCM1602 DACs, THD+N is measured with a fullscale, 1kHz digital sine wave as the test stimulus at the input
of the DAC. The digital generator is set to a 24-bit audio
word length and a sampling frequency of 44.1kHz, or 96kHz.
The digital generator output is taken from the unbalanced
S/PDIF connector of the measurement system. The
S/PDIF data is transmitted via coaxial cable to the digital
audio receiver on the DEM-DAI1602 demo board. The
receiver is then configured to output 24-bit data in either I2S
or left-justified data format. The DAC audio interface format
is programmed to match the receiver output format. The
analog output is then taken from the DAC post filter and
connected to the analog analyzer input of the measurement
system. The analog input is band-limited, using filters resident in the analyzer. The resulting THD+N is measured by
the analyzer and displayed by the measurement system.
Evaluation Board
DEM-DAI1602
S/PDIF
Receiver
PCM1602
2nd-Order
Low-Pass
Filter
f–3dB = 54kHz
S/PDIF
Output
Digital
Generator
100% Full-Scale
24-Bit, 1kHz
Sine Wave
Analyzer
and
Display
rms Mode
Band Limit
Notch Filter
HPF = 22Hz(1)
fC = 1kHz
LPF = 30kHz(1)
Option = 20kHz Apogee Filter(2)
NOTES: (1) There is little difference in measured THD+N when using
the various settings for these filters. (2) Required for THD+N test.
FIGURE 21. Test Setup for THD+N Measurements.
28
PCM1602
SBAS163
DYNAMIC RANGE
IDLE CHANNEL SIGNAL-TO-NOISE RATIO
Dynamic range is specified as A-Weighted, THD+N measured with a –60dBFS, 1kHz digital sine wave stimulus at
the input of the DAC. This measurement is designed to give
a good indication of how the DAC will perform, given a
low-level input signal.
The SNR test provides a measure of the noise of the DAC.
The input to the DAC is in all “0”s data, and the DAC’s
Infinite Zero Detect Mute function must be disabled (default condition at power-up for the PCM1602). This ensures that the delta-sigma modulator output is connected to
the output amplifier circuit so that idle tones (if present)
may be observed at the output. The dither function of the
digital signal generator must also be disabled to ensure an
all “0”s data stream at the input of the DAC.
The measurement setup for the dynamic range measurement
is shown in Figure 22, and is similar to the THD+N test
setup discussed previously. The differences include the
band-limit filter selection, the additional A-Weighting filter,
and the –60dBFS input level.
The measurement setup for SNR is identical to that used for
dynamic range, with the exception of the input signal level.
(see the notes provided in Figure 22.)
Evaluation Board
DEM-DAI1602
S/PDIF
Receiver
PCM1602(1)
2nd-Order
Low-Pass
Filter
f–3dB = 54kHz
S/PDIF
Output
Digital
Generator
Analyzer
and
Display
0% Full-Scale,
Dither Off (SNR)
–60dBFS,
1kHz Sine Wave
(Dynamic Range)
rms Mode
A-Weight
Filter(1)
Band Limit
HPF = 22Hz
LPF = 22kHz
Option = A-Weighting(2)
Notch Filter
fC = 1kHz
NOTES: (1) Infinite Zero Detect Mute disabled.
(2) Results without A-Weighting will be approximately 3dB worse.
FIGURE 22. Test Set-Up for Dynamic Range and SNR Meeasurements.
PCM1602
SBAS163
29
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
PCM1602KY
ACTIVE
LQFP
PT
48
250
PCM1602KY/2K
ACTIVE
LQFP
PT
48
2000
PCM1602Y
ACTIVE
LQFP
PT
48
250
PCM1602Y/2K
ACTIVE
LQFP
PT
48
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Amplifiers
Applications
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2003, Texas Instruments Incorporated