PCS2P20805A September 2006 rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver Functional Description Features • Advanced CMOS Technology The PCS2P20805A is a 2.5V Clock driver built using • Guaranteed low skew < 200pS (max.) advanced CMOS technology. The device consists of two • Very low propagation delay < 2.5nS (max) banks of drivers, each with a 1:5 fanout and its own output • Very low duty cycle distortion < 270pS (max) enable control. The device has a "heartbeat" monitor for • Very low CMOS power levels diagnostics and PLL driving. The MON output is identical to • Operating frequency up to 166MHz all other outputs and complies with the output specifications • TTL compatible inputs and outputs in • Two independent output banks with 3-state control capacitance inputs. The PCS2P20805A is designed for • 1:5 fanout per bank high speed clock distribution where signal quality and skew • "Heartbeat" monitor output are critical. The PCS2P20805A also allows single point-to- • VCC = 2.5V ± 0.2V point transmission line driving in applications such as • Available in SSOP and QSOP packages address distribution, where one signal must be distributed this document. The PCS2P20805A offers low to multiple receivers with low skew and high signal quality. Block Diagram Pin Diagram OEA INA INB 5 5 OA1 – OA5 OB1 – OB5 VCCA 1 20 VCCB OA1 2 19 OB1 OA2 3 18 OB2 OA3 4 17 OB3 GNDA 5 16 GNDB OA4 6 15 OB4 OA5 7 14 OB5 GNDQ 8 13 MON OEA 9 12 OEB INA 10 11 INB OEB MON PCS2P20805A SSOP/ QSOP PACKAGE TOP VIEW PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS2P20805A September 2006 rev 0.3 Pin Description Pin # Pin Names 9,12 OE ¯¯ A, OE ¯¯ B 10,11 INA, INB Clock Inputs 2,3,4,6,7 OA1-OA5 Clock Outputs 19,18,17,15,14 OB1-OB5 Clock Outputs 1 VCCA Power supply for Bank A 20 VCCB Power supply for Bank B 5 GNDA Ground for Bank A 16 GNDB Ground for Bank B 8 GNDQ Ground 13 MON Monitor Output Description 3-State Output Enable Inputs (Active LOW) Function Table Inputs Outputs OE ¯¯ A, OE ¯¯ B INA, INB OAn, OBn MON L L L L L H H H H L Z L H H Z H Note: H = HIGH; L = LOW; Z = High-Impedance Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter* Conditions Typ Max Unit CIN Input Capacitance VIN= 0V 3 4 pF COUT Output Capacitance VOUT = 0V 6 pF *This parameter is measured at characterization but not tested. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 2 of 11 PCS2P20805A September 2006 rev 0.3 Absolute Maximum Ratings Symbol Max Unit Input Power Supply Voltage -0.5 to +4.6 V VI Input Voltage -0.5 to +5.5 V VO Output Voltage -0.5 to VCC+0.5 V TJ Junction Temperature 150 °C Ts Max. Soldering Temperature (10 sec) 260 °C -65 to +165 °C 2 KV VCC TSTG TDV Description Storage Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Industrial: TA = -40°C to +85°C, VCC = 2.5V ± 0.2V Symbol Test Conditions1 Parameter Min Typ2 Max Unit VIH Input HIGH Level 1.7 5.5 V VIL Input LOW Level -0.5 0.7 V IIH Input HIGH Current VCC= Max. VI = 5.5V ±1 IIL Input LOW Current VCC= Max. VI = GND ±1 VO = VCC ±1 VO = GND ±1 IOZH IOZL VIK IODH High Impedance Output Current (3-State Outputs Pins) VCC= Max. Clamp Diode Voltage VCC= Min., IIN = -18mA Output HIGH Current 3,4 3,4 VCC= 2.5V, VIN = VIH or VIL, VO = 1.25V IODL Output LOW Current VCC= 2.5V, VIN = VIH or VIL, VO = 1.25V IOS Short Circuit Current VCC= Max., VO = GND 3,4 VOH Output HIGH Voltage VCC= Min. VIN = VIH or VIL VOL Output LOW Voltage VCC= Min. VIN = VIH or VIL IOH= -8mA IOH= -100µA µA -0.7 -1.2 V -15 -35 -90 mA 25 55 100 mA -30 -50 -120 mA 5 1.7 V VCC - 0.2 IOL= 8mA 0.2 IOL= 100µA 0.4 0.2 V Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 2.5V, 25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 3 of 11 PCS2P20805A September 2006 rev 0.3 Power Supply Characteristics Symbol Parameter Test Conditions1 ICCL ICCH ICCZ Quiescent Power Supply Current ∆ICC Power Supply Current per Input HIGH ICCD Dynamic Power Supply 3 Current per Output IC Total Power Supply 4 Current Typ2 Max Unit VCC = Max. VIN = GND or VCC 0.1 20 µA VCC = Max. VIN = VCC –0.6V 35 250 µA VIN = VCC VIN = GND 65 100 µA/MHz VIN = VCC VIN = GND 140 160 VIN = VCC –0.6V VIN = GND 140 160 VIN = VCC VIN = GND 170 200 VIN = VCC –0.6V VIN= GND 170 200 VCC= Max. CL= 15pF All Outputs Toggling VCC= Max. CL= 15pF All Outputs Toggling fi = 133MHz VCC= Max. CL= 15pF All Outputs Toggling fi = 166MHz Min mA Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 2.5V, +25°C ambient. 3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 4. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 4 of 11 PCS2P20805A September 2006 rev 0.3 Switching Characteristics Over Operating Range3,4 Symbol tPLH tPHL Conditions1 Parameter Min2 Max Unit 1 3 nS Propagation Delay INA to OAn, INB to OBn tR Output Rise Time (Measured from 0.8V to 2V) 1.5 nS tF Output Fall Time (Measured from 2V to 0.8V) 1.5 nS 270 pS 270 pS 550 pS 5.2 nS 5.2 nS 133 MHz 2.5 nS 5 tSK(O) Same device output pin to pin skew tSK(P) Pulse skew tSK(PP) Part to part skew CL= 15pF f ≤133MHz 6,9 7 tPLZ tPHZ Output Enable Time ¯¯ A to OAn, OE ¯¯ B to OBn OE Output Disable Time ¯¯ B to OBn ¯¯ A to OAn, OE OE fMAX Input Frequency tPLH tPHL Propagation Delay INA to OAn, INB to OBn tPZL tPZH 0.5 tR Output Rise Time (Measured from 0.7V to 1.7V) 1.25 nS tF Output Fall Time (Measured from 1.7V to 0.7V) 1.25 nS 200 pS 270 pS 550 pS 5.2 nS 5.2 nS 166 MHz 5 tSK(O) Same device output pin to pin skew tSK(P) Pulse skew tSK(PP) Part to part skew CL= 15pF 133MHz ≤ f ≤166MHz 6,9 7 tPLZ tPHZ Output Enable Time ¯¯ A to OAn, OE ¯¯ B to OBn OE Output Disable Time ¯¯ B to OBn ¯¯ A to OAn, OE OE fMAX Input Frequency tPZL tPZH Notes: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH and tPHL are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 5. Skew measured between all outputs under identical transitions and load conditions. 6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions. 7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature. 8. Airflow of 1m/s is recommended for frequencies above 133MHz. 9. This parameter is measured using f = 1MHz. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 5 of 11 PCS2P20805A September 2006 rev 0.3 Test Circuits and Waveforms 4.6V VCC Open GND 500Ω VIN VOUT Pulse Generator D.U.T RL CL RT 500Ω Enable and Disable Time Circuit VCC 3V INPUT tPHL1 tPLH1 VIN VOUT Pulse Generator D.U.T RL RT 1.25V 0V VOH OUTPUT 1 CL tSK(O) 1.25V VOL tSK(O) VOH OUTPUT 2 1.25V VOL tPHL2 tPLH2 CL = 15pF Test Circuit tSK(O) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | Output Skew – tSK(o) Switch Position Test Disable Low Enable Low Disable High Enable High Test Conditions Switch 4.6V GND Symbol VCC = 2.5V ±0.2V Unit CL 15 pF RT ZOUT of pulse generator Ω RL 33 Ω t R / tF 1 (0V to 2.5V or 2.5V to 0V) nS Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 6 of 11 PCS2P20805A September 2006 rev 0.3 Test Circuits and Waveforms ENABLE 2.5V DISABLE 2.5V CONTROL INPUT 1.25V tPZL tPLZ VOH 1.25V 0.3V VOH Package 1 OUTPUT VOL tPHZ tPZH SWITCH OPEN VOH tSK(PP) 1.25V VOL VOH 0.3V tSK(PP) VOH tSK(PP) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | Part-to- Part Skew Note: Part-to- Part Skew is for package and speed grade. 2.5V INPUT 1.25V 0V tPHL 2.5V INPUT tPHL tPLH VOH 1.7V OUTPUT 0.7V tF 1.25V VOL tPHL2 tPLH2 VOL Note: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH tR 1.25V VOL Package 2 OUTPUT Enable and Disable Times tPLH 1.25V 0V tPHL1 tPLH1 0V OUTPUT NORMALLY SWITCH LOW CLOSED OUTPUT NORMALLY HIGH INPUT 1.25V 1.25V 0V VOH OUTPUT VOL 1.25V tSK(P) = | tPLH - tPLH | VOL Pulse Skew Propagation Delay 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 7 of 11 PCS2P20805A September 2006 rev 0.3 Package Information 20-lead SSOP ( 209 mil ) Dimensions Symbol Inches Min Max Millimeters Min Max A 0.053 0.069 1.346 A1 0.004 0.010 0.102 0.254 A2 …. 0.059 …. 1.499 1.753 D 0.337 0.344 8.560 8.738 c 0.007 0.011 0.178 0.274 E 0.228 0.244 5.791 6.198 E1 0.150 0.157 3.810 3.988 L 0.016 0.035 0.406 0.890 L1 0.010 BASIC 0.254 BASIC b 0.008 0.014 0.203 0.356 R1 0.003 …. 0.08 ….. a 0° 8° 0° 8° e 0.025 BASIC 0.635 BASIC 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 8 of 11 PCS2P20805A September 2006 rev 0.3 20-lead QSOP Dimensions Symbol Inches Min Max Millimeters Min Max A 0.060 0.068 1.52 1.73 A1 0.004 0.008 0.10 0.20 b 0.009 0.012 0.23 0.30 c 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99 e 0.025 BSC 0.64 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 S 0.056 0.060 1.42 1.52 a 0° 8° 0° 8° 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 9 of 11 PCS2P20805A September 2006 rev 0.3 Ordering Information Part Number Marking Package Type Temperature PCS2P20805AG-20-AR 2P20805AG 20-Pin SSOP, TAPE & REEL , Green Commercial PCS2P20805AG-20-AT 2P20805AG 20-Pin SSOP, TUBE, Green Commercial PCS2P20805AG-20-DR 2P20805AG 20-Pin QSOP, TAPE & REEL, Green Commercial PCS2P20805AG-20-DT 2P20805AG 20-Pin QSOP, TUBE, Green Commercial PCS2I20805AG-20-AR 2I20805AG 20-Pin SSOP, TAPE & REEL, Green Industrial PCS2I20805AG-20-AT 2I20805AG 20-Pin SSOP, TUBE, Green Industrial PCS2I20805AG-20-DR 2I20805AG 20-Pin QSOP, TAPE & REEL, Green Industrial PCS2I20805AG-20-DT 2I20805AG 20-Pin QSOP, TUBE, Green Industrial Device Ordering Information P C S 2 P 2 0 8 0 5 A G - 2 0 - A R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 10 of 11 PCS2P20805A September 2006 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P20805A Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 11 of 11