PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver Features Description • Supports data rates up to 3.2Gbps on each lane • Adjustable Transmiter De-Emphasis & Amplitude • Adjustable Receiver Equalization • Spectrum Reference Clock Buffer Output • Optimized for SATAi/m applications • Input signal level detection & output squelch on all channels • 100-Ohm Differential CML I/O’s • Low Power (100mW per Channel) • Standby Mode – Power Down State • VDD Operating Range: 1.8V +/-0.1V • Packaging (Pb-free & Green):48-contact TQFN Pericom Semiconductor’s PI2EQX3232B is a low power, signal Re-Driver. The device provides programmable equalization, amplification, and de-emphasis, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference (ISI). PI2EQX3232B supports four 100-Ohm Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the Re-Driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the Re-Driver. A low-level input signal detection and output squelch function is provided for all four channels. Each channel operates fully independantly. When a channel is enabled (EN_x=1) and operating, that channels input signal level (on xI+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the output driver switches off, and the pin is pulled to VDD via a high impedance resistor. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericom’s PI2EQX3232B also provides power management Stand-by mode operated by an Enable pin. Block Diagram Sel_DE_A Sel_DE_B EN_A EN_B EN_C EN_D VDD 43 42 41 40 39 38 37 44 Sel_EQ_B 46 Sel_OL_A Sel_OL_B 47 Signal Detect 45 VDD Sel_EQ_A 48 Pin Description CML 07-0225 1 VDD 6 31 VDD CI+ CI- 7 30 CO+ 8 29 CO- VDD DO+ 9 28 VDD 10 27 DI+ DO- 11 26 DI- VDD 12 25 GND 22 23 OUT+ OUT- 24 21 IREF 20 GND Sel_DE_D IREF BI- Sel_DE_C OUTOUT+ 32 19 Buffer CKIN+ EN_ CLK BI+ 5 18 CKIN- VDD 33 17 -- Repeated 4 times -- 34 4 Sel_OL_C Sel_OL_D SEL_DE_ x 3 BO+ BO- Sel_EQ_D SEL_OL_x VDD 16 EN_x Power Management AO - 15 SEL_EQ _x AO+ 35 CKINSel_EQ_C xO- xI- 36 2 14 Limiting Amp 1 AI- 13 Equalizer AI+ CKIN+ xO+ EN_CLK CML xI+ PS8889D 10/03/07 PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver Pin Description Pin # 1 2 Pin Name AI+ AI- I/O I I 36 AO+ O 35 AO- O 33 32 BI+ BI- I I 4 BO+ O 5 BO- O 7 8 14 15 CI+ CICKIN+ CKIN- I I I I 30 CO+ O 29 CO- O 27 DI+ I Positive CML Output Channel C with internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_C=0. Drives to output common mode voltage when input is <VTH–. Negative CML Output Channel C with internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_C=0. Drives to output common mode voltage when input is <VTH–. Positive CML Input Channel D with internal 50Ω pull down 26 DI- I Negative CML Input Channel D with internal 50Ω pull down 10 DO+ O 11 DO- O 41, 40, 39, 38 EN_ [A,B,C,D] I 13 EN_CLK I 25, Center Pad 24 22 23 47 46 GND IREF OUT0+ OUT1SEL_EQ_A SEL_EQ_B PWR O O O I I 16 SEL_EQ_C I 17 SEL_EQ_D I 07-0225 Description Positive CML Input Channel A with internal 50Ω pull down Negative CML Input Channel A with internal 50Ω pull down Positive CML Output Channel A internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_A=0. Drives to output common mode voltage when input is <VTH–. Negative CML Output Channel A with internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_A=0. Drives to output common mode voltage when input is <VTH–. Positive CML Input Channel B with internal 50Ω pull down Negative CML Input Channel B with internal 50Ω pull down Positive CML Output Channel B with internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_B=0. Drives to output common mode voltage when input is <VTH–. Negative CML Output Channel B with internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_B=0. Drives to output common mode voltage when input is <VTH–. Positive CML Input Channel C with internal 50Ω pull down Negative CML Input Channel C with internal 50Ω pull down Differential Input Reference Clock Positive CML Output Channel D with internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_D=0. Drives to output common mode voltage when input is <VTH–. Negative CML Output Channel C with internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_D=0. Drives to output common mode voltage when input is <VTH–. Active HIGH LVCMOS signal input pins, when HIGH, it enables the CML output. When LOW, it disables the CML output (x0+, x0-) to HI-z state. Both x0+ & x0- outputs will be pulled up to VDD by internal 2kΩ resistor. Active HIGH LVCMOS signal input pin. When HIGH, it enables the OUTx+/OUTxoutputs. When LOW, it disables these outputs, with 50Ω to ground termination. Supply Ground External 475Ω resistor connection to set the differential output current Differential Reference Clock Output Selection pins for equalizer (see Amplifier Configuration Table) w/ 50kΩ internal pull up 2 PS8889D 10/03/07 PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver Pin Description (Continued) Pin # Pin Name I/O 45 44 18 19 43 42 20 21 3,6,9,12,28, 31,34,37,38 SEL_OL_A SEL_OL_B SEL_OL_C SEL_OL_D SEL_DE_A SEL_DE_B SEL_DE_C SEL_DE_D I I I I I I I I VDD PWR Description Selection pins for amplifier (see Amplifier Configuration Table) w/ 50kΩ internal pull up Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50kΩ internal pull up 1.8V Supply Voltage Output Swing Control SEL3_[A:D] 0 1 Output De-emphasis Adjustment Swing 1x 1.2x SEL5_[A:D] 0 1 De-emphasis 0dB -3.5dB Equalizer Selection SEL0_[A:D] 0 1 Compliance Channel [0:3.5dB] @ 1.6 GHz [0:7.5dB] @ 1.6 GHz Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ –65°C to +150°C Supply Voltage to Ground Potential ................................... –0.5V to +2.5V DC SIG Voltage ..........................................................–0.5V to VDD +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 800mW Operating Temperature .............................................................. 0 to +70°C 07-0225 3 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PS8889D 10/03/07 PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver AC/DC Electrical Characteristics (VDD = 1.8 ±0.1V) Symbol Ps Parameter Supply Power Latency CML Receiver Input RLRX Return Loss Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage VTHSignal Detect Threshold DC Differential Input ZRX-DIFF-DC Impedance DC Input Impedance ZRX-DC Conditions EN = LVCMOS Low EN = LVCMOS High From input to output Min. Typ. 50 MHz to 1.25 GHz Max. 0.1 0.6 W 2.0 ns 12 dB 0.200 EN_X = High Units V 50 150 mV 200 mVp-p 80 100 120 40 50 60 Ω Equalization JRS Residual Jitter(1,2) JRM Random Jitter(1,2) Total Jitter Deterministic jitter 0.3 0.2 1.5 Ulp-p psrms Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of Figure 1. FR4 Signal Source A B C Pericom Re-Driver SmA Connector SmA Connector In Out 30IN Figure 1. Test Condition Referenced in the Electrical Characteristic Table 07-0225 4 PS8889D 10/03/07 PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver AC/DC Electrical Characteristics (TA = 0 to 70˚C) Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (100Ω differential) Swing = 1.0x 200 375 Swing = 1.2x 250 450 Swing = 1.0x 400 750 Swing = 1.2x 500 900 VDIFFP Output Voltage Swing; | VTX-D+ - VTX-D- | Differential Swing VTX-DIFFP-P Differential Peak-to-peak Ouput Voltage; VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | tF, tR Transition Time 20% to 80% (1) ZOUT Output resistance Single ended ZTX-DIFF-DC CTX mVp-p mV 150 ps 40 50 60 Ω DC Differential TX Impedance 80 100 120 Ω AC Coupling Capacitor 75 200 nF 0.65 × VDD VDD LVCMOS Control Pins VIH Input High Voltage VIL Input Low Voltage 0.35 × VDD IIH Input High Current 250 IIL Input Low Current 500 V μA Note: 1. Using K28.7 (0011111000) pattern) 2. When 1.0x swing selected 3. When 1.2x swing selected 07-0225 5 PS8889D 10/03/07 PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver AC Switching Characteristics for Clock Buffer (VDD = 1.8 ±0.1V) (3) Symbol Trise / Tfall Parameters Rise and Fall Time (measured between 0.175V to 0.525V) (1) Min Max. 125 525 ΔTrise / ΔTfall Rise and Fall Time Variation VHIGH Voltage High including overshoot 660 VLOW Voltage Low including undershoot -150 Absolute crossing point voltages -200 550 200 250 45 55 VCROSS ΔVCROSS TDC 75 Total Variation of Vcross over all edges Duty Cycle (input duty cycle = 50%) (2) Units Notes 1 ps 900 1 1 mV 1 1 1 % 2 Notes: 1. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF. Configuration Test Load Board Termination Rs 33Ω 5% Clock TLA CLKBUF Rs 33Ω 5% Clock# TLB Rp 49.9Ω 1% 475Ω 1% Rp 49.9Ω 1% 2pF 5% 2pF 5% Figure 2. Configuration test load board termination Note: • TLA and TLB are 3” transmission lines. 07-0225 6 PS8889D 10/03/07 PI2EQX3232B 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver ( "$ %&$!& ( ( ( ( "$ %&$!& Packaging Mechanical: 48-Contact TQFN (ZD48) ( ( ( !%##!$ ! $ ''!&$ .OTES !LLDIMENSIONSAREINMILLIMETERSANGLESINDEGREES 2EF*%$%#-/6++$ 4HERMAL6IA$IAMETER2ECOMMENDED^MM 4HERMAL6IA0ITCH2ECOMMENDEDMM DATE: 03/10/06 DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) "ILATERALCOPLANARITYZONEAPPLIESTOTHEEXPOSEDHEATSINKSLUG ASWELLASTHETERMINALS PACKAGE CODE: ZD (ZD48) REVISION: A DOCUMENT CONTROL #: PD-2045 06-0252 Ordering Information Ordering Number Package Code Package Description PI2EQX3232BZDE ZD Pb-free & Green 48-Contact TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 07-0225 7 PS8889D 10/03/07