RED PLCD5580 YELLOW PLCD5581 HIGH EFFICIENCY RED PLCD5582 GREEN PLCD5583 HIGH EFFICIENCY GREEN PLCD5584 Low Power 0.145” 8-Character, 5x5 Dot Matrix Parallel Input Alphanumeric Intelligent Display Package Dimensions in inches (mm) 0.145 (3.68) 1.680 (42.67) max. 0.210 (5.34) 0.086 (2.19) 0.105 (2.67) 0.771 (19.58) 0.600 (15.24) 0.386 (9.8) Pin 1 Indicator 0.012 (0.30) typ. Intensity Code Color Bin (For Yellow Only) 0.209 (5.31) Part Number EIA Date Code PLCD558X SIEMENS WW FEATURES • Eight 0.145” (3.68 mm) High 5 x 5 Dot Matrix Characters in Red, Yellow, High Efficiency Red, Green, or High Efficiency Green • Built-in 2 Page, 256 Character ROM. Both Pages Mask Programmable for Custom Fonts • Built-in Decoders, Multiplexers and Drivers • Wide Viewing Angle, X Axis ±50°, Y Axis ±65° • Programmable Features: – Individual Flashing Character – Full Display Blinking – Multi-Level Dimming and Blanking – Clear Function – Lamp Test • Internal or External Clock • End Stackable Dual-In-Line Plastic Package • Low Power: 20% Less Power Consumption Than 5 X 7 Format 0.189 (4.79) 0.018 typ. (.46) Z 1 0.100 (2.54) typ. 0.160±.020 (4.06±.50) DESCRIPTION The PLCD5580 (Red), PLCD5581 (Yellow), PLCD5582 (High Efficiency Red), PLCD5583 (Green), and PLCD5584 (High Efficiency Green) are eight digit, 5x5 dot matrix, alphanumeric Programmable Displays. The 0.145 inch high digits are packaged in a rugged, high quality, optically transparent, standard 0.6 inch 28 pin plastic DIP. The on-board CMOS has a built-in two page, 256 character ROM. Both pages are mask programmable for 256 custom characters. The first page of ROM of the standard product contains 128 characters including ASCII, selected European and Scientific symbols. The second page contains Katakana Japanese characters, more European characters, Avionics, and other graphic symbols. The PLCD558X is designed for standard microprocessor interface techniques and is fully TTL compatible. The Clock I/O and Clock Select pins allow the user to synchronize multiple display modules. 2–131 Maximum Rating DC Supply Voltage ........................................ –0.5 to +7.0 Vdc Input Voltage Levels Relative to Ground...............................................–0.5 to VCC+0.5 Vdc Operating Temperature ................................. –40°C to +85°C Storage Temperature .................................... –40°C to +100°C Maximum Solder Temperature 0.063" below Seating Plane, t<5 sec...................................... 260°C Relative Humidity at 85°C................................................. 85% Switching Specifications (over operating temperature range and VCC=4.5 V). Symbol Description Min. Units Tbw Time Between Writes 30 ns Tacc(2) Display Access Time 130 ns Tas Address Setup Time 10 ns Tces Chip Enable Hold Time 0 ns Tah Address Hold Time 20 ns Tceh Chip Enable Hold Time 0 ns R0 Tw Write Active Time 100 ns R1 Tds Data Valid Prior to Rising Edge of Write 50 ns Tdh Data Hold Time 20 ns Trc(1) Reset Active Time 300 ns Tclr(3) Clear Cycle Time 3 µs Note: Maximum voltage is with no LEDs illuminated. Enlarged Character Font 0.033 (0.84) typ. 0.100 (2.54) C0 C1 C2 C3 C4 R2 0.145 (3.68) R3 0.011 (0.28) typ. R4 0.022 (0.56) typ. 1. Wait 300 ns min. after the reset function is turned off. 2. Tacc=Tas + Tw + Tah 3. The Clear Cycle Time may be shortened by writing a second Control Word with the Clear Bit disabled, 160 ns after the first control word that enabled the Clear Bit. Dimensions in inches (mm) Tolerance: .XXX=± .010 (.25) data write control word-clear bit enabled wait wait 130 ns data write control word-clear bit enabled The Flash RAM and Character RAM may not be accessed until the Clear Cycle is complete. Write Cycle Timing Diagram Tacc Tas Tah see Notes FL, A3-A0 CE see Notes Tces Tceh WR see Notes Tw Tbw Notes see Notes 1. All input voltages are (VIL=0.8 V, VIH=2.0 V) D7-D0 2. These wave forms are not edge triggered. 3. Tbw=Tas + Tah Tdh Tds PLCD5580/1/2/3/4 2–132 Optical Characteristics at 25°C VCC=5.0 V at Full Brightness Red PLCD5580 Description Symbol Min. Typ. Units Peak Luminous Intensity(1) IVpeak 70 90 µcd/dot Peak Wavelength λ(peak) 660 nm Dominant Wavelength λ(d) 639 nm Yellow PLCD5581 Description Symbol Min. Typ. Units Peak Luminous Intensity(1) IVpeak 130 210 µcd/dot Peak Wavelength λ(peak) 583 nm Dominant Wavelength λ(d) 585 nm High Efficiency Red PLCD5582 Description Symbol Min. Typ. Units Peak Luminous Intensity(1) IVpeak 150 330 µcd/dot Peak Wavelength λ(peak) 630 nm Dominant Wavelength λ(d) 626 nm Green PLCD5583 Description Symbol Min. Typ. Units Peak Luminous Intensity(1) IVpeak 150 260 µcd/dot Peak Wavelength λ(peak) 565 nm Dominant Wavelength λ(d) 570 nm High Efficiency Green PLCD5584 Description Symbol Min. Typ. Units Peak Luminous Intensity(1) IVpeak 200 510 µcd/dot Peak Wavelength λ(peak) 568 nm Dominant Wavelength λ(d) 574 nm Note 1. Peak luminous intensity is meaaured at TA=TJ=25°C. No time is allowed for the device to warm up prior to measurement. PLCD5580/1/2/3/4 2–133 Electrical Characteristics at 25°C Limits Parameters Conditions Min. Typ. Max. Units 4.5 5.0 5.5 V ICC Blank 0.5 1.0 mA VCC=5 V, VIN=5 V ICC 8 digits (1), 16 dots/character 240 290 mA VCC=5 V, “#” displayed in all eight digits IIP Current (with pull-up) 11 18 µA VCC=5 V, VIN=0 V to VCC, (WR, CE, FL, RST, ClkSel) ±1 µA VCC=5 V, VIN=0 V to VCC, (Clk I/O, A0–A3, D0–D7) VCC II Input leakage current (without pull-up) VIH Input Voltage High 2.0 VCC +0.3 V VCC=4.5 V to 5.5 V VIL Input Voltage Low GND –0.3 0.8 V VCC=4.5 V to 5.5 V 0.4 V VCC=4.5 V to 5.5 V, IOL=1.6 mA VOL Output Voltage Low (Clock Pin) VOH Output Voltage High (Clock Pin) 2.4 V VCC=4.5 V to 5.5 V, IOH=40 µA IOH Output Current High (Clock I/O) –0.9 mA VCC=4.5 V, VOH=2.4 V IOL Output Current Low (Clock I/O) 1.6 2 mA VCC=4.5 V, VOL=0.4 V 25 °C/W θJC Thermal Resistance, Junction to Case Fext External Clock, Input Frequency(2) 28 81.14 KHz VCC=5.0 V, CLKSEL=0 Fosc Internal Clock, Output Frequency(2) 28 81.14 KHz VCC=5.0 V, CLKSEL=1 Clock I/O Buss Loading 240 pF Clock Out Rise Time 500 ns VCC=4.5 V, VOH=2.4 V Clock Out Fall Time 500 ns VCC=4.5 V, VOL=0.4 V FM, Digit Multiplex Frequency 125 256 362.5 Hz Blinking Rate 0.98 2 2.83 Hz Notes: 1. Average ICC measured at full brightness. Peak ICC=5⁄8 x IAVG ICC (# displayed). 2. Internal/external frequency duty factor is 50%. PLCD5580/1/2/3/4 2–134 Top View TOP VIEW 28 15 1 14 Pin Assignment Pin Function 1 RST 2 3 4 5 6 7 FL A0 A1 A2 A3 Substr. bias 8 9 10 11 12 Substr. bias Substr. bias No connect CLKSEL CLK I/O Pin Function Pin Function 1 RST 28 D7 2 FL 27 D6 13 WR 3 A0 26 D5 4 A1 25 D4 5 A2 24 D3 6 A3 23 D2 7 Substr. bias 22 No Pin 8 Substr. bias 21 No Pin 9 Substr. bias 20 D1 10 No Connect 19 D0 11 CLKSEL 18 No Connect 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC GND GND CE No connect D0 D1 No pin No pin D2 D3 D4 D5 D6 D7 12 CLK I/O 17 CE 13 WR 16 GND (logic) 14 VCC 15 GND (supply) Definition Used to initialize a display and synchronize blinking for multiple displays Low input accesses the Flash RAM Address input LSB Address input Address input MSB Mode selector Optional connection to VCC. Can’t be used to supply power to display. See Definition 7 See Definition 7 Selects internal/external clock source Outputs master clock or inputs external clock A low will write data into the display if CE is low Positive power supply input Analog Ground for LED drivers Digital Ground for internal drivers Enables access to the display Data input LSB Data input Data input Data input Data input Data input Data input Data input MSB, selects ROM, page 1 or 2 Cascading the PLCD558X Displays WR FL RST VCC WR FL RST CLK I/O CLKSEL Up to14 More Displays in between Display D0-D7 A0-A4 WR FL RST CLK I/O CLKSEL Display D0-D7 A0-A4 CE CE Data I/O Address A6 A7 A8 A9 0 Address Decoder Address Decode Chip 1 to 14 15 PLCD5580/1/2/3/4 2–135 Character Set–ROM Page 1 D0 0 D1 0 D2 0 D3 0 D6 D5 D4 Hex 0 ASCII Code 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 A 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 1 1 E 1 1 1 1 F Notes 1. D7=0 2. High=1 level. Low=0 level. PLCD5580/1/2/3/4 2–136 Character Set–ROM Page 2 D0 0 D1 0 ASCII D2 0 Code D3 0 D6 D5 D4 Hex 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 A 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 1 1 E 1 1 1 1 F Notes 1. D7=1 2. High=1 level. Low=0 level. PLCD5580/1/2/3/4 2–137 Block Diagram DISPLAY Rows 0 to 9 0 1 2 3 4 5 6 7 Columns 0 to 19 Row Control Logic & Row Drivers RST CLK I/O CLKSEL OSC + 32 Counter +7 Counter Blink + 128 Rate Counter Mux Rate 7 Bit ASCII Code 8 x 8 Bits Address Lines Control Word Decode Logic Column Decoder Display Memory Latches D6 D5 D4 D3 D2 D1 D0 Control Word D7 Timing and Control Logic Row Decoder ROM 1 ROM 2 128x7 Bit ASCII Character Decode (4.48K Bits) 128x7 Bit Column ASCII Character Data Decode (4.48K Bits) Master Slave Latches Digit 0 to 8 Column Drivers for Digit 0 to 8 Flash RAM (8 x 1 Bit) Address Decoder A0 A1 A2 A3 WR CE FL The Clock Source could either be the internal oscillator (CLKSEL=1) of the device or an external clock (CLKSEL=0) could be an input from another PLCD211X display for the synchronization of blinking for multiple displays. Functional Description The PLCD558X block diagram is comprised of the following major blocks and registers. Display Memory consists of a 8x8 bit RAM block. Each of the eight 8-bit words holds the 7-bit ASCII data (bit D0-D6). The 8th bit, D7 selects 1 of the 2 pages of character ROM. D7=0 selects Page 1 of the ROM and D7=1 selects Page 2 of the ROM. A3=1. RST can be used to initialize display operation upon power up or during normal operation. When activated, RST will clear the Flash RAM and Control Word Register (00H) and reset the internal counter. All eight display memory locations will be set to 20H to show blanks in all digits. FL pin enables access to the Flash RAM. The Flash RAM will set (D0=1)or reset (D0=0) flashing of the character addressed by A0–A2. The 1x8 bit Control Word RAM is loaded with attribute data if A3=0. The Control Word Logic decodes attribute data for proper implementation. Character ROM is designed for two pages of 128 characters each. Both pages of the ROM are Mask Programmable for custom fonts. On the standard product page one contains standard ASCII, selected European characters and some scientific symbols. Page two contains Katakana characters, more European characters, avionics, and other graphic symbols. The Display Multiplexer controls the Row Drivers so no additional logic is required for a display system. The Display has eight digits. Each digit has 25 LEDs clustered into a 5x5 dot matrix. Theory of Operation The PLCD558X Programmable display is designed to work with all major microprocessors. Data entry is via an eight bit parallel bus. Three bits of address route the data to the proper digit location in the RAM. Standard control signals like WR and CE allow the data to be written into the display. D0–D7 data bits are used for both ASCII and control word data input. A3 acts as the mode selector. If A3=0, D0–D7 load the RAM with control word data. If A3=1, D0–D7 will load the RAM with ASCII and page select data. In the later mode, D7=0 selects Page 1 of Character ROM and D7=1 selects Page 2 of Character ROM. For normal operation FL pin should be held high. When FL is held low, Flash RAM is accessed to set character blinking. The seven bit ASCII code is decoded by the Character ROM to generate Column data. Twenty columns worth of data is sent out each display cycle and it takes fourteen display cycles to write into eight digits. The rows are being multiplexed in two sets of five rows each. The internal timing and control logic synchronizes the turning on of rows and presentation of column data to assure proper display operation. PLCD5580/1/2/3/4 2–138 Data Input Commands Signals Operation CE WR FL A3 A2 A1 A0 1 X x 1 x x x x x x x x x x No operation No operation 0 0 1 0 0 0 0 Write Control Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Digit 0 (left) Digit 1 Digit 2 Digit 3 Digit 4 Digit 5 Digit 6 Digit 7 (right) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Digit 0 (left) Digit 1 Digit 2 Digit 3 Digit 4 Digit 5 Digit 6 Digit 7 (right) Write display data to user RAM and Page Select Register D0–D6=ASCII Data D7=0 Select ROM1 D7=1 Select ROM 2 Write Flash RAM Register D0=0 Flashing Character off D0=1 Flashing Character on D1–D7=X X=don’t care Power up Sequence Upon power up display will come on at random. Thus the display should be reset on power-up. The reset will clear the Flash RAM, Control Word Register and reset the internal counter. All the digits will show blanks and display brightness level will be 100%. The character Flash Enable causes 2 Hz coming out of the counter to be ANDED with column drive signal and makes the column driver to cycle at 2 Hz. Thus the character flashes at 2 Hz. Microprocessor Interface The display Blink works the same way as the Flash Enable but causes all twenty column drivers to cycle at 2 Hz thereby making all eight digits to blink at 2 Hz. The interface to a microprocessor is through the 8-bit data bus (D0-D7), the 4-bit address bus (A0–A3) and control lines FL, CE and WR. The Lamp Test causes the column drivers to run at 1/2 duty cycle thus all the LEDs in all eight digits turn on at 50% intensity. To write data (ASCII/ Control Word) into the display CE should be held low, address and data signals stable and WR should be brought low. Clear bit clears the character RAM and writes a blank into the display memory. It however does not clear the control word. The Control Word is decoded by the Control Word Decode Logic. Each code has a different function. The code for display brightness changes the duty cycle for the column drivers. The peak LED current stays the same but the average LED current diminishes depending on the intensity level. ASCII Data or Control Word Data can be written into the display at this point. For multiple display operation, CLK I/O must be properly selected. CLK I/O will output the internal clock if CLKSEL=1, or will allow input from an external clock if CLKSEL=0. PLCD5580/1/2/3/4 2–139 Control Word Format Display Brightness The display can be programmed to vary between blank, 13%, 20%, 27%, 40%, 53%, 80%, and full brightness. Bits D0, D1 and D2 control the display brightness. CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Display Brightness 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 100% Brightness 80% Brightness 53% Brightness 40% Brightness 27% Brightness 20% Brightness 13% Brightness Blank Display X= Don’t care Flash RAM Function Character Flash is controlled by FL pin, bit D0 and control word bit D3. Combination of FL being low, proper digit address and D0 being high will write a flash bit into the Flash RAM Register. In the control word mode when D3 is brought high, the above mentioned character will flash. Setting the Flash Bit CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 0 0 X X A A A A A A X X X X X X X X X X X X X X 0 1 Flash RAM disabled Flash RAM enabled X=Don’t care A=Selected address Character Flash Control Word CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 1 1 0 0 X X X X X X 0 0 0 0 X X 0 0 0 1 B B B B B B Disable Flashing Char. Enabled Flashing Char. X=Don’t care B=Selected brightness Display Blinking Blinking function is independent of Flash function. When D4 is held high, entire display blinks at 2 Hz. CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 1 1 0 0 X X X X X X 0 0 0 0 X X 0 1 0 0 B B B B B B Display Blinking disabled Display Blinking enabled X=Don’t care B=Selected brightness Lamp Test Bit D6 when brought high will cause all the LEDs in all eight digits to light up at 53% brightness. Selecting or de-selecting Lamp Test has no effect on the display memory. CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 1 1 0 0 X X X X X X 0 0 0 0 X X 0 0 X 0 X X X X X X Lamp Test disabled Lamp Test enabled X=Don’t care PLCD5580/1/2/3/4 2–140 Clear Function Clear function will clear the display. The Flash RAM will be set to all zeros. An ASCII blank code (20H) will be written into the display memory. The user must 3 µs or write a new control word to the display with control word bit D7=0 to disable clear before writing any data to the display memory, otherwise all new data to the display memory will remain cleared. See Switching Specifications for clear function timing. CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 1 1 0 0 X X X X X X 0 1 X X X X X X X X X X X X X X Clear disabled Clear user RAM, page RAM, flash RAM and display X=Don’t care Control Word Format D7 CLEAR ENABLE D6 LAMP TEST D5 NOT USED D4 BLINK ENABLE D3 FLASH ENABLE D2 D1 D0 BRIGHTNESS CONTROL D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 BRIGHTNESS 100% 80% 53% 40% 27% 20% 13% 0% Blank D3 FLASH ENABLE 0 Disable Flashing Character 1 Enable Blinking Character D4 BLINKING DISPLAY 0 Disable Blinking Character 1 Enable Blinking Character D6 LAMP TEST 0 Disable Lamp Test 1 Enable Lamp Test (all dots on at 53% brightness) D7 CLEAR ENABLE 0 Disable Clear 1 Enable Clear (Clear Data RAM, Page RAM, Flash RAM) PLCD5580/1/2/3/4 2–141 Electrical and Mechanical Considerations Voltage Transient Suppression For best results power the display and the components that interface with the display to avoid logic inputs higher than VCC. Additionally, the LEDs may cause transients in the power supply line while they change display states. The common practice is to place a parallel combination of a .01 µF and a 22 µF capacitor between VCC and GND for all display packages. ESD Protection The input protection structure of the PLCD5580/1/2/3/4 provides significant protection against ESD damage. It is capable of withstanding discharges greater than 2 KV. Take all the standard precautions, normal for CMOS components. These include properly grounding personnel, tools, tables, and transport carriers that come in contact with unshielded parts. If these conditions are not, or cannot be met, keep the leads of the device shorted together or the parts in anti-static packaging. Soldering Considerations THE PLCD5580/1/2/3/4 can be hand soldered with SN63 solder using a grounded iron set to 260°C. Wave soldering is also possible following these conditions: Preheat that does not exceed 93°C on the solder side of the PC board or a package surface temperature of 85°C. Water soluble organic acid flux (except carboxylic acid) or resinbased RMA flux without alcohol can be used. Wave temperature of 245°C ± 5°C with a dwell between 1.5 sec. to 3.0 sec. Exposure to the wave should not exceed temperatures above 260°C for five seconds at 0.063" below the seating plane. The packages should not be immersed in the wave. Post Solder Cleaning Procedures The least offensive cleaning solution is hot D.I. water (60°C) for less than 15 minutes. Addition of mild saponifiers is acceptable. Do not use commercial dishwasher detergents. For faster cleaning, solvents may be used. Exercise care in choosing solvents as some may chemically attack the nylon package. Maximum exposure should not exceed two minutes at elevated temperatures. Acceptable solvents are TF (trichorotrifluorethane), TA, 111 Trichloroethane, and unheated acetone.(1) Note: 1. Acceptable commercial solvents are: Basic TF, Arklone, P. Genesolv, D. Genesolv DA, Blaco-Tron TF, Blaco-Tron TA, and Freon TA. Unacceptable solvents contain alcohol, methanol, methylene chloride, ethanol, TP35, TCM, TMC, TMS+, TE, or TES. Since many commercial mixtures exist, contact a solvent vendor for chemical composition information. Some major solvent manufacturers are: Allied Chemical Corporation, Specialty Chemical Division, Morristown, NJ; Baron-Blakeslee, Chicago, IL; Dow Chemical, Midland, MI; E.I. DuPont de Nemours & Co., Wilmington, DE. For further information refer to Appnotes 18 and 19 in the current Siemens Optoelectronic Data Book. An alternative to soldering and cleaning the display modules is to use sockets. Naturally, 28 pin DIP sockets .600" wide with .100" centers work well for single displays. Multiple display assemblies are best handled by longer SIP sockets or DIP sockets when available for uniform package alignment. Socket manufacturers are Aries Electronics, Inc., Frenchtown, NJ; Garry Manufacturing, New Brunswick, NJ; Robinson-Nugent, New Albany, IN; and Samtec Electronic Hardward, New Albany, IN. For further information refer to Appnote 22 in the current Siemens Optoelectronic Data Book. Optical Considerations The .200" high character of the PLCD588X gives readability up to eight feet. Proper filter selection enhances readability over this distance. Using filters emphasizes the contrast ratio between a lit LED and the character background. This will increase the discrimination of different characters. The only limitation is cost. Take into consideration the ambient lighting environment for the best cost/benefit ratio for filters. Incandescent (with almost no green) or fluorescent (with almost no red) lights do not have the flat spectral response of sunlight. Plastic band-pass filters are an inexpensive and effective way to strengthen contrast ratios. The PLCD5880/ 5882 are red/high efficiency red displays and should be matched with long wavelength pass filter in the 570 nm to 590 nm range. The PLCD5881/5883/5884 should be matched with a yellow-green band-pass filter that peaks at 565 nm. For displays of multiple colors, neutral density grey filters offer the best compromise. Additional contrast enhancement is gained by shading the displays. Plastic band-pass filters with built-in louvers offer the next step up in contrast improvement. Plastic filters can be improved further with anti-reflective coatings to reduce glare. The trade-off is fuzzy characters. Mounting the filters close to the display reduces this effect. Take care not to overheat the plastic filter by allowing for proper air flow. Optimal filter enhancements are gained by using circular polarized, anti-reflective, band-pass filters. The circular polarizing further enhances contrast by reducing the light that travels through the filter and reflects back off the display to less than 1%. Selecting the proper intensity of the displays allows 10,000 foot candle sunlight viewability. Several filter manufacturers supply quality filter materials. Some of them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homalite, Wilmington, DE; 3M Company, Visual Products Division, St. Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge, MA; Marks Polarized Corporation, Deer Park, NY, Hoya Optics, Inc., Fremont, CA. One last note on mounting filters: recessing displays and bezel assemblies is an inexpensive way to provide a shading effect in overhead lighting situations. Several bezel manufacturers are: R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plastic Corp., Burlingame, CA; Photo Chemical Products of California, Santa Monica, CA; I.E.E.-Atlas, Van Nuys, CA. PLCD5580/1/2/3/4 2–142