Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) DESCRIPTION The PLUS405-55 device is a bipolar, programmable state machine of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the 8 on-chip State Registers (QP0 - QP7). Two complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C0, C1). All state transition terms can include True, False and Don’t Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all of the 64 transition terms can be connected to any or all of the State and Output Registers. All state (QP0 - QP7) and output (QF0 - QF7) registers are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level “1”. This feature allows the state machine to be asynchronously initialized to known internal state and output conditions prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to “1”. If desired, the initialization input pin (INIT) can be converted to an Output Enable (OE) function as an additional user-programmable feature. Availability of two user-programmable clocks allows the user to design two independently clocked state machine functions consisting of four state and four output bits each. Order codes are listed in the Ordering Information Table below. PLUS405-55 FEATURES • 66.7MHz minimum guaranteed clock rate • 55MHz minimum guaranteed operating PIN CONFIGURATIONS N Package frequency (1/(tIS1 + tCKO1) • Functional superset of PLS105/105A • Field-programmable (Ti-W fusible link) • 16 input variables • 8 output functions • 64 transition terms • 8-bit State Register • 8-bit Output Register • 2 transition Complement Arrays • Multiple clocks • Programmable Asynchronous Initialization CLK 1 28 VCC I7 2 27 I8 I6 3 26 I9 I5/CLK 4 25 I10 I4 5 24 I11 I3 6 23 I12 I2 7 22 I13 I1 8 21 I14 I0 9 20 I15 F7 10 19 INIT/OE F6 11 18 F0 F5 12 17 F1 F4 13 16 F2 GND 14 15 F3 or Output Enable • Power-on preset of all registers to “1” • “On-chip” diagnostic test mode features for access to state and output registers • 950mW power dissipation (typ.) • TTL compatible • J-K or S-R flip-flop functions • Automatic “Hold” states • 3-State outputs N = Plastic DIP (600mil-wide) A Package I5/CLK I6 4 APPLICATIONS • Interface protocols • Sequence detectors • Peripheral controllers • Timing generators • Sequential circuits • Elevator contollers • Security locking systems • Counters • Shift registers 3 I7 CLK VCC I8 1 28 27 2 I9 26 I4 5 25 I10 I3 6 24 I11 I2 7 23 I12 I1 8 22 I13 I0 9 21 I14 F7 10 20 I15 F6 11 19 INIT/OE 12 13 14 15 16 17 18 F5 F4 GND F3 F2 F1 F0 A = Plastic Leaded Chip Carrier ORDERING INFORMATION OPERATING FREQUENCY ORDER CODE DRAWING NUMBER 28-Pin Plastic Dual In-Line (600mil-wide) 55MHz (tIS + tCKO) PLUS405–55N 0413B 28-Pin Plastic Leaded Chip Carrier 55MHz (tIS + tCKO) PLUS405–55A 0401F DESCRIPTION October 22, 1993 180 853–1546 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION POLARITY 1 CLK1 Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both state and output registers. Pin 1 only clocks P0–3 and F0–3 if Pin 4 is also being used as a clock. Active-High (H) 2, 3, 5–9, 26–27 20–22 I0 – I4, I7, I6 I8 – I9 I13 – I15 Logic Inputs: The 12 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of “H” and “L”. Active-High/Low (H/L) 4 CLK2 Logic Input/Clock: A user programmable function: • Logic Input: A 13th external logic input to the AND array, as above. Active-High/Low (H/L) • Clock: A 2nd clock for the State Registers P4–7 and Output Registers F4–7, as above. Active-High (H) Note that input buffer I5 must be deleted from the AND array (i.e., all fuse locations “Don’t Care”) when using Pin 4 as a Clock. 23 I12 Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard TTL or CMOS levels. When I12 is held at +10V, device outputs F0–F7 reflect the contents of State Register bits P0–P7. The contents of each Output Register remains unaltered. Active-High/Low (H/L) 24 I11 Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when exercising standard TTL levels. When I11 is held at +10V, device outputs F0–F7 become direct inputs for State Register bits P0–P7; a Low-to-High transition on the appropriate clock line loads the values on pins F0–F7 into the State Register bits P0–P7. The contents of each Output Register remains unaltered. Active-High/Low (H/L) 25 I10 Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercising standard TTL levels. When I10 is held at +10V, device outputs F0–F7 become direct inputs for Output Register bits Q0–Q7; a Low-to-High transition on the appropriate clock line loads the values on pins F0–F7 into the Output Register bits Q0–Q7. The contents of each State Register remains unaltered. Active-High/Low (H/L) 10–13 15–18 F0 – F7 Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which normally reflect the contents of Output Register Bits Q0–Q7, when enabled. When I12 is held at +10V, F0–F7 = (P0–P7). When I11 is held at +10V, F0–F7 become inputs to State Register bits P0–P7. When I10 is held at +10V, F0–F7 become inputs to Output Register bits Q0–Q7. Active-High (H) 19 INIT/OE Initialization or Output Enable Input: A user programmable function: • Initialization: Provides an asynchronous preset to logic “1” or reset to logic “0” of all State and Output Register bits, determined individually for each register bit through user programming. INIT overrides Clock, and when held High, clocking is inhibited and F0–F7 and P0–P7 are in their initialization state. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after INIT goes Low. See timing definition for tNVCK and tVCK. Active-High (H) • Output Enable: Provides an output enable function to buffers F0–F7 from the Output Active-Low (L) Registers. October 22, 1993 181 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 TRUTH TABLE 1, 2, 3, 4, 5, 6, 7 OPTION VCC INIT I10 I11 I12 CK J K QP QF F H * * * X X X H/L H/L QF L +10V X X X X QP L L L +10V X X X X QP H H L X +10V X X X L QF L L L L X X X +10V X X X +10V X X X X X X X X X H QP QP QF QF QF H QP QF H X X * X X X QP QF Hi-Z X +10V X X X X QP L L X +10V X X X X QP H H X X +10V X X X L QF L X L L X X X +10V X X X +10V X X X X X X X H QP QP QF QF QF H QP QF L X X X L QP QF QF X X X L H L L L L X X X H L H H H L X X X ↑ ↑ ↑ ↑ L L H H QP QF QF X X X X X X X H H +5V ↑ X OE ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ X X NOTES: 1. Positive Logic: S/R (or J/K) = T0 + T1 + T2 + . . . T63 Tn = (C0, C1) (I0, I1, I2, . . .) (P0, P1, . . . P7) 2. Either Initialization (Active-High) or Output Enable (Active-Low) are available, but not both. The desired function is a user-programmable option. 3. ↑ denotes transition from Low-to-High level. 4. * = H or L or +10V 5. X = Don’t Care (<5.5V) 6. H/L implies that either a High or a Low can occur, depending upon user-programmed selection (each State and Output Register individually programmable). 7. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels on the output pins are forced by the user. VIRGIN STATE A factory-shipped virgin device contains all fusible links intact, such that: 1. INIT/OE is set to INIT. In order to use the INIT function, the user must select either the PRESET or the RESET option for each flip-flop. Note that regardless of the user-programmed initialization, or even if the INIT function is not used, all registers are preset to “1” by the power-up procedure. 2. All transition terms are inactive (0). 3. All S/R (or J/K) flip-flop inputs are disabled (0). 4. The device can be clocked via a Test Array preprogrammed with a standard test pattern. LOGIC FUNCTION Q3 Q2 Q1 Q0 1 0 1 0 ⋅ ⋅ ⋅ A B C ... STATE REGISTER 0 0 0 1 Sn + 1 NEXT STATE ⋅ ⋅ ⋅ ⋅ ⋅ SET Q0: J0 = (Q2 Q1 Q0) A B C . . . K0 = 0 RESET Q1: J1 = 0 K1 = (Q3 Q2 Q1 Q0) A B C . . . ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ HOLD Q2: J2 = 0 K2 = 0 RESET Q3: J3 = (Q3 Q2 Q1 Q0) A B C . . . K3 = (Q3 Q2 Q1 Q0) A B C . . . 5. Clock 2 is inactive. October 22, 1993 PRESENT STATE SR 182 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 FUNCTIONAL DIAGRAM P63 I P0 15 I/CLK X2 J Q (4) K P R 4 4 J Q (4) K P R 4 4 Q J (4) 4 F K P R J Q 4 4 CK (4) K P R 4 F 4 4 INIT/OE October 22, 1993 183 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 LOGIC DIAGRAM DETAIL A I0 9 I1 8 19 INIT/OE I2 7 I3 6 I4 5 I5/CLK 4 I6 3 I7 2 I8 27 I9 26 I10 25 I11 24 I12 23 I13 22 I14 21 I15 20 DETAIL B DETAIL C 18 F0 17 F1 16 F2 15 F3 13 F4 12 F5 11 F6 10 F7 1 CLK NOTE: Denotes a programmable fuse location. October 22, 1993 DETAIL D 184 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 DETAILS FOR REGISTERS FOR PLUS405 STATE REGISTERS J 19 INIT/OE Q TO INIT LINE TO AND ARRAY Ps P K R CLK Detail A Detail B TO INIT LINE OUTPUT REGISTERS J Q FROM PIN 4 (I5/CLK) Fn FROM PIN 1 CLK P K R CLK Detail C Detail D COMPLEMENT ARRAY DETAIL P63 P62 P2 P1 P0 C0 C1 A B D E C1 C0 TO OR ARRAY The Complement Array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms. AND terms connected to it are active (High). If, however, all the connected terms are inactive (Low), which is a classic unknown state, the output of the Complement Array will be High. The concept is deceptively simple. If you subscribe to the theory that the expressions (/A * /B * /C) and (A + B + C) are equivalent, you will begin to see the value of this single term NOR array. Consider the Product Terms A, B and D that represent defined states. They are also connected to the input of the Complement Array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to Product Term E, which could be used in turn to reset the state machine to a known state. Without the Complement Array, one would have to generate product terms for The Complement Array is a single OR gate with inputs from the AND array. The output of the Complement Array is inverted and fed back to the AND array (NOR). The output of the array will be Low if any one or more of the October 22, 1993 185 all unknown or illegal states. With very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources. Note that the PLUS405 sequencers have 2 Complement Arrays which allow the user to design 2 independent Complement functions. This is particularly useful if 2 independent state machines have been implemented on one device. Note that use of the Complement Array adds an additional delay path through the device. Please refer to the AC Electrical Characteristics for details. Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER VCC Supply voltage VIN Input voltage THERMAL RATINGS RATINGS UNIT +7 VDC Maximum junction 150°C +5.5 VDC Maximum ambient 75°C Allowable thermal rise ambient to junction 75°C VOUT Output voltage +5.5 VDC IIN Input currents –30 to +30 mA IOUT Output currents +100 mA Tamb Operating temperature range 0 to +75 °C Tstg Storage temperature range –65 to +150 °C TEMPERATURE NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = MAX 2.0 TYP1 MAX UNIT Input voltage2 VIH High VIL Low VIC Clamp3 Output V VCC = MIN VCC = MIN, IIN = –12mA –0.8 0.8 V –1.2 V voltage2 VOH High VCC = MIN, IOH = –2mA 2.4 V VOL Low VCC = MIN, IOL = 9.6mA 0.35 0.45 V Input current IIH High VCC = MAX, VIN = VCC <1 30 µA IIL Low VCC = MAX, VIN = 0.45V –20 –250 µA VCC = MAX, VOUT = 2.7V 1 40 µA VCC = MAX, VOUT = 0.45V –1 –40 µA –70 mA 225 mA Output current IO(OFF) Hi-Z state 3, 4 IOS Short circuit ICC VCC supply current5 VOUT = 0V –15 VCC = MAX 190 VCC = 5.0V, VIN = 2.0V 8 pF VCC = 5.0V, VOUT = 2.0V 10 pF Capacitance CIN Input COUT Output NOTES: 1. All typical values are at VCC = 5V. Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Duration of short-circuit should not exceed one second. 5. ICC is measured with the INIT/OE input grounded, all other inputs at 4.5V and the outputs open. October 22, 1993 186 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 AC ELECTRICAL CHARACTERISTICS R1 = 470Ω, R2 = 1kΩ, CL = 30pF, 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER FROM TO MIN TYP1 MAX UNIT Pulse width tCKH1 Clock High; CLK1 (Pin 1) CK+ CK– 7.5 6 ns tCKL1 Clock Low; CLK1 (Pin 1) CK– CK+ 7.5 6 ns tCKP1 CLK1 Period CK+ CK+ 15 12 ns tCKH2 Clock High; CLK2 (Pin 4) CK+ CK– 7.5 6 ns tCKL2 Clock Low; CLK2 (Pin 4) CK– CK+ 7.5 6 ns tCKP2 CLK2 Period CK + CK + 15 12 ns tINITH Initialization pulse INIT– INIT+ 14 12 ns Setup time tIS1 Input Input ± CK+ 10 9 ns tIS2 Input (through Complement Array) Input ± CK+ 18 15 ns tVS Power-on preset VCC+ CK– 0 –10 ns tVCK Clock resume (after Initialization) INIT– CK– 0 –5 ns tNVCK Clock lockout (before Initialization) CK– INIT– 12 5 ns Input CK+ Input ± 0 –5 ns Hold time tIH Propagation delay tCKO1 Clock1 (Pin 1) CK1+ Output ± 6.5 8 ns tCKO2 Clock2 (Pin 4) CK2+ Output ± 7.0 8 ns 2 Output Enable OE– Output – 6.5 8 ns tOD2 Output Disable OE+ Output + 6.5 8 ns tINIT Initialization INIT+ Output + 12 18 ns tPPR Power-on Preset VCC + Output + 0 10 ns tOE Notes on following page October 22, 1993 187 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 AC ELECTRICAL CHARACTERISTICS (Continued) R1 = 470Ω, R2 = 1kΩ, CL = 30pF, 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS FROM TO MIN TYP1 Input ± Output ± 55.6 64.5 MHz Input ± Output ± 55.6 62.5 MHz Input through Complement Array ± Output ± 38.5 46.5 MHz Input through Complement Array ± Output ± 38.5 45.5 MHz Register Output ± Register Input ± 66.7 83.3 MHz Register Input ± 55.6 66.7 MHz t IS2 Register Output through Complement Array ± Minimum guaranteed Clock frequency CK + CK + 66.7 83.3 MHz SYMBOL PARAMETER MAX UNIT Frequency of operation CLK1; (without Complement Array) fMAX1 1 t IS1 t CKO1 CLK2; (without Complement Array) fMAX2 1 t IS1 t CKO2 CLK1; (with Complement Array) fMAX3 1 t IS2 t CKO1 CLK2; (with Complement Array) fMAX4 1 t IS2 t CKO2 Internal feedback without Complement Array (CLK1 or CLK2) fMAX5 1 t CKL t CKH Internal feedback with Complement Array (CLK1 or CLK2) fMAX6 fCLK 1 NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. All propagation delays and setup times are measured and specified under worst case conditions. TEST LOAD CIRCUIT VOLTAGE WAVEFORMS VCC +5V +3.0V S1 90% 10% C1 C2 0V R1 I0 F0 2.5ns tR tF 2.5ns +3.0V INPUTS I15 R2 DUT F7 CK 10% OUTPUTS INIT/OE GND 0V 2.5ns 2.5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. NOTE: C1 and C2 are to bypass VCC to GND. October 22, 1993 90% CL Input Pulses 188 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 TIMING DIAGRAMS +3V 1.5V I0 – I15 1.5V 0V tIH tIS +3V 1.5V CLK 1.5V 1.5V tIS tCKH 0V tCKL tCKP F0 – F7 VOH 1.5V 1.5V tCKO VOL tOD fMAX +3V 1.5V 1.5V OE 0V tOE Sequential Mode +3V I0 – I15 1.5V 0V +3V 1.5V CLK 1.5V 1.5V 1.5V 0V tIS tCKO tCKH tCKL VOH 1.5V F0 – F7 1.5V tINIT ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ tVCK INIT 1.5V 1.5V tNVCK VOL tCKO +3V 1.5V tINITH 0V Asynchronous Initialization +5V ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 4.5V VCC 0V tPPR F0 – F7 CLK VOH 1.5V 1.5V [Fn] = 1 [Fn] + 1 VOL tCKO +3V 1.5V 1.5V 1.5V 0V tCKH tVS fMAX I0 – I15 +3V 1.5V 1.5V 0V tIS Power-On Preset October 22, 1993 189 tIH Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 TIMING DIAGRAMS (Continued) +3V I0 – I11, I13 – I15 1.5V 0V +10V 8.0V 8.0V +3V I12 1.5V 1.5V 0V tIH tIS Q0 – Q7 +3V 1.5V CLK INTERNAL STATE REG. 1.5V ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ tCKH (NS) (PS) tSRE (Fn) F0 – F7 1.5V tCKO (Fn+1) 1.5V ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 0V VOH VOL tSRD (NS) VOH (Fn+1) 1.5V VOL OE 0V Diagnostic Mode – State Register Outputs ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 8.0V +10V 8.0V +3V I11 tRJS F0 – F7 (INPUTS) 1.5V (FORCED DIN) 1.5V CLK tIS +3V 1.5V tRH ( 0V tRJH 0V +3V 1.5V 0V tCKH QP STATE REG. VOH (DIN) VOL tCKO Diagnostic Mode – State Register Input Jam ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ) ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 8.0V +10V 8.0V +3V I10 tRJS F0 – F7 (INPUTS) 1.5V (FORCED DIN) 1.5V CLK tIS 0V +3V 1.5V 0V tCKH QF STATE REG. VOH (DIN) tCKO Diagnostic Mode – Output Register Input Jam October 22, 1993 +3V 1.5V tRH ( 0V tRJH 190 VOL Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 TIMING DEFINITIONS SYMBOL PARAMETER tCKH1, 2 Width of input clock pulse. tCKP1, 2 Minimum guaranteed clock period. tIS1 Required delay between beginning of valid input and positive transition of Clock. tCKO1, 2 tPPR tIS2 tRJH fMAX1, 2 Delay between positive transition of Clock and when Outputs become valid (with INIT/OE Low). SYMBOL PARAMETER SYMBOL fMAX6 Minimum guaranteed internal operating frequency with Complement Array, with internal feedback from state register through Complement Array, to state register. tINITH Width of initialization input pulse. tVS Required delay between VCC (after power-on) and negative transition of Clock preceding first reliable clock pulse. tOD Delay between beginning of Output Enable High and when Outputs are in the OFF-state. fCLK Minimum guaranteed clock frequency (register toggle frequency). PARAMETER tCKL1, 2 Interval between clock pulses. Delay between VCC (after power-on) and when Outputs become preset at “1”. tIH Required delay between positive transition of Clock and end of valid Input data. tINIT Required delay between beginning of valid Input and positive transition of Clock, when using optional Complement Array (two passes necessary through the AND Array). Delay between positive transition of Initialization and when Outputs become valid. tOE Delay between beginning of Output Enable Low and when Outputs become valid. tSRD Delay between input I12 transition to Logic mode and when the Outputs reflect the contents of the Output Register. tRH Required delay between positive transition of Clock and end of valid Input data when jamming data into State or Output Registers in diagnostic mode. tVCK Required delay between negative transition of Asynchronous Initialization and negative transition of Clock preceding first reliable clock pulse. Required delay between positive transition of clock, and return of input I10, I11 or I12 from Diagnostic Mode (10V). tSRE tRJS Minimum guaranteed operating frequency; input to output (CLK1 and CLK2). fMAX3, 4 Minimum guaranteed operating frequency; input through Complement Array, to output (CLK1 and CLK2). fMAX5 Minimum guaranteed internal operating frequency; with internal feedback from state register to state register. October 22, 1993 tNVCK Delay between input I12 transition to Diagnostic Mode and when the Outputs reflect the contents of the State Register. Required delay between inputs I11, I10 or I12 transition to Diagnostic Mode (10V), and when the output pins become available as inputs. Required delay between the negative transition of the clock and the negative transition of the Asynchronous Initialization to guarantee that the clock edge is not detected as a valid negative transition. 191 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) LOGIC PROGRAMMING PLUS405-55 INITIALIZATION/OE OPTION – (INIT/OE) The PLUS405-55 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL and CUPL design software packages also support the PLUS405-55 architecture. INIT/OE INIT/OE INIT INIT = 0 E=1 (ALWAYS ENABLED) All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. E (INITIALIZATION DISABLED) OPTION CODE OPTION CODE INITIALIZATION1 H OE L PROGRAMMING THE PLUS405: The PLUS405 has a power-up preset feature. This feature insures that the device will power-up in a known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state. PLUS405-55 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only. To implement the desired logic functions, each logic variable (I, B, P, S, T, etc.) from the logic equations is assigned a symbol. TRUE, COMPLEMENT, PRESET, RESET, OUTPUT ENABLE, INACTIVE, etc., symbols are defined below. INITIALIZATION OPTION – (INIT) P R P INIT R P INIT R P INIT R INIT ACTION CODE ACTION CODE ACTION CODE ACTION CODE INDETERMINATE4 O PRESET H RESET L INDETERMINATE4 – “AND” ARRAY – (I), (P) i, p I, P i, p i, p I, P I, P i, p i, p Tn i, p I, P i, p Tn i, p Tn Tn STATE CODE STATE CODE STATE CODE STATE CODE INACTIVE1, 2 O I, P H I, P L DON’T CARE – Notes are on next page. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 192 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 “OR” ARRAY – J-K FUNCTION – (N), (F) Tn Tn N, F J N, F K Q Tn N, F J N, F K Q Tn N, F J N, F K Q N, F J N, F K Q ACTION CODE ACTION CODE ACTION CODE ACTION CODE TOGGLE1, 6 O SET H RESET L NO CHANGE – “COMPLEMENT” ARRAY – (C) c c c c c Tn c c Tn c Tn ACTION CODE ACTION CODE ACTION INACTIVE1, 3 O GENERATE A PROPAGATE CLOCK OPTION – (CLK1/CLK2) CODE • Tn ACTION CODE TRANSPARENT – PROGRAMMING/SOFTWARE SUPPORT CLK2 CLK2 CLK1 CLK1 Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information. OPTION CODE OPTION CODE CLK1 ONLY1 L CLK1 and CLK2 5 H NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Tn will be unconditionally inhibited if any one of its I or P link pairs is left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn. 4. These states are not allowed when using INITIALIZATION option. 5. Input buffer I5 must be deleted from the AND array (i.e., all fuse locations “Don’t Care”) when using second clock option. 6. A single product term cannot drive more than 8 registers by itself when used in TOGGLE mode. October 22, 1993 193 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 PLUS405 PROGRAM TABLE AND OR INACTIVE 0 INACTIVE 0 I, P H GENERATE A I, P L DON’T CARE – Im, Ps PROPAGATE • TRANSPARENT – Cn OPTIONS INACTIVE OR TOGGLE 0 SET H RESET NO CHANGE INIT H OE L L CLK1 ONLY L – CLK1 AND 2 H INIT/OE Ns, Fr CLK1/ CLK2 INITIALIZATION/OUTPUT ENABLE CLOCK 1/2 CUSTOMER SYMBOLIZED PART # PROGRAM TABLE PHILIPS DEVICE # CUSTOMER NAME CF (XXXX) REV DATE AND COMP. INPUT (Im) PRESENT STATE (Ps) ARRAY C1 C0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 P7 P6 P5 P4 P3 P2 P1 P0 OR NEXT STATE (Ns) OUTPUT (Fr) N7 N6 N5 N4 N3 N2 N1 N0 F7 F6 F5 F4 F3 F2 F1 F0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 PIN NO. 2 0 2 1 2 2 2 2 3 4 2 5 2 2 6 7 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 5 1 6 1 7 PIN LABELS NOTES: 1. The device is shipped with all links initially intact. Thus, a background of “0” for all Terms, and an “H” for the IN/E and H for the clock option, exists in the table, shown BLANK instead for clarity. 2. Unused Cn Im, and Ps bits are normally programmed Don’t Care (—). 3. Unused Transition Terms can be left blank for future code modification, or programmed as (—) for maximum speed. October 22, 1993 194 1 8 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic sequencer (16 × 64 × 8) PLUS405-55 SNAP RESOURCE SUMMARY DESIGNATIONS P63 I P0 DIN405 NIN405 15 I/CLK DIN405 NIN405 AND NOR X2 JKFF405 Q J CK405 (4) K P R 4 4 J Q (4) K P R 4 CK405 4 J Q (4) 4 F K P R OUT405 4 4 J CK Q (4) K P R 4 F OUT405 4 4 INIT/OE October 22, 1993 195