32K x 32 SRAM MODULE PUMA 2S1000 - 020/025/35/45 Issue 4.4 : April 2001 Elm Road, West Chirton, North Shields, Tyne and Wear, NE29 8SE England, Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997 Description The PUMA 2S1000 is a 1Mbit high speed static RAM organised as 32K x 32 in a 66 pin ceramic PGA package. Access times of 20ns, 25ns, 35ns or 45ns are available. The device has a user configurable output width by 8 ,16 or 32 bits, and features a low power standby mode with 3.0V battery back-up capability. The package includes on board decoupling capacitors and is suitable for thermal ladder operations. It may be screened in accordance with MIL-STD-883. 1,048,576 bit CMOS High Speed Static RAM Features • Very Fast Access times of 20/25/35/45 ns. • User Configurable as 8 / 16 / 32 bit wide output. • Operating Power 1.6 W (max) 8 bit • Low Power Standby 44 mW (max) - L Version • Upgradeable Package. • Package Suitable for Thermal Ladder Applications. • On board decoupling capacitors. • Low voltage data retention. • May be screened in accordance with MIL-STD-883. Block Diagram Pin Definition A0~A14 OE WE4 WE3 WE2 WE1 32Kx8 SRAM 32Kx8 SRAM 32Kx8 SRAM 32Kx8 SRAM CS1 CS2 CS3 CS4 D0~D7 D8~D15 D16~D23 D24~D31 1 12 23 34 45 56 D8 2 WE2 13 D15 24 D24 35 VCC 46 D31 57 D9 3 D10 4 CS2 14 D14 25 CS4 47 D30 58 GND 15 D13 26 D25 36 D26 37 WE4 48 D29 59 A13 5 D11 16 D12 27 A6 38 D27 49 D28 60 A14 6 A10 17 OE 28 A7 39 A3 50 A0 61 NC 7 A11 18 NC 29 NC 40 A4 51 A1 62 NC 8 A12 19 WE1 30 A8 41 A5 52 A2 63 NC 9 VCC 20 D7 31 A9 42 WE3 53 D23 64 D0 10 CS1 21 D6 32 D16 43 CS3 54 D1 11 D2 NC 22 D5 33 D4 D17 44 D18 GND 55 D19 D22 65 D21 66 D20 D3 VIEW FROM ABOVE Pin Functions A0~A14 CS1~4 WE1~4 V CC Address Inputs Chip Select Write Enable Power (+5V) D0~D31 OE NC GND Data Inputs/Outputs Output Enable No Connect Ground ISSUE 4.4 : April 2001 PUMA 2S1000 - 25/35/45 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Voltage on any pin relative to VSS (2) VT -0.5V to +7.0 Power Dissipation PT 4 Storage Temperature V W o -65 to +150 TSTG C Notes : (1)Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Symbol min typ(1) max Unit Supply Voltage V CC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 - VCC+0.5 V Input Low Voltage VIL -0.5 - 0.8 Parameter Operating Temperature TA 0 - -40 TAI TAM - -55 - V 70 o 85 o (I suffixI) 125 o (M, MB suffix) C C C DC Electrical Characteristics (VCC=5V±10%,TA=-55°C to +125°C) Parameter Symbol I/P Leakage Current Test Condition min typ(1) max Unit ILI1 VIN=0V to VCC -8 - 8 µA ILO CS =VIH or OE=VIH,VI/O=0V to VCC,WE =VIL -8 - 8 µA Output Leakage Current 8 bit Average Supply Current 32 bit ICC32 CS =VIL, Min. cycle, II/O=0mA, 100% Duty. - - 660 mA 16 bit ICC16 As above - - 410 mA 8 bit ICC8 As above - - 285 mA TTL ISB CS =VIH, Min Cycle. - - 160 mA ISB2 CS ≥VCC-0.2V, 0.2V≥VIN≥VCC-0.2V - - 8 mA Output Voltage Low VOL IOL=8.0mA - - 0.4 V Output Voltage High VOH IOH=-4.0mA 2.4 - - V Standby Supply Current -L Version Notes: (2) (2) (2) (2) (2) CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be operated simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. Capacitance (VCC=5V±10%,TA=25°C) Parameter Input Capacitance I/O Capacitance: Symbol CIN CI/O Test Condition VIN =0V VI/O=0V Note:This parameter is calculated and not measured. 2 typ max Unit - 38 18 pF pF PUMA 2S1000 - 25/35/45 ISSUE 4.4 : April 2001 Operating Modes The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the PUMA 2S1000. Mode CS OE WE Not Selected 1 X X ISB,ISB1,ISB2 High Z OutputDisable 0 1 1 ICC High Z Read 0 0 1 ICC DOUT Read Cycle Write 0 X 0 ICC DIN Write Cycle 1 = VIH, 0 = VIL, VCC Current I/O Pin Reference Cycle Power Down X = Don't Care Note: CS is accessed through CS1~4, and WE is accessed through WE1~4. For correct operation, CS1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation. WE1~4 must also be operated in the same manner. Low Vcc Data Retention Characteristics - L Version Only (VCC = 5.0V±10%, TA=-55°C to +125°C) Parameter Symbol Test Condition min typ max Unit 2.0 - 5.5 V VCC for Data Retention VDR CS≥VCC-0.2V, VIN≥0V Data Retention Current ICCDR1 VCC=2.0V, CS≥VCC-0.2V, VIN≥0V - - 8 mA As above - - 1.2 mA -L Version ICCDR2 Chip Deselect to Data Retention Time t CDR See Retention Waveform 0 - - ns Operation Recovery Time tR See Retention Waveform t RC - - ns Note: CS above is accessed through CS1~4. AC Test Conditions Output Load * Input pulse levels: 0V to 3.0V * Input rise and fall times: 3ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * Vcc=5V±10% I/O Pin 166 Ω 1.76V 30pF 3 ISSUE 4.4 : April 2001 PUMA 2S1000 - 25/35/45 AC OPERATING CONDITIONS Read Cycle Parameter Symbol 20 min max Read Cycle Time tRC 20 - Address Access Time tAA - 20 Chip Select Access Time tACS - Output Enable to Output Valid tOE Output Hold from Address Change Chip Selection to Output in Low Z Output Disable to Output in High Z (3) min 35 max min 45 max Unit 35 - 45 - ns - 25 - 35 - 45 ns 20 - 25 - 35 - 45 ns - 9 - 12 - 15 - 20 ns tOH 3 - 5 - 5 - 5 - ns tCLZ 3 - 6 - 6 - 6 - ns tOLZ 0 - 0 - 0 - 0 - ns tCHZ 0 8 0 12 0 15 0 20 ns tOHZ 0 8 0 12 0 15 0 20 ns min 35 max min max Unit (3) 25 25 max - Output Enable to Output in Low Z Chip Deselection to Output in High Z min Write Cycle Parameter Symbol 20 min max min 25 max 45 Write Cycle Time tWC 20 - 25 - 35 - 45 - ns Chip Selection to End of Write tCW 13 - 20 - 30 - 40 - ns Address Valid to End of Write tAW 13 - 20 - 30 - 40 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 13 - 15 - 20 - 25 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Write to Output in High Z tWHZ 0 8 0 15 0 18 0 20 ns Data to Write Time Overlap tDW 10 - 20 - 20 - 20 - ns Data Hold from Write Time tDH 0 - 0 - 0 - 0 - ns Output Active from End of Write tOW 0 - 5 - 5 - 5 - ns Consult factory 4 PUMA 2S1000 - 25/35/45 ISSUE 4.4 : April 2001 Read Cycle 1 Timing Waveform (1) t RC Address t AA OE t OE t OH t OLZ t CLZ CS1~4 t ACS t CHZ(3) t OHZ(3) High-Z Dout Read Cycle 2 Timing Waveform Data Valid (1) (2) (4) t RC Address t AA t t OH Dout OH Data Valid Notes: (1) WE1~4 is High for Read Cycle. (2) Device is continuously selected, CS1~4=VIL. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. (4) OE=VIL. 5 ISSUE 4.4 : April 2001 PUMA 2S1000 - 25/35/45 Write Cycle No.1 Timing Waveform t WC Address t AS(3) OE t AW tWR t CW(4) (2) (6) CS1~4 t WP(1) WE1~4 t OHZ(3,9) t OW High-Z Dout t DW High-Z Din Write Cycle No.2 Timing Waveform t DH Data Valid (5) t WC Address t CW C S 1~4 (4) (6) t AW t WR(2) t WP(1) W E1 ~4 t AS(3) t OH t WHZ(3,9) t OW D out t DW D in (8) High-Z High-Z Data Valid 6 tDH (7) PUMA 2S1000 - 25/35/45 ISSUE 4.4 : April 2001 Data Retention Waveform DATA RETENTION MODE Vcc 4.5V 4.5V tCDR tR 2.2V VDR CS1~4 0V CS1~4>Vcc-0.2V AC Write Characteristics Notes (1) (2) (3) (4) (5) (6) (7) (8) (9) A write occurs during the overlap (tWP) of a low CS and a low WE. tWR is measured from the earlier of CS or WE going high to the end of write cycle. During this period, I/O pins are in the output state. Input signals out of phase must not be applied. If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain in a high impedance state. OE is continuously low. (OE=VIL) Dout is in the same phase as written data of this write cycle. Dout is the read data of next address. If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied to I/O pins. tWHZ and tOHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage levels. This parameter is sampled and not 100% tested. CS and WE above refer to CS1~4 and WE1~4 respectively. 7 ISSUE 4.4 : April 2001 PUMA 2S1000 - 25/35/45 PACKAGE DETAILS 66 Pin Ceramic PGA 27.55 (1.085) square 27.05 (1.065) square 4.83 (0.190) 4.32 (0.170) 2.54 (0.100) typ. 15.24 (0.60) typ 0.51 (0.020) 0.38 (0.015) 1.40 (0.055) 2.54 (0.100) typ. 1.14 (0.045) 1.27 (0.050) 0.64 (0.025) 8.13 (0.320) max 1.52 (0.060) 1.02 (0.040) Dimensions in mm (inches) SCREENING Military Screening Procedure Module Screening Flow for high reliability product is in accordance with Mil-883 method 5004 . MB MODULE SCREENING FLOW SCREEN TEST METHOD LEVEL Visual and Mechanical External visual Temperature cycle 2017 Condition B or manufacturers equivalent 1010 Condition C (10 Cycles, -65oC to +150oC) 100% 100% Per applicable Device Specifications at TA=+25oC TA=+125oC,160hrs minimum. 100% 100% Burn-In Pre-Burn-in electrical Burn-in Final Electrical Tests Per applicable Device Specification Static (DC) a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Functional a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Switching (AC) a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Percent Defective allowable (PDA) Calculated at Post Burn-in at TA=+25oC Quality Conformance Per applicable Device Specification External Visual 2009 Per vendor or customer specification 8 10% Sample 100% PUMA 2S1000 - 25/35/45 ISSUE 4.4 : April 2001 ORDERING INFORMATION PUMA 2S1000LMB - 35 Speed 020 025 35 45 Temp. range/screening = = = = 20 ns 25 ns 35 ns 45 ns Blank = Commercial Temperature. I = Industrial Temperature. M = Military Temperature. MB = Screened in accordance with MIL-STD-883. Power Consumption Memory Organisation Memory Technology Package Blank = Standard Part. L = Low Power Part. 1000 = 32K x 32, configurable as 64K x 16 and 128K x 8 S = Static RAM. PUMA 2 = 66 pin Ceramic PGA. Note : Although this data is believed to be accurate, the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 9