Data Sheet RAA207703GBM/7704GBM/7705GBM R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Synchronous Buck Regulator with Internal Power MOSFETs Description The RAA207703GBM is monolithic synchronous buck regulator with power MOSFETs in extremely small package. The RAA207703GBM delivers high output current by small Rds(on) Power MOSFETs. Constant on time control architecture provides fast transient response, and minimize external components. The RAA207703GBM operates skip mode at light load, it provides high efficiency in all load condition. The RAA207703GBM incorporates internal 5V LDO, so the regulator can operates single power supply. Three current ability products can be selected. Features · · · · · · · · · · · · · · · · Input voltage range: 5.5 V to 16 V (internal LDO use), 3.0 V to 16 V (external 5 V use) Output voltage range: 0.8 V to 5.0 V Constant-On-Time control Built-in power MOSFETs suitable for PC, Server application Internal 5 V LDO for single power supply operation 5 V LDO / external 5 V input selectable (LDO remote ON/OFF) Switching frequency: Adjustable up to 2 MHz High average output current, up to 15 A (7703GBM), 10 A (7704GBM), 5 A (7705GBM) Controllable driver: Remote ON/OFF Power Good function Over current protection/Over voltage protection/Thermal shutdown function Built-in bootstrapping diode Soft Start period adjustable Enhanced light load mode function for higher efficiency Extremely small chip size package with solder bump Pb-Free/Halogen-Free Application Circuit VIN V5_OUT SET BOOT VIN AVIN ON/OFF SS RAA207703GBM RAA207704GBM SW RAA207705GBM Vout PGOOD FB LDO_EN# PGND SGND R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 1 of 23 RAA207703GBM/7704GBM/7705GBM Pin Arrangement Top View <RAA207703GBM> <RAA207704GBM> 1 2 3 4 5 V5_ OUT SGND FB LDO_ EN# AVIN BOOT SET PGO OD SS SW VIN VIN SW SW SW <RAA207705GBM> 1 2 3 4 5 1 2 3 4 5 A V5_ OUT SGND FB LDO_ EN# AVIN A V5_ OUT SGND FB LDO_ EN# AVIN A ON/ OFF B BOOT SET PGO OD SS ON/ OFF B BOOT SET PGO OD SS ON/ OFF B VIN VIN C SW VIN VIN VIN VIN C SW SW VIN VIN VIN C SW SW VIN D SW SW SW SW VIN D SW SW PGND PGND PGND D PGND PGND PGND PGND E SW PGND PGND PGND PGND E SW SW SW PGND PGND F SW SW SW PGND PGND F SW PGND PGND PGND PGND G Bottom View <RAA207703GBM> <RAA207704GBM> 5 4 3 2 1 AVIN LDO_ EN# FB SGND V5_ OUT ON/ OFF SS PGO OD SET VIN VIN VIN VIN SW PGND <RAA207705GBM> 5 4 3 2 1 A AVIN LDO_ EN# FB SGND V5_ OUT BOOT B ON/ OFF SS PGO OD SET VIN SW C VIN VIN VIN SW SW SW D VIN SW PGND PGND PGND SW E PGND PGND PGND SW SW SW F PGND PGND PGND PGND PGND SW G CSP 35-pin package 2.67 mm × 3.87 mm R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 5 4 3 2 1 A AVIN LDO_ EN# FB SGND V5_ OUT A BOOT B ON/ OFF SS PGO OD SET BOOT B VIN SW C VIN VIN VIN SW SW C SW SW SW D PGND PGND PGND SW SW D PGND PGND PGND SW E PGND SW SW SW F CSP 30-pin package 2.67 mm × 3.37 mm CSP 20-pin package 2.67 mm × 2.37 mm Page 2 of 23 RAA207703GBM/7704GBM/7705GBM Pin Description Pin Name Pin No. Description Remarks V5_OUT SGND 1A 2A Controller voltage Controller analog GND FB LDO_EN# 3A 4A Feedback voltage input pin Internal 5 V LDO enable pin AVIN BOOT 5A 1B Analog input voltage Bootstrap voltage pin Should be connected to VIN on PCB pattern To be supplied +5 V through integrated SBD SET PGOOD 2B 3B Constant on time program pin Power good indicator pin Tie resistor between SW and SET pin Pull low when No Good (open drain output) SS ON/OFF 4B 5B Soft start period program pin Operation enable pin Tie capacitor between SS and SGND Operation stop when "L" signal asserted VIN SW — — Input voltage Switching node — Power GND PGND Note: Controller supply (5 V regulator output) Should be connected to PGND on PCB pattern Should be connected to SGND on PCB pattern Pin assign of 1A-5A & 1B-5B is common through RAA207703GBM, RAA207704GBM and RAA207705GBM. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 3 of 23 RAA207703GBM/7704GBM/7705GBM Block Diagram V5_OUT AVIN VIN Enable ON/OFF 1M 5V LDO TSD LDO_EN# TSD 1M UVLO 4.3 V SET BOOT UVLO 2.5 mA Ripple Comparator 0.8 V + + – SS Enable UVLO Fault 1.0 V – OCP OCP 1 shot timer OVP + FB 0.72 V – Control Logic UVLO + ZCD Enable PGOOD TSD delay – + V5_OUT Fault Protection Function SW ZCD Comparator Fault OVP PGND TSD OCP OVP SGND 1. Truth table for the ON/OFF pin ON/OFF Input Driver Chip Status 2. Truth table for LDO_EN# pin LDO_EN# Input 5 V Regulator Status "L" "Open" Shutdown (operation STOP) Shutdown (operation STOP) "L" "Open" LDO enable LDO enable "H" Enable (Normal operation) "H" LDO disable R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 4 of 23 RAA207703GBM/7704GBM/7705GBM Absolute Maximum Ratings (Ta = 25°C) Item Input voltage Symbol VIN, AVIN Switch node voltage BOOT voltage SW VBOOT 20(DC), 23(<10 ns) 25(DC), 28(<10 ns) V V 1 1, 2 Controller voltage V5_OUT current V5_OUT ICC –0.3 to +6 –20 to +0.1 V mA 1 3 FB pin voltage ON/OFF voltage VFB VON/OFF –0.3 to V5_OUT +0.3 –0.3 to VIN V V 1, 4 1 LDO_EN# voltage SET voltage VLDO_EN# VSET –0.3 to VIN –0.3 to VIN V V 1 1 PGOOD voltage PGOOD sink current VPGOOD IPGOOD –0.3 to VIN +2 V mA 1 3 Operating junction temperature Storage temperature Tj-opr Tstg –40 to +125 –55 to +150 °C °C Notes: 1. 2. 3. 4. Ratings –0.3 to +20 Unit V Notes 1 Rated voltages are relative to voltages on the SGND and PGND pins. BOOT – V5_OUT < 20 V For rated current, (+) indicates inflow to the chip and (–) indicates outflow. V5_OUT + 0.3 V < 6 V Thermal Information Item Thermal resistance (junction to air when device is mounted on evaluation board) Note: Symbol qj-a Part No. Value Unit Note RAA207703GBM RAA207704GBM 27 33 °C/W 1 RAA207705GBM 39 1. Not assured value, just reference for design. Above data is taken using Renesas's reference board. Recommended Operating Condition Item Input voltage Symbol VIN Ratings 3.0 to 16 Unit V Analog input voltage Controller voltage AVIN V5_OUT 4.5 to 16 4.5 to 5.5 V V Continuous output current IOUT 0 to 15 0 to 10 0 to 5 A R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Remarks When V5_OUT is supplied externally 15 A: RAA207703GBM 10 A: RAA207704GBM 5 A: RAA207705GBM Page 5 of 23 RAA207703GBM/7704GBM/7705GBM Electrical Characteristics (Ta = 25°C, VIN = 12 V, unless otherwise specified) Item Supply Remote ON/OFF 5 V LDO enable Symbol Min Typ Max Unit Test Conditions AVIN start threshold VH — 4.3 4.5 V AVIN shutdown threshold in CCM VL 3.6 3.8 — V AVIN shutdown threshold in ELL mode VLDCM — 3.0 3.6 V In ELL mode (DCM, fSW < 100 kHz) AVIN quiescent current Iq — 400 550 mA Output = no load, ELL mode AVIN disable current (LDO_EN# = 12 V) IIAIN-DISBL1 — 70 150 mA ON/OFF = 0 V, LDO_EN# = 12 V VIN disable current (LDO_EN# = 0 V) IIAIN-DISBL2 — 130 200 mA ON/OFF = 0 V, LDO_EN# = 0 V AVIN operating current (RAA207703GBM) ICIN — 40 — mA fSW = 1 MHz, ton = 200 ns AVIN operating current (RAA207704GBM) ICIN — 35 — mA AVIN operating current (RAA207705GBM) ICIN — 20 — mA VIN disable current IIIN-DISBL1 — — 5 mA ON/OFF = 0 V 3.3 / 5.0 V interface Disable level VDISBL — — 0.6 V Enable level VENBL 2.0 — — V Pull-down resistance RDISBL 0.7 1 1.3 MW ON/OFF = 1 V 5 V LDO on level VLDO_ON — — 0.6 V 5 V LDO off level VLDO_OFF 2.0 — — V Pull-down resistance RLDO 0.7 1 1.3 MW 5 V LDO output 5 V LDO output voltage VLDO 4.5 5.0 5.5 V FB Comparator threshold voltage VFB_COMP 792 800 808 mV FB input current IFB_IN –0.1 0 +0.1 mA FB = 1 V 1shot timer High MOSFET on pulse width PW 170 210 250 ns VIN = 12 V, Rset = 30 kW High MOSFET minimum on pulse width PMIN_ON — 70 — ns High MOSFET minimum off pulse PMIN_OFF — 50 — ns LDO_EN# = 1 V at no load Power good indicator Rising threshold on FB VPG_rise 0.67 0.72 0.77 V Power good falling hysteresis dVPG — 50 — mV Power good resistance RPG 0.25 0.5 1 kW Soft start Soft start bias current ISS 1.8 2.5 3.3 mA Over voltage protection OVP trip voltage on FB VOVP 0.95 1.00 1.05 V Over current protection OCP trip current (RAA207703GBM) IOCP 16.0 20.0 24.0 A Fixed internally, inductor peak current *1 OCP trip current (RAA207704GBM) IOCP 11.5 14.0 17.0 A Fixed internally, inductor peak current *1 OCP trip current (RAA207705GBM) IOCP 6.4 8.0 9.6 A Fixed internally, inductor peak current *1 TSD trip temperature TTSD 130 150 — °C *1 Temperature hysteresis Thys — 15 — °C *1 Over temperature protection Note: FB = 0 V * 1 Not directly tested. Assured by related characteristics test. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 6 of 23 RAA207703GBM/7704GBM/7705GBM Efficiency Performance (VIN = 12 V, L = 1 mH, fsw = 500 kHz (at CCM) no airflow, unless otherwise specified) RAA207703GBM Efficiency - Output Current (Light Load) RAA207703GBM Efficiency - Output Current (Heavy Load) 98 100 Vout = 5.0V 90 80 70 60 50 40 88 86 84 82 80 78 0.01 0.1 0 1 3 6 9 12 15 Iout (A) Iout (A) RAA207704GBM Efficiency - Output Current (Light Load) RAA207704GBM Efficiency - Output Current (Heavy Load) 98 Vout = 3.3V 90 Vout = 5.0V 94 Efficiency (%) Vout = 1.5V V Vout = 1.2 V Vout = 1.0 70 60 50 40 92 Vout = 1.8 V Vout = 1.5 V 90 Vou t=1 .2V Vou t= 1.0V 88 86 84 30 82 20 80 10 0.001 Vout = 5.0V Vout = 3.3 V 96 Vout = 1.8V 80 78 0.01 0.1 0 1 2 4 6 8 10 Iout (A) Iout (A) RAA207705GBM Efficiency - Output Current (Light Load) RAA207705GBM Efficiency - Output Current (Heavy Load) 100 Vout = 1.8V Vout = 3.3V 98 Vout = 5.0V 90 96 80 94 Vout = 1.0V 70 60 Efficiency (%) Efficiency (%) Vou t= 1.8V Vou t= 1.5 V Vo ut =1 .2V Vo ut =1 .0V 90 20 100 Efficiency (%) 92 30 10 0.001 Vout = 5.0V Vout = 3.3 V 94 Vout = 1.5V V Vout = 1.2 V Vout = 1.0 Efficiency (%) Efficiency (%) 96 Vout = 3.3V Vout = 1.8V Vout = 1.2V Vout = 1.5V 50 40 Vout = 3.3V 92 Vout = 1.8V Vout = 1.5V 90 88 Vout = 1.2 V Vout = 1.0 V 86 84 30 82 20 80 10 0.001 Vout = 5.0V 78 0.01 0.1 Iout (A) R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 1 0 1 2 3 4 5 Iout (A) Page 7 of 23 RAA207703GBM/7704GBM/7705GBM Operating Performance (RAA207703GBM, VIN = 12 V, Vout = 1.2 V, L = 0.42 mH, Cout = 5 ´ 47 mF, ton = 130 ns, unless otherwise specified) Load Regulation Characteristics Line Regulation Characteristics 1.220 1.220 1.215 1.215 1.210 1.210 Iout = 1A 1.205 Vout (V) Vout (V) VIN = 16V VIN = 12V 1.200 1.195 VIN = 5V 1.205 Iout = 15A 1.200 Iout = 0A 1.195 1.190 1.190 1.185 1.185 1.180 1.180 0 2 4 6 8 10 12 14 6 16 8 10 14 12 Iout (A) VIN (V) Switching Frequency - Load Characteristics FB Voltage - Temperature Characteristics 1200 16 820 815 1000 FB Voltage (V) 810 fsw (kHz) 800 600 400 805 800 795 790 200 785 0 0 2 4 6 8 Iout (A) R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 10 12 14 16 780 –50 –25 0 25 50 75 100 125 Temperature (°C) Page 8 of 23 RAA207703GBM/7704GBM/7705GBM Operating Waveform (RAA207703GBM, VIN = 12 V, Vout = 1.2 V, L = 0.42 mH, Cout = 5 ´ 47 mF, ton = 130 ns, unless otherwise specified) Typical Operation at Full Load Typical Operation at No Load IL: 5A/div. IL: 5A/div. Vout: 20mV/div. Vout: 20mV/div. SW: 10V/div. SW: 10V/div. 400ns/div. 400ns/div. Soft-start at Full Load Soft-start at No Load IL: 5A/div. IL: 5A/div. PGOOD: 5V/div. PGOOD: 5V/div. Vout: 1V/div. Vout: 1V/div. ON/OFF: 5V/div. ON/OFF: 5V/div. 400ms/div. 400ms/div. Soft-discharge Shutdown Load Transient (0 A to 10 A) IL: 5A/div. PGOOD: 5V/div. IL: 5A/div. Vout: 1V/div. Vout: 50mV/div. ON/OFF: 5V/div. 1ms/div. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 200ms/div. Page 9 of 23 RAA207703GBM/7704GBM/7705GBM Description of Operation The RAA207703GBM operates as voltage-ripple based constant on time control architecture. Converter output is controlled by output voltage ripple which is determined by inductor ripple current and ESR & ESL of output capacitor. Each switching cycle starts High-side MOSFET turn on which time is decided by 1 shot timer. After High-side MOSFET turns off, Low side turns on, and it keeps until FB voltage becomes lower than reference voltage. In light load condition, Low-side MOSFET on time is decided by inductor zero current. Switching Frequency, Constant on Time Setting Rset SET SW Switching Frequency in CCM mode is determined by following equation. Switching Frequency: (Vout / VIN) • (1 / ton) [Hz] ¼(1) Here, ton is High-side MOSFET on time, and it is determined by following equation. On time pulse: (50 pF • 1 V / (VIN – 2.0 V)) • Rset + 60 ns [s] ¼(2) From above equation, constant on time is change depend on VIN, so switching frequency is almost constant when VIN change. This architecture is suitable for battery application. From the above equation, Rset is calculated by Rset: (Vout / (VIN • Fsw) – 60 ns) • (VIN – 2.0 V) / (50 pF • 1 V) [W] ¼(3) Here, Fsw is switching frequency. 1000 1300 VIN = 5 V 900 Rset = 30 kW 1100 VIN = 12 V Rset = 10 kW 1000 700 On Time [ns] On Time [ns] 800 Rset = 51 kW 1200 VIN = 8.5 V 600 500 400 900 800 700 600 500 400 300 300 200 100 10 200 100 20 30 40 50 60 Rset [kW] 70 80 90 100 4 6 8 10 12 14 16 VIN [V] Minimum on time is 70 ns (typ.), so recommended on time pulse is more than 100 ns. Maximum operating frequency is restricted by minimum on time and minimum off time (50 ns, please see next chapter). R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 10 of 23 RAA207703GBM/7704GBM/7705GBM Maximum Duty Cycle Operation Maximum duty cycle is restricted by following equation. Max. duty: 1 – (50 ns • Fsw) ¼(4) Here, 50 ns means High-side minimum off time. If FB voltage does not reach reference voltage after the High-side MOSFET turn on time is expired, Low-side MOSFET turns on 50 ns, and next switching cycle starts. Especially, this condition occurs when output load transient state. SW 50 ns IL (inductor current) Soft Start SS SGND Css Soft start ramp period is adjustable by external capacitor (Css) selection. When converter start operating, 2.5 mA current from SS pin charges capacitor between SS and GND. Soft start period is determined by following equation. Soft Start period: Css • 0.8 V / 2.5 mA [s] ¼(5) Here, 0.8 V is internal reference voltage Vref. IC operates diode emulation mode at Soft start period, so it can prevent from reverse current when pre-bias condition. Soft start restarts when Enable signal re-entered, and after OCP, OVP, TSD, UVL release condition. Power Good Indicator Power good indicator is useful for controlling multi-converter systems for sequential start up and shut down. FB voltage is monitored continuously by power good comparator. The power good comparator compares FB pin and 90% internal reference voltage (0.72 V). When FB reaches reference voltage, PGOOD pin becomes high impedance after internal delay (30% of soft start period). Under the fault condition (UVLO, OVP, OCP, TSD), PGOOD pin is pulled low. 0.80 V 0.72 V SS FB Vout PGOOD Soft start period Power Good delay (30% soft start period) Note: PGOOD pin is connected V5_OUT through resistor. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 11 of 23 RAA207703GBM/7704GBM/7705GBM Over Voltage Protection (OVP) When FB voltage exceeds 125% of reference voltage (1.00 V), switching stops immediately and latched Low-side MOSFET on state in order to pull the output voltage. To leave the OVP condition, V5_OUT needs to be pulled under the UVLO level, and re-enter the signal. 125% Vref FB High MOSFET signal Low MOSFET signal V5_OUT delay PGOOD Note: PGOOD pin is connected V5_OUT through resistor. Over Current Protection (OCP) OCP detection circuit monitors High-side MOSFET drain-source current. When the current exceeds fixed level four times, IC starts hiccup operation. In the hiccup operation, switching stops and operate 1 ms timer. After 1 ms timer is expired, IC operates again from soft start state. If IC detect OCP in the soft start circuit, hiccup operation start again. PGOOD SS OCP detect OCP level IL 0A SW 1 ms wait 1 ms wait Note: PGOOD pin is connected V5_OUT through resistor. Thermal Shutdown (TSD) Thermal sensor monitors junction temperature of IC. When junction temperature exceeds 150°C, switching stops. After junction temperature become 135°C, IC restart switching from soft start (Non-latched function). Enhanced Light Load Function (ELL) IC operates diode emulation mode in light load condition. To enhance light load efficiency, IC detects light load condition automatically, and operate as Enhanced Light Load mode (ELL). In ELL mode, bias current of IC becomes small, so this function can improve the efficiency. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 12 of 23 RAA207703GBM/7704GBM/7705GBM Start-up Sequence for External 5 V Use When LDO function is used, start-up sequence is free. However, it needs specific start-up sequence when LDO function is not used. Please set start-up sequence from following. IC cannot start-up when "V5_OUT & ON/OFF rise first, VIN rises secondly" sequence. (1) VIN to V5_OUT (ON/OFF is pulled up to V5_OUT) VIN 4.3 V V5_OUT (ON/OFF) Vout Soft start period (2) VIN or V5_OUT to ON/OFF (ON/OFF = "H" asserted after VIN & V5_OUT rise) VIN (or V5_OUT) V5_OUT (or VIN) ON/OFF Vout Soft start period Note: VIN, V5_OUT sequence does not matter in this start-up. ON/OFF Pin Slew Rate Restriction When ON/OFF pin is driven by another controller, the slew rate of H to L transition must be higher than –5 V/ms monotonically (must be rapid transition). If the slew rate is lower than –5 V/ms (slow transition), switching noise affect ON/OFF pin input circuit and lead to malfunction in case of heavy load state. Recommended drive impedance of ON/OFF pin is less than 10 kW. If ON/OFF pin is always pulled up to V5_OUT or VIN via resistance, slew rate is not a matter. 5V more than –5V/ms 5V V5_OUT ON/OFF Slew rate restriction: ON/OFF is controlled externally R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 V5_OUT ON/OFF No slew rate restriction: ON/OFF is connected via resistance Page 13 of 23 RAA207703GBM/7704GBM/7705GBM Controller Power Supply The RAA207703GBM incorporates internal 5 V LDO, so it can operate with single power supply. LDO_EN# can control LDO operation, and select the controller power supply from LDO or V5_OUT pin. When LDO_EN# = H state, external 5 V should be applied to V5_OUT pin and AVIN pin. Typical pin connection of each operation are below. VIN V5_OUT AVIN 5V VIN VIN V5_OUT LDO_EN# AVIN VIN LDO_EN# Operation with single power supply Operation with multi power supply Note: Truth table for LDO_EN# pin LDO_EN# Input "L" 5 V Regulator Status LDO enable "Open" "H" LDO enable LDO disable Stability Criteria, Output Voltage Setting for High ESR Output Capacitor Small output ripple voltage makes control loop unstable in constant on time architecture. Ripple voltage needs to be larger than 15 mV on FB pin. When using high ESR (>50 mW) capacitor such as Electrolytic capacitor, Polymer aluminum capacitor for output capacitor, ripple voltage on FB pin will be more than 15 mV. VIN Lout Vout SW FB R1 ESR R2 Cout Stability criteria From loop stability analysis, constant on time control system must satisfy below equation. Stability criteria: ESR • Cout > ton / 2 ¼(6) Here, ton is constant on time. If the system cannot satisfy above equation, subharmonic oscillation will occur. Vout setting FB comparator compares FB voltage and internal accurate reference voltage (0.8 V). Feedback loop controls FB voltage to match the reference voltage. However, Vout ripple voltage affects FB voltage. So, effective FB pin voltage Vfb will be below. (Here, Vout ripple from bulk capacitance is ignored) Effective FB voltage (Vfb): 0.8 V + ½ ((VIN – Vout) • ton • ESR • R2 / (Lout • (R1 + R2))) [V] ¼(7) Here, R1 and R2 is output voltage divider resistor, Lout is inductance of output filter and ESR means ESR of output capacitor (refer to above figure). 0.8 V in above equation means reference voltage of IC. Considering Vout ripple voltage, Vout voltage becomes below equation. Vout: Vfb • (R1 + R2) / R2 [V] ¼(8) R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 14 of 23 RAA207703GBM/7704GBM/7705GBM Operating with Small ESR Output Capacitor When using low-ESR output capacitor like MLCC, voltage ripple on output voltage node is very small. So, voltage ripple needs to be enhanced by additional components. Recommended ripple enhance method is like below figure. VIN Lout Vout SW FB Rf Cf R1 ESR(<5mW) R2 Cout Cr Ripple injection on FB pin Rf and Cf make ripple voltage using inductor DCR ripple. Cr is used for AC ripple injection to FB pin. Ripple voltage between Rf and Cf is described by following equation. Vripple: (VIN – Vout) • ton / (Rf • Cf) [V] ¼(9) Rf: (VIN – Vout) • ton / (Vripple • Cf) [V] ¼(10) Recommended ripple voltage is between 15 mV and 20 mV. Stability criteria To keep voltage ripple amplitude on FB pin, below equation should be satisfied. Stability criteria(1): 1 / (2p • Cf • Fsw) << 1 / (2p • Cr • Fsw) << R1 • R2 / (R1 + R2) ¼(11) Here, Fsw means switching frequency at CCM mode. Recommended value for Cf = 0.01 mF, and Cr = 1000 pF. R1 and R2 are recommended between 10 kW and 100 kW. From loop stability analysis of above circuit configuration, the system must satisfy below equation. Stability criteria(2): Lout • Cout / (Rf • Cf) > ton / 2 ¼(12) If the system cannot satisfy above equation, subharmonic oscillation will occur. Capacitance - voltage dependence is must be considered when MLCC use. Vout setting Additional ripple voltage and ESR voltage ripple also affects Vout accuracy. From above figure, total ripple voltage on FB pin is described by below equation. Ripple voltage on FB pin: (VIN – Vout) • ton / (Rf • Cf) + (VIN – Vout) • ton • ESR / (Lout) [V] ¼(13) Effective FB pin voltage is described by below equation. Effective FB voltage (Vfb): 0.8 V + ½ ((VIN – Vout) • ton / (Rf • Cf) + (VIN – Vout) • ton • ESR / (Lout)) [V] ¼(14) So, actual Vout voltage is described by below equation. Vout: Vfb • (R1 + R2) / R2 [V] ¼(15) R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 15 of 23 RAA207703GBM/7704GBM/7705GBM BOOT Resistance 0.1m/25V BOOT Rboot SW SW node spike occurs when IC is operating. Turn-on spike voltage exceeds absolute maximum voltage of SW pin depends on operating condition. To suppress the spike voltage, adding boot resistor (Rboot) is effective. Recommended Rboot is below. Recommended Rboot Part No. RAA207703GBM RAA207704GBM RAA207705GBM R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 VIN = 12 V 3.9 W VIN = 5 V 0W 2.0 W 0W 0W 0W Page 16 of 23 RAA207703GBM/7704GBM/7705GBM Design Example (VIN = 12 V, Vout = 1.2 V, Fsw = 500 kHz (at CCM), L = 0.47 mH) ON/OFF C3 C1 C2 R4 30k R5 3.9 3300p/10V 51k 1m/10V R3 C4 13k 15k 22m/6.3V 22m/6.3V 22m/6.3V 22m/6.3V C113 C114 C115 22m/6.3V C112 C111 R1 0.01m/25V 27k R6 C5 B1 B2 B3 B4 B5 C1 D1 D2 D3 D4 E1 F1 F2 F3 G1 R2 10m/16V C103 RAA207703GBM SW_C1 SW_D1 SW_D2 SW_D3 SW_D4 SW_E1 SW_F1 SW_F2 SW_F3 SW_G1 1000p/25V 10m/16V C102 VIN_C2 VIN_C3 VIN_C4 VIN_C5 VIN_D5 PGND_E2 PGND_E3 PGND_E4 PGND_E5 PGND_F4 PGND_F5 PGND_G2 PGND_G3 PGND_G4 PGND_G5 10m/16V C101 C2 C3 C4 C5 D5 Vout L1 0.47mH E2 E3 E4 E5 F4 F5 G2 G3 G4 G5 +12V BOOT SET PGOOD SS ON/OFF V5_OUT SGND FB LDO_EN# AVIN U7 A1 A2 A3 A4 A5 0.1m/25V 1. Setting of ton (constant on time) In this condition, calculated on time is from equation (1), Calculated ton: 1.2 V / 12 V • (1 / 500 kHz) = 200 ns From equation (3), Calculated R4 = (1.2V / (12 V • 500 kHz) – 60 ns) • (12 V – 2 V) / (50 pF • 1 V) = 28 kW so choose R4 = 30 kW from E24 series. So, actual on pulse ton is decided by equation (2), Constant on time: ((50 pF • 1 V / (12 V – 2 V)) • 30 kW + 60 ns = 210 ns 2. Setting of ripple injection resistance Voltage ripple on FB pin needs to be more than 15 mV. Here, C4 = 0.01 mF, C5 = 1000 pF and ESR of output cap = 0.5 mW. To obtain 15 mV additional ripple on FB pin from R6, C4 and C5 network circuit, R6 is calculated by equation (10). Calculated R6: (12 V – 1.2 V) • 210 ns / (15 mV • 0.01 mF) = 15.1 kW So choose R6 = 15 kW from E24 series and actual ripple voltage from injection circuit becomes 15.1 mV. So, Total ripple voltage on FB pin is calculate by equation (13), Total ripple voltage: (12 V – 1.2 V) • 210 ns / (15 kW • 0.01 mF) + (12 V – 1.2 V) • 210 ns / 0.47 mH • 0.5 mW =17.5 mV 3. Setting of output voltage resistor From above setting, effective FB voltage is from equation (15), Effective FB voltage: 800 mV + 17.5 mV / 2 = 808.8 mV When R1 = 13 kW, R2 is decided from equation (15). R2 = 13 kW / ((1.2 V / 808.8 mV) – 1) = 26.8 kW So, choose R2 = 27 kW from E24 series. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 17 of 23 RAA207703GBM/7704GBM/7705GBM 4. Stability criteria confirmation For output capacitor, please confirm stability criteria. Stability criteria from equation (11), 1 / (2p • 0.01 mF • 500 kHz) = 32 W << 1 / (2p • 1000 pF • 500 kHz) = 318 W << 13 kW • 27 kW / (13 kW + 27 kW) = 8.8 kW so, above criteria is satisfied. For output capacitor, please confirm stability criteria. Stability criteria from equation (12), Cout > (210 ns / 2) • 15 kW • 0.01 mF / 0.47 mH = 34 mF So, choose 110 mF (22 mF ´ 5 pcs.) for output capacitor. Here, please consider voltage dependence of capacitor. If you cannot satisfy above criteria, please consider below changes. ¾ increase L or Cout value ¾ increase frequency (decrease constant on time) ¾ change Rf value. 5. Other components C1 = 1 mF / 10 V and C2 = 0.1 mF / 25 V are recommended. C3 decides soft start period from equation (5). R5 is decided from the table in “Boot Resistance” section. Input and output capacitors are decided considering voltage ripple, current ripple and voltage tolerance. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 18 of 23 RAA207703GBM/7704GBM/7705GBM Board Layout Example (RAA207703GBM) Board layer example: 4 layer, internal 2nd and 3rd layer are used for GND plane. SW plane VIN plane SW plane VIN plane GND plane Vout plane GND plane Top Layer Bottom Layer 1. Power part ¾ Input capacitor should be placed close to VIN and PGND pin to reduce switching noise and to improve the efficiency. ¾ Many thermal via should be placed on VIN, SW and PGND planes to spread heat to board. Furthermore, VIN, SW planes on bottom layer are effective for thermal spread (If available). 2. Control part ¾ Decoupling capacitor between V5_OUT and SGND should be placed as close as possible to the chip in order to stable operation. ¾ Also, SGND, PGND via should be placed as close as possible to the chip, and connect each pin low impedance by internal GND plane. ¾ FB resistance should be placed close to chip and FB wiring should be short to avoid noise. Furthermore, additional ripple circuit wiring should be kept away from high dv/dt plane such as SW and BOOT wiring. ¾ To ensure the reliability of chip - board connection, we recommend Solder Mask Defined (SMD) layout. But you can also use Non-Solder Mask Defined (NSMD) layout as far as you can ensure the reliability. In the case of SMD layout, we recommend below size. Solder resist open size: 280 mm, Land size: 280 mm + 50 to 100 mm (please consider processing accuracy) R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 19 of 23 RAA207703GBM/7704GBM/7705GBM Representative Inductors Maker NEC Tokin MPC series ALPS Green Device GLMC series TOKO FDVE0630 series TDK SPM5030 series Note: Inductance [mH] 0.42 DL/L0 = 20% Change [A] 20.0 Dimensions [mm] 6.7 ´ 8.0 ´ 4.0 0.60 0.88 19.0 24.0 6.7 ´ 8.0 ´ 5.0 10.0´ 11.5 ´ 4.0 1.0 0.47 25.0 1 13.9 * 10.0 ´ 11.7 ´ 5.5 6.5 ´ 7.4 ´ 3.0 1.0 1.5 10 * 1 8.8 * 1 6.5 ´ 7.4 ´ 3.0 6.5 ´ 7.4 ´ 3.0 0.33 0.47 15.9 15.6 6.7 ´ 7.4 ´ 3.0 6.7 ´ 7.4 ´ 3.0 0.75 1.0 10.9 9.5 6.7 ´ 7.4 ´ 3.0 6.7 ´ 7.4 ´ 3.0 0.35 0.47 14.9 11.0 5.0 ´ 5.2 ´ 3.0 5.0 ´ 5.2 ´ 3.0 0.75 9.7 5.0 ´ 5.2 ´ 3.0 Inductance [mH] DL/L0 = 30% Change [A] Dimensions [mm] 0.68 1.0 8.3 6.8 4.2 ´ 4.2 ´ 2.0 4.2 ´ 4.2 ´ 2.0 1.5 0.47 5.7 8.3 4.2 ´ 4.2 ´ 2.0 4.4 ´ 4.1 ´ 1.2 1.0 4.8 4.4 ´ 4.1 ´ 1.2 * 1 30% change · Small size inductor for RAA207705GBM Maker TOKO FDSD0420 series TDK SPM4012 series Representative Output Capacitors Maximum Voltage [V] Capacitance [mF] Sanyo POSCAP series Sanyo OS-CON series Maker 2.0 to 10 2.0 to 10 47 to 330 47 to 330 Murata MLCC series TDK MLCC series 6.3 to 10 6.3 to 10 22 to 47 22 to 47 TAIYO YUDEN MLCC series 6.3 to 10 22 to 47 R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 20 of 23 RAA207703GBM/7704GBM/7705GBM Package Dimensions · RAA207703GBM MASS[Typ.] 0.02g Unit: mm A 2.67 ± 0.05 0.5 0.335 ± 0.05 3.34 2.0 0.335 ± 0.05 0.67 Previous Code — 0.265 ± 0.05 RENESAS Code SWBG0035ZA-A 0.67 JEITA Package Code — A 3.87 ± 0.05 B B C D E F 0.5 0.5 0.265 ± 0.05 ø 0.05 M S AB 0.4 ± 0.04 35– ø0.32 ± 0.05 0.5 5 4 3 2 1 0.05 0.5 4× 0.33 G S SEATING PLANE 0.08 S Note: 1. Ball pitch dimension is specified with the center of balls. 2. Datum A and B are axes defined by the ball grid array, not by the Package Outline. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 0.235 ± 0.04 C area C area Page 21 of 23 RAA207703GBM/7704GBM/7705GBM · RAA207704GBM MASS[Typ.] 0.02g Unit: mm A 0.5 0.335 ± 0.05 2.67 ± 0.05 0.335 ± 0.05 2.84 2.0 0.67 Previous Code — 0.265 ± 0.05 RENESAS Code SWBG0030ZA-A 0.67 JEITA Package Code — 3.37 ± 0.05 A B B C 0.5 0.265 ± 0.05 ø 0.05 M S AB 0.4 ± 0.04 30– ø0.32 ± 0.05 0.5 5 4 3 2 1 0.05 0.5 4× 0.08 D E F S SEATING PLANE 0.08 S Note: 1. Ball pitch dimension is specified with the center of balls. 2. Datum A and B are axes defined by the ball grid array, not by the Package Outline. R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 0.235 ± 0.04 C area C area Page 22 of 23 RAA207703GBM/7704GBM/7705GBM · RAA207705GBM JEITA Package Code — RENESAS Code SWBG0020ZA-A Previous Code — MASS[Typ.] 0.01g Unit: mm 2.37 ± 0.05 A 1.84 0.67 0.5 0.335 ± 0.05 1.84 2.67 ± 0.05 0.265 ± 0.05 2.0 0.335 ± 0.05 0.67 A B B 5 4 3 2 1 0.25 0.05 ø 0.05 M S AB 0.4 ± 0.04 20– ø0.32 ± 0.05 0.5 4× 0.265 ± 0.05 C D S SEATING PLANE 0.08 S 0.235 ± 0.04 C area C area Note: 1. Ball pitch dimension is specified with the center of balls. 2. Datum A and B are axes defined by the ball grid array, not by the Package Outline. Ordering Information Part Name Quantity Shipping Container RAA207703GBM#HC0 RAA207704GBM#HC0 2000 pcs 2000 pcs Taping Reel Taping Reel RAA207705GBM#HC0 2000 pcs Taping Reel R07DS0892EJ0100 Rev.1.00 Aug 02, 2013 Page 23 of 23 Notice 1. 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