RENESAS 7701GBM

Preliminary Datasheet
RAA207700GBM/7701GBM/7702GBM
R07DS0891EJ0001
Rev.0.01
Nov 29, 2012
Synchronous Buck Regulator with
Internal Power MOSFETs
Description
The RAA207700GBM is monolithic synchronous buck regulator with power MOSFETs in extremely small package.
The RAA207700GBM delivers high output current by small Rds(on) Power MOSFETs. Constant on time control
architecture provides fast transient response, and minimize external components. The RAA207700GBM operates skip
mode at light load, it provides high efficiency in all load condition. Three current ability products can be selected.
Features

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


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


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Wide input voltage range: 3 V to 16 V
Constant-On-Time control
Built-in power MOSFETs suitable for PC, Server application
Very low stand-by current: 0.1 A (typ.)
Very low quiescent current :320 A (typ. at no load)
Switching frequency: Adjustable up to 2 MHz
High average output current, up to 15 A (7700GBM), 10 A (7701GBM), 5 A (7702GBM)
Controllable driver: Remote on/off
Power Good function
Over current protection/Over voltage protection/Thermal shutdown function
Built-in bootstrapping diode
Soft Start period adjustable
Enhanced light load mode function for higher efficiency
High drivability built-in line switch driver for low-loss line switch driving
Extremely small chip size package with solder bump
Pb-Free/Halogen-Free
Application Circuit
VCIN
VIN
VCIN
SET
BOOT
VIN
ON/OFF
SS RAA207700GBM
RAA207701GBM SW
RAA207702GBM
VOUT_1
PGOOD
Line SW
control signal
FB
LS_IN
PGND
LS_OUT
SGND
Discrete Line SW
VOUT_2
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Page 1 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Pin Arrangement
Top View
<RAA207700GBM>
1
2
<RAA207701GBM>
3
4
5
LS_
OUT
1
A
VCIN
2
<RAA207702GBM>
3
4
5
SGND
FB
LS_
IN
LS_
OUT
1
A
VCIN
2
3
4
5
SGND
FB
LS_
IN
LS_
OUT
A
VCIN
SGND
FB
LS_
IN
BOOT
SET
PGO
OD
SS
ON/
OFF
B
BOOT
SET
PGO
OD
SS
ON/
OFF
B
BOOT
SET
PGO
OD
SS
ON/
OFF
B
SW
VIN
VIN
VIN
VIN
C
SW
VIN
VIN
VIN
VIN
C
SW
SW
VIN
VIN
VIN
C
SW
SW
SW
SW
VIN
D
SW
SW
SW
SW
VIN
D
SW
SW
PGND
PGND
PGND
D
SW
PGND
PGND
PGND
PGND
E
SW
PGND
PGND
PGND
PGND
E
SW
SW
SW
PGND
PGND
F
SW
SW
SW
PGND
PGND
F
SW
PGND
PGND
PGND
PGND
G
Bottom View
<RAA207700GBM>
<RAA207701GBM>
5
4
3
2
1
LS_
OUT
LS_
IN
FB
SGND
VCIN
ON/
OFF
SS
PGO
OD
SET
VIN
VIN
VIN
VIN
SW
PGND
<RAA207702GBM>
5
4
3
2
1
A
LS_
OUT
LS_
IN
FB
SGND
VCIN
BOOT
B
ON/
OFF
SS
PGO
OD
SET
VIN
SW
C
VIN
VIN
VIN
SW
SW
SW
D
VIN
SW
PGND
PGND
PGND
SW
E
PGND
PGND
PGND
SW
SW
SW
F
PGND
PGND
PGND
PGND
PGND
SW
G
CSP 35-pin package
2.7 mm × 3.9 mm
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
5
4
3
2
1
A
LS_
OUT
LS_
IN
FB
SGND
VCIN
A
BOOT
B
ON/
OFF
SS
PGO
OD
SET
BOOT
B
VIN
SW
C
VIN
VIN
VIN
SW
SW
C
SW
SW
SW
D
PGND
PGND
PGND
SW
SW
D
PGND
PGND
PGND
SW
E
PGND
SW
SW
SW
F
CSP 30-pin package
2.7 mm × 3.4 mm
CSP 20-pin package
2.7 mm × 2.4 mm
Page 2 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Pin Description
Pin Name
VCIN
SGND
FB
LS_IN
LS_OUT
BOOT
SET
PGOOD
SS
ON/OFF
VIN
SW
PGND
Note:
Pin No.
1A
2A
3A
4A
5A
1B
2B
3B
4B
5B
—
—
—
Description
Controller input voltage (+5 V input)
Controller analog GND
Feedback voltage input pin
Line SW driver control pin
Line SW driver output pin
Bootstrap voltage pin
Constant on time program pin
Power good indicator pin
Soft start period program pin
Operation enable pin
Input voltage
Switching node
Power ground
Remarks
Controller supply input
Should be connected to PGND on PCB pattern
To be supplied +5 V through integrated SBD
Tie resistor between SW and SET
Pull low when No Good (open drain output)
Tie capacitor between SS and SGND
Operation stop when L signal asserted
Should be connected to SGND on PCB pattern
Pin assign of 1A-5A & 1B-5B is common through RAA207700GBM, RAA207701GBM and RAA207702GBM.
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Page 3 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Block Diagram
SET
VCIN
VIN
Enable
ON/OFF
1M
TSD
UVLO
4.3 V
BOOT
TSD
UVLO
2.5 μA
SS
Enable
UVLO
Fault
Ripple
Comparator
0.8 V
+
+
–
1.0 V
OCP
1 shot
timer
OVP
–
FB
0.72 V
–
UVLO
Control
Logic
+
ZCD
Enable
PGOOD
TSD
delay
SW
ZCD
Comparator
+
–
+
VCIN
Fault
VIN
Protection
Function
LS_IN
Fault
OVP
PGND
1M
TSD
OCP
OVP
LS_OUT
1. Truth table for the ON/OFF pin
ON/OFF Input
"L"
"Open"
"H"
Driver Chip Status
Shutdown (operation STOP)
Shutdown (operation STOP)
Enable (Normal operation)
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
SGND
2. Truth table for Line Switch driver
LS_IN Input
"L"
"Open"
"H"
LS_OUT Status
GND
GND
VIN
Page 4 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Absolute Maximum Ratings
(Ta = 25°C)
Item
Input voltage
Switch node voltage
BOOT voltage
Controller voltage
Input pin voltage (FB, LS_IN)
ON/OFF voltage
SET voltage
PGOOD voltage
PGOOD sink current
Operating junction temperature
Storage temperature
Notes: 1.
2.
3.
4.
Symbol
VIN
SW
VBOOT
VCIN
VINPUT
VON/OFF
VSET
VPGOOD
IPGOOD
Tj-opr
Tstg
Ratings
–0.3 to +20
20(DC), 23(<10 ns)
25(DC), 28(<10 ns)
–0.3 to +6
–0.3 to VCIN +0.3
–0.3 to VIN
–0.3 to VIN
–0.3 to VIN
+2
–40 to +125
–55 to +150
Unit
V
V
V
V
V
V
V
V
mA
°C
°C
Notes
1
1
1, 2
1
1, 3
1
1
1
4
Rated voltages are relative to voltages on the SGND and PGND pins.
BOOT – VCIN < 20 V
VCIN + 0.3 V < 6 V
For rated current, (+) indicates inflow to the chip.
Recommended Operating Condition
Item
Input voltage
Controller voltage
Continuous output current
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Symbol
VIN
VCIN
IOUT
Ratings
3 to 16
4.5 to 5.5
0 to 15
0 to 10
0 to 5
Unit
V
V
A
Remarks
15 A: RAA207700GBM
10 A: RAA207701GBM
5 A: RAA207702GBM
Page 5 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Electrical Characteristics
(Ta = 25°C, VCIN = 5 V, VIN = 12 V, SW = 0 V, unless otherwise specified)
Item
Supply
Remote
on/off
Line_SW
input
Line_SW
output
Symbol
Min
Typ
Max
Unit
Test Conditions
VCIN start threshold
VH
—
4.3
4.5
V
VCIN shutdown threshold in
CCM
VL
3.6
3.8
—
V
VCIN shutdown threshold in
ELL mode
VLCCM
—
3.0
3.6
V
VCIN operating current
(RAA207700GBM)
ICIN
—
40
—
mA
VCIN operating current
(RAA207701GBM)
ICIN
—
35
—
mA
VCIN operating current
(RAA207702GBM)
ICIN
—
20
—
mA
VCIN quiescent current
Iq
—
320
400
A
Output = no load, ELL mode
VCIN disable current
ICIN-DISBL
—
0.1
5
A
ON/OFF = 0 V, LS_IN = 0 V
VIN disable current
IIN-DISBL
—
0.1
5
A
ON/OFF = 0 V, LS_IN = 0 V
Disable level
VDISBL
—
—
0.6
V
3.3 / 5.0 V interface
Enable level
VENBL
2.0
—
—
V
Pull-down resistance
RDISBL
0.7
1
1.3
M
Line SW off level
VLSIN_OFF
—
—
0.6
V
Line SW on level
VLSIN_ON
2.0
—
—
V
Pull-down resistance
RLS_IN
0.7
1
1.3
M
LS_IN = 1 V
Line SW on output voltage
VLSW_ON
VIN–0.5
VIN
—
V
LS_IN = 5 V
Line SW off output voltage
VLSW_OFF
—
—
0.1
V
Line SW on source current
ILSW_SOURCE
—
25
—
mA
Line SW off sink current
ILSW_SINK
—
25
—
mA
VIN = 12 V, LS_IN = 0 V
Line SW on propagation delay
TPLSWON
—
300
—
ns
LSIN to LSOUT rising
Line SW off propagation delay
TPLSWOFF
—
300
—
ns
LSIN to LSOUT falling
LS_IN = 5 V
In ELL mode
(DCM, fSW < 100 kHz)
fSW = 1 MHz,
Ton = 200 ns
3.3 / 5.0 V interface
ON/OFF = 1 V
3.3 / 5.0 V interface
3.3 / 5.0 V interface
LS_IN = 0 V
VIN = 12 V, LS_IN = 5 V
Line SW drive current of VIN
IIN-LS
—
8
20
A
Comparator threshold voltage
VFB_COMP
792
800
808
mV
FB input current
IFB_IN
–0.1
0
+0.1
A
Power
Rising threshold on FB
VPG_rise
0.67
0.72
0.77
V
good
indicator
Power good hysteresis
dVPG
—
50
—
mV
Power good resistance
RPG
0.25
0.5
1
k
Soft start
Soft start bias current
ISS
1.8
2.5
3.2
A
Over
OVP trip voltage on FB
VOVP
0.95
1.00
1.05
V
OCP trip current
(RAA207700GBM)
IOCP
16.0
20.0
24.0
A
Fixed internally *
1
OCP trip current
(RAA207701GBM)
IOCP
12.0
15.0
18.0
A
Fixed internally *
1
OCP trip current
(RAA207702GBM)
IOCP
6.4
8.0
9.6
A
Fixed internally *
1
Over
TSD trip temperature
TTSD
130
150
—
°C
*
1
temperature
protection
Temperature hysteresis
Thys
—
30
—
°C
*
1
FB
FB = 1 V
FB = 0 V
voltage
protection
Over
current
protection
Note:
*1 Not directly tested. Assured by related characteristics test.
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Page 6 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Description of Operation
The RAA207700GBM operates as voltage-ripple based constant on time control architecture. Converter output is
controlled by output voltage ripple which is determined by inductor ripple current and ESR & ESL of output capacitor.
Each switching cycle starts High-side MOSFET turn on which time is decided by 1 shot timer. After High-side
MOSFET turns off, Low side turns on, and it keeps until FB voltage becomes lower than reference voltage. In light load
condition, Low-side MOSFET on time is decided by inductor zero current.
Switching Frequency, Constant on Time Setting
Rset
SET
SW
Switching Frequency in CCM mode is determined by following equation.
Switching Frequency: (Vout/Vin) • (1/ton) [Hz]
Here, ton is High-side MOS on time, and it is determined by following equation.
On time pulse: (50 pF • 1 V / Vin – 2.0 V) • Rset + 50 ns [s]
From above equation, constant on time is change depend on Vin, so switching frequency is almost constant when VIN
change. This architecture is suitable for battery application. From the above equation, Rset is calculated by
Rset: (Vout / (Vin • Fsw) – 50 ns) • (Vin – 2.0 V) / (50 pF • 1 V) []
1700
1300
VIN = 12 V
VIN = 5 V
1100
1300
1000
1100
On Time [ns]
On Time [ns]
Rset = 30 kΩ
1200
1500
900
700
900
800
700
600
500
500
400
300
300
200
100
100
0
50
100
150
Rset [kΩ]
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
200
250
4
6
8
10
12
14
16
VIN [V]
Page 7 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Maximum Duty Cycle Operation
Maximum duty cycle is restricted by following equation.
Max. duty: 1 – (50 ns • Fsw)
Here, Fsw is switching frequency.
If FB voltage does not reach reference voltage after the High-side MOSFET turn on time is expired, Low-side
MOSFET turns on 50 ns, and next switching cycle starts. Especially, this condition occurs when output load transient
state.
SW
50 ns
IL
(inductor current)
Soft Start
SS
SGND
Css
Soft start ramp period is adjustable by external capacitor (Css) selection. When converter start operating, 2 A current
from SS pin charges capacitor between SS and GND. Soft start period is determined by following equation.
Soft Start period: Css • 0.8 V / 2.5 A [s]
Here, 0.8 V is internal reference voltage Vref. IC operates diode emulation mode at Soft start period, so it can prevent
from reverse current when pre-bias condition. Soft start restarts when Enable signal re-entered, and after OCP, OVP,
TSD, UVL release condition.
Power Good Indicator
Power good indicator is useful for controlling multi-converter systems for sequential start up and shut down. FB voltage
ismonitored continuously by power good comparator. The power good comparator compares FB pin and 90% internal
referencevoltage (0.72 V). When FB reaches reference voltage, PGOOD pin becomes high impedance after internal
delay (30% of soft start period). Under the fault condition (UVLO, OVP, OCP, TSD), PGOOD pin is pulled low.
0.80 V
0.72 V
SS
FB
Vout
PGOOD
Soft start period
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Power Good delay
(30% soft start period)
Page 8 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Over Voltage Protection (OVP)
When FB voltage exceeds 125% of reference voltage (1.00 V), switching stops immediately and latched Low-side
MOSFET on state in order to pull the output voltage. To leave the OVP condition, VCIN needs to be pulled under the
UVLO level, and re-enter the signal.
125% Vref
90% Vref
FB
High MOSFET
signal
Low MOSFET
signal
ON/OFF
(UVL)
delay
PGOOD
Over Current Protection (OCP)
OCP detection circuit monitors high-side MOSFET drain-source current. When the current exceeds fixed level eight
time, IC starts hiccup operation. In the hiccup operation, switching stops and operate 1 ms timer. After 1 ms timer is
expired, IC operates again from soft start state. If IC detect OCP in the soft start circuit, hiccup operation start again.
PGOOD
SS
OCP detect
OCP
level
IL
0A
SW
1 ms wait
1 ms wait
Note: PGOOD pin is connected VCIN through resistor.
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Page 9 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Thermal Shutdown (TSD)
Thermal sensor monitors junction temperature of IC. When junction temperature exceeds 150°C, switching stops. After
junction temperature become 125°C, IC restart switching from soft start (Non-latched function).
Enhanced Light Load Function (ELL)
IC operates diode emulation mode in light load condition. To enhance light load efficiency, IC detects light load
condition automatically, and operate as Enhanced Light Load mode (ELL). In ELL mode, bias current of IC becomes
small, so this function can improve the efficiency.
Line Switch Driver
The RAA207700GBM/7701GBM/7702GBM incorporates high drivability built in line switch driver. The line switch
driver can drives large gate capacitance MOSFET with low power consumption. (Typical 8 A at Vin = 12 V)
Line switch driver operates independent of voltage regulator’s state.
VIN
VIN
0 V - VIN
0 V - 3.3 V
Input signal
LS_IN
Vout1
LS_OUT
Discrete
MOSFET
Vout2
Note: This function is independent of state of voltage regulator.
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Page 10 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Stability Criteria, Output Voltage Setting for High ESR Output Capacitor
Small output ripple voltage makes control loop unstable in constant on time architecture. Ripple voltage needs to be
larger than 15 mV on FB pin. When using high ESR (>50 m) capacitor such as Electrolytic capacitor, Polymer
aluminum capacitor for output capacitor, ripple voltage on FB pin will be more than 15 mV.
VIN
Lout
Vout
SW
FB
R1
ESR
R2
Cout
Stability criteria
From loop stability analysis, constant on time control system must satisfy below equation.
Stability criteria: ESR • Cout > ton / 2
Here, ton is constant on time. If the system cannot satisfy above equation, subharmonic oscillation will occur.
Vout setting
FB comparator compares FB voltage and internal accurate reference voltage (0.8 V). Feedback loop controls FB voltage
to match the reference voltage. Therefore, output voltage is set by following equation.
Vout: 0.8 V • (R1+R2) / R2
Here, R1 and R2 is output voltage divider resister (refer to above figure). However, ripple voltage on FB pin affects FB
voltage, so Vout slightly shifts from setting value. If the system needs high accuracy, adjust Vout by changing R1, R2
value.
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Page 11 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Operating with Small ESR Output Capacitor
When using low-ESR output capacitor like MLCC, voltage ripple on output voltage node is very small. So voltage
ripple needs to be enhanced by additional components. Recommended ripple enhance method is like below figure.
VIN
Lout
Vout
SW
FB
Rf
Cf
R1
Cout
Cr
R2
Ripple injection on FB pin
Rf and Cf make ripple voltage using inductor DCR ripple. Cr is used for AC ripple injection to FB pin. Ripple voltage
between Rf and Cf is described by following equation.
Vripple: (VIN – VOUT) • ton / (Rf • Cf)
Make sure above ripple voltage is larger than 15 mV.
Stability criteria
From loop stability analysis of above circuit configuration, the system must satisfy below equation.
Stability criteria: Lout • Cout / (Rf • Cf ) > ton / 2
If the system cannot satisfy above equation, subharmonic oscillation will occur.
Vout setting
Output voltage setting is basically same concept as high ESR capacitor use case. Ripple voltage from injection circuit
affects FB voltage, so it need to be adjust R1, R2 for high accuracy system.
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Page 12 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Board Layout Example (RAA207700GBM)
VIN plane
SW
plane
RAA207700GBM
Vout
plane
Input Cap.
GND plane
Inductor
Output Cap.
Top Layer (Top view)
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Page 13 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Representative Inductors
Maker
NEC Tokin
MPC series
ALPS Green Device
GLMC series
TOKO
FDVE0630 series
TDK
SPM5030 series
Note:
Inductance [H]
L/L0 = 20% Change [A]
Dimensions [mm]
0.42
0.60
0.88
20.0
19.0
24.0
6.7  8.0  4.0
6.7  8.0  5.0
10.0 11.5  4.0
1.0
0.47
1.0
25.0
13.9 *1
10 *1
1.5
0.33
0.47
0.75
8.8 *
15.9
15.6
10.9
10.0  11.7  5.5
6.5  7.4  3.0
6.5  7.4  3.0
6.5  7.4  3.0
6.7  7.4  3.0
6.7  7.4  3.0
6.7  7.4  3.0
1.0
0.35
0.47
9.5
14.9
11.0
6.7  7.4  3.0
5.0  5.2  3.0
5.0  5.2  3.0
0.75
9.7
5.0  5.2  3.0
Inductance [H]
0.68
1.0
L/L0 = 30% Change [A]
8.3
6.8
Dimensions [mm]
4.2  4.2  2.0
4.2  4.2  2.0
1.5
0.47
5.7
8.3
4.2  4.2  2.0
4.4  4.1  1.2
1.0
4.8
4.4  4.1  1.2
1
*1 30% change
 Small size inductor for RAA207702GBM
Maker
TOKO
FDSD0420 series
TDK
SPM4012 series
Representative Output Capacitors
Maker
Sanyo POSCAP series
Sanyo OS-CON series
Murata MLCC series
TDK MLCC series
TAIYO YUDEN MLCC series
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
Maximum Voltage [V]
2.0 to 10
2.0 to 10
6.3 to 10
6.3 to 10
6.3 to 10
Capacitance [F]
47 to 330
47 to 330
22 to 47
22 to 47
22 to 47
Page 14 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
Package Dimensions
 RAA207700GBM
0.335 ± 0.05
3.34
2.67 ± 0.05
0.67
0.5
0.335 ± 0.05
0.67
2.0
0.265 ± 0.05
A
A
3.87 ± 0.05
B
B
C
D
E
F
G
0.5
0.5
0.265 ± 0.05
φ0.05 M S AB
0.4 ± 0.04
35-φ0.32±0.05
0.5
5 4 3 2 1
0.5
0.05
0.33
4×
S
SEATING PLANE
0.08 S
0.235 ± 0.04
C area
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
C area
Page 15 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
 RAA207701GBM
0.335 ± 0.05
2.84
2.67 ± 0.05
0.67
0.5
0.335 ± 0.05
0.265 ± 0.05
2.0
0.67
A
A
3.37 ± 0.05
B
B
C
D
E
0.5
0.265 ± 0.05
φ0.05 M S AB
0.4 ± 0.04
30-φ0.32±0.05
0.5
5 4 3 2 1
0.05
0.5
4×
0.08
F
S
SEATING PLANE
0.08 S
0.235 ± 0.04
C area
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
C area
Page 16 of 17
RAA207700GBM/7701GBM/7702GBM
Preliminary
 RAA207702GBM
0.335 ± 0.05
2.37 ± 0.05
A
1.84
2.67 ± 0.05
0.67
0.5
0.335 ± 0.05
0.67
2.0
0.265 ± 0.05
A
B
B
C
4×
0.25
φ0.05 M S AB
0.4 ± 0.04
20-φ0.32±0.05
0.5
5 4 3 2 1
0.05
0.265 ± 0.05
D
S
SEATING PLANE
0.08 S
0.235 ± 0.04
C area
R07DS0891EJ0001 Rev.0.01
Nov 29, 2012
C area
Page 17 of 17
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