RFMD RF2908

RF2908
11
915MHZ SPREAD SPECTRUM RECEIVER WITH
PLL FREQUENCY SYNTHESIZER
Typical Applications
• Digital Cordless Telephones
• Inventory Tracking
• Secure Communication Links
• Wireless Security
• Wireless LANs
• Battery Powered Applications
Product Description
The RF2908 is a monolithic integrated circuit specifically
designed for direct-sequence spread-spectrum systems
operating in the 902MHz to 928MHz ISM band. The part
includes a direct conversion receiver, quadrature demodulator, dual IF amplifiers with gain control and RSSI, onchip programmable baseband filters, dual data comparators, and a serially programmable 86-channel PLL frequency synthesizer. Two cell or regulated three cell (3.6V
maximum) battery applications are supported by the part.
The part is also designed to operate in compliance with
FCC Part 15.247. The device is provided in 48-lead plastic LQFP packaging.
.362
.346
.020
.362
.346
.280
.272
.280
.272
Optimum Technology Matching® Applied
üSi Bi-CMOS
GaAs HBT
GaAs MESFET
SiGe HBT
Si CMOS
.011
.007
.057
.053
7°MAX
0°MIN
.031
.021
Si BJT
.006
.002
.007
MAX
Package Style: LQFP-48
11
Features
1,2
LNA
IN Q±
TRANSCEIVERS
• FCC Part 15.247 Compliant
MOUT Q±
• Direct Conversion Receiver
47,48
IF Amp
Q Data Amp
LNA IN 6
39 Q DATA
• On-Chip 86 Channel Frequency
Synthesizer
+45°
-45°
42 IF OUT Q
RSSI
Gain Control
19 IF OUT I
PLL
Freq. Synth.
21 I DATA
IF Amp
23
24
11,12
13,14
MOUT I±
IN I±
• 2.7V to 3.6V Operation
I Data Amp
Ref
Refer to the Detailed Functional Block Diagram for description of full functionality
Functional Block Diagram
Rev C1 010904
• On-Chip Selectable IF Bandwidths
Ordering Information
RF2908
915MHz Spread Spectrum Receiver with PLL Frequency Synthesizer
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
11-85
RF2908
Absolute Maximum Ratings
Parameter
Ratings
Unit
Supply Voltage
Control Voltages
Input RF Level
Output Load VSWR
Operating Ambient Temperature
Storage Temperature
-0.5 to +3.6
-0.5 to +3.6
+20
50:1
-40 to +85
-40 to +150
VDC
VDC
dBm
Parameter
°C
°C
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Specification
Min.
Typ.
Max.
Unit
902 to 928
100
6.0
-12
+5.5
-100
-65
0.35 to 3.1
30
65
MHz
dB
dB
dBm
dBm
dBm
dBm
V
mV/dB
dB
T=25 °C, VCC =3.6V, Freq=915MHz
Overall
Frequency Range
Cascaded Voltage Gain
Cascaded Noise Figure
Cascaded Input IP3
RX Sensitivity
LO Leakage
RSSI DC Output Range
RSSI Sensitivity
RSSI Dynamic Range
Condition
60
8.0
High Gain
Low Gain
IF BW =960kHz, Freq=915MHz, S/N=8dB
At LNA IN
RLOAD =51kΩ
LNA and Mixer
Operating Frequency Range
Voltage Gain
Noise Figure
RF Input Impedance
RF Input VSWR
Input IP3
TRANSCEIVERS
11
902 to 928
22
6.0
50
2:1
-20
Quadrature Phase Balance
Quadrature Amplitude Balance
Mixer Output Impedance
DC Current Consumption
11-86
8.0
MHz
dB
dB
Ω
150
26
-12
+5.5
±3
±5
dBm
dBm
°
±1
200
33
250
39
dB
Ω
mA
At maximum gain. ATTN=LOW
At minimum gain. ATTN=HIGH
With expected LO amplitude and harmonic
content.
Differential
Operating at a 3.3V supply voltage.
Rev C1 010904
RF2908
Parameter
Specification
Min.
Typ.
Max.
Unit
Condition
IF and Data Amplifiers
IF Frequency Range
Voltage Gain
Noise Figure
Note 1
77
Input IP3
Output DC Offset
Gain Control Range
Gain Control Voltage Range
Gain Control Sensitivity
VGA Output Voltage
VGA DC Output Voltage
Output P1dB
RSSI Range
RSSI Output Voltage Compliance
Input Impedance
65
1.2
80
5
35
-65
+2
0
70
25
2.0
55
-0.08
500
1.7
1.64
60
0.5 to 2.4
1.5
2
1
9.6
83
2.5
MHz
dB
dB
dB
dBm
dBm
mV
dB
V
dB/mV
mVPP
V
VPP
dB
V
kΩ
At maximum gain setting
At minimum gain setting
At maximum gain setting
At minimum gain setting
Driving a 5kΩ load
At maximum gain setting
Maximum RSSI is 2.5V or VCC -0.3, whichever is less.
Differential
Note 1. The lower cutoff frequency is a function of: a) input DC blocking cap size; b) DC
feedback capacitor; and, c) gain setting. But,
recommended component values will yield a
cutoff of <10kHz.
Filters
Five pole Bessel
Bandwidth
1, 2, 4, 8
Passband Ripple
Group Delay
Ultimate Rejection
MHz
1
100
80
dB
ns
100
dB
100
dB
MHz
ns
V
Five pole Bessel internal LPF.
Three pole external LPF.
Selectable from 1, 2, 4, and 8MHz. Refer to
“IF Bandwidth Response” chart.
At 8MHz, increasing as bandwidth
decreases.
11
Data Amplifiers
Voltage Gain
Bandwidth
Rise and Fall Time
Logic High Output
10
2
5
VCC -0.3V
Logic Low Output
0.3
V
Can sink/source 1mA and maintain these
logic levels.
Can sink/source 1mA and maintain these
logic levels.
PLL, Synthesizer, VCO and
LO
VCO Tuning Range
VCO Sensitivity
Charge Pump Current
Reference Frequency Crystal
Reference Crystal Rs
Phase Noise
LO Output Level
Lock Time
Step Size
Rev C1 010904
20
800 to 1200
30
100
9.6
60
-66
-96
-10
1.5
300
40
20
80
MHz
MHz/V
µA
MHz
Ω
dBc/Hz
dBc/Hz
dBm
ms
kHz
Determined by external resistor.
KPD =100µA/2π=0.0159ma/2π rad
10kHz offset.
100kHz offset.
Into 100Ω differential load
From sleep mode.
86 channels in the 902MHz to 928MHz ISM
band.
11-87
TRANSCEIVERS
Characteristics
RF2908
Parameter
Specification
Min.
Typ.
Max.
Unit
Condition
Power Down Control
Logical Controls “ON”
Logical Controls “OFF”
Control Input Impedance
Turn On Time
VCC -0.3V
VCC +0.3V
V
Voltage supplied to the input
0.3
V
MΩ
ms
Voltage supplied to the input
>1
1
1
ms
100
µs
0
Turn Off Time
RX to TX and TX to RX Time
Reference Crystal=9.6MHz. Dependent on
reference crystal. Higher frequencies reduce
turn on/off times.
Reference Crystal=9.6MHz. Dependent on
reference crystal. Higher frequencies reduce
turn on/off times.
Power Supply
Voltage
Current Consumption
2.7
3.3
50
3.6
62
V
mA
50
45
57
µA
mA
VCC =3.3V; RX ENABL=HIGH;
PLL ENABL=HIGH
VCC =3.3V; Sleep Mode
VCC =3.3V; RX ENABL=LOW;
PLL ENABL=HIGH
TRANSCEIVERS
11
11-88
Rev C1 010904
RF2908
Function
MOUT Q-
2
3
4
5
6
7
8
9
10
MOUT Q+
MIX VCC
MIX GND
LNA GND
LNA IN
SW GND
LNA VCC
SW GND2
ATTN
11
12
MOUT I+
MOUT I-
13
14
15
16
17
IN I+
IN IGND2
DCFB I
VCC2
18
19
20
21
GND3
IF OUT I
VCC3
I DATA
22
23
RSSI I
OSC B
24
OSC E
25
LE
26
PLL CLK
27
PLL DATA
28
29
30
31
PLL GND
PLLD VCC
LO OUT B
RESNTR+
32
33
34
RESNTRLO OUT
DO
Rev C1 010904
Description
Interface Schematic
The complementary quadrature phase signal output from the front-end
mixer. See pin 2.
The quadrature phase signal output from the front-end mixer.
Supply voltage for the front-end quadrature mixers.
Ground connection for the front-end quadrature mixers.
Ground connection for the low noise amplifier (LNA).
Input to the attenuator and LNA.
Ground connection for the input attenuator.
Supply voltage for the LNA.
Ground connection for the input attenuator.
Input attenuator control point. When connected “high”, the attenuator
adds 20dB of series attenuation. When connected “low”, the attenuator
adds 0dB of series attenuation.
The in-phase signal output from the front-end mixer.
The complementary in-phase signal output from the front-end mixer.
See pin 12.
Input for the in-phase IF channel.
Complementary input for the in-phase IF channel.
Ground for VCC2.
DC feedback capacitor for in-phase channel.
Power supply for VGA amplifier 3, differential to single-ended converter,
and post filter.
Ground for VCC3.
Analog signal IF output for in-phase channel.
Power supply for data amplifier.
Logic-level data output for the in-phase channel. This is a digital output
signal obtained from the output of a Schmitt trigger.
Received signal strength indicator for the in-phase channel.
11
Base connection point for external reference crystal. The reference
crystal is connected between this pin and ground.
Emitter connection point for external reference crystal. Feedback
capacitors are connected between this pin and ground.
Latches data entered into the serial port. Data is clocked into the latch
on the rising edge of LE. See table and timing diagram.
PLL shift register clock. The rising edges of this clocking signal load in
the serial data present at the PLL DATA input pin into the internal latch.
See table and timing diagram.
Input data for loading the counters. Clocked, serial data at this port is
presented to the shift register, then to the latch, and finally to the
counter. Each clock transition sends a single bit to the on-board 7-bit
shift register. The MSB is loaded first. See table and timing diagram.
Ground connection for the PLL.
TRANSCEIVERS
Pin
1
Supply voltage for the PLL.
Complementary local oscillator output. See pin 33.
This port is used to supply DC voltage to the VCO as well as tune the
center frequency of the VCO.
This is the complementary port to pin 31. Refer to pin 31.
Local oscillator output.
Connection point for the loop filter.
11-89
RF2908
Pin
35
Function Description
PLL ENABL This pin is used to power up or down the VCO and PLL. A logic high
36
RX ENABL
37
BW SEL2
38
BW SEL1
39
Q DATA
40
41
42
43
44
RSSI Q
VREF
IF OUT Q
VGC
VCC1
45
46
47
48
DCFB Q
GND1
IN QIN Q+
Interface Schematic
(PLL ENABL>2.0V) powers up the VCO and PLL circuitry. A logic low
(PLL ENABL<1.0V) powers down the PLL and VCO.
Enable pin for the receiver circuits. RX ENABL>2.0V powers up all
receiver functions. RX ENABL<1.0V turns off all receiver functions
except the PLL functions and the RF mixer.
Bandwidth select logic input. Pin 37 and pin 38 provide a two bit control
word for the setting of the IF bandwidth. See Table1.
Bandwidth select logic input. Pin 37 and pin 38 provide a two bit control
word for the setting of the IF bandwidth. See Table1.
Logic-level data output for the quadrature channel. This is a digital output signal obtained from the output of a Schmitt trigger.
Received signal strength indicator for the quadrature channel.
Gain control reference voltage.
Analog signal IF output for quadrature channel.
Gain control voltage.
Power supply for bias circuits and VGA amplifiers for both the in-phase
and quadrature channels.
DC feedback capacitor for quadrature channel.
Ground for VCC1 for both the in-phase and quadrature channels.
Minus input for quadrature channel
Plus input for quadrature channel
Table 1: Bandwidth Selection Controls
BWSEL1
BWSEL2
0
0
1
1
0
1
0
1
TRANSCEIVERS
11
11-90
IF-3dB
Frequency
1MHz
2MHz
4MHz
8MHz
Rev C1 010904
RF2908
Table 2: Channel Plan
Data
f, MHz
Data
f, MHz
Data
f, MHz
Data
f, MHz
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
902.4
*
903
903.3
903.6
903.9
904.2
904.5
904.8
905.1
905.4
905.7
906
906.3
906.6
906.9
907.2
907.5
907.8
908.1
908.4
908.7
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
909
909.3
909.6
909.9
910.2
910.5
910.8
911.1
911.4
911.7
912
912.3
912.6
912.9
913.2
913.5
913.8
914.1
914.4
914.7
915
915.3
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
915.6
915.9
916.2
916.5
916.8
917.1
917.4
917.7
918
918.3
918.6
918.9
919.2
919.5
919.8
920.1
920.4
920.7
921
921.3
921.6
921.9
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
922.2
922.5
922.8
923.1
923.4
923.7
924
924.3
924.6
924.9
925.2
925.5
925.8
926.1
926.4
926.7
927
927.3
927.6
927.9
*Data 1 is invalid.
Timing Diagram
11
H
L
0
0
1
0
1
MSB
...
0
LSB
TRANSCEIVERS
0
DATA
H
...
CLK
L
tCWH
tCWL
tCS
tCH
tES
tEW
H
...
LE
L
Minimum Times:
tCWH
tCWL
tEW
tES
tCS
tCH
Rev C1 010904
= 143 ns
= 143 ns
= 74 ns
= 143 ns
= 36 ns
= 36 ns
0
time
Example: Load Sequence for Channel #10 (905.4 MHz)
t
Decimal 10 = 0 0 0 1 0 1 0 Binary
MSB
LSB
11-91
RF2908
Differential Filter Design Information
Butterworth Response
L
RS
C1
C2
L
RS
RL
RL
12
12
1
1
C1bw ⋅ --- ⋅ 10
C2bw ⋅ --- ⋅ 10
6
2
2
Lbw ⋅ RL ⋅ 10
C1 = -------------------------------------- ;C2 = -------------------------------------- ;L = ----------------------------------2 ⋅ π ⋅ fc ⋅ RL
2 ⋅ π ⋅ fc ⋅ RL
2 ⋅ π ⋅ fc
C1bw = 4.5325 ;C2bw = 13.5691 ;Lbw = 0.1743
RS
RS = 125 ;RL = 1000 ;------- = 0.125
RL
Differential LC Filter Component Values
(Butterworth Response)
100000
TRANSCEIVERS
11
Component Value
10000
1000
C2 (pF)
100
C1 (pF)
10
L (µH)
1
1.E+05
1.E+06
1.E+07
Frequency
11-92
Rev C1 010904
RF2908
Differential Filter Design Information (Cont.)
Bessel Response
L
RS
C1
C2
L
RS
RL
RL
12
12
1
1
C1bw ⋅ --- ⋅ 10
C2bw ⋅ --- ⋅ 10
6
2
2
Lbw ⋅ RL ⋅ 10
C1 = -------------------------------------- ;C2 = -------------------------------------- ;L = ----------------------------------2 ⋅ π ⋅ fc ⋅ RL
2 ⋅ π ⋅ fc ⋅ RL
2 ⋅ π ⋅ fc
C1bw = 2.6163 ;C2bw = 13.6373 ;Lbw = 0.1083
RS
RS = 125 ;RL = 1000 ;------- = 0.125
RL
Differential LC Filter Component Values
(Bessel Response)
100000
TRANSCEIVERS
11
Component Value
10000
1000
C2 (pF)
100
C1 (pF)
10
L (µH)
1
1.E+05
1.E+06
1.E+07
Frequency
Rev C1 010904
11-93
RF2908
IN Q-
GND1
DCFB Q
VCC1
VGC
IF OUT Q
VREF
RSSI Q
Q DATA
BW SEL1
BW SEL2
48
47
46
45
44
43
42
41
40
39
38
37
LNA GND
5
32 RESNTR-
LNA IN
6
31 RESNTR+
SW GND
7
30 LO OUT B
LNA VCC
8
29 PLLD VCC
SW GND2
9
28 PLL GND
ATTN
10
27 PLL DATA
MOUT I+
11
26 PLL CLK
MOUT I-
12
25 LE
13
14
15
16
17
18
19
20
21
22
23
24
OSC E
33 LO OUT
OSC B
4
RSSI I
MIX GND
I DATA
34 DO
VCC3
3
IF OUT I
MIX VCC
GND3
35 PLL ENABL
VCC2
2
DCFB I
MOUT Q+
GND2
36 RX ENABL
IN I-
1
IN I+
MOUT Q-
TRANSCEIVERS
11
IN Q+
Pin Out
11-94
Rev C1 010904
RF2908
ATTN
LNA VCC
MIX VCC
MOUT Q-
MOUT Q+
IN Q+
IN Q-
VCC1
VCC2
VCC3
Detailed Functional Block Diagram
10
8
4
1
2
48 47
44
17
20
LNA
39 Q DATA
LNA IN 6
0-25 dB
SW GND1 7
0-20 dB
-12-+12
17dB
42 IF OUT Q
6 dB
-0.5/-20.5
45 DCFB Q
+45°
-45°
SW GND2 9
22 RSSI I
41 VREF
LNA GND 5
40 RSSI Q
PLL ON 35
RX ENABL 36
BW SEL2 37
43 VGC
Chip
Control
21 I DATA
BW SEL1 38
MIX VCC 3
19 IF OUT I
MOUT I+ 11
18 GND3
MOUT I- 12
16 DCFB I
Phase
Detector
Charge Pump
IN I+ 13
IN I- 14
OSC B 23
Ref. Osc.
15 GND2
46 GND1
34 DO
300 kHz
300 kHz
5-bit Counter
/32
7-Bit Counter
/94
OSC E 24
32 33
28
29
PLLD GND
PLLD VCC
7
7-Bit
Latch
7
7-Bit Shift
Register
26 PLL CLK
25 LE
27 PLL DATA
11
TRANSCEIVERS
LO OUT
30 31
LO OUT B
VCO
RESNTR+
902-928
MHz
RESNTR-
Prescaler
32/33
7-Bit Swallow
Counter
0-85
Rev C1 010904
11-95
RF2908
Application Schematic
915MHz
+3.3V REG
Refer to Filter Design Information
for Component Values
L
+3.3V REG
10Ω
C
10Ω
0.01µF
0.01µF
C
L
0.1µF
47pF
+3.3V REG
+3.3V REG
+3.3V REG
10Ω
10Ω
10Ω
0.1µF
47pF
0.1µF
10
8
3
1
2
47 48
47pF
0.1µF
44
47pF
17
0.1µF
39
LNA
6.8nH
47pF
20
6
0-25 dB
7
42 0.27µF
6 dB
45
22
5
41
40
37
56pF
43
Chip
Control
21
4
19
11
18
12
16
C
0.1µF
L
56pF
1µF
38
L
C
17dB
35
36
0.1µF
-12-12dB
+45°
-45°
9
Refer to Filter Design
Information for
Component Values
0-20 dB
-0.5/-20.5
Phase
Detector
Charge Pump
13
14
Ref. Osc.
100pF
300 kHz
5-bit Counter
/32
7-Bit Counter
/94
24
100pF
15
46
34
300 kHz
23
902-928 MHz
30
31
32
11
7-Bit Swallow
Counter
0-85
7
7-Bit
Latch
7
7-Bit Shift
Register
33
28
26
25
27
Prescaler
32/33
VCO
0.27µF
29
0.1µF
6.8nH
TRANSCEIVERS
6.8nH
47pF
2kΩ
10Ω
0.1µF
4.7µF
220pF
22kΩ
Loop Filter
2.2nF
47pF
+3.3V REG
11-96
Rev C1 010904
RF2908
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
J8
IF OUT Q
GC
IF VCC
VREF
C46
1 µF
C21
47 nF
C22
220 nF
C44
68 pF
DCFBQ
Q RSSI
J7
Q DATA
C23
100 nF
L8
10 µH
BW SEL1
46
45
44
43
42
41
40
39
38
37
VGC
VREF
RSSI Q
Q DATA
BW SEL1
BW SEL2
RX 36
ENBL
1
MOUT Q2 MOUT Q+
C40
10 nF
VCC
R6
10 Ω
J1
RF IN
47
IF OUT Q
C41
10 nF
VCC1
T2
5:1
GND1
C42
10 pF
C24
100 nF 48
DCFB Q
50 Ω µstrip
RX ENABL
PLL ENABL
L9
10 µH
IN Q-
J9
Q MIX OUT
BW SEL2
C25
1 nF
IN Q+
C26
470 pF
50 Ω µstrip
C33
10 nF
C34
22 pF
L5
8.2 nH
VCC
R5
10 Ω
C35
10 nF
C36
22 pF
C14
220 pF
R4
33 kΩ
PLL ENABL 35
3 MIX VCC
DO 34
4 MIX GND
LO OUT 33
5 LNA GND
RESNTR- 32
6 LNA IN
RESNTR+ 31
7 SW GND
LO OUT B 30
8 LNA VCC
PLLD VCC 29
9 SW GND2
C15
4.7 nF
C12
Open
50 Ω µstrip
R7
0Ω
C11
47 pF
L3
5.6 nH
C13
Open
J6
LO OUT
PLL VCC
C9
10 nF
C10
22 pF
L2
5.6nH
R3
0Ω
C5
47 pF
R2
1 kΩ
50 Ω µstrip
C6
Open
J5
LO OUTB
C7
Open
PLL GND 28
PLL VCC
C37
10 nF
PLL DATA 27
11 MOUT I+
MOUT IIN I-
GND2
DCFB I
VCC2
GND3
IF OUT I
VCC3
I DATA
RSSI I
OSC B
OSC E
C19 13
100 nF
14
15
16
17
18
19
20
21
22
23
24
50 Ω µstrip
C39
10 pF
T1
5:1
12
C38
10 nF
L6
10 µH
C16
470 pF
C1
33 pF
R7
0Ω
P2-1
C31
100 pF
C32
10 nF
P2-3
P1
Rev C1 010904
P3
1
IF VCC
2
GND
3
GC
P3-1
P3-3
P6
1
DCFBQ
2
GND
3
VREF
R11
27 kΩ
R10
12 kΩ
11
J4
I DATA
P2
P1-3
R12
12 kΩ
IF VCC
J3
IF OUT
P1-1
R8
12 kΩ
LE
I RSSI
C20
220 nF
C30
10 nF
C45
1 µF
PLL CLK
R13
27 kΩ
C43
68 pF
I DCFB
C29
100 pF
R9
27 kΩ
X1
9.6 MHz
C18
100 nF
2908400-
R2
1 kΩ
PLL DATA
LE 25
IF VCC
C28
10 nF
C4
22 pF
C2
68 pF
L7
10 µH
C27
100 pF
C3
10 nF
PLL CLK 26
IN I+
J2
I MIX OUT
10 ATTN
P6-1
P6-3
Q RSSI
2
GND
3
I RSSI
P4-1
NC
P7
1
PLL VCC
2
GND
3
PLL ON
P7-1
P7-3
P5
AMP D-Sub
P4
1
1
DCFBI
2
GND
3
P8
1
ATTN
2
GND
3
RX ENABL
P8-1
P8-3
TRANSCEIVERS
ATTN
1
BW SEL1
2
GND
3
BW SEL2
NC
1
P5-2
2
LE
P5-3
3
PLL DATA
NC
4
NC
5
NC
6
NC
7
P5-8
8
PLL CLK
9
GND
11-97
RF2908
Evaluation Board Layout
Board Size 3.050” x 3.050”
Board Thickness 0.032”, Board Material FR-4, Multi-Layer
Assembly
TRANSCEIVERS
11
11-98
Rev C1 010904
RF2908
Top
Mid 1
TRANSCEIVERS
11
Rev C1 010904
11-99
RF2908
Mid 2
Back
TRANSCEIVERS
11
11-100
Rev C1 010904
RF2908
RF2908 IF Bandwidth Response
65.0
55.0
45.0
Gain (dB)
35.0
25.0
15.0
BW_SEL (0-0)
BW_SEL (0-1)
5.0
BW_SEL (1-0)
BW_SEL (1-1)
-5.0
-15.0
-25.0
-35.0
0.1
1.0
10.0
100.0
IF Frequency (MHz)
TRANSCEIVERS
11
Rev C1 010904
11-101
RF2908
IIP3 versus Voltage Gain
Noise Figure versus Voltage Gain
(Non-Matched Input Z)
40.0
10.0
-40°C
-40°C
+25°C
0.0
+25°C
35.0
+100°C
+100°C
-10.0
30.0
Noise Figure (dB)
IP3 (dB)
-20.0
-30.0
-40.0
-50.0
25.0
20.0
15.0
10.0
-60.0
5.0
-70.0
-80.0
0.0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
Voltage Gain (dB)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
Voltage Gain (dB)
Voltage Gain versus Gain Control Voltage
90.0
-40°C
80.0
+25°C
+100°C
Voltage Gain (dB)
70.0
TRANSCEIVERS
11
60.0
50.0
40.0
30.0
20.0
10.0
0.0
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
Gain Control Voltage (V)
11-102
Rev C1 010904