Page No. : 1/9 RS2258 Second‐Side Regulation Current Mode PWM Power Switcher General Description RS2258 combines a dedicated current mode PWM controller with a high voltage power MOSFET. It is optimized for high performance, low standby power, and cost effective off‐line flyback converter applications in sub 27W range. RS2258 offers complete protection coverage with automatic self‐recovery feature including Cycle‐by‐Cycle current limiting (OCP), over load protection (OLP), VDD over voltage clamp and under voltage lockout (UVLO). Excellent EMI performance is achieved with Orister proprietary frequency Jiggling technique together with soft switching control at the totem pole gate drive output. The tone energy at below 20KHz is minimized in the design and audio noise is eliminated during operation. RS2258 is offered in DIP‐8 package. Features Applications ● Power on Soft Start Reducing MOSFET VDS Stress ● Frequency Jiggling to reduce EMI ● Burst Mode Control For Improved Efficiency and Minimum Standby power Design ● Audio Noise Free Operation ● Fixed 50KHz Switching Frequency ● Internal Synchronized Slope Compensation ● Low VDD Startup Current and Low Operating Current ● Leading Edge Blanking on Current Sense Input ● Good Protection Coverage With Auto Self‐Recovery ◎ VDD Over Voltage Clamp and Under Voltage Lockout with Hysteresis (UVLO) ◎ Line Input Compensated Cycle‐by‐Cycle Over‐current Threshold Setting For Constant Output Power Limiting Over Universal Input Voltage Range ◎ Overload Protection (OLP) ◎ Over Voltage Protection (OVP) ● DIP‐8 Package ● RoHS Compliant and 100% Lead (Pb)‐Free and Green (Halogen Free with Commercial Standard) ● ● ● ● ● ● ● Battery Charger Digital Cameras and camcorder Adaptor PDA power supplies VCR, SVR, STB, DVD & DVCD Player SMPS Set‐Top Box (STB) Power Auxiliary Power Supply for PC and Server Open‐frame SMPS Application Circuits 1 1 L1 C4 T1 VOUT D1 4 - + 2 AC IN C1 C2 R5 R2 D4 C5 R1 3 2 Np D2 R3 C3 C6 R6 Naux GND U2 U1 VDDG VDD FB GND GND 4 1 3 2 R7 R9 C8 DRAIN SENSE DRAIN R4 Ns D3 D5 R8 RS2258 C7 RS431 R10 DS‐RS2258‐09 May, 2010 www.Orister.com Page No. : 2/9 This integrated circuit can be damaged by ESD. Orister Corporation recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Pin Assignment DIP‐8 PACKAGE DIP‐8 PIN 1 2 SYMBOL VDDG VDD 3 FB 4 SENSE 5, 6 DRAIN 7, 8 GND DESCRIPTION Internal Gate Driver Power Supply Pin DC Power Supply Input Pin Feedback input Pin. The PWM duty cycle is determined by voltage level into this pin and the current‐sense signal at Pin 4 Current Sense Input Pin HV MOSFET Drain Pin. The Drain pin is connected to the primary lead of the transformer Ground Pin Ordering Information DEVICE RS2258 Y Z DEVICE CODE Y is package designator : P: DIP‐8 Z is Lead Free designator : P: Commercial Standard, Lead (Pb) Free and Phosphorous (P) Free Package G: Green (Halogen Free with Commercial Standard) DS‐RS2258‐09 May, 2010 www.Orister.com Page No. : 3/9 Block Diagram Absolute Maximum Ratings Parameter Drain Voltage (off state) VDD Voltage VDDG Input Voltage VDD Clamp Continuous Current FB Input Voltage Sense Input Voltage Operating Ambient Temperature Storage Temperature Lead Temperature (soldering, 10sec) ESD Voltage Protection, Human Body Model ESD Voltage Protection, Machine Model Symbol VDRAIN VDD VDDG_IN IVDD_CLAMP VFB_IN VSENSE_IN TOPR TSTG ‐ ‐ ‐ Ratings ‐0.3 to 6ϱ0 ‐0.3 to 30 ‐03 to 30 10 ‐0.3 to 7 ‐0.3 to 7 ‐40 to +85 ‐55 to +150 +260 2 200 Units V V V mA V V o C o C o C KV V NOTE: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and function operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute‐maximum–rated conditions for extended periods may affect device reliability. 2. Caution: Stress above the listed absolute maximum rating may cause permanent damage to the device. * HBM B: 2000V to 3999V Output Power Table DIP‐8 Package 230VAC ±15% Open Frame (Note) 21W 85 to 265VAC Open Frame (Note) 18W Notes: Maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sink, at 50 oC ambient. DS‐RS2258‐09 May, 2010 www.Orister.com Page No. : 4/9 Electrical Characteristics (TA=25°C, VDD=16V, unless otherwise specified) Symbol Istartup IVDD UVLO(ON) UVLO(OFF) OVP(ON) VDD_CLAMP VFB_OPEN IFB_SHORT VTH_0D VTH_PL TD_PL ZFB_IN TSOFTSTART TBLANKING ZSENSE_IN TD_OC VTH_OC FOSC ΔFTEMP ΔF_VDD DMAX FBURST B_VDSS RDS(ON) ΔF_VDD Parameter Test Conditions Supply Voltage (VDD) VDD=14.5V, Measure VDD Start up Current Leakage current into VDD Operation Current VFB=3V VDD Under Voltage Lockout Enter ‐ VDD Under Voltage Lockout Exit(Recovery) ‐ CS=0V, FB=3V Ramp up VDD Over voltage protection voltage until gate clock is off VDD Zener clamp Voltage IDD=10mA Feedback Input Section(FB pin) VFB Open Loop Voltage ‐ Short FB pin to GND and FB pin short circuit current measure current Zero Duty Cycle FB Threshold Voltage ‐ Power Limiting FB Threshold Voltage ‐ Power Limiting Debounce Time ‐ Input Impedance ‐ Current Sense Input(Sense Pin) Soft start time ‐ Leading edge blanking time ‐ Input Impedance ‐ From Over Current Occurs till the Gate drive output Over Current Detection and Control Delay start to turn off Internal Current Limiting Threshold Voltage FB=3.3V Oscillator Normal Oscillation Frequency ‐ Frequency Temperature Stability ‐ Frequency Voltage Stability ‐ Maximum duty cycle FB=3.3V, CS=0V Burst Mode Base Frequency ‐ Power MOSFET Section MOSFET Drain Source Breakdown Voltage ‐ Static Drain to Source On Resistance VGS=10V, IDS=1A Frequency Frequency Modulation range /Base ͘ ‐ frequency Min Typ. Max Unit ‐ 3.0 20 uA ‐ 14.2 8.5 2.0 15.8 9.0 ‐ 16.0 9.5 mA V V 27.0 28.5 30.0 V ‐ 30 ‐ V 5.4 5.6 6.0 V ‐ 1.55 ‐ mA ‐ ‐ ‐ ‐ 0.8 3.7 50 4 ‐ ‐ ‐ ‐ V V ms KΩ ‐ ‐ ‐ 4 300 40 ‐ ‐ ‐ ms ns KΩ ‐ 120 ‐ ns 0.76 0.8 0.82 V 45 ‐ ‐ 70 ‐ 50 5 5 80 22 55 ‐ ‐ 90 ‐ KHz % % % KHz ‐ ‐ 6ϱ0 3.0 ‐ 3.6 V Ω ‐4 ‐ 4 % DS‐RS2258‐09 May, 2010 www.Orister.com Page No. : 5/9 Detail Description The RS2258 is a low power off‐line SMPS Switcher optimized for off‐line flyback converter applications in sub 10W power range. The burst mode control greatly reduces the standby power consumption and helps the design easily to meet the international power conservation requirements. Startup Current and Start up Control Startup current of RS2258 is designed to be very low so that VDD could be charged up above UVLO threshold level and device starts up quickly. A large value startup resistor can therefore be used to minimize the power loss yet achieve a reliable startup in application. For AC/DC adaptor with universal input range design, a 2MΩ, 1/8W startup resistor could be used together with a VDD capacitor to provide a fast startup and yet low power dissipation design solution. Operation current The Operation current of RS2258 is low at 2mA. Good efficient is achieved with RS2258 low operating current together with the ‘Extended burst mode’ control features. Soft Start RS2258 features an internal 4 ms soft start to soften the electrical stress occurring in the power supply during startup. It is activated during the power on sequence. As soon as VDD reaches UVLO(OFF), the peak current is gradually increased from nearly zero to the maximum level of 0.77V. Every restart up is followed by a soft start. Frequency Jiggling Mode for EMI improvement The frequency Jiggling Mode (switching frequency modulation) is implemented in RS2258. The oscillation frequency is modulated so that the tone energy is spread out. The spread spectrum minimizes the conduction band EMI and therefore eases the system design. Extended Burst Mode Operation At light load or zero load condition, most of the power dissipation in a switching mode power supply is from switching loss on the MOSFET, the core loss of the transformer and the loss on the snubber circuit. The magnitude of power loss is in proportion to the switching frequency. Lower switching frequency leads to the reduction on the power loss and thus conserves the energy. The switching frequency is internally adjusted at no load or light load condition. The switch frequency reduces at light/no load condition to improve the conversion efficiency. At light load or no load condition, the FB input drops below burst mode threshold level and device enters Burst Mode control. The Gate drive output switches only when VDD voltage drops below a preset level and FB input is active to output an on state to minimize the switching loss and reduce the standby power consumption to the greatest extend. The switching frequency control also eliminates the audio noise at any loading conditions. Oscillator Operation The switching frequency of RS2258 is internally fixed at 50 KHz. No external frequency setting components are required for PCB design simplification. Current Sensing and Leading Edge Blanking Cycle‐by‐Cycle current limiting is offered in RS2258 current mode PWM control. The switch current is detected by sense resistor into the sense pin. An internal leading edge blank circuit chops off the sensed voltage spike at initial internal power MOSFET on state due to snubber diode reverse recovery and surge gate current of internal power MOSFET so that the external RC filtering on sense input is no longer needed. The current limiting comparator is disabled and cannot turn off the internal power MOSFET during the blanking period. The PWM duty cycle is determined by the current sense input voltage and the FB input voltage. DS‐RS2258‐09 May, 2010 www.Orister.com Page No. : 6/9 Internal synchronized Slope Compensation Built‐in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM generation. This greatly improves the close loop stability at CCM and prevents the sub‐harmonic oscillation and thus reduces the output ripple voltage. Drive The internal power MOSFET in RS2258 is driven by a dedicated gate driver for power switch control. Too weak the gate driving strength results in higher conduction and switch loss of MOSFET while too strong gate drive results the compromise of EMI. A good tradeoff is achieved through the built‐in totem pole gate design with right output strength and dead time control. The low idle loss and good EMI system design is easier to achieve with this dedicated control scheme. In addition to the gate drive control scheme mentioned, the gate drive strength can also be adjusted externally by a resistor connected between VDD and VDDG, the falling edge of the Drain output can be well controlled. It provides great flexibility for system EMI design. Protection Controls Good power supply system reliability is achieved with its rich protection features including Cycle‐by‐Cycle current limiting (OCP), Over Load Protection (OLP) and over voltage clamp, Under Voltage Lockout on VDD (UVLO). With Orister Proprietary technology, the OCP is line voltage compensated to achieve constant output power limit over the universal input voltage range. At overload condition when FB input voltage exceeds power limit threshold value for more than TD_PL, control circuit reacts to shut down the switcher. Switcher restarts when VDD voltage drops below UVLO limit. VDD is supplied by transformer auxiliary winding output. It is clamped when VDD is higher than 30V. The output of RS2258 is shut down when VDD drops below UVLO(ON) limit and Switcher enters power on start‐up sequence thereafter. DS‐RS2258‐09 May, 2010 www.Orister.com Page No. : 7/9 DIP‐8 Dimension NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS‐001. DS‐RS2258‐09 May, 2010 www.Orister.com Page No. : 8/9 Soldering Methods for Orister’s Products 1. Storage environment: Temperature=10oC~35oC Humidity=65%±15% 2. Reflow soldering of surface‐mount devices Figure 1: Temperature profile tP Critical Zone TL to TP TP Ramp-up TL tL Temperature Tsmax Tsmin tS Preheat 25 Ramp-down t 25oC to Peak Time Profile Feature Average ramp‐up rate (TL to TP) Sn‐Pb Eutectic Assembly o <3 C/sec Pb‐Free Assembly <3oC/sec ‐ Temperature Min (Tsmin) 100oC 150oC ‐ Temperature Max (Tsmax) 150oC 200oC 60~120 sec 60~180 sec Preheat ‐ Time (min to max) (ts) Tsmax to TL ‐ Ramp‐up Rate o <3 C/sec <3 C/sec Time maintained above: ‐ Temperature (TL) ‐ Time (tL) o 217oC 183 C 60~150 sec Peak Temperature (TP) Time within 5oC of actual Peak Temperature (tP) Ramp‐down Rate Time 25oC to Peak Temperature o o o 60~150 sec 240 C +0/‐5 C 260oC +0/‐5oC 10~30 sec 20~40 sec <6oC/sec <6oC/sec <6 minutes <8 minutes Peak temperature Dipping time 3. Flow (wave) soldering (solder dipping) Products Pb devices. Pb‐Free devices. o o 245 C ±5 C o o 260 C +0/‐5 C 5sec ±1sec 5sec ±1sec DS‐RS2258‐09 May, 2010 www.Orister.com Page No. : 9/9 Important Notice: © Orister Corporation Orister cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an Orister product. No circuit patent licenses, copyrights, mask work rights, or other intellectual property rights are implied. Orister reserves the right to make changes to their products or specifications or to discontinue any product or service without notice. Except as provided in Orister’s terms and conditions of sale, Orister assumes no liability whatsoever, and Orister disclaims any express or implied warranty relating to the sale and/or use of Orister products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent Orister deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed. Orister and the Orister logo are trademarks of Orister Corporation. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders. DS‐RS2258‐09 May, 2010 www.Orister.com