SPANSION S29PL256N80FFWW02

S29PL-N MirrorBit™ Flash Family
29PL256N, S29PL127N, S29PL129N,
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
Notice to Readers: This document indicates states the current technical
specifications regarding the Spansion product(s) described herein. The
Preliminary status of this document indicates that a product qualification has
been completed, and that initial production has begun. Due to the phases of
the manufacturing process that require maintaining efficiency and quality, this
document may be revised by subsequent versions or modifications due to
changes in technical specifications.
Publication Number S29PL-N_00 Revision A Amendment 4 Issue Date November 23, 2005
P r e l i m i n a r y
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product
life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon
Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO range. Changes
may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
S29PL-N MirrorBit™ Flash Family
S29PL256N, S29PL127N, S29PL129N,
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
The Spansion S29PL-N is the latest generation 3.0-Volt page mode read family fabricated using the 110 nm MirrorbitTM
Flash process technology. These 8-word page-mode Flash devices are capable of performing simultaneous read and write
operations with zero latency on two separate banks. These devices offer fast page access times of 25 to 30 ns, with
corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to operate without wait states. The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and
CE2#) that allow each half of the memory space to be controlled separately.
Distinctive Characteristics
Architectural Advantages
Hardware Features
„
32-Word Write Buffer
„
Dual Chip Enable Inputs (only for S29PL129N)
— Two CE# inputs control selection of each half of the
memory space
„
Single Power Supply Operation
— Full Voltage range of 2.7 – 3.6 V read, erase, and
program operations for battery-powered applications
— Voltage range of 2.7 – 3.1 V valid for PL-N MCP
products
„
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
„
4-Bank Sector Architecture with Top and Bottom
Boot Blocks
„
256-Word Secured Silicon Sector Region
— Up to 128 factory-locked words
— Up to 128 customer-lockable words
„
Manufactured on 0.11 µm Process Technology
„
Data Retention of 20 years Typical
„
Cycling Endurance of 100,000 Cycles per Sector
Typical
„
WP#/ACC (Write Protect/Acceleration) Input
— At VIL, hardware level protection for the first and last
two 32 Kword sectors.
— At VIH, allows the use of DYB/PPB sector protection
— At VHH, provides accelerated programming in a
factory setting
„
Dual Boot and No Boot Options
„
Low VCC Write Inhibit
Security Features
„
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors to prevent
program or erase operations within that sector
— Sectors can be locked and unlocked in-system at VCC
level
„
Password Sector Protection
— A sophisticated sector protection method locks
combinations of individual sectors to prevent program
or erase operations within that sector using a user
defined 64-bit password
Performance Characteristics
Read Access Times (@ 30 pF, Industrial Temp.)
Typical Program & Erase Times (typical values) (See Note)
Random Access Time, ns (tACC)
65
70
80
Typical Word
40 µs
Page Access Time, ns (tPACC)
25
30
30
Typical Effective Word (32 words in buffer)
9.4 µs
Max CE# Access Time, ns (tCE)
65
70
80
Accelerated Write Buffer Program
Max OE# Access Time, ns (tOE)
25
30
30
Typical Sector Erase Time (32-Kword Sector)
Typical Sector Erase Time (128-Kword Sector)
6 µs
300 ms
1.6 s
Note: : Typical program and erase times assume the following
conditions: 25°C, 3.0 V VCC, 10,000 cycles; checkerboard data pattern.
Current Consumption (typical values)
8-Word Page Read
6 mA
Simultaneous Read/Write
65 mA
Program/Erase
25 mA
Standby
20 µA
S29PL-N
256
129
127
VBH064
8.0 x 11.6 mm,
64-ball
Package Options
VBH084
8.0 x 11.6 mm,
84-ball
„
„
„
Publication Number S29PL-N_00 Revision A Amendment 4 Issue Date November 23, 2005
LAA064
11 x 13 mm, 64-ball
Fortified BGA
„
„
P r e l i m i n a r y
Contents
1
2
3
4
5
6
7
8
9
2
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Input/Output Descriptions and Logic Symbols . . . . . . . . . . . . . . . . . . . . . . 7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Connection Diagrams/Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Special Handling Instructions for FBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 VBH084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2.1 Connection Diagram – S29PL256N MCP Compatible Package. . . . . . . . . . . . . . . . . .9
4.2.2 Physical Dimensions – VBH084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 VBH064, 8 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 Connection Diagram – S29PL127N MCP Compatible Package . . . . . . . . . . . . . . . . . 11
4.3.2 Connection Diagram – S29PL129N MCP Compatible Package . . . . . . . . . . . . . . . . . 12
4.3.3 Physical Dimensions – VBH064, 8 x 11.6 mm – S29PL-N . . . . . . . . . . . . . . . . . . . . . . 13
4.3.4 Connection Diagram – S29PL-N Fortified Ball Grid Array Package . . . . . . . . . . . . . 14
4.3.5 Physical Dimensions – LAA064, 11 x 13 mm – S29PL-N . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 MCP Look-Ahead Connection Diagram/Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 16
4.4.1 For All Page Mode MCPs Comprised of Code Flash + (p)SRAM + Data Flash . . . . . . 16
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1.1 Dual Chip Enable Device Description and Operation (PL129N Only) . . . . . . . . . . . 21
7.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.2.1 Non-Page Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.2.2 Page Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.3 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7.4 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7.4.1 Single Word Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7.4.2 Write Buffer Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7.4.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7.4.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
7.4.5 Erase Suspend/Erase Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7.4.7 Accelerated Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4.8 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7.4.9 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
7.6 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
7.7 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
7.8 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . 48
8.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
8.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
8.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
8.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
8.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.7.1 WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.7.2 Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.7.3 Write Pulse Glitch Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.7.4 Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
10
11
12
13
14
9.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . 56
10.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
10.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
10.3 Secured Silicon Sector Entry and Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . .57
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.6 VCC Power Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11.7.1 DC Characteristics (VCC = 2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11.7.2 DC Characteristics (VCC = 2.7 V to 3.1 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
11.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.8.1 Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.8.2 Read Operation Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.8.3 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
11.8.4 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
11.8.5 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
11.8.6 BGA Ball Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
12.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Commonly Used Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
3
P r e l i m i n a r y
Tables
Table 2.1
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6.1
PL256N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6.2
PL127N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6.3
PL129N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7.1
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7.2
Dual Chip Enable Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7.3
Word Selection within a Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7.4
Autoselect Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7.5
Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7.6
Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7.7
Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7.8
Write Buffer Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7.9
Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7.10 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7.11 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7.12 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7.13 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7.14 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7.15 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7.16 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7.17 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7.18 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 7.19 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 8.1
Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 8.2
Sector Protection Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 10.1
Secured Silicon Sector Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 10.2 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 10.3 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 10.4 Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 12.1 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 12.2 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 12.3 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 12.4 System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 12.5 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 12.6 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Figures
Figure 2.1
Figure 4.1
Figure 4.2
Logic Symbols – PL256N, PL129N, and PL127N .........................................................7
Connection Diagram – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)..........................9
Physical Dimensions – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)........................ 10
Figure 4.3
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N) ....................... 11
Figure 4.4
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL129N) ....................... 12
Figure 4.5
Physical Dimensions – 64-Ball Fine-Pitch Ball Grid Array (S29PL-N)...........................................13
Figure 4.6
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N, S29PL256N) ............14
Figure 4.7
Physical Dimensions – 64-Ball Fortified Ball Grid Array (S29PL-N)..............................................15
Figure 4.8
MCP Look-Ahead Diagram .................................................................................... 16
Figure 7.1
Figure 7.2
Single Word Program Operation ............................................................................ 27
Write Buffer Programming Operation ..................................................................... 30
Figure 7.3
Sector Erase Operation ........................................................................................ 32
Figure 7.4
Write Operation Status Flowchart .......................................................................... 39
Figure 7.5
Simultaneous Operation Block Diagram for S29PL256N and S29PL127N ..................... 43
Figure 7.6
Simultaneous Operation Block Diagram for S29PL129N ............................................ 44
Figure 8.1
Figure 8.2
Advanced Sector Protection/Unprotection ............................................................... 48
Lock Register Program Algorithm........................................................................... 52
Figure 11.1
Figure 11.2
Maximum Negative Overshoot Waveform ............................................................... 59
Maximum Positive Overshoot Waveform ................................................................. 59
Figure 11.3
Test Setup ......................................................................................................... 60
Figure 11.4
Input Waveforms and Measurement Levels............................................................. 61
Figure 11.5
VCC Power-Up Diagram ........................................................................................ 61
Figure 11.6
Read Operation Timings ....................................................................................... 64
Figure 11.7
Page Read Operation Timings ............................................................................... 65
Figure 11.8
Reset Timings..................................................................................................... 65
Figure 11.9
Program Operation Timings .................................................................................. 67
Figure 11.10 Accelerated Program Timing Diagram .................................................................... 67
Figure 11.11 Chip/Sector Erase Operation Timings ..................................................................... 68
Figure 11.12 Back-to-back Read/Write Cycle Timings ................................................................. 68
Figure 11.13 Data# Polling Timings (During Embedded Algorithms).............................................. 69
Figure 11.14 Toggle Bit Timings (During Embedded Algorithms)................................................... 69
Figure 11.15 DQ2 vs. DQ6 ...................................................................................................... 70
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
5
P r e l i m i n a r y
1
Ordering Information
The ordering part number is formed by a valid combination of the following:
S29PL
256
N
65 GA W W0 0
PACKING TYPE
0
= Tray
2
= 7-inch Tape and Reel
3
= 13-inch Tape and Reel
MODEL NUMBER
(VCC Range)
W0
= 2.7 – 3.1 V
00
= 2.7 – 3.6 V
TEMPERATURE RANGE
W
= Wireless (–25°C to +85°C)
I
= Industrial (–40°C to +85°C)
PACKAGE TYPE AND MATERIAL
FA
= Fortified BGA, Lead (Pb)-free Compliant package
FF
= Fortified BGA, Lead (Pb)-free package
GA
= Very Thin Fine-Pitch MCP-compatible BGA,
Lead (Pb)-free Compliant Package
GF
= Very Thin Fine-Pitch MCP-compatible BGA,
Lead (Pb)-free Package
SPEED OPTION
65
= 65 ns
70
= 70 ns
80
= 80 ns
PROCESS TECHNOLOGY
N
= 110 nm MirrorBit™ Technology
FLASH DENSITY
256
= 256 Mb
129
= 128 Mb (Dual CE#)
127
= 128 Mb (Single CE#)
DEVICE FAMILY
S29PL = 3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory
Valid Combinations
Base Ordering
Part Number
Package Type, Material,
& Temperature Range
Model
Number
Packing
Type
65, 70
GAW, GFW
W0
0, 2, 3
(Note 1)
2.7 – 3.1 V
80
FAW, FFW
00
0, 2, 3
(Note 1)
2.7 – 3.6 V
S29PL256N
S29PL127N
S29PL129N
S29PL256N,
S29PL127N
VIO Range
Speed
Option
Package Type
(Note 2)
VBH084 8.0 x 11.6 mm
84-ball MCP-Compatible (FBGA)
VBH064 8.0 x 11.6 mm
64-ball MCP-Compatible (FBGA)
LAA064 11x13 mm
64-Ball (Fortified BGA)
Notes:
1.
2.
6
Type 0 is standard. Specify other options as required.
BGA package marking omits leading S29 and packing
type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult your local sales
office to confirm availability of specific valid combinations
and to check on newly released combinations.
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
2
Input/Output Descriptions and Logic Symbols
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1
Symbol
Input/Output Descriptions
Type
Description
Amax – A0
Input
Address bus
DQ15 – DQ0
I/O
16-bit data inputs/outputs/float
CE#
Input
Chip Enable input
OE#
Input
Output Enable input
WE#
Input
Write Enable
VSS
Supply
Device ground
NC
Not connected
Pin Not Connected Internally
RY/BY#
Output
Ready/Busy output and open drain.
When RY/BY#= VIH, the device is ready to accept read operations and commands.
When RY/BY#= VOL, the device is either executing an embedded algorithm or the device
is executing a hardware reset operation.
VCC
Supply
Device Power Supply
RESET#
Input
Hardware reset pin
CE1#, CE2#
Input
Chip Enable inputs for S29PL129 device
max +1
22
Amax–A0
16
DQ15 – DQ0
CE#
A21 – A0
CE1#
OE#
CE2#
WE#
OE#
WP#/ACC
WE#
RY/BY#
RESET#
VCC
16
DQ15 – DQ0
WP#/ACC
RY/BY#
RESET#
VCC
Notes:
1.
Amax = 23 for the PL256N and 22 for the PL127N.
Logic Symbol – PL256N and PL127N
Figure 2.1
November 23, 2005 S29PL-N_00_A4
Logic Symbol – PL129N
Logic Symbols – PL256N, PL129N, and PL127N
S29PL-N MirrorBit™ Flash Family
7
P r e l i m i n a r y
3
Block Diagram
DQ15–DQ0
RY/BY# (See Note)
VCC
VSS
Sector
Switches
Input/Output
Buffers
RESET#
Erase Voltage
Generator
WE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
Timer
Amax – A3
Y-Decoder
Address Latch
VCC Detector
X-Decoder
Data Latch
Y-Gating
Cell Matrix
A2–A0
Notes:
1.
2.
3.
8
RY/BY# is an open drain output.
Amax = A23 (PL256N), A22 (PL127N), A21 (PL129N).
PL129N has two CE# pins CE1# and CE2#.
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
4
Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S29PL256N.
4.1
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of time.
4.2
VBH084, 8.0 x 11.6 mm
4.2.1 Connection Diagram – S29PL256N MCP Compatible Package
A10
A1
NC
B2
B3
B4
B5
B6
B7
B8
B9
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
C2
C3
C4
C5
C6
C7
C8
C9
RFU
A7
RFU
WP#/ACC
WE#
A8
A11
RFU
D2
D3
D4
D5
D6
D7
D8
D9
A3
A6
RFU
RST#
RFU
A19
A12
A15
E2
E3
E4
E5
E6
E7
E8
E9
A2
A5
A18
RY/BY#
A20
A9
A13
A21
F2
F3
F4
F5
F6
F7
F8
F9
A1
A4
A17
RFU
A23
A10
A14
A22
G2
G3
G4
G5
G6
G7
G8
G9
A0
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J2
J3
J4
J5
J6
J7
J8
RFU
DQ0
DQ10
VCC
RFU
DQ12
DQ7
VSS
K2
K3
K4
K5
K6
K7
K8
K9
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
L2
L3
L4
L5
L6
L7
L8
L9
RFU
RFU
RFU
VCC
RFU
RFU
RFU
RFU
NC
Legend
Reserved for
Future Use
J9
M1
M10
NC
NC
Notes:
1.
2.
Top view—balls facing down.
Recommended for wireless applications
Figure 4.1
November 23, 2005 S29PL-N_00_A4
Connection Diagram – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)
S29PL-N MirrorBit™ Flash Family
9
P r e l i m i n a r y
4.2.2 Physical Dimensions – VBH084, 8.0 x 11.6 mm
0.05 C
(2X)
D
D1
A
e
10
9
e
7
8
SE
7
6
E1
E
5
4
3
2
1
M
A1 CORNER
INDEX MARK
L
K
B
10
H
G
F
E
SD
6
0.05 C
(2X)
J
D
C
B
A
A1 CORNER
7
NXφb
φ 0.08 M C
TOP VIEW
φ 0.15 M C A B
BOTTOM VIEW
0.10 C
A2
A
A1
C
0.08 C
SEATING PLANE
SIDE VIEW
NOTES:
PACKAGE
VBH 084
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
11.60 mm x 8.00 mm NOM
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.76
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
NOTE
OVERALL THICKNESS
BALL HEIGHT
11.60 BSC.
BODY SIZE
E
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
BALL FOOTPRINT
E1
7.20 BSC.
BALL FOOTPRINT
MD
12
ROW MATRIX SIZE D DIRECTION
ME
10
ROW MATRIX SIZE E DIRECTION
N
84
TOTAL BALL COUNT
0.33
---
0.43
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
(A2-A9, B10-L10,
M2-M9, B1-L1)
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
BALL DIAMETER
e
DEPOPULATED SOLDER BALLS
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
BODY THICKNESS
D
φb
4.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
Note: Recommended for wireless applications
Figure 4.2 Physical Dimensions – 84-ball Fine-Pitch Ball Grid Array (S29PL256N)
10
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
4.3
VBH064, 8 x 11.6 mm
4.3.1 Connection Diagram – S29PL127N MCP Compatible Package
A1
A10
NC
NC
B5
B7
RFU
RFU
Reserved for
Future Use
C3
C4
C5
C6
C7
C8
A7
RFU
WP/ACC
WE#
A8
A11
D2
D3
D4
D5
D6
D7
D8
D9
A3
A6
RFU
RST#
RFU
A19
A12
A15
E5
E6
E7
E8
E9
RY/BY#
A20
A9
A13
A21
F4
F7
F8
F9
A17
A10
A14
A22
E2
E3
E4
A2
A5
A18
F2
F3
A1
A4
G2
G3
G4
G7
G8
G9
A0
VSS
DQ1
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H2
CE1#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J2
J3
J4
J5
J6
J7
J8
J9
RFU
DQ0
DQ10
VCC
RFU
DQ12
DQ7
VSS
K3
K4
K5
K6
K7
K8
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
L5
L6
RFU
RFU
Legend
No Connection
M1
M10
NC
NC
Notes:
1.
2.
Top view—balls facing down.
Recommended for wireless applications
Figure 4.3
November 23, 2005 S29PL-N_00_A4
Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N)
S29PL-N MirrorBit™ Flash Family
11
P r e l i m i n a r y
4.3.2 Connection Diagram – S29PL129N MCP Compatible Package
A1
A10
NC
NC
B5
B7
RFU
RFU
Reserved for
Future Use
C3
C4
C5
C6
C7
C8
A7
RFU
WP/ACC
WE#
A8
A11
D2
D3
D4
D5
D6
D7
D8
D9
A3
A6
RFU
RST#
RFU
A19
A12
A15
E5
E6
E7
E8
E9
RY/BY#
A20
A9
A13
A21
E2
E3
E4
A2
A5
A18
F2
F3
F4
F7
F8
F9
A1
A4
A17
A10
A14
CE2#
G2
G3
G4
G7
G8
G9
A0
VSS
DQ1
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H2
CE1#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J2
J3
J4
J5
J6
J7
J8
J9
RFU
DQ0
DQ10
VCC
RFU
DQ12
DQ7
VSS
K3
K4
K5
K6
K7
K8
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
L5
L6
RFU
RFU
Legend
No Connection
M1
M10
NC
NC
Notes:
1.
2.
Top view—balls facing down.
Recommended for wireless applications
Figure 4.4 Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL129N)
12
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
4.3.3 Physical Dimensions – VBH064, 8 x 11.6 mm – S29PL-N
0.05 C
(2X)
D
D1
A
e
10
9
e
7
8
SE
7
6
E1
E
5
4
3
2
1
M
A1 CORNER
INDEX MARK
L
K
B
10
H
G
F
E
SD
6
0.05 C
(2X)
J
D
C
B
A
A1 CORNER
7
NXφb
φ 0.08 M C
TOP VIEW
φ 0.15 M C A B
BOTTOM VIEW
0.10 C
A2
A
A1
C
0.08 C
SEATING PLANE
SIDE VIEW
NOTES:
PACKAGE
VBH 064
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
11.60 mm x 8.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.76
NOTE
OVERALL THICKNESS
BALL HEIGHT
11.60 BSC.
BODY SIZE
E
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
BALL FOOTPRINT
E1
7.20 BSC.
MD
12
ROW MATRIX SIZE D DIRECTION
ME
10
ROW MATRIX SIZE E DIRECTION
N
64
0.33
---
BALL FOOTPRINT
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
TOTAL BALL COUNT
0.43
BALL DIAMETER
e
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
(A2-9,B1-4,B7-10,C1-K1,
M2-9,C10-K10,L1-4,L7-10,
G5-6,F5-6)
DEPOPULATED SOLDER BALLS
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
BODY THICKNESS
D
φb
4.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3330 \ 16-038.25b
Note: Recommended for wireless applications
Figure 4.5 Physical Dimensions – 64-Ball Fine-Pitch Ball Grid Array (S29PL-N)
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
13
P r e l i m i n a r y
4.3.4 Connection Diagram – S29PL-N Fortified Ball Grid Array Package
A8
B8
C8
D8
E8
F8
G8
H8
NC
A22
A23
VCC
VSS
NC
NC
NC
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
RFU
DQ15
VSS
A6
B6
C6
D6
E6
F6
G6
H6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
A21
A19
DQ5
DQ12
VCC
DQ4
C4
D4
E4
F4
G4
H4
A18
A20
DQ2
DQ10
DQ11
DQ3
WE#
A4
RESET#
B4
RY/BY# WP#/ACC
A3
B3
C3
D3
E3
F3
G3
H3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A2
B2
C2
D2
E2
F2
G2
H2
A3
A4
A2
A1
A0
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
NC
NC
NC
NC
NC
RFU
NC
NC
Notes:
1.
2.
Top view—balls facing down.
A23 is NC on PL127N.
Figure 4.6 Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N, S29PL256N)
14
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
4.3.5 Physical Dimensions – LAA064, 11 x 13 mm – S29PL-N
Note: Recommended for automotive applications
Figure 4.7 Physical Dimensions – 64-Ball Fortified Ball Grid Array (S29PL-N)
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
15
P r e l i m i n a r y
4.4
MCP Look-Ahead Connection Diagram/Physical Dimensions
4.4.1 For All Page Mode MCPs Comprised of Code Flash + (p)SRAM + Data Flash
A1
A2
A9
A10
NC
NC
NC
NC
B1
B2
B9
B10
NC
NC
NC
C2
C3
C4
RFU
VSS
RFU
D2
D3
RFU
A7
D4
C5
C6
F2-CE# F-VCC or
(N-VCC)
D5
R-LB# WP#/ACC
E2
E3
E4
A3
A6
R-UB#
F2
F3
F4
F5
A2
A5
A18
F-RY/BY#
G2
G3
G4
A4
A17 R2-CE1# or
(N-WE#)
E5
C7
C8
C9
N-PRE
N-ALE#
N-CLE
NC
Legend:
X
RFU
(Reserved for
Future Use)
X
Code Flash Only
D6
D7
D8
D9
WE#
A8
A11
N1-CE#
X
MirrorBit Data
Only
E7
E8
E9
A19
A12
A15
F6
F7
F8
F9
A20
A9
A13
A21
G6
G7
G8
G9
X
A23
A10
A14
A22
Flash/xRAM
Shared
E6
F-RST# R1-CE2
X
A1
G5
H2
H3
H4
A0
VSS
DQ1
J2
J3
J4
J5
F1-CE#
OE#
DQ9
DQ3
H5
H7
H8
H9
DQ6
A24
A16
J6
J7
J8
J9
DQ4
DQ13
DQ15
RFU
H6
R2-VCC R2-CE2 or
(or N-VCC) (N-RE#)
Flash/Data
Shared
X
pSRAM Only
X
xRAM Shared
K2
K3
K4
K5
K6
K7
K8
K9
R1-CE1#
DQ0
DQ10
F-VCC
R1-VCC
DQ12
DQ7
VSS
L2
L2
L3
L4
L5
L6
L7
L8
L9
R1-VCC
DQ8
DQ2
DQ11
A25
DQ5
DQ14
N-WP#
M2
M3
M4
M5
M6
M7
M8
M9
A27
A26
VSS
F-VCC
F-VIO
RFU
X
NAND or pSRAM
X
NAND
N2-CE# R-VCCQ
N1
N2
N9
N10
NC
NC
NC
NC
P1
P2
P9
P10
NC
NC
NC
NC
Notes:
1.
2.
3.
F1 and F2 denote XIP/Code Flash, while F3 and F4 denote Data/Companion Flash.
In addition to being defined as F2-CE#, Ball C5 can also be assigned as F1-CE2# for code flash that has two chip enable
signals.
F-VIO is RFU on the PL-N product family.
Figure 4.8
16
MCP Look-Ahead Diagram
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
To provide customers with a migration path to higher densities, as well as the option to stack
more die in a package, Spansion has prepared a standard pinout that supports:
„
NOR Flash and SRAM densities up to 4 Gb
„
NOR Flash and PSRAM densities up to 4 Gb
„
NOR Flash and PSRAM and Data Storage densities up to 4 Gb
The signal locations of the resultant MCP device are shown above. Note that for different densities, the actual package outline can vary. However, any pinout in any MCP is a subset of the pinout
shown above.
In some cases, there may be outrigger balls in locations outside the grid shown above. In such
cases, the user is advised to treat these as RFUs, and not connect them to any other signal.
In case of any further inquiries about the above look-ahead pinout, please see the application
note, Design-in Scalable Wireless Solutions with Spansion Products, or contact a Spansion sales
office.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
17
P r e l i m i n a r y
5
Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
„ Using the Operation Status Bits in AMD Devices
„ Simultaneous Read/Write vs. Erase Suspend/Resume
„ MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
„ Design-In Scalable Wireless Solutions with Spansion Products
„ Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
„ Spansion Low-Level Drivers
„ Enhanced Flash Drivers
„ Flash File System
CAD Modeling Support
„ VHDL and Verilog
„ IBIS
„ ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support:
Email
US and Canada: [email protected]
Asia Pacific: [email protected]
Europe, Middle East, and Africa
Japan: http://edevice.fujitsu.com/jp/support/tech/#b7
Frequently Asked Questions (FAQ)
http://ask.amd.com/
http://edevice.fujitsu.com/jp/support/tech/#b7
Phone
US: (408) 749-5703
Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453
Sunnyvale, CA 94088-3453, USA
Telephone: 408-962-2500 or
1-866-SPANSION
Spansion Japan Limited
4-33-4 Nishi Shinjuku, Shinjuku-ku
Tokyo, 160-0023
Telephone: +81-3-5302-2200
Facsimile: +81-3-5302-2674
http://www.spansion.com
18
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
6
Product Overview
The S29PLxxxN family consists of 256 and 128 Mb, 3.0 volts-only, simultaneous read/write
page-mode read Flash devices that are optimized for wireless designs of today that demand large
storage array and rich functionality, while requiring low power consumption. These products also
offer 32-word buffer for programming with program and erase suspend/resume functionality. Additional features include:
„ Advanced Sector Protection methods for protecting an individual or group of sectors as required,
„ 256-word of secured silicon area for storing customer and factory secured information
„ Simultaneous Read/Write operation
6.1
Memory Map
The S29PL-N devices consist of 4 banks organized as shown in Tables 6.1, 6.2, and 6.3.
48
15
D
4 MB
4
SA02
010000h-017FFFh
64
SA03
018000h-01FFFFh
256
SA04
020000h-03FFFFh
1E0000h-1FFFFFh
SA19
200000h-21FFFFh
Notes
Sector Starting Address –
Sector Ending Address
Sector Starting Address Sector Ending Address
(see note)
…
SA018
256
…
256
…
…
008000h-00FFFFh
64
256
SA66
7E0000h-7FFFFFh
256
SA67
800000h-81FFFFh
…
12 MB
48
000000h-007FFFh
SA01
256
SA114
DE0000h-DFFFFFh
256
SA115
E00000h-E1FFFFh
…
C
12 MB
SA00
64
…
B
64
…
15
Address Range
…
4 MB
A
Sector/
Sector Range
…
4
Sector Size
(KB)
…
Sector
Count
PL256N Sector and Memory Address Map
…
Bank
Size
Bank
Table 6.1
256
SA129
FC0000h-FDFFFFh
64
SA130
FE0000h-FE7FFFh
64
SA131
FE8000h-FEFFFFh
64
SA132
FF0000h-FF7FFFh
64
SA133
FF8000h-FFFFFFh
First Sector, Sector Starting Address Last Sector, Sector Ending Address
(see note)
First Sector, Sector Starting Address Last Sector, Sector Ending Address
(see note)
Sector Starting Address Sector Ending Address
(see note)
Sector Starting Address Sector Ending Address
Note: Ellipses indicate that other addresses in sector range follow the same pattern.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
19
P r e l i m i n a r y
Table 6.2
6 MB
24
7
D
2 MB
4
64
SA03
018000h-01FFFFh
256
SA04
020000h-03FFFFh
256
SA10
0E0000h-0FFFFFh
256
SA11
100000h-11FFFFh
Notes
Sector Starting Address Sector Ending Address
Sector Starting Address –
Sector Ending Address
(see note)
…
010000h-017FFFh
…
SA02
…
24
008000h-00FFFFh
64
256
SA34
3E0000h-3FFFFFh
256
SA35
400000h-41FFFFh
…
C
6 MB
000000h-007FFFh
SA01
256
SA58
6E0000h-6FFFFFh
256
SA59
700000h-71FFFFh
…
B
SA00
64
…
7
64
…
2 MB
Address Range
…
A
Sector/
Sector Range
…
4
Sector Size
(KB)
…
Sector
Count
…
Bank
Size
…
Bank
PL127N Sector and Memory Address Map
256
SA65
7C0000h-7DFFFFh
64
SA66
7E0000h-7E7FFFh
64
SA67
7E80000h-7EFFFFh
64
SA68
7F0000h-7F7FFFh
64
SA69
7F8000h-7FFFFFh
First Sector, Sector Starting Address Last Sector, Sector Ending Address
(see note)
First Sector, Sector Starting Address Last Sector, Sector Ending Address
(see note)
Sector Starting Address Sector Ending Address
(see note)
Sector Starting Address Sector Ending Address
Note: Ellipses indicate that other addresses in sector range follow the same pattern.
Table 6.3
4
1A
2 MB
Sector/
Sector
Range
Address Range
64
SA00
000000h-007FFFh
64
SA01
008000h-00FFFFh
64
SA02
010000h-017FFFh
64
SA03
018000h-01FFFFh
SA04
020000h-03FFFFh
Sector Size
(KB)
…
256
SA34
3E0000h-3FFFFFh
256
SA35
000000h-01FFFFh
…
…
100000h-11FFFFh
256
SA58
2E0000h - 2FFFFFh
256
SA59
300000h-31FFFFh
…
7
0E0000h-0FFFFFh
SA11
…
24
SA10
256
…
6 MB
24
SA65
3C0000h-3DFFFFh
64
SA66
3E0000h-3E7FFFH
64
SA67
3E8000h-3EFFFFh
64
SA68
3F0000h-3F7FFFh
64
SA69
3F8000h-3FFFFFh
256
2B
2 MB
4
20
VIH
…
2A
6 MB
VIL
CE2#
256
…
1B
…
256
7
CE1#
…
Sector
Count
…
Bank
Size
…
Bank
PL129N Sector and Memory Address Map
VIH
VIL
S29PL-N MirrorBit™ Flash Family
Notes
Sector Starting Address Sector Ending Address
Sector Starting Address –
Sector Ending Address
(see note)
First Sector, Sector Starting Address Last Sector, Sector Ending Address
(see note)
First Sector, Sector Starting Address Last Sector, Sector Ending Address
(see note)
Sector Starting Address Sector Ending Address
(see note)
Sector Starting Address Sector Ending Address
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
7
Device Operations
This section describes the read, program, erase, simultaneous read/write operations, and reset
features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Table 12.1 and Table 12.2). The command register itself does not occupy any addressable memory location. Instead, the command register is
composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as input to the internal state
machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence can place the device in an
unknown state, in which case the system must write the reset command to return the device to
the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation. Table 7.1 describes the required state
of each control pin for any particular operation.
Table 7.1
Device Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(Amax – A0)
DQ15 – DQ0
Read
L
L
H
H
X
AIN
DOUT
Write
L
H
L
H
X
(See Note)
AIN
DIN
Standby
H
X
X
H
X
AIN
High-Z
Output Disable
L
H
H
H
X
AIN
High-Z
Reset
X
X
X
L
X
AIN
High-Z
Operation
Legend: L = Logic Low = VIL, H = Logic High = VIH, VHH = 8.5 – 9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address
In, DIN = Data In, DOUT = Data Out
Note: WP#/ACC must be high when writing to upper two and lower two sectors (PL256N: 0, 1,132, and 133; PL127/129N:
0, 1, 68, and 69)
7.1.1 Dual Chip Enable Device Description and Operation (PL129N Only)
The dual CE# product (PL129N) offers a reduced number of address pins to accommodate processors with a limited addressable range. This product operates as two separate devices in a
single package and requires the processor to address half of the memory space with one chip enable and the remaining memory space with a second chip enable. For more details on the
addressing features of the Dual CE# device refer to Table 6.3 on page 20 for the PL129N Sector
and Memory Address Map.
Dual chip enable products must be setup appropriately for each operation. To place the device
into the active state either CE1# or CE2# must be set to VIL. To place the device in standby mode,
both CE1# and CE2# must be set to VIH. Table 7.2 describes the required state of each control
pin for any particular operation.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
21
P r e l i m i n a r y
Table 7.2
Operation
Dual Chip Enable Device Operation
CE1# CE2# OE# WE#
Read
Write
L
H
H
L
L
H
RESET#
WP#/ACC
Addresses
(A21 – A0)
DQ15 – DQ0
X
AIN
DOUT
AIN
DIN
L
H
H
H
L
H
X
(Note 2)
H
L
Standby
H
H
X
X
H
X
X
High-Z
Output Disable
L
L
H
H
H
X
X
High-Z
Reset
X
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect
(High Voltage)
X
X
X
X
VID
X
AIN
DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH,VID = 11.5–12.5 V, VHH = 8.5 – 9.5 V,
X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1.
2.
7.2
The sector and sector unprotect functions may also be implemented by programming equipment.
WP#/ACC must be high when writing to the upper two and lower two sectors.
Asynchronous Read
The internal state machine is set for reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. Each bank remains enabled for read access until the command register contents are altered.
7.2.1 Non-Page Random Read
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data
at the output inputs. The output enable access time is the delay from the falling edge of the OE#
to valid data at the output (assuming the addresses have been stable for at least tACC – tOE time).
7.2.2 Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM
read operation. This mode provides faster read access speed for random locations within a page.
The random or initial page access is tACC or tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When
CE# is deasserted (= VIH), the reassertion of CE# for subsequent access has access time of tACC
or tCE. Here again, CE# selects the device and OE# is the output control and should be used to
gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by
keeping Amax – A3 constant and changing A2 – A0 to select the specific word within that page.
Address bits Amax – A3 select an 8-word page, and address bits A2 – A0 select a specific word
within that page. This is an asynchronous operation with the microprocessor supplying the specific
word location. See Table 7.3 for details on selecting specific words.
22
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. Each bank is ready to read array data after completing an Embedded
Program or Embedded Erase algorithm. All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever
happens first.
Reads from the memory array may be performed in conjunction with the Erase Suspend and Program Suspend features. After the device accepts an Erase Suspend command, the corresponding
bank enters the erase-suspend-read mode, after which the system can read data from any nonerase-suspended sector within the same bank. The system can read array data using the standard
read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the
system may once again read array data with the same exception. After the device accepts a Program Suspend command, the corresponding bank enters the program-suspend-read mode, after
which the system can read data from any non-program-suspended sector within the same bank.
Table 7.3
7.3
Word Selection within a Page
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
Autoselect
The Autoselect mode allows the host system to access manufacturer and device identification,
and verify sector protection, through identifier codes output from the internal register (separate
from the memory array) on DQ15-DQ0. This mode is primarily intended to allow equipment to
automatically match a device to be programmed with its corresponding programming algorithm.
When verifying sector protection, the sector address must appear on the appropriate highest
order address bits (see Table 7.5). The remaining address bits are don't care. When all necessary
bits have been set as required, the programming equipment can then read the corresponding
identifier code on DQ15-DQ0.
The Autoselect codes can also be accessed in-system through the command register. Note that if
a Bank Address (BA) on the four uppermost address bits is asserted during the third write cycle
of the Autoselect command, the host system can read Autoselect data from that bank and then
immediately read array data from the other bank, without exiting the Autoselect mode.
„ To access the Autoselect codes, the host system must issue the Autoselect command.
„ The Autoselect command sequence can be written to an address within a bank that is either
in the read or erase-suspend-read mode.
„ The Autoselect command cannot be written while the device is actively programming or erasing in the other bank.
„ Autoselect does not support simultaneous operations or page modes.
„ The system must write the reset command to return to the read mode (or erase-suspendread mode if the bank was previously in Erase Suspend).
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
23
P r e l i m i n a r y
See Table 12.1 for command sequence details.
Table 7.4
CE#
A
–
A5 –
OE# WE# max A10 A9 A8 A7 A6
A3 A2 A1 A0
See Note
A12
A4
Description
Manufacturer ID
Device ID:
Autoselect Codes
L
L
L
L 0001h
L
L
L
L
H 227Eh
Read
Cycle 2
L
H
H
H
223Ch (PL256N)
L 2220h (PL127N)
2221h (PL129N)
Read
Cycle 3
L
H
H
H
2200h (PL256N)
H 2200h (PL127N)
2200h (PL129N)
H
0000h
Unprotected
(Neither DYB nor PPB Locked),
L
0001h
Protected
(Either DYB or PPB Locked)
H
- DQ15 - DQ8 = 0
- DQ7 - Factory Lock Bit
1 = Locked, 0 = Not Locked
- DQ6 -Customer Lock Bit
1 = Locked, 0 = Not Locked
- DQ5 - Handshake Bit
1 = Reserved,
H
0 = Standard Handshake
- DQ4 & DQ3 WP# Protection Boot Code
00 = WP# Protects both Top Boot
and Bottom Boot Sectors,
11 = No WP# Protection
- DQ2 - DQ0 = 0
Read
Cycle 1
Sector
Protection
Verification
Indicator Bit
L
L
L
L
H
L
H
L
H
L
H
BA
BA
SA
BA
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
X
DQ15 to DQ0
L
L
L
L
L
L
L
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
Note: For the PL129N Either CE1# or CE2# must be low to access Autoselect Codes
Software Functions and Sample Code
Table 7.5
Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Word Address
Data
Unlock Cycle 1
Write
BAx555h
0x00AAh
Unlock Cycle 2
Write
BAx2AAh
0x0055h
Autoselect Command
Write
BAx555h
0x0090h
Table 7.6
Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle
Operation
Word Address
Data
Unlock Cycle 1
Write
base + xxxh
0x00F0h
Notes:
1.
2.
3.
Any offset within the device works.
BA = Bank Address. The bank address is required.
base = base address.
The following is a C source code example of using the autoselect function to read the manufacturer ID. See the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
24
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*((UINT16 *)bank_addr + 0x555) = 0x00AA; /* write unlock cycle 1 */
*((UINT16 *)bank_addr + 0x2AA) = 0x0055; /* write unlock cycle 2 */
*((UINT16 *)bank_addr + 0x555) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *((UINT16 *)bank_addr + 0x000); /* read manuf. id */
/* Autoselect exit */
*((UINT16 *)base_addr + 0x000) = 0x00F0; /* exit autoselect (write reset command) */
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
25
P r e l i m i n a r y
7.4
Program/Erase Operations
These devices are capable of single word or write buffer programming operations which are described in the following sections. The write buffer programming is recommended over single word
programming as it has clear benefits from greater programming efficiency. See Table 7.1 on
page 21 for the correct device settings required before initiation of a write command sequence.
Note the following details regarding the program/erase operations:
„ When the Embedded Program algorithm is complete, the device then returns to the read
mode.
„ The system can determine the status of the program operation by using DQ7 or DQ6. See
Write Operation Status for information on these status bits.
„ A 0 cannot be programmed back to a 1. Attempting to do so causes the device to set DQ5 =
1 (halting any further operation and requiring a reset command). A succeeding read shows
that the data is still 0.
„ Only erase operations can convert a 0 to a 1.
„ A hardware reset immediately terminates the program operation and the program command
sequence should be reinitiated once the device has returned to the read mode, to ensure data
integrity.
„ Any commands written to the device during the Embedded Program Algorithm are ignored
except the Program Suspend command.
„ Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress.
„ Programming is allowed in any sequence and across sector boundaries for single word programming operation.
7.4.1 Single Word Programming
In single word programming mode, four Flash command write cycles are used to program an individual Flash address. While this method is supported by all Spansion devices, in general it is not
recommended for devices that support Write Buffer Programming. See Table 12.1 for the required bus cycles and Figure 7.1 for the flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See Write Operation Status for information on these status bits.
Single word programming is supported for backward compatibility with existing Flash driver software and use of write buffer programming is strongly recommended for general programming.
The effective word programming time using write buffer programming is approximately four times
faster than the single word programming time.
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S29PL-N MirrorBit™ Flash Family
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Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
(Exceeded Timing Limits)
No
PASS. Device is in
read mode.
Figure 7.1
FAIL. Issue reset command
to return to read array mode.
Single Word Program Operation
Software Functions and Sample Code
Table 7.7
Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Word Address
Data
Unlock Cycle 1
Write
Base + 555h
00AAh
Unlock Cycle 2
Write
Base + 2AAh
0055h
Program Setup
Write
Base + 555h
00A0h
Program
Write
Word Address
Data Word
Note: Base = Base Address.
The following is a C source code example of using the single word program function. See the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program Command
*/
*((UINT16 *)base_addr + 0x555) =
*((UINT16 *)base_addr + 0x2AA) =
*((UINT16 *)base_addr + 0x555) =
*((UINT16 *)pa)
=
/* Poll for program completion */
November 23, 2005 S29PL-N_00_A4
0x00AA;
0x0055;
0x00A0;
data;
/*
/*
/*
/*
write
write
write
write
unlock cycle 1
unlock cycle 2
program setup command
data to be programmed
S29PL-N MirrorBit™ Flash Family
*/
*/
*/
*/
27
P r e l i m i n a r y
7.4.2 Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard word
programming algorithms. The Write Buffer Programming command sequence is initiated by first
writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming occurs. At this point, the system
writes the number of word locations minus 1 that is loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses are
loaded with data and therefore when to expect the Program Buffer to Flash confirm command.
The number of locations to program cannot exceed the size of the write buffer or the operation
aborts. (Number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first
address/data pair to be programmed, and selects the write-buffer-page address. All subsequent
address/data pairs must fall within the elected-write-buffer-page.
The write-buffer-page is selected by using the addresses Amax – A5.
The write-buffer-page addresses must be the same for all address/data pairs loaded into the write
buffer. (This means Write Buffer Programming cannot be performed across multiple write-bufferpage. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer-page,
the operation ABORTS.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data
pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter
decrements for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command is programmed into the device. The software takes care
of the ramifications of loading a write-buffer location more than once. The counter decrements
for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program
Buffer to Flash command at the Sector Address. Any other address/data write combinations abort
the Write Buffer Programming operation. The device then goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This
eliminates the need to store an address in memory because the system can load the last address
location, issue the program confirm command at the last loaded address location, and then data
bar poll at that same address.
The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation,
the device returns to READ mode.
If the write buffer command sequence is entered incorrectly the device enters write buffer abort.
When an abort occurs the write-to buffer-abort reset command must be issued to return the device to read mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
„ Load a value that is greater than the page buffer size during the Number of Locations to Program step.
„ Write to an address in a sector different than the one specified during the Write-Buffer-Load
command.
„ Write an Address/Data pair to a different write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation.
„ Write data other than the Confirm Command after the specified number of data load cycles.
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Use of the write buffer is strongly recommended for programming when multiple words are to be
programmed. Write buffer programming is approximately four times faster than programming
one word at a time. Note that the Secured Silicon, the CFI functions, and the Autoselect Codes
are not available for read when a write buffer programming operation is in progress.
Software Functions and Sample Code
Table 7.8
Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Operation
Word Address
Data
1
Unlock
Write
Base + 555h
00AAh
2
Unlock
Write
Base + 2AAh
0055h
3
Write Buffer Load Command
Write
Program Address
0025h
4
Write Word Count
Write
Program Address
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36
Load Buffer Word N
Write
Program Address, Word N
Word N
Last
Write Buffer to Flash
Write
Sector Address
0029h
Notes:
1.
2.
3.
Base = Base Address.
Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles
can be from 6 to 37.
For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words)
possible.
The following is a C source code example of using the write buffer program function. See the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
All addresses to be written to the flash in
*/
/*
one operation must be within the same flash
*/
/*
page. A flash page begins at addresses
*/
/*
evenly divisible by 0x20.
*/
UINT16 *src = source_of_data;
/* address of source data
*/
UINT16 *dst = destination_of_data;
/* flash destination address
*/
UINT16 wc
= words_to_program -1;
/* word count (minus 1)
*/
*((UINT16 *)base_addr + 0x555) = 0x00AA;
/* write unlock cycle 1
*/
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
/* write unlock cycle 2
*/
*((UINT16 *)sector_address)
= 0x0025;
/* write write buffer load command */
*((UINT16 *)sector_address)
= wc;
/* write word count (minus 1)
*/
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
/* increment destination pointer
*/
src++;
/* increment source pointer
*/
if (wc == 0) goto confirm
/* done when word count equals zero */
wc--;
/* decrement word count
*/
goto loop;
/* do it again
*/
confirm:
*((UINT16 *)sector_address)
= 0x0029;
/* write confirm command
*/
/* poll for completion */
/* Example: Write
*((UINT16 *)addr
*((UINT16 *)addr
*((UINT16 *)addr
November 23, 2005 S29PL-N_00_A4
Buffer Abort Reset */
+ 0x555) = 0x00AA;
/* write unlock cycle 1
+ 0x2AA) = 0x0055;
/* write unlock cycle 2
+ 0x555) = 0x00F0;
/* write buffer abort reset
S29PL-N MirrorBit™ Flash Family
*/
*/
*/
29
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
SA 29h
wc = 0?
No
Wait 4 µs
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
No
Write Buffer
Abort Desired?
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write to a Different
Sector Address to Cause
Write Buffer Abort
Polling Status
= Done?
Yes
No
No
Yes
Error?
Yes
Write Buffer
Abort?
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
Figure 7.2
Write Buffer Programming Operation
7.4.3 Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 12.1, and
Figure 7.3.) The device does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during
these operations.
After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-out period, additional sector addresses and sector erase commands can be written.
Loading the sector erase buffer can be done in any sequence, and the number of sectors can be
from one sector to all sectors. The time between these additional cycles must be less than tSEA.
Any sector erase address and command following the exceeded time-out (tSEA) may or may not
30
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P r e l i m i n a r y
be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period
resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase
timer has timed out (see DQ3: Sector Erase Timeout State Indicator). The time-out begins from
the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the
system can read data from the non-erasing banks. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for
information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.
Figure 7.3 illustrates the algorithm for the erase operation. See AC Characteristics for the Erase/
Program Operations parameters and timing diagrams.
Software Functions and Sample Code
Table 7.9
Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle
Description
Operation
Word Address
Data
1
Unlock
Write
Base + 555h
00AAh
2
Unlock
Write
Base + 2AAh
0055h
3
Setup Command
Write
Base + 555h
0080h
4
Unlock
Write
Base + 555h
00AAh
5
Unlock
Write
Base + 2AAh
0055h
6
Sector Erase Command
Write
Sector Address
0030h
Unlimited additional sectors can be selected for erase; command(s) must be written within tSEA.
The following is a C source code example of using the sector erase function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x555) = 0x0080;
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)sector_address)
= 0x0030;
November 23, 2005 S29PL-N_00_A4
/*
/*
/*
/*
/*
/*
write
write
write
write
write
write
unlock cycle 1
*/
unlock cycle 2
*/
setup command
*/
additional unlock cycle 1 */
additional unlock cycle 2 */
sector erase command
*/
S29PL-N MirrorBit™ Flash Family
31
P r e l i m i n a r y
WriteUnlock
UnlockCycles:
Cycles:
Write
Address555h,
555h,Data
DataAAh
AAh
Address
Address2AAh,
2AAh,Data
Data55h
55h
Address
UnlockCycle
Cycle11
Unlock
UnlockCycle
Cycle22
Unlock
WriteSector
SectorErase
EraseCycles:
Cycles:
Write
Address555h,
555h,Data
Data80h
80h
Address
Address555h,
555h,Data
DataAAh
AAh
Address
Address2AAh,
2AAh,Data
Data55h
55h
Address
SectorAddress,
Address,Data
Data30h
30h
Sector
CommandCycle
Cycle11
Command
CommandCycle
Cycle22
Command
CommandCycle
Cycle33
Command
Specifyfirst
firstsector
sectorfor
forerasure
erasure
Specify
Select
Select
Additional
Additional
Sectors?
Sectors?
No
No
Yes
Yes
WriteAdditional
Additional
Write
SectorAddresses
Addresses
Sector
No
No
Yes
Yes
PollDQ3.
DQ3.
Poll
DQ3==1?
1?
DQ3
Eachadditional
additionalcycle
cyclemust
mustbe
bewritten
writtenwithin
withintSEA
tSEAtimeout
timeout
• •Each
Timeoutresets
resetsafter
aftereach
eachadditional
additionalcycle
cycleisiswritten
written
• •Timeout
ensure
Thehost
hostsystem
systemmay
maymonitor
monitorDQ3
DQ3ororwait
waittSEA
tSEAtotoensure
• •The
acceptanceofoferase
erasecommands
commands
acceptance
Nolimit
limiton
onnumber
numberofofsectors
sectors
• •No
LastSector
Sector
Last
Selected?
Selected?
Commandsother
otherthan
thanErase
EraseSuspend
Suspendororselecting
selecting
• •Commands
additionalsectors
sectorsfor
forerasure
erasureduring
duringtimeout
timeoutreset
resetdevice
device
additional
readingarray
arraydata
data
totoreading
No
No
Yes
Yes
Wait44µsµs
Wait
PerformWrite
WriteOperation
Operation
Perform
StatusAlgorithm
Algorithm
Status
Yes
Yes
Statusmay
maybe
beobtained
obtainedby
byreading
readingDQ7,
DQ7,DQ6
DQ6and/or
and/orDQ2.
DQ2.
Status
Done?
Done?
No
No
DQ5==1?
1?
DQ5
No
No
Errorcondition
condition(Exceeded
(ExceededTiming
TimingLimits)
Limits)
Error
Yes
Yes
PASS.Device
Devicereturns
returns
PASS.
readingarray.
array.
totoreading
FAIL.Write
Writereset
resetcommand
command
FAIL.
returntotoreading
readingarray.
array.
totoreturn
Notes:
1.
2.
See Table 12.1 for erase command sequence.
See the section on DQ3 for information on the sector erase timeout.
Figure 7.3
Sector Erase Operation
7.4.4 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 12.1. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all
zero data pattern prior to electrical erase. The system is not required to provide any controls or
timings during these operations. The Command Definition tables (Table 12.1 and Table 12.2)
show the address and data requirements for the chip erase command sequence.
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When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
Software Functions and Sample Code
Table 7.10
Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Operation
Word Address
Data
1
Unlock
Write
Base + 555h
00AAh
2
Unlock
Write
Base + 2AAh
0055h
3
Setup
Command
Write
Base + 555h
0080h
4
Unlock
Write
Base + 555h
00AAh
5
Unlock
Write
Base + 2AAh
0055h
6
Chip Erase
Command
Write
Base + 555h
0010h
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*((UINT16 *)base_addr + 0x555) =
*((UINT16 *)base_addr + 0x2AA) =
*((UINT16 *)base_addr + 0x555) =
*((UINT16 *)base_addr + 0x555) =
*((UINT16 *)base_addr + 0x2AA) =
*((UINT16 *)base_addr + 0x000) =
0x00AA;
0x0055;
0x0080;
0x00AA;
0x0055;
0x0010;
/*
/*
/*
/*
/*
/*
write
write
write
write
write
write
unlock cycle 1
*/
unlock cycle 2
*/
setup command
*/
additional unlock cycle 1 */
additional unlock cycle 2 */
chip erase command
*/
7.4.5 Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation,
including the minimum tSEA time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation.
When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to suspend the erase operation. However,
when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address within erasesuspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to
Table 7.18 for information on these status bits.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
33
P r e l i m i n a r y
After an erase-suspended program operation is complete, the bank returns to the erase-suspendread mode. The system can determine the status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence.
See Write Buffer Programming and Autoselect for details.
To resume the sector erase operation, the system must write the Erase Resume command. The
bank address of the erase-suspended bank is required when writing this command. Further writes
of the Resume command are ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Software Functions and Sample Code
Table 7.11
Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle
Operation
Word Address
Data
1
Write
Bank Address
00B0h
The following is a C source code example of using the erase suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */
*((UINT16 *)bank_addr + 0x000) = 0x00B0;
/* write suspend command
Table 7.12
*/
Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle
Operation
Word Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */
*((UINT16 *)bank_addr + 0x000) = 0x0030;
/* write resume command
/* The flash needs adequate time in the resume state */
*/
7.4.6 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a Write to Buffer programming operation so that data can read from any nonsuspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) and
updates the status bits.
After the programming operation has been suspended, the system can read array data from any
non-suspended sector. The Program Suspend command can also be issued during a programming
operation while an erase is suspended. In this case, data can be read from any addresses not in
Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area,
then user must use the proper command sequences to enter and exit this region.
34
S29PL-N MirrorBit™ Flash Family
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P r e l i m i n a r y
The system can also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes
are not stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect for
more information.
After the Program Resume command is written, the device reverts to programming. The system
can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See Write Operation Status for more information.
The system must write the Program Resume command (address bits are don't cares) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program
Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming.
Software Functions and Sample Code
Table 7.13 Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle
Operation
Word Address
Data
1
Write
Bank Address
00B0h
The following is a C source code example of using the program suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */
*((UINT16 *)base_addr + 0x000) = 0x00B0;
/* write suspend command
Table 7.14
*/
Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle
Operation
Word Address
Data
1
Write
Bank Address
0030h
The following is a C source code example of using the program resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */
*((UINT16 *)base_addr + 0x000) = 0x0030;
/* write resume command
*/
7.4.7 Accelerated Program
Accelerated single word programming, write buffer programming, sector erase, and chip erase
operations are enabled through the ACC function. This method is faster than the standard chip
program and erase command sequences.
The accelerated chip program and erase functions must not be used more than 10
times per sector. In addition, accelerated chip program and erase should be performed at room
temperature (25°C ±10°C).
This function is primarily intended to allow faster manufacturing throughput at the factory. If the
system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program and
erase operations. The system can then use the Write Buffer Load command sequence provided
by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is required while in Unlock
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
35
P r e l i m i n a r y
Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation,
returns the device to normal operation.
„ Sectors must be unlocked prior to raising WP#/ACC to VHH.
„ The WP#/ACC must not be at VHH for operations other than accelerated programming and
accelerated chip erase, or device damage can result.
„ Set the ACC pin at VCC when accelerated programming not in use.
7.4.8 Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program data, instead
of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 12.1, Memory Array Commands
shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the bank address and the data 90h.
The second cycle need only contain the data 00h. The bank then returns to the read mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
Table 7.15
Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Operation
Word Address
Data
1
Unlock
Write
Base + 555h
00AAh
2
Unlock
Write
Base + 2AAh
0055h
3
Entry Command
Write
Base + 555h
0020h
/* Example: Unlock Bypass Entry Command
*/
*((UINT16 *)bank_addr + 0x555) = 0x00AA;
/* write unlock cycle 1
*((UINT16 *)bank_addr + 0x2AA) = 0x0055;
/* write unlock cycle 2
*((UINT16 *)bank_addr + 0x555) = 0x0020;
/* write unlock bypass command
/* At this point, programming only takes two write cycles.
*/
/* Once you enter Unlock Bypass Mode, do a series of like
*/
/* operations (programming or sector erase) and then exit
*/
/* Unlock Bypass Mode before beginning a different type of
*/
/* operations.
*/
36
S29PL-N MirrorBit™ Flash Family
*/
*/
*/
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Table 7.16
Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Word Address
Data
1
Program Setup Command
Write
Base +xxxh
00A0h
2
Program Command
Write
Program Address
Program Data
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode!
*/
*((UINT16 *)bank_addr + 0x555) = 0x00A0;
/* write program setup command
*((UINT16 *)pa)
= data;
/* write data to be programmed
/* Poll until done or error.
*/
/* If done and more to program, */
/* do above two cycles again.
*/
Table 7.17
*/
*/
Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Operation
Word Address
Data
1
Reset Cycle 1
Write
Base +xxxh
0090h
2
Reset Cycle 2
Write
Base +xxxh
0000h
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
7.4.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the writebuffer-page during Write Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page returns false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded
Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of the sectors selected for
erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode.
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 can change asynchronously with DQ6 – DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
November 23, 2005 S29PL-N_00_A4
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P r e l i m i n a r y
samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ6 – DQ0 may be
still invalid. Valid data on DQ7 – DQ0 appears on successive read cycles.
See the following for more information: Table 7.18, Write Operation Status, shows the outputs
for Data# Polling on DQ7. Figure 7.4, Write Operation Status Flowchart, shows the Data# Polling
algorithm. Figure 11.13, Data# Polling Timings (During Embedded Algorithms) shows the Data#
Polling timing diagram.
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S29PL-N MirrorBit™ Flash Family
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START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
Read 1
DQ5=1?
YES
YES
Read 2
Read3=
valid data?
NO
NO
Read 3
Read 2
YES
Program
Operation
Failed
Write Buffer
Programming?
YES
NO
Programming
Operation?
Read 3
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 1)
YES
DQ6
toggling?
(Note 4)
(Note 1)
DQ6
toggling?
TIMEOUT
NO
YES
Read3
DQ1=1?
DEVICE
ERROR
NO
(Note 2)
NO
(Note 5)
YES
Device BUSY,
Re-Poll
DQ2
toggling?
YES
NO
Read 2
Device BUSY,
Re-Poll
Erase
Operation
Complete
Read 3
Read3
DQ1=1
AND DQ7 ≠
Valid Data?
YES
Write Buffer
Operation
Failed
NO
Device BUSY,
Re-Poll
Figure 7.4
November 23, 2005 S29PL-N_00_A4
Device in
Erase/Suspend
Mode
Notes:
1. DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2. DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3. May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
4. Write buffer error if DQ1 of last read =1.
5. Invalid state, use RESET command to exit operation.
6. Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7. Data polling algorithm valid for all operations except advanced sector
protection.
Write Operation Status Flowchart
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P r e l i m i n a r y
DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo-
rithm is in progress or complete, or whether the device has entered the Erase Suspend mode.
Toggle Bit I can be read at any address in the same bank, and is valid after the rising edge of the
final WE# pulse in the command sequence (prior to the program or erase operation), and during
the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately tASP (all sectors protected toggle time), then returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7, see DQ7: Data# Polling.
If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete.
See the following for additional information: Figure 7.4, Write Operation Status Flowchart,
Figure 11.14, Toggle Bit Timings (During Embedded Algorithms), Table 7.18, Write Operation
Status, and Figure 11.15, DQ2 vs. DQ6.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the
change in state.
DQ2: Toggle Bit II . The Toggle Bit II on DQ2, when used with DQ6, indicates whether a partic-
ular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether
that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse
in the command sequence. DQ2 toggles when the system reads at addresses within those sectors
that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 7.18, Write Operation Status to compare outputs for DQ2 and DQ6. See the following for additional information:
Figure 7.4, Write Operation Status Flowchart and Figure 11.14, Toggle Bit Timings (During Embedded Algorithms).
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status,
it must read DQ7 – DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erases operation. The system can
read array data on DQ7 – DQ0 on the following read cycle. However, if after the initial two read
cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit might have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the reset command to return to reading array
data. The remaining scenario is that the system initially determines that the toggle bit is toggling
and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through
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successive read cycles, determining the status as described in the previous paragraph. Alternatively, it can choose to perform other system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine the status of the operation. Refer to
Figure 7.4, Write Operation Status Flowchart for more details.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded
a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that
the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if
the system tries to program a 1 to a location that was previously programmed to 0. Only an erase
operation can change a 0 back to a 1, Under this condition, the device halts the operation, and
when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the
system must write the reset command to return to the read mode (or to the erase-suspend-read
mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence,
the system may read DQ3 to determine whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command. When the time-out
period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase
commands from the system can be assumed to be less than tSEA, the system need not monitor
DQ3. See Sector Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device
accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-sequent sector erase
command. If DQ3 is high on the second status check, the last command might not have been
accepted. Table 7.18 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.
Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset
command sequence to return the device to reading array data. See Write Buffer Programming
Operation for more details.
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Table 7.18
Standard
Mode
Program
Suspend
Mode
(Note 3)
Erase
Suspend
Mode
Write Operation Status
Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ1
(Note 4)
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
N/A
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
Data
Data
Data
Data
Data
Data
Erase Suspended
Sector
1
No Toggle
0
N/A
Toggle
N/A
Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Data
DQ7#
Toggle
0
N/A
N/A
N/A
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
N/A
Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
N/A
BUSY State
DQ7#
Toggle
0
N/A
N/A
0
Exceeded Timing Limits
DQ7#
Toggle
1
N/A
N/A
0
ABORT State
DQ7#
Toggle
0
N/A
N/A
1
Embedded Erase Algorithm
Reading within Program
Suspended Sector
Reading within Non-Program
Suspended Sector
Erase-Suspend-Read
Erase-Suspend-Program
Erase
Suspend
Mode
Write to
Buffer
(Note 5)
Erase-SuspendRead
Notes:
1.
2.
3.
4.
5.
42
DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details.
Data are invalid for addresses in a Program Suspended sector.
DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write
Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
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7.5
Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. An erase operation may also be
suspended to read from or program another location within the same bank (except the sector
being erased). Figure 11.12, Back-to-back Read/Write Cycle Timings shows how read and write
cycles may be initiated for simultaneous operation with zero latency. See the table, DC Characteristics for read-while-program and read-while-erase current specifications.
VCC
VSS
Mux
Bank A
Bank B
X-Decoder
Amax–A0
WE#
CE#
WP#/ACC
State
Control
and
Command
Register
RY/BY#
Status
DQ15 – DQ0
Control
Mux
X-Decoder
Amax–A0
DQ0 – DQ15
Bank C
Y-gate
Bank C Address
X-Decoder
Amax – A0
OE#
DQ15–DQ0
RESET#
DQ15–DQ0
Bank B Address
DQ15–DQ0
Amax – A0
X-Decoder
DQ15–DQ0
Amax – A0
Y-gate
Bank A Address
Bank D Address
Bank D
Mux
Note: Amax = A23 (PL256N), A22 (PL127N)
Figure 7.5
November 23, 2005 S29PL-N_00_A4
Simultaneous Operation Block Diagram for S29PL256N and S29PL127N
S29PL-N MirrorBit™ Flash Family
43
P r e l i m i n a r y
CE1# = L
CE2# = H
VCC
VSS
Mux
Bank 1A
Bank 1B
X-Decoder
A21 – A0
CE1#
CE2#
WP#/ACC
State
Control
and
Command
Register
RY/BY#
DQ15 – DQ0
Control
CE1# = H
CE2# = L
DQ0 – DQ15
A21 – A0
Status
X-Decoder
Bank 2A
Y-gate
Bank 2A Address
Mux
X-Decoder
A21 – A0
DQ15 – DQ0
WE#
OE#
DQ15 – DQ0
RESET#
DQ15 – DQ0
Bank 1B Address
DQ15 – DQ0
A21 – A0
X-Decoder
Y-gate
Bank 1A Address
A21 – A0
Bank 2B Address
Bank 2B
Mux
Figure 7.6
44
Simultaneous Operation Block Diagram for S29PL129N
S29PL-N MirrorBit™ Flash Family
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7.6
Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or
CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase
one sector, multiple sectors, or the entire device. Table 6.1 and Table 6.2 indicate the address
space that each sector occupies. The device address space is divided into four banks: Banks B
and C contain only 128 Kword sectors, while Banks A and D contain both 32 Kword boot sectors
in addition to 128 Kword sectors. A bank address is the set of address bits required to uniquely
select a bank. Similarly, a sector address is the address bits required to uniquely select a sector.
ICC2 in DC Characteristics represents the active current specification for the write mode. see AC
Characteristics contains timing specification tables and timing diagrams for write operations.
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7.7
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, and ignores all read/write commands for the duration
of the RESET# pulse. The device also resets the internal state machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held
at VIL, but not at VSS, the standby current is greater.
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up
firmware from the Flash memory upon a system reset.
See Figure 11.5 and Figure 11.8 for timing diagrams.
7.8
Software Reset
Software reset is part of the command set (see Table 12.1) that also returns the device to array
read mode and must be used for the following conditions:
1.
To exit Autoselect mode
2.
To reset software when DQ5 goes high during write status operation that indicates program
or erase cycle was not successfully completed
3.
To exit sector lock/unlock operation.
4.
To return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
5.
To reset software after any aborted operations
Software Functions and Sample Code
Table 7.19
Reset
(LLD Function = lld_ResetCmd)
Cycle
Operation
Word Address
Data
Reset Command
Write
Base + xxxh
00F0h
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
„ This command resets the banks to the read and address bits are ignored.
„ Reset commands are ignored once erasure has begun until the operation is complete.
„ Once programming begins, the device ignores reset commands until the operation is complete
„ The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system
was writing to the read mode.
„ If the program command sequence is written to a bank that is in the Erase Suspend mode,
writing the reset command returns that bank to the erase-suspend-read mode.
„ The reset command may be also written during an Autoselect command sequence.
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„ If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
„ If DQ1 goes high during a Write Buffer Programming operation, the system must write the
Write to Buffer Abort Reset command sequence to RESET the device to reading array data.
The standard RESET command does not work during this condition.
„ To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence (see command tables for detail).
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8
Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase
operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of
protecting data stored in the memory array. An overview of these methods in shown in Figure 8.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
Password Method
Persistent Method
(DQ2)
(DQ1)
WP# = VIL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
PPB Lock Bit
(Notes 1, 2, 3)
0 = PPBs Locked
1 = PPBs Unlocked
Persistent
Protection Bit (PPD)
Dynamic
Protection Bit (DYB)
(Notes 5, 6)
(Notes 7, 8, 9)
Sector 0
PPB 0
DYB 0
Sector 1
PPB 1
DYB 1
Sector 2
PPB 2
DYB 2
Sector N-2
PPB N-2
DYB N-2
Sector N-1
PPB N-1
DYB N-1
PPB N
DYB N
Memory Array
Sector N
(Note 4)
Notes:
1.
2.
3.
4.
5.
Bit is volatile, and defaults to 1 on reset.
Programming to 0 locks all PPBs to their current state.
Once programmed to 0, requires hardware reset to unlock.
N = Highest Address Sector.
0 = Sector Protected,
1 = Sector Unprotected.
Figure 8.1
48
6. PPBs programmed individually, but cleared collectively.
7. 0 = Sector Protected,
1 = Sector Unprotected.
8. Protect effective only if PPB Lock Bit is unlocked and
corresponding PPB is 1 (unprotected).
9. Volatile Bits: defaults to user choice upon power-up
(see ordering options).
Advanced Sector Protection/Unprotection
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8.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and
all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see Ordering Information). The device programmer or host system must then choose which sector
protection method to use. Programming (setting to 0) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode:
„ Lock Register Persistent Protection Mode Lock Bit (DQ1)
„ Lock Register Password Protection Mode Lock Bit (DQ2)
Table 8.1
Device
S29PL256N
DQ15 – 05
Undefined
DQ4
DYB Lock Boot Bit
0 = sectors
power up
protected
1 = sectors
power up
unprotected
Lock Register
DQ3
PPB One-Time
Programmable Bit
0 = All PPB erase
command disabled
1 = All PPB Erase
command enabled
DQ2
Password
Protection
Mode Lock Bit
DQ1
Persistent
Protection
Mode Lock Bit
DQ0
Secured
Silicon Sector
Protection Bit
For programming lock register bits see Table 12.2.
Notes
1.
If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit.
2.
After the Lock Register Bits Command Set Entry command sequence is written, reads and
writes for Bank A are disabled, while reads from other banks are allowed until exiting this
mode.
3.
If both lock bits are selected to be programmed (to zeros) at the same time, the operation
aborts.
4.
Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the
Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following three
states:
1.
Constantly locked. The selected sectors are protected and cannot be reprogrammed unless
PPB lock bit is cleared via a password, hardware reset, or power cycle.
2.
Dynamically locked. The selected sectors are protected and can be altered via software
commands.
3.
Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 8.2 – 8.6.
8.2
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by
the device, and therefore do not require system monitoring.
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Notes
1.
Each PPB is individually programmed and all are erased in parallel.
2.
Entry command disables reads and writes for the bank selected.
3.
Reads within that bank return the PPB status for that sector.
4.
Reads from other banks are allowed while writes are not allowed.
5.
All Reads must be performed using the Asynchronous mode.
6.
The specific sector addresses (A23 – A14 PL256N and A22 – A14 PL127N/PL129N) are written at the same time as the program command.
7.
If the PPB Lock Bit is set, the PPB Program or erase command does not execute and timesout without programming or erasing the PPB.
8.
There are no means for individually erasing a specific PPB and no specific sector address is
required for this operation.
9.
Exit command must be issued after the execution which resets the device to read mode and
re-enables reads and writes for Bank A.
10. The programming state of the PPB for a given sector can be verified by writing a PPB Status
Read Command to the device as described by the flow chart below.
8.3
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified.
DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared
(erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected
state respectively. This feature allows software to easily protect sectors against inadvertent
changes yet does not prevent the easy removal of protection when changes are needed.
Notes
8.4
1.
The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed. When
the parts are first shipped, the PPBs are cleared (erased to 1) and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen.
2.
If the option to clear the DYBs after power up is chosen, (erased to 1), then the sectorsmay
be modified depending upon the PPB state of that sector.
3.
The sectors would be in the protected state If the option to set the DYBs after power up is
chosen (programmed to 0).
4.
It is possible to have sectors that are persistently locked with sectors that are left in the
dynamic state.
5.
The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected
state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be
cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can
then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks
the PPBs, and the device operates normally again.
6.
To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command
early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB
and DYB bits have the same function when WP#/ACC = V HH as they do when WP#/
ACC = VIH.
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed
to 0), this bit locks all PPB and when cleared (programmed to 1), unlocks each sector. There is
only one PPB Lock Bit per device.
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Notes
8.5
1.
No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit.
2.
The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the
desired settings.
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector
Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition
to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the
password mode of operation. Successful execution of the Password Unlock command by entering
the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1.
There is no special addressing order required for programming the password. Once the
Password is written and verified, the Password Mode Locking Bit must be set to prevent access.
2.
The Password Program Command is only capable of programming 0s. Programming a 1
after a cell is programmed as a 0 results in a time-out with the cell as a 0.
3.
The password is all 1s when shipped from the factory.
4.
All 64-bit password combinations are valid as a password.
5.
There is no means to verify what the password is after it is set.
6.
The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data
bus and further password programming.
7.
The Password Mode Lock Bit is not erasable.
8.
The lower two address bits (A1 – A0) are valid during the Password Read, Password Program, and Password Unlock.
9.
The exact password must be entered in order for the unlocking function to occur.
10. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent
a hacker from running through all the 64-bit combinations in an attempt to correctly match
a password.
11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is
given to the device.
12. Password verification is only allowed during the password programming operation.
13. All further commands to the password region are disabled and all operations are ignored.
14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the
PPB Lock Bit.
15. Entry command sequence must be issued prior to any of any operation and it disables reads
and writes for Bank A. Reads and writes for other banks excluding Bank A are allowed.
16. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode.
17. A program or erase command to a protected sector enables status polling and returns to
read mode without having modified the contents of the protected sector.
18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing
individual status read commands DYB Status, PPB Status, and PPB Lock Status to the
device.
November 23, 2005 S29PL-N_00_A4
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P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
* Not on future devices
Program Data (PD): See text for Lock Register
definitions
Caution: Lock data may only be progammed once.
Wait 4 µs
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
DQ5 = 1?
No
Error condition (Exceeded Timing Limits)
Yes
PASS. Write Lock Register
Exit Command:
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Figure 8.2
52
FAIL. Write rest command
to return to reading array.
Lock Register Program Algorithm
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
8.6
Advanced Sector Protection Software Examples
Table 8.2
Unique Device PPB Lock Bit
0 = locked, 1 = unlocked
Sector Protection Schemes
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Sector Protection Status
Any Sector
0
0
x
Protected through PPB
Any Sector
0
0
x
Protected through PPB
Any Sector
0
1
1
Unprotected
Any Sector
0
1
0
Protected through DYB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
1
0
Protected through DYB
Any Sector
1
1
1
Unprotected
Table 8.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB Lock Bit is locked (set to 0), no changes to the PPBs are
allowed. The PPB Lock Bit can only be unlocked (reset to 1) through a hardware reset or power
cycle. See also Figure 8.1 for an overview of the Advanced Sector Protection feature.
8.7
Hardware Data Protection Methods
The device offers data protection at the sector level via hardware control:
„ When WP#/ACC is at VIL, the four outermost sectors are locked (device specific).
There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods:
8.7.1 WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors.
This function is provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection method.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions
in the outermost boot sectors. The outermost boot sectors are the sectors containing both the
lower and upper set of sectors in a dual-boot-configured device.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the boot sectors
were last set to be protected or unprotected. That is, sector protection or unprotection for these
sectors depends on whether they were last protected or unprotected.
Note that the WP#/ACC pin must not be left floating or unconnected as inconsistent behavior of
the device may result.
The WP#/ACC pin must be held stable during a command sequence execution
8.7.2 Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets
to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control inputs to prevent unintentional writes when VCC is
greater than VLKO.
November 23, 2005 S29PL-N_00_A4
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P r e l i m i n a r y
8.7.3 Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.7.4 Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read
mode on powerup.
54
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9
9.1
Power Conservation Modes
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at VCC ±0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during
erasure or programming, the device draws active current until the operation is completed. ICC3
in DC Characteristics represents the standby current specification
9.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for tACC + 20 ns.
The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard
address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC6 in DC Characteristics represents the
automatic sleep mode current specification.
9.3
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at VSS ±0.2 V, the device draws CMOS standby current (ICC4). If RESET#
is held at VIL but not within VSS ±0.2 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
9.4
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the
high impedance state.
November 23, 2005 S29PL-N_00_A4
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55
P r e l i m i n a r y
10 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words
in length that consists of 128 words for factory data and 128 words for customer-secured areas.
All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory
Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Secured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6)
is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped
from the factory.
Note the following general conditions:
„ While the Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank A.
„ On power up, or following a hardware reset, the device reverts to sending commands to the
normal address space.
„ Reads outside of sector 0 return memory array data.
„ Sector 0 is remapped from the memory array to the Secured Silicon Sector array.
„ Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit
command must be issued to exit Secured Silicon Sector Mode.
„ The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.
Table 10.1
10.1
Secured Silicon Sector Addresses
Sector
Sector Size
Address Range
Customer
128 words
000080h-0000FFh
Factory
128 words
000000h-00007Fh
Factory Secured Silicon Sector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has
the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to the
field.
These devices are available pre programmed with one of the following:
„ A random, 8-word secure ESN only within the Factory Secured Silicon Sector
„ Customer code within the Customer Secured Silicon Sector through the SpansionTM programming service.
„ Both a random, secure ESN and customer code through the Spansion programming service.
Customers may opt to have their code programmed through the Spansion programming services.
Spansion programs the customer's code, with or without the random ESN. The devices are then
shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured
Silicon Sector permanently locked. Contact your local representative for details on using Spansion
programming services.
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10.2
Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing
customers to utilize that sector in any manner they choose. If the security feature is not required,
the Customer Secured Silicon Sector can be treated as an additional Flash memory space.
Please note the following:
„ Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is
permanently set to 1.
„ The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Customer Secured Silicon Sector lock must be used with
caution as once locked, there is no procedure available for unlocking the Customer Secured
Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space
can be modified in any way.
„ The accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer Secured Silicon Sector, but are available when reading in Banks B
through D.
„ Once the Customer Secured Silicon Sector is locked and verified, the system must write the
Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0.
10.3
Secured Silicon Sector Entry and Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured
Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence.
See the Command Definition Tables
Table 12.1, Memory Array Commands.
Table 12.2, Sector Protection Commands for address and data requirements for both command
sequences.
The Secured Silicon Sector Entry Command allows the following commands to be executed
„ Read customer and factory Secured Silicon areas
„ Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon Sector command sequence, it may read
the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the
memory array. This mode of operation continues until the system issues the Exit Secured Silicon
Sector command sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector
Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User Guide
(available soon on www.amd.com and www.fujitsu.com) for general information on Spansion
Flash memory software development guidelines.
November 23, 2005 S29PL-N_00_A4
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Table 10.2
Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Word Address
Data
Unlock Cycle 1
Write
Base + 555h
00AAh
Unlock Cycle 2
Write
Base + 2AAh
0055h
Entry Cycle
Write
Base + 555h
0088h
Note: Base = Base Address.
/* Example: SecSi Sector
*((UINT16 *)base_addr +
*((UINT16 *)base_addr +
*((UINT16 *)base_addr +
Entry Command */
0x555) = 0x00AA;
0x2AA) = 0x0055;
0x555) = 0x0088;
Table 10.3
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Secured Silicon Sector Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Word Address
Data
Unlock Cycle 1
Write
Base + 555h
00AAh
Unlock Cycle 2
Write
Base + 2AAh
0055h
Program Setup
Write
Base + 555h
00A0h
Program
Write
Word Address
Data Word
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm.
*/
Table 10.4
Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Cycle
Operation
Word Address
Data
Unlock Cycle 1
Write
Base + 555h
00AAh
Unlock Cycle 2
Write
Base + 2AAh
0055h
Exit Cycle
Write
Base + 555h
0090h
Note: Base = Base Address.
/* Example: SecSi Sector
*((UINT16 *)base_addr +
*((UINT16 *)base_addr +
*((UINT16 *)base_addr +
*((UINT16 *)base_addr +
58
Exit Command */
0x555) = 0x00AA;
0x2AA) = 0x0055;
0x555) = 0x0090;
0x000) = 0x0000;
/*
/*
/*
/*
write
write
write
write
unlock cycle
unlock cycle
SecSi Sector
SecSi Sector
S29PL-N MirrorBit™ Flash Family
1
2
Exit cycle 3
Exit cycle 4
*/
*/
*/
*/
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
11
11.1
Electrical Specifications
Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except as noted below (Note 1). . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VIO + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0V
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1.
2.
3.
4.
Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage
transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2.
Minimum DC input voltage on pin WP#⁄ACC is –0.5 V. During voltage transitions, WP#⁄ACC may overshoot VSS to 2.0 V
for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on pin WP#⁄ACC is +9.5 V, which may overshoot to
10.5 V for periods up to 20 ns.
No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than
one second.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 11.1
Maximum Negative Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
Figure 11.2
November 23, 2005 S29PL-N_00_A4
20 ns
Maximum Positive Overshoot Waveform
S29PL-N MirrorBit™ Flash Family
59
P r e l i m i n a r y
11.2
Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.7 V to 3.1 V or
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V
(Note 3)
Notes:
1.
2.
3.
11.3
Operating ranges define those limits between which the functionality of the device is guaranteed.
For all AC and DC specifications, VIO = VCC.
Voltage range of 2.7 – 3.1 V valid for PL-N MCP products.
Test Conditions
Device
Under
Test
CL
Figure 11.3
Table 11.1
Test Setup
Test Specifications
Test Condition
All Speeds
Unit
30
pF
Output Load Capacitance, CL (including jig capacitance)
11.4
Input Rise and Fall Times
VCC = 3.0 V
5
ns
Input Pulse Levels
VCC = 3.0 V
0.0 – 3.0
V
Input timing measurement reference levels
VCC/2
V
Output timing measurement reference levels
VCC/2
V
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
60
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State
(High Z)
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
11.5
Switching Waveforms
All Inputs and Outputs
VIO
Input
VCC/2
Measurement Level
VCC/2
Output
0.0 V
Figure 11.4
11.6
Input Waveforms and Measurement Levels
VCC Power Up
Parameter
Description
Test Setup
Speed
Unit
tVCS
VCC Setup Time
Min
250
µs
tREAD
Time between RESET# high and CE# low
Min
200
ns
Notes:
1.
2.
VCC ramp rate must exceed 1 V/400 µs.
VIO is internally connected to VCC.
tVCS
VCC
VCC min
VIH
RESET#
tRead
CE#
Figure 11.5
November 23, 2005 S29PL-N_00_A4
VCC Power-Up Diagram
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11.7
DC Characteristics
11.7.1 DC Characteristics (VCC = 2.7 V to 3.6 V)
(CMOS Compatible)
Parameter
Symbol
ILI
Parameter Description
(Notes)
Min
(Note 2)
Test Conditions
Typ
(Note 2)
Max
Unit
±2.0
µA
±1.0
µA
30
45
mA
Input Load Current
VIN = VSS to VCC, VCC = VCC
ILO
Output Leakage Current
VOUT = VSS to VCC, OE# = VIH
VCC = VCC max (6)
ICC1
VCC Active Read Current (1, 3)
OE# = VIH,
VCC = VCC max (1, 6)
ICC2
VCC Active Write Current (3)
OE# = VIH, WE# = VIL
25
50
mA
ICC3
VCC Standby Current
CE# (7), RESET#,
WP#/ACC = VCC ± 0.3 V
20
40
µA
ICC4
VCC Reset Current
RESET# = VSS ± 0.3 V
300
500
µA
ICC5
Automatic Sleep Mode (4)
VIH = VCC ±0.3 V; VIL = VSS ± 0.3 V
20
40
µA
ICC6
VCC Active Read-While-Write
Current (1)
OE# = VIH
5 MHz
35
50
mA
ICC7
VCC Active Program-While-EraseOE# = VIH
Suspended Current (5)
27
55
mA
ICC8
VCC Active Page Read Current
6
10
mA
OE# = VIH, 8 word
Page Read
max
(6)
5 MHz
40 MHz
VIL
Input Low Voltage
VCC = 2.7 to 3.6 V
–0.5
0.8
V
VIH
Input High Voltage
VCC = 2.7 to 3.6 V
2.0
VCC + 0.3
V
VHH
Voltage for ACC Program
Acceleration
VCC = 3.0 V ±10% (6)
8.5
9.5
V
0.1
V
2.5
V
VOL
Output Low Voltage
IOL = 100 µA, VCC = VCC min (6)
VOH
Output High Voltage
IOH = –100 µA (6)
VLKO
Low VCC Lock-Out Voltage (5)
VCC – 0.2
2.3
V
Notes:
1.
2.
3.
4.
5.
6.
7.
62
The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH.
Maximum ICC specifications are tested with VCC = VCC max, TA = TAmax. Typical ICC specifications are with typical
VCC=3.0 V, TA = +25°C.
ICC is active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC +30 ns. Typical sleep mode
current is 1 µA.
Not 100% tested.
The data in the table is for VCC range 2.7 V to 3.6 V (recommended for standalone applications).
CE1# and CE2# for the PL129N.
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
11.7.2 DC Characteristics (VCC = 2.7 V to 3.1 V)
(CMOS Compatible)
Parameter
Symbol
ILI
Parameter Description
(Notes)
Test Conditions
Min
Typ
Max
Unit
±2
µA
±1
µA
28
40
mA
Input Load Current
VIN = VSS to VCC, VCC = VCC
ILO
Output Leakage Current
VOUT = VSS to VCC, OE# = VIH
VCC = VCC max (6)
ICC1
VCC Active Read Current (1, 2)
OE# = VIH,
VCC = VCC max (1, 6)
ICC2
VCC Active Write Current (2, 3)
OE# = VIH, WE# = VIL
22
40
mA
ICC3
VCC Standby Current (2)
CE# (7), RESET#, WP#/ACC
= VCC ± 0.3 V
20
40
µA
max
(6)
5 MHz
ICC4
VCC Reset Current (2)
RESET# = VSS ± 0.3 V
300
500
µA
ICC5
Automatic Sleep Mode (2, 4)
VIH = VCC ±0.3 V; VIL = VSS ± 0.1 V
20
40
µA
ICC6
VCC Active Read-While-Write
Current (1, 2)
OE# = VIH
33
45
mA
ICC7
VCC Active Program-While-EraseSuspended Current (2, 5)
OE# = VIH
24
45
mA
ICC8
VCC Active Page Read Current (2)
OE# = VIH,
8 word Page Read
6
9
mA
VIL
Input Low Voltage
VCC = 2.7 to 3.6 V
–0.5
0.8
V
VCC = 2.7 to 3.6 V
2.0
VCC + 0.3
V
8.5
9.5
V
0.1
V
2.5
V
5 MHz
40 MHz
VIH
Input High Voltage
VHH
Voltage for ACC Program Acceleration VCC = 3.0 V ±10% (6)
VOL
Output Low Voltage
IOL = 100 µA, VCC = VCC min (6)
VOH
Output High Voltage
IOH = –100 µA (6)
VLKO
Low VCC Lock-Out Voltage (5)
VCC – 0.2
2.3
V
Notes:
1.
2.
3.
4.
5.
6.
7.
The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH.
Maximum ICC specifications are tested with VCC = VCC max, TA = TAmax. Typical ICC specifications are with typical
VCC=2.9 V, TA = +25°C.
ICC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 1 µA.
Not 100% tested.
Data in table is for VCC range 2.7 V to 3.1 V (recommended for MCP applications)
CE1# and CE2# for the PL129N.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
63
P r e l i m i n a r y
11.8
AC Characteristics
11.8.1 Read Operations
Parameter
Description
(Notes)
JEDEC
Std.
tAVAV
tRC
tAVQV
tACC Address to Output Delay
tELQV
tCE
Speed Options
Test Setup
65
70
80
Unit
Min
65
70
80
ns
CE#, OE# = VIL
Max
65
70
80
ns
OE# = VIL
Max
65
70
80
ns
Max
25
30
30
ns
25
30
30
ns
Read Cycle Time (1)
Chip Enable to Output Delay (5)
tPACC Page Access Time
tGLQV
tOE
Output Enable to Output Delay
Max
tEHQZ
tDF
Chip Enable to Output High Z (3)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (1, 3)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (3)
Min
5
ns
Read
Min
0
ns
Toggle and Data# Polling
Min
10
ns
tOEH Output Enable Hold Time (1)
Notes:
1.
2.
3.
4.
5.
Not 100% tested.
See Figure 11.3 and Table 11.1 for test specifications
Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE#
high to the data bus driven to VCC /2 is taken as tDF.
For 70pf Output Load Capacitance, 2 ns is added to the above tACC ,tCE ,tPACC ,tOE values for all speed grades
CE1# and CE2# for the PL129N.
11.8.2 Read Operation Timing Diagrams
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Valid Data
Data
RESET#
RY/BY#
0V
Figure 11.6
64
Read Operation Timings
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
A22 to A3
Same page Addresses
A2 to A0
Aa
Aa+1
Aa+2
Aa+3
Aa+4
Aa+5
Aa+6
Aa+7
tACC
tCE
CE#
tOEH
OE#
tOE
tDF
tPACC
WE#
tOH
High-Z
Output
Da
tPACC
tOH
Da+1
tPACC
tPACC
tOH
Da+2
tOH
Da+3
tPACC
tOH
tPACC
tOH
Da+4
tPACC
tOH
tOH
Da+5
Da+6
Da+7
Figure 11.7 Page Read Operation Timings
11.8.3 Hardware Reset (RESET#)
Parameter
All Speed Options
Description
JEDEC
Unit
Std.
tRP
RESET# Pulse Width
Min
30
µs
tRH
Reset High Time Before Read (See Note)
Min
200
ns
Note: Not 100% tested.
CE#, OE#
tRH
RESET#
tRP
Figure 11.8
November 23, 2005 S29PL-N_00_A4
Reset Timings
S29PL-N MirrorBit™ Flash Family
65
P r e l i m i n a r y
11.8.4 Erase/Program Timing
Parameter
Speed Options
Description (Notes)
Unit
JEDEC
Std
tAVAV
tWC
Write Cycle Time (1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
35
ns
tAHT
Address Hold Time From CE# or OE# high during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
30
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
10
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
40
ns
tWHDL
tWPH
Write Pulse Width High
Min
25
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tWHWH1
tWHWH1
Programming Operation
Typ
40
µs
tWHWH1
tWHWH1
Accelerated Programming Operation
Typ
24
µs
tWHWH2
tWHWH2
Sector Erase Operation
Typ
1.6
sec
tVHH
VHH Rise and Fall Times
Min
250
ns
Write Recovery Time from RY/BY#
Min
0
ns
tBUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
tWEP
Noise Pulse Margin on WE#
Max
3
ns
tSEA
Sector Erase Accept Time-out
Max
50
µs
tESL
Erase Suspend Latency
Max
20
µs
tPSL
Program Suspend Latency
Max
20
µs
tASP
Toggle Time During Sector Protection
Typ
100
µs
tPSP
Toggle Time During Programming Within a Protected Sector
Typ
1
µs
tWLAX
tRB
65
70
80
65
70
80
ns
Notes:
1.
2.
3.
4.
66
Not 100% tested.
In program operation timing, addresses are latched on the falling edge of WE#.
See Program/Erase Operations for more information.
Does not include the preprogramming time.
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
DOUT
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address
Figure 11.9
Program Operation Timings
VHH
WP#/ACC
VIL or VIH
VIL or VIH
tVHH
Figure 11.10
November 23, 2005 S29PL-N_00_A4
tVHH
Accelerated Program Timing Diagram
S29PL-N MirrorBit™ Flash Family
67
P r e l i m i n a r y
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
30h
Status
DOUT
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status)
Figure 11.11
Addresses
Chip/Sector Erase Operation Timings
tWC
tWC
tRC
Valid PA
Valid RA
tWC
Valid PA
Valid PA
tAH
tAS
tAS
tCPH
tACC
tAH
tCE
CE#
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tWPH
tDF
tDS
tOH
tDH
Data
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Figure 11.12
68
Read Cycle
CE# Controlled Write Cycles
Back-to-back Read/Write Cycle Timings
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ6–DQ0
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle
Figure 11.13
Data# Polling Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
DQ6/DQ2
tOE
Valid Data
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle
Figure 11.14
November 23, 2005 S29PL-N_00_A4
Toggle Bit Timings (During Embedded Algorithms)
S29PL-N MirrorBit™ Flash Family
69
P r e l i m i n a r y
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase
Erase Suspend
Read
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to
toggle DQ2 and DQ6.
Figure 11.15
DQ2 vs. DQ6
11.8.5 Erase and Programming Performance
Parameter
(Notes)
128 Kword
Sector Erase Time
32 Kword
Device
Condition
Typ
(Note 1)
Max
(Note 2)
VCC
1.6
7
ACC
1.6
7
VCC
0.3
4
ACC
0.3
4
VCC
202 (PL256N)
100 (PL127N)
100(PL129N)
900 (PL256N)
450 (PL127N)
450 (PL129N)
ACC
130 (PL256N)
65 (PL127N)
65 (PL129N)
512 (PL256N)
256 (PL127N)
256 (PL129N)
VCC
40
400
ACC
24
240
VCC
9.4
94
ACC
6
60
VCC
300
3000
ACC
192
1920
VCC
157.3 (PL256N)
78.6 (PL127N)
78.6 (PL129N)
315 (PL256N)
158 (PL127N)
158 (PL129N)
ACC
100 (PL256N)
50 (PL127N)
50 (PL129N)
200 (PL256N)
100 (PL127N)
100 (PL129N)
Chip Erase Time
Word Programming Time
Effective Word Programming Time
utilizing Program Write Buffer
Total 32-Word Buffer
Programming Time
Chip Programming Time
using 32-Word Buffer (3)
Unit
Comments
(Notes)
s
Excludes 00h programming
prior to erasure (4)
s
µs
Excludes system level overhead
(5)
µs
µs
s
Erase Suspend/Erase Resume
<20
µs
Program Suspend/Program Resume
<20
µs
Excludes system level overhead
(5)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
70
Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 10,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
Under worst case conditions of 90°C, VCC = 2.7 V, 100,000 cycles. All values are subject to change.
The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
See Table 12.1 and Table 12.2 for further information on command definitions.
Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions.
See Application Note Erase Suspend/Resume Timing for more details.
Word programming specification is based upon a single word programming operation not utilizing the write buffer.
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
11.8.6 BGA Ball Capacitance
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
7
10
pF
COUT
Output Capacitance
VOUT = 0
8
12
pF
CIN2
Control Pin Capacitance
VIN = 0
8
11
pF
Notes:
1.
2.
Sampled, not 100% tested.
Test conditions TA = 25°C, f = 1.0 MHz.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
71
P r e l i m i n a r y
72
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
12 Appendix
This section contains information relating to software control or interfacing with the Flash device.
For additional information and assistance regarding software, see Additional Resources, or explore the Web at www.amd.com and www.fujitsu.com.
Table 12.1
Device ID (10)
6
555
AA
2AA
55
[BA]555
90
[BA]X01 227E [BA]X0E
Indicator Bits
4
555
AA
2AA
55
[BA]555
90
[BA]X03
AA
AA
29
AA
AA
AA
B0
30
98
AA
A0
80
80
98
90
2AA
2AA
55
55
555
SA
A0
25
2AA
2AA
2AA
55
55
55
555
555
555
F0
80
80
2AA
PA
SA
XXX
55
PD
30
10
555
20
XXX
00
555
88
555
90
Read (7)
Reset (8)
Program
Write to Buffer (17)
Program Buffer to Flash
Write to Buffer Abort Reset (17)
Chip Erase
Sector Erase
Program/Erase Suspend (14)
Program/Erase Resume (15)
CFI Query (16)
Unlock Bypass Entry
Unlock Bypass Program (12, 13)
Unlock
Unlock Bypass Sector Erase (12, 13)
Bypass
Unlock Bypass Erase (12, 13)
Mode
Unlock Bypass CFI (12, 13)
Unlock Bypass Reset
Secured Silicon Sector Command Definitions
Secured Silicon Sector Entry (18)
Secured
Secured Silicon Sector Program
Silicon
Secured Silicon Sector Read
Sector
Secured Silicon Sector Exit (19)
Cycles
Manufacturer ID
1
1
4
Bus Cycles (Notes 1 – 6)
First
Second
Third
Fourth
Addr
Data Addr Data
Addr
Data
Addr
Data
RA
RD
XXX
F0
555
AA 2AA 55 [BA]555 90 [BA]X00 0001
Command Sequence
(Notes)
Autoselect
(9)
Memory Array Commands
4
555
6
555
1
SA
3
555
6
555
6
555
1
BA
1
BA
1 [BA]555
3
555
2
XX
2
XX
2
XX
1
BA
2
XX
3
2
1
4
555
XX
RA
555
AA 2AA 55
A0
PA data
data
AA 2AA 55
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse whichever
happens later.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
Notes:
1. See (Table 7.1) for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read
cycle, fourth through sixth cycles of the Autoselect commands,
fourth cycle of the password verify command, and any cycle
reading at RD(0) and RD(1).
4. Data bits DQ15 – DQ8 are don’t care in command sequences,
except for RD, PD, WD, PWD, and PWD3 – PWD0.
5. Unless otherwise noted, these address bits are don’t cares:
PL127: A22 – A15; 129N: A21 – A15; PL256N: A23 – A14.
6. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
7. No unlock or command cycles required when bank is reading
array data.
8. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
November 23, 2005 S29PL-N_00_A4
Fifth
Addr
Data
Sixth
Addr
Data
(Note
[BA]X0F 2200
10)
PA
SA
(Note
11)
Data
WC
PA
PD
WBL
PD
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
XX
00
SA = Sector Address. PL127/129N = A22 – A15;
PL256N = A23 – A15.
BA = Bank Address. PL256N = A23 – A21; PL127N = A22 – A20;
PL127N = A21 – A20.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
9.
10.
11.
12.
13.
14.
15.
16.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See
Autoselect.
Device IDs: PL256N = 223Ch; PL127N = 2220h;
PL129N = 2221h.
See Autoselect.
The Unlock Bypass command sequence is required prior to this
command sequence.
The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
The total number of cycles in the command sequence is
determined by the number of words written to the write buffer.
The maximum number of cycles in the command sequence is 37.
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73
P r e l i m i n a r y
21. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address equals 55h on all
future devices, but 555h for PL256N.
22. Requires Entry command sequence prior to execution. Secured
Silicon Sector Exit Reset command is required to exit this mode;
device may otherwise be placed in an unknown state.
17. Command sequence resets device for next command after writeto-buffer operation.
18. Entry commands are needed to enter a specific mode to enable
instructions only available within that mode.
19. The Exit command must be issued to reset the device into read
mode. Otherwise the device hangs.
20. The following mode cannot be performed at the same time.
Autoselect/CFI/Unlock Bypass/Secured Silicon. Command
sequence resets device for next command after write-to-buffer
operation.
Command Sequence
(Notes)
Lock Register Command Set Definitions
Lock Register Command Set Entry (25)
Lock Register Bits Program (26)
Lock
Register Lock Register Bits Read
Lock Register Command Set Exit (27)
Password Protection Command Set Definitions
Password Protection
Command Set Entry (25)
Password Program
Password
Cycles
Table 12.2
Sector Protection Commands
First
Addr Data
Second
Addr Data
3
2
1
2
555
XX
00
XX
AA
A0
data
90
2AA
00
55
data
XX
00
3
555
AA
2AA
55
2
XX
PWD0/
00/01 PWD1/
A0
02/03 PWD2/
PWD3
PWD0
01
PWD1
25
00
03
Password Read
4
00
Password Unlock
7
00
Password Protection
2
XX
90
XX
Command Set Exit (27)
Non-Volatile Sector Protection Command Set Definitions
Non-Volatile Sector Protection
3 555
AA
2AA
Command Set Entry (25)
PPB Program
2
XX
A0 [BA]SA
All PPB Erase (22)
2
XX
80
00
PPB
PPB Status Read
1 [BA]SA RD(0)
Non-Volatile Sector Protection
2
XX
90
XX
Command Set Exit (27)
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Volatile Sector Protection Freeze
3 555
AA
2AA
Command Set Entry (25)
2
XX
A0
XX
PPB Lock PPB Lock Bit Set
Bit
PPB Lock Bit Status Read
1
BA
RD(0)
Global Volatile Sector Protection Freeze
2
XX
90
XX
Command Set Exit (27)
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection
3 555
AA
2AA
Command Set Entry (25)
DYB Set
2
XX
A0 [BA]SA
DYB Clear
2
XX
A0 [BA]SA
DYB
DYB Status Read
1 [BA]SA RD(0)
Volatile Sector Protection
2
XX
90
XX
Command Set Exit (27)
Legend:
X = Don’t care
RA = Read Address.
RD = Read Data.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse whichever
happens later.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
SA = Sector Address. PL127/129N = A22 – A15; PL256N = A23 –
A15
74
Bus Cycles (Notes 1 – 6)
Third
Fourth
Fifth
Sixth
Seventh
Addr Data Addr Data Addr Data Addr Data Addr Data
555
40
555
60
02
00
PWD2
PWD0
[BA]555
C0
555
50
[BA]555
E0
03
01
PWD3
PWD1
02
PWD2
03
PWD3
00
29
00
55
00
30
00
55
00
00
55
00
01
00
BA = Bank Address. PL256N = A23 – A21; PL127N = A22 – A20;
PL127N = A21 – A20.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
PWD3 – PWD0 = Password Data. PD3 – PD0 present four 16 bit
combinations that represent the 64-bit Password
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if
unprotected, DQ0 = 1.
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Notes:
1. See (Table 7.1) for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read
cycle, fourth through sixth cycles of the Autoselect commands,
and password verify commands, and any cycle reading at RD(0)
and RD(1).
4. Data bits DQ15 – DQ8 are don’t care in command sequences,
except for RD, PD, WD, PWD, and PWD3 – PWD0.
5. Unless otherwise noted, these address bits are don’t cares:
PL127: A22 – A15; 129N: A21 – A15; PL256N: A23 – A14.
6. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
7. No unlock or command cycles required when bank is reading
array data.
8. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
9. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See
Autoselect.
10. The data is 0000h for an unlocked sector and 0001h for a locked
sector.
11. Device IDs: PL256N = 223Ch; PL127N = 2220h;
PL129N = 2221h.
12. See Autoselect.
13. The Unlock Bypass command sequence is required prior to this
command sequence.
14. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass
mode.The system may read and program in non-erasing sectors,
or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
12.1
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.The total number of cycles in
the command sequence is determined by the number of words
written to the write buffer. The maximum number of cycles in
the command sequence is 37.
17. The entire four bus-cycle sequence must be entered for which
portion of the password.
18. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass
mode.The system may read and program in non-erasing sectors,
or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
19. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
20. Command is valid when device is ready to read array data or
when device is in autoselect mode.The total number of cycles in
the command sequence is determined by the number of words
written to the write buffer. The maximum number of cycles in
the command sequence is 37.
21. The entire four bus-cycle sequence must be entered for which
portion of the password.
22. The ALL PPB ERASE command pre-programs all PPBs before
erasure to prevent over-erasure of PPBs.
23. WP#/ACC must be at VHH during the entire operation of this
command.
24. Command sequence resets device for next command after writeto-buffer operation.
25. Entry commands are needed to enter a specific mode to enable
instructions only available within that mode.
26. If both the Persistent Protection Mode Locking Bit and the
password Protection Mode Locking Bit are set a the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode.
27. The Exit command must be issued to reset the device into read
mode. Otherwise the device hangs.
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12.3 – 12.6) within that bank. All reads outside of the
CFI address range, within the bank, return non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available at www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*((UINT16 *)bank_addr + 0x555) = 0x0098;
/* write CFI entry command
*/
/* Example: CFI Exit command */
*((UINT16 *)bank_addr + 0x000) = 0x00F0;
/* write cfi exit command
*/
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P r e l i m i n a r y
For further information, please see the CFI Specification (see JEDEC publications JEP137-A and
JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.
Table 12.3
CFI Query Identification String
Addresses
Data
10h
11h
12h
0051h
0052h
0059h
Description
Query Unique ASCII string QRY
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Table 12.4
Addresses
Data
Description
1Bh
0027h
VCC Min. (write/erase)
D7 – D4: volt, D3 – D0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase)
D7 – D4: volt, D3 – D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0006h
Typical timeout per single byte/word write 2N µs
20h
0009h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
000Bh
Typical timeout per individual block erase 2N ms
22h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
0003h
Max. timeout for byte/word write 2N times typical
24h
0003h
Max. timeout for buffer write 2N times typical
25h
0002h
Max. timeout per individual block erase 2N times typical
26h
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Addresses
Data
27h
0019h (PL256N)
0018h (PL127N)
0018h (PL129N)
28h
29h
0001h
0000h
Flash Device Interface description (see CFI publication 100)
2Ah
2Bh
0006h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Table 12.5
76
System Interface String
Device Geometry Definition
Description
Device Size = 2N byte
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0000h
0001h
Erase Block Region 1 Information
(see the CFI specification or CFI publication 100)
31h
007Dh (PL256N)
003Dh (PL127N)
003Dh (PL129N)
32h
33h
34h
0000h
0000h
0004h
35h
36h
37h
38h
0003h
0000h
0000h
0001h
Erase Block Region 2 Information
(see the CFI specification or CFI publication 100)
Erase Block Region 3 Information
(see the CFI specification or CFI publication 100)
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Table 12.6
Primary Vendor-Specific Extended Query
Addresses
Data
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string PRI
43h
0031h
Major version number, ASCII (reflects modifications to the silicon)
44h
0034h
Minor version number, ASCII (reflects modifications to the CFI table)
45h
0010h
Address Sensitive Unlock (Bits 1 – 0)
0 = Required, 1 = Not Required
Silicon Technology (Bits 5 – 2) 0100 = 0.11 µm
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0008h (PL-N)
Sector Protect/Unprotect scheme
01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode,
04 = 29LV800 mode 07 = New Sector Protect mode,
08 = Advanced Sector Protection
4Ah
0073h (PL256N)
003Bh (PL127N)
003Bh (PL129N)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors except Bank A
4Bh
0000h
4Ch
0002h (PL-N)
4Dh
0085h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7 – D4: Volt, D3 – D0: 100 mV
4Eh
0095h
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7 – D4: Volt, D3 – D0: 100 mV
4Fh
0001h
Top/Bottom Boot Sector Flag
00h = No Boot, 01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top
Boot Device
50h
0001h
Program Suspend
0 = Not supported, 1 = Supported
51h
0001h
Unlock Bypass
00 = Not Supported, 01=Supported
52h
0007h
Secured Silicon Sector (Customer OTP Area) Size 2N bytes
53h
000Fh
Hardware Reset Low Time-out during an embedded algorithm to read mode
Maximum 2N ns
54h
000Eh
Hardware Reset Low Time-out not during an embedded algorithm to read mode
Maximum 2N ns
55h
0005h
Erase Suspend Time-out Maximum 2N µs
56h
0005h
Program Suspend Time-out Maximum 2N µs
57h
0004h
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
58h
0013h (PL256N)
000Bh (PL127N)
000Bh (PL129N)
Bank A Region Information. X = Number of sectors in bank
59h
0030h (PL256N)
0018h (PL127N)
0018h (PL129N)
Bank 1 Region Information. X = Number of sectors in bank
5Ah
0030h (PL256N)
0018h (PL127N)
0018h (PL129N)
Bank 2 Region Information. X = Number of sectors in bank
5Bh
0013h (PL256N)
000Bh (PL127N)
000Bh (PL129N)
Bank 3 Region Information. X = Number of sectors in bank
November 23, 2005 S29PL-N_00_A4
Description
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
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P r e l i m i n a r y
13 Commonly Used Terms
Term
Definition
ACC
ACCelerate. A special purpose input signal which allows for faster programming or
erase operation when raised to a specified voltage above VCC. In some devices ACC
may protect all sectors when at a low voltage.
Amax
Most significant bit of the address input [A23 for 256 Mbit, A22 for 128 Mbit, A21 for
64 Mbit]
Amin
Least significant bit of the address input signals (A0 for all devices in this document).
Asynchronous
Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Autoselect
Read mode for obtaining manufacturer and device information as well as sector
protection status.
Bank
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Boot sector
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power on or reset.
Boundary
Location at the beginning or end of series of memory locations.
Burst Read
See synchronous read.
Byte
8 bits
CFI
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
Clear
Zero (Logic Low Level)
Configuration Register
Special purpose register which must be programmed to enable synchronous read
mode
Continuous Read
Synchronous method of burst read whereby the device reads continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Erase
Returns bits of a Flash memory array to their default state of a logical One (High Level).
Erase Suspend/Erase Resume
Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
BGA
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
Linear Read
Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
or without wraparound before requiring a new initial address.
MCP
Multi-Chip Product. A method of combining integrated circuits in a single package by
stacking multiple die of the same or different devices.
Memory Array
The programmable area of the product available for data storage.
MirrorBit™ Technology
Spansion™ trademarked technology for storing multiple bits of data in the same
transistor.
Page
Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.
78
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Term
Definition
Page Read
Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less page
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.
Password Protection
Sector protection method which uses a programmable password, in addition to the
Persistent Protection method, for protection of sectors in the Flash memory device.
Persistent Protection
Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.
Program
Stores data into a Flash memory by selectively clearing bits of the memory array to
leave a data pattern of ones and zeros.
Program Suspend/Program
Resume
Halts a programming operation to read data from any location that is not selected for
programming or erase.
Read
Host bus cycle that causes the Flash to output data onto the data bus.
Registers
Dynamic storage bits for holding device control information or tracking the status of
an operation.
Secured Silicon
An area consisting of 256 bytes in which any word may be programmed once, and the
entire area may be protected once from any future programming. Information in this
area may be programmed at the factory or by the user. Once programmed and
protected there is no way to change the secured information. This area is often used
to store a software readable identification such as a serial number.
Sector Protection
Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase ignore the program or erase commands related to that
sector.
Sector
An Area of the memory array in which all bits must be erased together by an erase
operation.
Simultaneous Operation
Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank. Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.
Synchronous Operation
Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).
VersatileIO™ (VIO)
Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.
Unlock Bypass
Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two Unlock
write cycles, of the usual 4 cycle Program command, are not required – reducing all
Program commands to two bus cycles while in this mode.
Word
November 23, 2005 S29PL-N_00_A4
Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.
S29PL-N MirrorBit™ Flash Family
79
P r e l i m i n a r y
Term
Definition
Wraparound
Special burst read mode where the read address wraps or returns back to the lowest
address boundary in the selected range of words, after reading the last Byte or Word
in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read
words in the sequence 2, 3, 0, 1.
Write
Interchangeable term for a program/erase operation where the content of a register
and or memory location is being altered. The term write is often associated with writing
command cycles to enter or exit a particular mode of operation.
Write Buffer
Multi-word area in which multiple words may be programmed as a single operation. A
Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary
respectively.
Write Buffer Programming
Method of writing multiple words, up to the maximum size of the Write Buffer, in one
operation. Using Write Buffer Programming results in greater than eight times faster
programming time than by using single word at a time programming commands.
Write Operation Status
Allows the host system to determine the status of a program or erase operation by
reading several special purpose register bits.
80
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
81
P r e l i m i n a r y
14 Revisions
Revision A0 (February 28, 2005)
Initial Release
Revision A1 (August 8, 2005)
Performance Characteristics
Updated Package Options
MCP Look-Ahead Connection Diagram
Corrected Pinout
Memory Map
Added Sector and Memory Address Map for S29PL127N
Device Operation Table
Added Dual Chip Enable Device Operation Table
VCC Power Up
Updated tVCS.
Added VCC ramp rate restriction
DC Characteristics
Updated typical and maximum values.
Revision A2 (October 25, 2005)
Ordering Information
Updated table.
Connection Diagram and Package Dimensions - S29PL-N Fortified BGA
Added pinout and package dimensions.
Global
Changed data sheet status from Advance Information to Preliminary.
Removed Byte Address Information
Distinctive and Performance Characteristics
Removed Enhanced VersatileI/O, updated read access times, and Package options.
Logic Symbol and Block Diagram
Removed VIO from Logic Symbol and Block Diagram.
Erase and Programming Performance
Updated table.
Write Buffer Programming
Updated Write Buffer Abort Description.
Operating Ranges
Updated VIO supply voltages.
DC characteristics
Updated ICC1, ICC4, ICC6.
82
S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005
P r e l i m i n a r y
Revision A3 (November 14, 2005)
Ordering Information
Updated table
Valid Combinations Table
Updated table
Revision A4 (November 23, 2005)
Logic Symbols
Removed VIO from the illustrations
Block Diagram
Removed VIO from the illustration
Connection Diagrams
Modified Fortified BGA Pinout (LAA064)
PL129N Sector and Memory Address Map
Updated Address Ranges for Banks 2A and 2B
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product
names used in this publication are for identification purposes only and may be trademarks of their respective companies.
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit™ Flash Family
83