ETC S9518

SUMMIT
S9518
MICROELECTRONICS, Inc.
Nonvolatile DACPOT™ Electronic Potentiometer
With Debounced Push Button Interface
FEATURES
Digitally Controlled Electronic Potentiometer
OVERVIEW
• 8-Bit Digital-to-Analog Converter (DAC)
– Independent Reference Inputs
– Differential Non-Linearity - ±0.5LSB max
– Integral Non-Linearity - ±1LSB max
• VOUT Value in EEPROM for Power-On Recall
– Equivalent to 256-Step Potentiometer
• Unity Gain Op Amp Drives up to 1mA
The S9518 DACPOT trimmer is an 8-bit nonvolatile DAC
designed to replace mechanical potentiometers. The
S9518 includes a unity-gain amplifier to buffer the DAC
output and enables VOUT to swing from rail to rail. The
DACPOT trimmer operates over a supply voltage range of
2.7V to 5.5V.
The S9518’s simple push button input provides an ideal
interface for operator adjusted equipment. This interface
allows for quick and easy adjustment of even the most
sophisticated systems.
• Simple Trimming Adjustment
– Debounced Push Button Interface
• Low Noise Operation
• “Clickless” Transitions between DAC Steps
The S9518 is a pin-compatible performance upgrade for
other industry nonvolatile potentiometers. The S9518
offers double the resolution of these devices and provides
‘clickless’ transitions of VOUT.
• No Mechanical Wearout Problem
– 1,000,000 Stores (typical)
– 100 Year Data Retention
• Operation from +2.7V to +5.5V Supply
• Low Power, 1mW max at +5V
FUNCTIONAL BLOCK DIAGRAM
VDD
Debounce Circuit
& Write Control
Logic
8-bit Data Register
8-bit E2PROM
VH
VOUT
8-bit DAC
VL
UP DWN STR
SUMMIT MICROELECTRONICS, Inc.
•
300 Orchard City Drive, Suite 131
© SUMMIT MICROELECTRONICS, Inc. 1999
2017-04 4/24/99
GND
•
Campbell, CA 95008
1
2017 ILL2.2
•
Telephone 408-378-6461
•
Fax 408-378-6586
•
www.summitmicro.com
Characteristics subject to change without notice
S9518
PIN NAMES
Symbol
PINOUT
Description
UP
PB Input, Moves VOUT Toward
VH Input
DWN
PB Input, Moves VOUT Toward
VL Input
VH
Vref High
GND
Ground
VOUT
Trimmed Voltage Output
VL
UP
1
8
VDD
DWN
2
7
STR
VH
3
6
VL
GND
4
5
VOUT
2017 ILL1.1
Vref Low
STR
Store Input, Providing a Control
Input to Initiate a Store Operation
VDD
Supply Voltage (2.7V to 5.5V)
2017 PGM T1.0
Analog Section
The S9518 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital values into equivalent analog
output voltages in proportion to the applied reference
voltage.
counter increments faster, one count every 50ms, until
the push-button is released. Changes to the DAC output
using the UP input do not alter the data stored in
EEPROM. The STR input updates the nonvolatile
EEPROM memory.
DWN is an active low push-button input that decrements
the counter and moves the potentiometer output voltage
towards the VL reference input. The DWN control input
also includes an internal 50kohm pull-up resistor and a
30ms debounce period to prevent multiple pulsing. A
LOW logic level will also change the potentiometer tap
position after the debounce period. If the DWN pushbutton is kept depressed, the counter continues to decrement at the rate of one count every 250ms for one second.
After one second the counter decrements at one count
every 50ms until the push-button is released. Changes to
the DAC output using the DWN input do not alter the data
stored in EEPROM.
Reference Inputs
The voltage differential between the VL and VH inputs
sets the full-scale output voltage range. VL must be equal
to or greater than ground (a positive voltage). VH must be
greater than VL and less than or equal to VDD. See
specifications on page 5 for guaranteed operating limits.
Output Buffer Amplifier
The voltage output is from a precision unity-gain follower
that can slew up to 1V/µs.
Digital Interface
The interface provides simple push button control of an
up/down counter that drives the DAC. The DAC output is
a ratiometric voltage output.
STR This input can be used in two ways:
1) If the input is tied LOW, then AUTOSTORE is enabled. When VDD powers-down an automatic store
cycle takes place that updates the nonvolatile
EEPROM memory.
UP is an active low push-button input. An internal pull-up
resistor, with nominal value of 50kohm, eliminates an
external resistor that would be required with push button
control. A 30ms debounce period is included in the input
timing to prevent multiple pulsing of the counter. Either a
switch closure to ground or a LOW logic level will, after the
debounce time, change the potentiometer tap position.
UP moves the output voltage towards the VH reference
input. If the UP push-button is kept depressed, the
counter will continue to increment at the rate of one count
every 250ms for one second. After one second the
2) STR is an active low push-button input that also
updates the nonvolatile memory. The input is
debounced but does not have an internal pull-up
resistor. For every valid push, the S9518 will store the
current potentiometer position to EEPROM.
2017-04 4/24/99
2
S9518
DEVICE OPERATION
There are five main blocks to the S9518: an 8-bit
EEPROM memory; input debounce circuits, control logic,
and 8-bit counter; 8-bit data register; decode section and
resistor ladder (DAC); and the buffer amplifier. The input
control section operates just like an up/down counter. The
output of this counter is fed to the data register and then
decoded to activate one of 255 electronic switches connected to the resistor ladder. Each switch connects a point
on the ladder to the buffer amplifier input. When requested, the contents of the counter can be stored in
EEPROM memory and retained for future use. The ladder
is comprised of 256 resistors of equal value connected in
series. At the bottom of the ladder and at the junctions of
the resistors there are electronic switches that transfer the
voltage at each point to the buffer amplifier and hence to
the output. The S9518 is designed to interface directly to
two push button switches that effectively move the potentiometer wiper up or down. The UP and DWN inputs
increment or decrement the 8-bit counter respectively.
The data input to the DAC is decoded to select one of the
256 wiper positions along the resistive ladder. The wiper
increment input, UP and the wiper decrement input, DWN
are connected to internal pull-ups so that they normally
remain HIGH. When pulled LOW by an external push
button switch or a logic LOW level input, the wiper will be
switched to the next adjacent tap position. Internal
debounce circuitry prevents inadvertent switching of the
wiper position if UP or DWN remain LOW for less than
30ms (typical). Each of the buttons can be pushed either
once for a single increment/decrement or held low continuously for a multiple increments/decrements. The
number of increments/decrements of the wiper position
Effect of VDD Removal
The resistor ladder, connected between VH and VL, does
not change value when VDD is removed. However, the
buffer amplifier no longer functions and consequently a
high impedance appears at the VOUT pin.
Figure 1: Typical circuit with STR store pin used in
AUTOSTORE mode
Figure 2: Typical circuit with STR store pin
controlled by push button switch
VCC
depends on how long the button is pushed. When making
a continuous push, after the first second, the increment/
decrement speed increases. For the first second the
device will be in the slow scan mode. Then if the button is
held for longer than one second the device will go into the
fast scan mode. As soon as the button is released the
S9518 will return to a standby condition. The DAC,
whether set to 00 or FF, acts like its mechanical equivalent
and does not move beyond the last position. That is, the
counter does not wrap around when clocked beyond FF
or below 00.
AUTOSTORE
The value of the counter is stored in EEPROM memory
whenever the chip senses a power-down of VDD while
STR is enabled (held LOW). When power is restored, the
contents of the memory are recalled and the counter reset
to the last value stored. If AUTOSTORE is to be implemented, STR is typically hard wired to GND. If STR is held
HIGH during power-up and then taken LOW, the wiper will
not respond to the UP or DWN inputs until STR is brought
HIGH and the store is complete. Figure 1.
Manual (Push Button) Store
When STR is not enabled (held HIGH) a push button
switch may be used to pull STR LOW and released to
perform a manual store of the wiper position in EEPROM
memory. Figure 2.
3.3µF
8
1
VDD
UP
2
DWN
7
STR
VCC
GND
VH
VOUT
VL
4
3
20KΩ
5
6
8
1
VDD
UP
2
DWN
7
STR
VH 3
VOUT 5
VL 6
GND
2017 ILL3.0
2017 ILL4.0
2017-04 4/24/99
3
S9518
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
Storage Temperature
Voltage on pins with reference to GND:
Analog Inputs
Digital Inputs
Analog Outputs
Digital Outputs
Lead Solder Temperature (10 secs)
-55°C to +125°C
-65°C to +150°C
-0.5V to VDD+.5V
-0.5V to VDD+.5V
-0.5V to VDD+.5V
-0.5V to VDD+.5V
300°C
RECOMMENDED OPERATING CONDITIONS
Condition
*COMMENT
Stresses above those listed under Absolute
Maximum Ratings may cause permanent
damage to the device. These are stress
ratings only, and functional operation of the
device at these or any other conditions outside those listed in the operation sections of
this specification is not implied. Exposure to
any absolute maximum rating for extended
periods may affect device performance and
reliability.
Min
Max
Temperature
-40°C
+85°C
VDD
+2.7V
+5.5V
2017 PGM T2.2
2017-04 4/24/99
4
S9518
DAC DC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, VrefH = VDD, VrefL = 0V, TA = -40°C to +85°C, unless specified otherwise
Accuracy
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
INL
Integral Non-Linearity
ILOAD = 100µA,
-
0.5
±1
LSB
DNL
Differential Non-Linearity
ILOAD = 100µA,
Guaranteed but not tested
-
0.1
±0.5
LSB
References VH
VrefH Input Voltage
VrefL
-
VDD
V
VL
VrefL Input Voltage
Gnd
-
VrefH
V
RIN
VrefH to VrefL Resistance
-
38k
-
Ω
TCRIN
Temperature Coefficient
of RIN
VrefH to VrefL
-
600
-
ppm/°C
Analog
GEFS
Full-Scale Gain Error
DATA = FF
±1
LSB
Output
VOUTZS
Zero-Scale Output Voltage DATA = 00
0
20
mV
TCVOUT
VOUT Temperature
Coefficient
-
50
µV/°C
+1000
µA
VDD = +5, ILOAD = 50µA,
VrefH = +5V, VrefL = 0V
Guaranteed but not tested
-
IL
Amplifier Output Load Current
-200
ROUT
Amplifier Output Resistance ILOAD = 100µA VDD = +5V
VDD = +3V
-
10
20
PSRR
Power Supply Rejection
ILOAD = 10µA
-
-
1
eN
Amplifier Output Noise
f = 1kHz, VDD = +5V
-
90
-
THD
Total Harmonic Distortion
VIN = 1V rms, f = 1kHz
-
0.08
-
BW
Bandwidth - 3dB
VIN = 100mV rms
-
300
-
Ω
Ω
LSB/V
nV/
HZ
%
kHz
2017 PGM T3.4
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
VZAP
ESD Susceptibility
ILTH
Max
Unit
Test Method
2000
V
MS-883, TM 3015
Latch-Up
100
mA
JEDEC Standard 17
TDR
Data Retention
100
Years
MS-883, TM 1008
NEND
Endurance
1,000,000
Stores
MS-883, TM 1033
2017 PGM T4.0
2017-04 4/24/99
5
S9518
DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VH = VDD, VL = 0V, Unless otherwise specified
Symbol
Parameter
Conditions
IDD
Supply Current
during store, note 1
STR =
ISB
Supply Standby Current
IIH
Input Leakage Current
IIL
Input Leakage Current, note 2
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Min
Max
Units
1.2
mA
200
µA
VIN = VDD
10
µA
VIN = 0V
-100
µA
2
VDD
V
0
0.8
V
2017 PGM T5.1
Notes:
1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference
resistor chain.
2. UP and DWN have internal pull-up resistors of approximately 50kΩ. When the input is pulled to ground the resulting output current
will be VDD/50kΩ.
AC OPERATING CHARACTERISTICS VDD = +4.5V to +5.5V
Limits
Symbol
Parameter
Min.
Typ.
fGAP
Time Between Two Separate Push Button Events
tDB
Debounce Time
tS SLOW
After Debounce to Wiper Change on a Slow Mode
tS FAST
Wiper Change on a Fast Mode
tPU
Power-Up to Wiper Stable
tR VDD
VDD Power-Up Rate
tASTO
AUTOSTORE Cycle Time
tASTH
AUTOSTORE Threshold Voltage
4
tASEND
AUTOSTORE Cycle End Voltage
3.5
Max.
Units
µs
0
30
60
ms
100
250
375
ms
25
50
75
ms
500
µs
50
mV/µs
0.2
2
ms
V
V
2017 PGM T6.0
2017-04 4/24/99
6
S9518
VDD
5
VASTH
VOLTS (V)
AUTOSTORE CYCLE IN PROGRESS
VASEND
tASTO
STORE TIME
TIME (ms)
2017 ILL5.0
FIGURE 3. AUTOSTORE CYCLE TIMING DIAGRAM
Notes:
VASTH - AUTOSTORE threshold voltage
VASEND - AUTOSTORE cycle end voltage
tASTO - AUTOSTORE cycle time
(6) Typical values are for TA = 25°C and nominal supply voltage.
(7) This parameter is periodically sampled and not 100% tested.
tDB
tGAP
UP
1LSB Step
VOUT
2017 ILL6.0
FIGURE 4. SLOW MODE TIMING
tDB
UP
tS FAST
tS SLOW
1LSB Step
VOUT
1 Second
2017 ILL7.0
FIGURE 5. FAST MODE TIMING
2017-04 4/24/99
7
S9518
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
.050 (1.27) TYP.
.050 (1.270) TYP.
8 Places
.157 (4.00)
.150 (3.80)
.275 (6.99) TYP.
.030 (.762) TYP.
8 Places
1 .196 (5.00)
.189 (4.80)
FOOTPRINT
.061 (1.75)
.053 (1.35)
.020 (.50) x45°
.010 (.25)
.0192 (.49)
.0138 (.35)
.0098 (.25)
.004 (.127)
.05 (1.27) TYP.
.035 (.90)
.016 (.40)
.244 (6.20)
.228 (5.80)
8pn JEDEC SOIC ILL.2
ORDERING INFORMATION
S
S9518
Package
S = 8 Lead SOIC
Base Part Number
2017 ILL8.0
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
© Copyright 1999 SUMMIT Microelectronics, Inc.
2017-04 4/24/99
8