INTEGRATED CIRCUITS DATA SHEET SAA5290 One page Economy Teletext/TV microcontroller Preliminary specification File under Integrated Circuits, IC02 Philips Semiconductors February 1995 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 FEATURES General • Complete one page teletext decoder and TV microcontroller in a single 52-pin package • Eastern European, Western European and Turkish language variants covered in one device DESCRIPTION • Double size, double width and double height character capability for On-Screen Display (OSD) The SAA5290 is a single-chip one page teletext decoder and television control microcontroller. The device will decode 625-line based World System Teletext transmissions and provides television control functions and On-Screen Display (OSD) functions. • Enhanced display features including meshing and shadowing • Separate display and acquisition timing for increased flexibility The teletext decoder hardware is a derivative of the SAA5254 (IVT1.1X), and the TV control functionality provided by an on-chip industrial standard 80C51 microcontroller. A single-page static RAM is included on-board providing a complete one page teletext decoder and OSD memory. • Minimum peripheral component count • 525 line and 625 line display synchronization • Standby mode through power-down of teletext and analog hardware. Microcontroller The SAA5290 is available as a mask-programmed ROM version. An EEPROM version is also available for product development. Both versions are available in an SDIP52 package. • 16 kbytes masked ROM (16 kbytes EEPROM variant for product development) • 256 bytes of on-chip RAM • Six 6-bit Pulse Width Modulators (PWM) and one 14-bit precision PWM • 4-bit Digital-to-Analog Converter (DAC) and comparator with a 3-input multiplexer allowing implementation of 3 Analog-to-Digital Converters (ADC) in software • 2 high current (10 mA) open-drain outputs • Interrupt logic 0 triggered on rising and falling edges, providing pulse-width measurement for remote control decoding • Master and slave bit-level I2C-bus hardware. ORDERING INFORMATION PACKAGE TYPE NUMBER SAA5290ZP/nnn(1) SAA5290ZP/NVI(2) MEMORY NAME DESCRIPTION VERSION ROM SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 EEPROM SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 Notes 1. nnn is a three-digit number referencing the microcontroller program ROM mask. 2. I is a digit number referring to the language variant of the SAA5290ZP/NV. February 1995 2 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD supply voltage 4.5 5.0 5.5 V IDDM microcontroller supply current − 25 40 mA IDDA analog supply current − 35 50 mA IDDT teletext supply current − 20 30 mA fxtal crystal frequency − 12 − MHz Tamb operating ambient temperature −20 − +70 °C BLOCK DIAGRAM BLACK handbook, full pagewidth 25 IREF VDDA V DDT 38 39 26 VDDM 44 37 CVBS0 CVBS1 2 23, 24 TELETEXT ACQUISITION DATA SLICER 36 DISPLAY TIMING 27 3 PAGE RAM ACQUISITION TIMING 34, 33, 32 35 DISPLAY 29 VSYNC HSYNC FRAME R, G, B VDS COR SAA5290 OSCIN OSCOUT OSCGND 41 31 42 RGBREF OSCILLATOR 40 16K x 8 ROM 256 x 8 RAM TEXT INTERFACE ANALOG-TODIGITAL CONVERTER PULSE WIDTH MODULATOR data RESET 80C51 MICROCONTROLLER 43 address PORT 3 13 28 22 VSSD1 VSSD2 VSSA PORT 2 5 9 to 12, 30 P3.0 to P3.4/ ADC0 to ADC2 8 1 to 8 P2.0 to P2.7 PWM Fig.1 Block diagram. February 1995 3 TIMER/ CTRS/ I 2 C PORT 1 8 45 to 52 P1.0 to P1.7 / INT0, INT1, T0, T1, SDA, SCL PORT 0 8 14 to 21 P0.0 to P0.7 MLC102 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 PINNING SYMBOL PIN DESCRIPTION P2.0/TPWM 1 P2.1/PWM0 2 P2.2/PWM1 3 PORT 2: 8-bit open-drain bidirectional port with alternative functions. P2.0/TPWM is the output for the 14-bit high precision PWM. P2.1/PWM0 to P2.6/PWM5 are the outputs for the 6-bit PWMs 0 to 5. P2.3/PWM2 4 P2.4/PWM3 5 P2.5/PWM4 6 P2.6/PWM5 7 P2.7 8 P3.0/ADC0 9 P3.1/ADC1 10 P3.2/ADC2 11 P3.3 12 P3.4 30 PORT 3: 5-bit open-drain bidirectional port with alternative functions. P3.0/ADC0 to P3.2/ADC2 are the inputs for the software ADC facility. VSSD1 13 digital ground 1 for teletext and microcontroller circuits. P0.0 14 P0.1 15 PORT 0: 8-bit open-drain bidirectional port. P0.5 and P0.6 have 10 mA current sinking capability at 0.5 V for direct drive of LEDs. P0.2 16 P0.3 17 P0.4 18 P0.5 19 P0.6 20 P0.7 21 VSSA 22 analog ground. CVBS0 23 CVBS1 24 Composite video input. A positive-going 1 V (peak-to-peak) input is required, connected via a 100 nF capacitor. BLACK 25 Video black level storage input. This pin should be connected to VSSA via a 100 nF capacitor. IREF 26 Reference current input for analog circuits, connected to VSSA via a 27 kΩ resistor. FRAME 27 De-interlace output synchronized with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection currents. VSSD2 28 Digital ground 2. COR 29 Open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display. RGBREF 31 DC input voltage to define the output HIGH level on the RGB pins. B 32 Dot rate character output of the BLUE colour information. G 33 Dot rate character output of the GREEN colour information. R 34 Dot rate character output of the RED colour information. VDS 35 Video/data switch push-pull output for dot rate fast blanking. HSYNC 36 Horizontal sync dedicated input for a TTL-level version of the horizontal sync pulse. The polarity of this pulse is programmable by register bit TXT1.H POLARITY. February 1995 4 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SYMBOL SAA5290 PIN DESCRIPTION VSYNC 37 Vertical sync dedicated input for a TTL-level version of the vertical sync pulse. The polarity of this pulse is programmable by register bit TXT1.V POLARITY. VDDA 38 +5 V analog power supply. VDDT 39 +5 V teletext power supply. OSCGND 40 Crystal oscillator ground. OSCIN 41 12 MHz crystal oscillator input. OSCOUT 42 12 MHz crystal oscillator output. RESET 43 If the reset input is HIGH for 2 machine cycles (24 oscillator periods) while the oscillator is running, the SAA5290 is reset. This pin should be connected to VDDM via a 2.2 µF capacitor. VDDM 44 +5 V microcontroller power supply. P1.0/INT1 45 P1.1/T0 46 P1.2/INT0 47 P1.3/T1 48 PORT 1: 8-bit open-drain bidirectional port with alternative functions. P1.0/INT1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse. P1.1/T0 is the counter/timer 0. P1.2/INT0 is external interrupt 0. P1.3/T1 is the counter/timer 1. P1.6/SCL is the serial clock input for I2C-bus. P1.7/SDA is the serial data port for the I2C-bus. P1.6/SCL 49 P1.7/SDA 50 P1.4 51 P1.5 52 February 1995 5 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 handbook, halfpage P2.0/TPWM 1 52 P2.1/PWM0 2 51 P1.4 P2.2/PWM1 3 50 P1.7/SDA P2.3/PWM2 4 49 P1.6/SCL P2.4/PWM3 5 48 P1.3/T1 P2.5/PWM4 6 47 P1.2/INT0 P2.6/PWM5 7 46 P1.1/T0 P2.7 8 45 P1.0/INT1 P3.0/ADC0 9 44 VDDM P3.1/ADC1 10 43 RESET P3.2/ADC2 11 42 OSCOUT P3.3 12 41 OSCIN VSSD1 13 P1.5 40 OSCGND SAA5290 P0.0 14 39 VDDT P0.1 15 38 VDDA P0.2 16 37 VSYNC P0.3 17 36 HSYNC P0.4 18 35 VDS P0.5 19 34 R P0.6 20 33 G P0.7 21 32 B VSSA 22 31 RGBREF CVBS0 23 30 P3.4 CVBS1 24 29 COR BLACK 25 28 VSSD2 IREF 26 27 FRAME MLC103 Fig.2 Pin configuration. February 1995 6 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 QUALITY AND RELIABILITY This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated Circuits SNW-FQ-611-Part E” (see “Quality Reference Handbook”, order number 9398 510 63011). The principal requirements are shown in Tables 1 to 4. Group A Table 1 Acceptance tests per lot REQUIREMENTS(1) TEST Mechanical cumulative target: <80 ppm Electrical cumulative target: <80 ppm Group B Table 2 Processability tests (by package family) REQUIREMENTS(1) TEST Solderability <7% LTPD Mechanical <15% LTPD Solder heat resistance <15% LTPD Group C Table 3 Reliability tests (by process family) TEST CONDITIONS REQUIREMENTS(1) Operational life 168 hours at Tj = 150 °C <1500 FPM; equivalent to <100 FITS at Tj = 70 °C Humidity life temperature, humidity, bias 1000 hours, 85 °C, 85% RH (or equivalent test) <2000 FPM Temperature cycling performance Tstg(min) to Tstg(max) <2000 FPM Table 4 Reliability tests (by device type) TEST ESD and latch-up CONDITIONS ESD Human body model 2000 V, 100 pF, 1.5 kΩ <15% LTPD ESD Machine model 200 V, 200 pF, 0 Ω <15% LTPD latch-up 100 mA, 1.5 × VDD (absolute maximum) <15% LTPD Notes to Tables 1 to 4 1. ppm = fraction of defective devices, in parts per million. LTPD = Lot Tolerance Percent Defective. FPM = fraction of devices failing at test condition, in Failures Per Million. FITS = Failures In Time Standard. February 1995 REQUIREMENTS(1) 7 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage (all supplies) −0.3 +6.5 VI input voltage (any input) note 1 −0.3 VDD + 0.5 V VO output voltage (any output) note 1 −0.3 VDD + 0.5 V V IO output current (each output) − ±10 mA IIOK DC input or output diode current − ±20 mA ∆VSS difference between VSSD, VSSA and OSCGND − ±0.1 V ∆VDD difference between VDDM, VDDT and VDDA − ±0.1 V Tamb operating ambient temperature −20 +70 °C Tstg storage temperature −55 +125 °C note 2 Notes 1. This maximum value has an absolute maximum of 6.5 V independent of VDD. 2. Except in standby mode. CHARACTERISTICS VDD = 5 V ± 10%; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage (VDD to VSS) 4.5 5.0 5.5 V IDDM microcontroller supply current − 25 40 mA IDDA analog supply current − 35 50 mA IDDT teletext supply current − 20 30 mA Digital inputs RESET VIL LOW level input voltage −0.3 − 0.2VDD − 0.1 V VIH HIGH level input voltage 0.7VDD − VDD + 0.3 ILI input leakage current CI input capacitance VI = 0 to VDD V −10 − +10 µA − − 4 pF HSYNC AND VSYNC Vthf switching threshold falling 0.2VDD − − V Vthr switching threshold rising − − 0.8VDD V VHYS hysteresis voltage − 0.33VDD − V CI input capacitance − − 4 pF February 1995 8 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SYMBOL PARAMETER SAA5290 CONDITIONS MIN. TYP. MAX. UNIT Digital outputs R, G AND B (note 1) VOL LOW level output voltage IOL = 2 mA 0 − 0.2 V VOH HIGH level output voltage IOH = −2 mA VRGBREF − 0.3 VRGBREF VRGBREF + 0.4 V |ZO| output impedance − − 150 Ω CL load capacitance − − 50 pF IO DC output current − − −4 mA tr output rise time between 10% and 90%; − CL = 50 pF − 20 ns tf output fall time between 90% and 10%; − CL = 50 pF − 20 ns − − VDD V 0 − 0.5 V COR (OPEN-DRAIN OUTPUT) VOH HIGH level pull-up output voltage VOL LOW level output voltage IOL LOW level output current − − 2 mA CL load capacitance − − 25 pF IOL = 2 mA VDS VOL LOW level output voltage IOL = 1.6 mA 0 − 0.2 V VOH HIGH level output voltage IOH = −1.6 mA VDD − 0.3 − VDD + 0.4 V CL load capacitance − − 50 pF tr output rise time between 10% and 90%; − CL = 50 pF − 20 ns tf output fall time between 90% and 10%; − CL = 50 pF − 20 ns − − 20 ns R, G, B AND VDS tskew skew delay between any two pins FRAME VOH HIGH level output voltage IOL = 8 mA 0 − 0.5 V VOL LOW level output voltage IOL = −8 mA VDD − 0.5 − VDD V IOL LOW level output current −8 − +8 mA CL load capacitance − − 100 pF February 1995 9 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SYMBOL PARAMETER SAA5290 CONDITIONS MIN. TYP. MAX. UNIT Digital input/outputs P0.0 TO P0.4, P0.7, P1.0 TO P1.5, P2.0 TO P2.7 AND P3.0 TO P3.5 VIL LOW level input voltage −0.3 VIH HIGH level input voltage 0.2VDD + 0.9 − CI input capacitance VOL LOW level output voltage CL load capacitance IOL = 3.2 mA − 0.2VDD − 0.1 V VDD + 0.3 V − − 4 pF 0 − 0.45 V − − 50 pF − 0.2VDD − 0.1 V P0.5 AND P0.6 VIL LOW level input voltage −0.3 VIH HIGH level input voltage 0.2VDD + 0.9 − VDD + 0.3 V CI input capacitance − − 4 pF VOL LOW level output voltage 0 − 0.45 V CL load capacitance − − 50 pF IOL = 10 mA P1.6 AND P1.7 VIL LOW level input voltage −0.3 − +1.5 V VIH HIGH level input voltage 3.0 − VDD + 0.3 V CI input capacitance − − 5 pF VOL LOW level output voltage 0 − 0.5 V CL load capacitance − − 400 pF tf output fall time − − 200 ns IOL = 3 mA between 3 and 1 V Analog inputs CVBS0 AND CVBS1 Vsync sync voltage amplitude 0.1 0.3 0.6 V Vvid(p-p) video input voltage amplitude (peak-to-peak value) 0.7 1.0 1.4 V Zsource source impedance − − 250 Ω VIH HIGH level input voltage 3.0 − VDD + 0.3 V |ZI| input impedance 2.5 5.0 − kΩ CI input capacitance − − 10 pF resistor to ground − 27 − kΩ IREF Rgnd RGBREF (note 1) VI input voltage −0.3 − VDD V II DC input current − − 12 mA February 1995 10 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SYMBOL PARAMETER SAA5290 CONDITIONS MIN. TYP. MAX. UNIT ADC0, ADC1 AND ADC2 VIL LOW level input voltage −0.3 − VDD V Analog input/output BLACK Cblack storage capacitor to ground − 100 − nF Vblack black level voltage for nominal sync amplitude 1.8 2.15 2.5 V ILI input leakage current −10 − +10 µA Crystal oscillator OSCIN VIL LOW level input voltage −0.3 − 0.2VDD − 0.1 V VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V CI input capacitance − − 10 pF fosc crystal oscillator frequency − 12 − MHz CO output capacitance − − 10 pF − 12 − MHz OSCOUT CRYSTAL SPECIFICATION (note 2) fxtal nominal frequency CL load capacitance − 32 − pF C1 series capacitance Tamb = 25 °C − 18.5 − fF C0 parallel capacitance Tamb = 25 °C − 4.9 − pF Rr resonance resistance Tamb = 25 °C Ω Txtal temperature range Xj adjustment tolerance Xd drift Tamb = 25 °C − 35 − −20 +25 +70 °C 10−6 − − ±50 × − − ±30 × 10−6 Notes 1. All RGB current is sourced from the RGBREF pin. The maximum effective series resistance between RGBREF and the R, G and B pins is 150 Ω. 2. Crystal order number 4322 143 05561. February 1995 11 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 Table 5 Characteristics for the I2C-bus interface SYMBOL PARAMETER INPUT OUTPUT I2C-BUS SPECIFICATION SCL timing tHD;STA START condition hold time ≥4.0 µs note 1 ≥4.0 µs tLOW SCL LOW time ≥4.7 µs note 1 ≥4.7 µs tHIGH SCL HIGH time ≥4.0 µs ≥4.0 µs; note 2 ≥4.0 µs trC SCL rise time ≤1.0 µs note 3 ≤1.0 µs tfC SCL fall time ≤0.3 µs ≤0.3 µs; note 4 ≤0.3 µs ≥250 ns note 1 ≥250 ns ≥0 ns note 1 ≥0 ns SDA timing tSU;DAT1 data set-up time tHD;DAT data hold time tSU;STA repeated START set-up time ≥4.7 µs note 1 ≥4.7 µs tSU;STO STOP condition set-up time ≥4.0 µs note 1 ≥4.0 µs tBUF bus free time ≥4.7 µs note 1 ≥4.7 µs trD SDA rise time ≤1.0 µs note 3 ≤1.0 µs tfD SDA fall time ≤0.3 µs ≤0.3 µs; note 4 ≤0.3 µs Notes 1. This parameter is determined by the user software. It must comply with the I2C-bus specification. 2. This value gives the auto-clock pulse length which meets the I2C-bus specification for the special crystal frequency. Alternatively, the SCL pulse must be timed by software. 3. The rise time is determined by the external bus line capacitance and pull-up resistor. It must be less than 1 µs. 4. The maximum capacitance on bus lines SDA and SCL is 400 pF. repeated START condition START or repeated START condition START condition STOP condition t SU;STA t rD 0.7V DD SDA (input / output) 0.3VDD t fD t rC t BUF t fC t SU;STO 0.7VDD SCL (input / output) 0.3VDD t HD;STA t LOW t HIGH t SU;DAT1 t HD;DAT dth Fig.3 I2C-bus interface timing. February 1995 12 t SU;DAT3 t SU;DAT2 MLC104 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 FUNCTIONAL DESCRIPTION OFF-CHIP MEMORY Introduction The SAA5290 does not support the use of off-chip program memory or off-chip data memory. This means that the SAA5290 does not have any of EA, RD, WR, ALE or PSEN pins. The 4 MOVX instructions which move data to and from external RAM should not be used. The SAA5290 is an integrated teletext decoder and microcontroller. The teletext decoder is derived from the SAA5254 single page teletext decoder IC, with a number of enhancements to increase its suitability for on-screen display applications. The microcontroller is a derivative of the industry standard 80C51 microcontroller. A block diagram of the SAA5290 is given in Fig.1. IDLE AND POWER-DOWN MODES Idle and power-down modes are not supported by the SAA5290. As a consequence, the respective bits in PCON are not available. Microcontroller The functionality of the microcontroller used on the SAA5290 is described here with reference to the industry standard 80C51 microcontroller. A full description of its functionality can be found in the handbook 80C51-based 8-bit microcontrollers IC20. Using the 80C51 as a reference, the changes made for the SAA5290 fall into two categories, features not supported by the SAA5290 and features found on the SAA5290 but not supported by the 80C51. UART FUNCTION The 80C51 UART is not available in the SAA5290. As a consequence the SCON and SBUF SFRs are removed and the ES bit in the IE SFR is unavailable. Additional features for the SAA5290 The following features are provided by the SAA5290 in addition to the standard 80C51 features. 80C51 features not supported by the SAA5290 INTERRUPTS INTERRUPT PRIORITY The IP SFR is not implemented and all interrupts are treated with the same priority level. The SAA5290 retains the normal prioritization of interrupts within a level. The external INT1 interrupt is modified to generate an interrupt on both the rising and falling edges of the INT1 pin, when EX1 bit is set. This facility allows for software pulse width measurement for handling of a remote control. Table 6 BIT LEVEL I2C-BUS INTERFACE Interrupts and their vector addresses Reset 000H External INT0 003H Timer 0 00BH External INT1 013H The bit-level serial I/O supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C-bus specification concerning the input levels and output drive capability. Consequently, these pins have an open-drain output configuration. All the four following modes of the I2C-bus are supported. Timer 1 01BH • Master transmitter I2C-bus 053H • Master receiver EVENT PROGRAM MEMORY ADDRESS • Slave transmitter February 1995 13 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 • Slave receiver. LED SUPPORT I2C-bus hardware, The advantages of the bit-level compared with a full software I2C-bus implementation are: Port pins P0.5 and P0.6 have a 10 mA current sinking capability to enable LEDs to be driven directly. • The hardware can generate the SCL pulse PWM DACS • Testing a single bit (RBF or WBF respectively) is sufficient as a check for error-free transmission. The SAA5290 has six 6-bit PWM DACs and one14-bit PWM DAC. These allow direct control of other parts of the television. I2C-bus hardware operates on serial bit level The bit-level and performs the following functions: The low resolution 6 bit DACs are controlled by their corresponding SFR (PWM0 to PWM5) and are connected as alternative outputs of Port P2. The port bit corresponding to the PWM should be set to logic 1 for correct operation of the PWM. • Filtering the incoming serial data and clock signals • Recognizing the START condition • Generating a serial interrupt request SI after reception of a START condition and the first falling edge of the serial clock • Recognizing the STOP condition Table 7 Special Function Registers PWM0 to PWM5 • Recognizing a serial clock pulse on the SCL line • Latching a serial bit on the SDA line (SDI) • Stretching the SCL LOW period of the serial clock to suspend the transfer of the next serial data bit D7 D6 D5 D4 D3 D2 D1 D0 PWE − PV5 PV4 PV3 PV2 PV1 PV0 If the PWE bit for a particular port is set to logic 1, the PWM is active and controls its assigned port pin. If the PWE bit is set to logic 0 the corresponding port pin is controlled by the bit in the corresponding port register for that port. • Setting Read Bit Finished (RBF) when the SCL clock pulse has finished and Write Bit Finished (WBF) if there is no arbitration loss detected (i.e. SDA = logic 0 while SDO = logic 1) • Setting a Bus Busy (BB) flag on a START condition and clearing this flag on a STOP condition The output of the PWM is a pulse of period 21.33 µs with a duty cycle determined by the binary value, PV5 to PV0, multiplied by 0.33 µs. The 14 bit PWM is controlled with SFR registers TDACL and TDACH. • Releasing the SCL line and clearing the CLH, RBF and WBF flags to resume transfer to the next serial data bit Table 8 Special Function Register TDACL • Setting a serial clock LOW-to-HIGH detected (CLH) flag • Generating an automatic clock if the single bit data register S1BIT is used in master mode. D7 D6 D5 D4 D3 D2 D1 D0 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0 D1 D0 TD13 TD12 TD11 TD10 TD9 TD8 The following functions must be done in software: • Handling the I2C-bus START interrupts Table 9 Special Function Register TDACH • Converting serial data to parallel data when receiving • Converting parallel data to serial data when transmitting • Comparing the received slave address with its own address D6 PWE − D5 D4 D3 D2 If the PWE bit is set to logic 1, the TPWM is active and controls Port P2.0. If the PWE bit is set to logic 0 the port pin is controlled by the bit in the corresponding port register for P2.0. • Interpreting the acknowledge information • Guarding the I2C-bus status if RBF or WBF = logic 0. Additionally, if acting as master: The output of the TPWM is a pulse of period 42.66 µs with a duty cycle determined by the binary value, TD13 to TD7, multiplied by 0.33 µs. • Generating START and STOP conditions • Handling bus arbitration • Generating serial clock pulses if S1BIT is not used. Three SFRs support the function of the bit-level I2C-bus hardware, they are S1INT, S1BIT and S1SCS. February 1995 D7 14 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 The 7 least significant bits, TD6 to TD0, extend the HIGH time of a proportion of the pulses by 0.33 µs. If the LSB is set then 1 in 128 cycles is extended, if bit 1 is set then 1 in 64 cycles is extended, and so on. SOFTWARE ADC Up to 3 successive approximation ADCs can be implemented in software by making use of the on-board 4-bit DAC and multiplexed voltage comparator. The software ADC uses 3 analog inputs which are multiplexed with P3.0 to P3.2. The control of the ADC is achieved using the SAD SFR. SAD.5 and SAD.6 select one of the three inputs to pass to the comparator. The other input comes from the DAC whose input is set by SAD bits 0 to 3. The output of the comparator is SAD bit 7 and is valid by the next instruction after starting the comparison by setting SAD.ST to logic 1. Microcontroller interfacing The 80C51 CPU communicates with the peripheral functions using Special Function Registers (SFRs) which are addressed as RAM locations. The registers in the teletext decoder appear as normal SFRs in the microcontroller memory map, but are written to using a serial bus. This bus is controlled by dedicated hardware which uses a simple handshake system for software synchronization. The SFR memory map is given in Table 10. February 1995 15 February 1995 Port 0 Port 1 Port 2 Port 3 Power Control Program Status Word Pulse Width Modulator 0 Pulse Width Modulator 1 Pulse Width Modulator 2 Pulse Width Modulator 3 Pulse Width Modulator 4 Pulse Width Modulator 5 Serial I2C data P2(2) P3(2)(3) PCON(3) PSW(2) PWM0(3) PWM1(3) PWM2(3) PWM3(3) PWM4(3) PWM5(3) S1BIT(3) Low byte DPL P1(2) High byte DPH P0(2) Data Pointer (2 bytes): DPTR: Interrupt Enable B register IE(2)(3) Accumulator B(2) DESCR. ACC(2) SYMBOL 16 D9H PV5 PV5 PV5 PV5 PV5 PV5 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ SDI/ SDO PWE PWE PWE PWE PWE PWE F0 AC D5 ∗ CY ∗ ∗ − D6 − − A5 95 ∗ PV4 PV4 PV4 PV4 PV4 PV4 RS1 D4 ∗ B4 A4 94 84 ∗ 85 AC ∗ − − F4 E4 AD − − F5 E5 D7 A6 96 A7 97 86 ES1 87 AE EA − − AF − F6 E6 − F7 E7 MSB ∗ PV3 PV3 PV3 PV3 PV3 PV3 RS0 D3 GF1 B3 A3 93 83 ET1 AB − − F3 E3 ∗ PV2 PV2 PV2 PV2 PV2 PV2 0V D2 GF0 B2 A2 92 82 EX1 AA − − F2 E2 ∗ PV1 PV1 PV1 PV1 PV1 ∗ PV0 PV0 PV0 PV0 PV0 PV0 P ∗ ∗ B0 A0 90 80 D0 PV1 LSB EX0 A8 − − F0 E0 D1 ∗ B1 A1 91 81 ET0 A9 − − F1 E1 BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 00H − − − − − − 000000X0B XXXX00XXB XXX11111B FFH FFH FFH X0H 00H 00H 00H 00H RESET VALUE (HEX) One page Economy Teletext/TV microcontroller DEH DDH DCH D7H D6H D5H D0H 87H B0H A0H 90H 80H A8H 82H 83H F0H E0H DIRECT ADDR. (HEX) Table 10 SAA5290 Special Function Register map (note 1) Philips Semiconductors Preliminary specification SAA5290 February 1995 E8H Software A to D Stack Pointer 81H Timer/counter 88H control TPWM High byte TPWM Low byte Timer 0 High byte Timer 1 High byte Timer 0 Low byte Timer 1 Low byte Timer/counter 89H mode Teletext register 0 Teletext register 1 Teletext register 2 Teletext register 3 SAD(2) (3) SP TCON(2) TDACH TDACL TH0 TH1 17 TL0 TL1 TMOD TXT0(3) TXT1(3) TXT2(3) TXT3(3) C3H C2H CH1 ∗ ∗ ∗ ∗ ∗ ∗ ACQ OFF 8-BIT ∗ GATE − − − − TD3 TD11 IE1 8B SAD3 EB RBF DB ∗ PRD4 ∗ X26 PRD3 ∗ FULL FIELD DISABLE DISPLAY HDR STATUS ROLL ROW ONLY AUTO FRAME ∗ X24 POS GATE M0 − M1 − − − − C/T − − − − − − − − TD4 TD12 TR0 8C ST EC BB DC ∗ − − − TD5 TD13 ∗ TD6 TF0 8D CH0 ED CLH DD ∗ TR1 TD7 PWE TF1 8E VHI 8F EE SCI/ SDO EF DE SDI/ SDO ∗ DF SI MSB ∗ M1 − − − − TD1 TD9 IE0 89 SAD1 E9 STR D9 ∗ ∗ M0 − − − − TD0 TD8 IT0 88 SAD0 E8 ENS D8 ∗ LSB 00H 00H 00H 00H 00H 00H 00H 00H 00H 07H 00H − − RESET VALUE (HEX) PRD2 SC2 PRD1 SC1 PRD0 SC0 00H 00H FIELD H V 00H POLARITY POLARITY POLARITY DISABLE FRAME C/T − − − − TD2 TD10 IT1 8A SAD2 EA WBF DA ∗ BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION One page Economy Teletext/TV microcontroller C1H C0H 8BH 8AH 8DH 8CH D2H D3H D8H S1SCS(2)(3) Serial I2C control DIRECT ADDR. (HEX) DAH DESCR. Serial I2C interrupt S1INT(3) SYMBOL Philips Semiconductors Preliminary specification SAA5290 February 1995 18 Teletext register 5 Teletext register 6 Teletext register 7 Teletext register 8 Teletext register 9 Teletext register 10 Teletext register 11 Teletext register 12 Teletext register 13 TXT5(3) TXT6(3) TXT7(3) TXT8(3) TXT9(3) TXT10(3) TXT11(3) TXT12(3) TXT13(2)(3) B8H CCH CBH CAH C9H C8H C7H C6H C5H C4H DIRECT ADDR. (HEX) BE ∗ ∗ ROM VER R4 D6 BF 625/525 SYNC D7 ∗ BD ROM VER R3 D5 C5 ∗ BC ROM VER R2 D4 C4 ∗ BB ROM VER R1 D3 C3 R3 ∗ R4 ∗ BA ROM VER R0 D2 C2 R2 ∗ ∗ A0 ∗ CLEAR MEM. ∗ ∗ TEXT IN TEXT IN C MESH ENABLE ∗ TEXT OUT TEXT OUT B MESH ENABLE ∗ COR IN COR IN ∗ ∗ COR OUT COR OUT EAST/ WEST SNG/DBL BOX ON HEIGHT 24 BKGND IN BKGND IN ∗ STATUS CURSOR CONCEAL TOP/ ROW ON /REVEAL BTM TOP BKGND OUT BKGND OUT ∗ MSB 3. SFRs are modified or added to the 80C51 SFRs. 2. SFRs are bit addressable. ∗ B9 TXT ON D1 C1 R1 ∗ BOX ON 1-23 PICTURE ON OUT PICTURE ON OUT TRANS ENABLE BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION 1. The star (∗) indicates these bits are inactive and must be written to logic 0 for future compatibility. Notes Teletext register 4 DESCR. TXT4(3) SYMBOL TXT I/FACE BUSY B8 VIDEO QUALITY D0 C0 R0 CVBS0/ CVBS1 BOX ON 0 PICTURE ON IN PICTURE ON IN SHADOW ENABLE LSB 00H 00H 00H 00H 00H 00H 00000011B 00000011B 00H RESET VALUE (HEX) Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 Table 11 SFR description REGISTER FUNCTION IE - Interrupt Enable EA Disable all interrupts (logic 0) or use individual enable bits (logic 1). ES1 I2C-bus interrupt enable (logic 1). ET1 Enable Timer 1 overflow interrupt (logic 1). EX1 Enable external interrupt 1 (logic 1). ET0 Enable Timer 0 overflow interrupt (logic 1). EX0 Enable external interrupt 0 (logic 1). PCON - Power Control GF0 General purpose flag bit 0. GF1 General purpose flag bit 1. PWM0 to PWM5 - 6-bit Pulse Width Modulator control registers PWE Activate this 6-bit PWM and take over port pin (logic 1). PV0 to PV5 Value to output by this 6-bit PWM. SAD - Software ADC control VHI Analog input voltage greater than DAC output voltage (logic 1). CH0 and CH1 See Table 12. ST Initiate voltage comparison (logic 1). This is automatically reset. SAD0 to SAD3 4-bit DAC input value. The DAC output of this value is compared with analog input voltage. S1BIT - Serial I2C-bus data (READ) SDI I2C-bus data bit latched-in from SDA on the last rising edge of SCL. S1BIT - Serial I2C-bus data (WRITE) SDO I2C-bus data bit output. S1INT - Serial I2C-bus interrupt SI I2C-bus interrupt flag. S1SCS - Serial I2C-bus control (READ) SDI Serial data input at SDA. SCI Serial clock input at SCL. CLH Clock LOW-to-HIGH transition flag. BB Bus busy flag. RBF Read bit finished flag. WBF Write bit finished flag. STR Clock stretching enable (logic 1). ENS Enable serial I/O (logic 1). February 1995 19 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 REGISTER FUNCTION S1SCS - Serial I2C-bus control (WRITE) SDO Serial data output at SDA. SCO Serial clock output at SCL. CLH Clock LOW-to-HIGH transition. STR Clock stretching enable (logic 1). ENS Enable serial I/O (logic 1). TDACH - 14-bit PWM MSB register PWE Activate this 14-bit PWM and take over port pin (logic 1). TD8 to TD13 6 LSBs of this value to be output by the 14-bit PWM. TDACL - 14-bit PWM LSB register TD0 to TD7 8 LSBs of this value to be output by the 14-bit PWM. TXT0 - Teletext register 0 (WRITE only) X24 POSITION Store packet 24 in extension packet memory (logic 0) or page memory (logic 1). AUTO FRAME Frame output switched off automatically if any video displayed (logic 1). DISABLE HDR ROLL Do not write rolling headers and time into memory (logic 1). STATUS ROW ONLY Display only memory row (logic 1). DISABLE FRAME Frame output always LOW (logic 1). TXT1 - Teletext register 1 (WRITE only) 8-BIT Data in packets 0 to 24 written into memory without error checking (logic 1). ACQ OFF Prevent teletext acquisition section writing to memory (logic 1). X26 Disable automatic processing of packet 26 data (logic 1). FULL FIELD Accept teletext on TV lines 2 to 22 only (logic 0) or on any line (logic 1). FIELD POLARITY VSYNC in first half of the line (logic 0) or second half of the line (logic 1) at start of even field. H POLARITY HSYNC input positive-going (logic 0) or negative-going (logic 1). V POLARITY VSYNC input positive-going (logic 0) or negative-going (logic 1). TXT2 - Teletext register 2 (WRITE only) SC0 to SC2 Start column at which page request data written into TXT3 SFR is placed. TXT3 - Teletext register 3 (WRITE only) PRD0 to PRD4 Page request data. TXT4 - Teletext register 4 (WRITE only) B MESH ENABLE Enable meshing of area with black background (logic 1). C MESH ENABLE Enable meshing of area with other background colours (logic 1). TRANS ENABLE Black background colour is transparent i.e. video is displayed (logic 1). SHADOW ENABLE Enable south-east shadowing (logic 1). EAST/WEST Western European languages displayed (logic 0) or Eastern European languages displayed (logic 1). February 1995 20 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 REGISTER FUNCTION TXT5 - Teletext register 5 (WRITE only) BKGND OUT Background colour displayed outside teletext boxes (logic 1). BKGND IN Background colour displayed inside teletext boxes (logic 1). COR OUT COR output active outside teletext boxes (logic 1). COR IN COR output active inside teletext boxes (logic 1). TEXT OUT Text displayed outside teletext boxes (logic 1). TEXT IN Text displayed inside teletext boxes (logic 1). PICTURE ON OUT Video picture displayed outside teletext boxes (logic 1). PICTURE ON IN Video picture displayed inside teletext boxes (logic 1). TXT6 - Teletext register 6 (WRITE only) − This register has the same meaning as TXT5 but is only invoked if either newsflash (C5) or the subtitle (C6) bit in Row 25 of the basic page memory is set. TXT7 - Teletext register 7 (WRITE only) STATUS ROW TOP Display Row 24 below (logic 0) or above (logic 1) teletext page. CURSOR ON Display cursor at location pointed to by TXT9 and TXT10 (logic 1). CONCEAL/REVEAL Display characters in areas with the conceal attribute set (logic 1). TOP/BOTTOM Display Rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set. SNG/DBL HEIGHT Display each character at twice normal height (logic 1). BOX ON 24 Enable teletext boxes in memory Row 24 (logic 1). BOX ON 1-23 Enable teletext boxes in memory Rows 1 to 23 (logic 1). BOX ON 0 Enable teletext boxes in memory Row 0 (logic 1). TXT8 - Teletext register 8 (WRITE only) CVBS0/CVBS1 CVBS0 input (logic 0) or CVBS1 (logic 1) inputs used for teletext. TXT9 - Teletext register 9 (WRITE only) CLEAR MEMORY Write 20H into every location in teletext memory (logic 1). A0 Access basic page memory (logic 0) or extension packet memory (logic 1) with TXT11 SFR. R0 to R4 Memory row to be accessed with TXT11 SFR. TXT10 - Teletext register 10 (WRITE only) C0 to C5 Memory column to be accessed with TXT11 SFR. TXT11 - Teletext register 11 D0 to D7 February 1995 data byte written to, or read from, teletext memory. 21 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 REGISTER FUNCTION TXT12 - Teletext register 12 (READ only) 625/525 SYNC A 625 line CVBS signal (logic 0), or a 525 line CVBS signal (logic 1) is being input. ROM VER R0 to R4 Mask programmable to identify character set version. TXT ON Teletext power has been applied to the device (logic 1). VIDEO QUALITY CVBS input can be locked on by the teletext decoder (logic 1). TXT13 - Teletext register 13 (READ only) TXT I/FACE BUSY Text interface busy and no access for either READ or WRITE is allowed to SFRs TXT0 to TXT11 (logic 1). This register bit performs the software handshake to the teletext control registers. Table 12 CH1 and CH0 selection CH1 CH0 INPUT PIN 0 0 none 0 1 ADC0 1 0 ADC1 1 1 ADC2 February 1995 22 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 TELETEXT DECODER FUNCTIONAL DESCRIPTION Data slicer Acquisition timing One is constant and is proportional to the difference between the black level of the video and the slicing level. The other is produced only when the video is below the slicing level, and is also proportional to the difference between the slicing level and the input, but has a magnitude13 times greater. The acquisition timing is generated from a logic level positive-going composite sync signal ‘VCS’. This signal is generated by the sync separator circuit which adaptively slices the sync pulses at 50% of their height. It is able to do this over a wide range of sync amplitudes by using the same basic principle used on VIP1 (SAA5230) and VIP2 (SAA5231). The black level is determined by a sync-gated peak detector. The video is negatively peak detected into an external capacitor (BLACK, pin 25), but not during the sync pulse VCS. The two currents are integrated on the CVBS input coupling capacitor and the net effect is to alter the mean input voltage until the (fixed) slicing level is correct. Figure 4 is a block diagram showing the principles of operation. It relies upon the fact that the ratio of the sync width to the line time is approximately 13 : 1. In order to slice the sync pulse at the correct 50% level two currents are generated. The acquisition clocking and timing are locked to the VCS signal using a digital phased-locked-loop. The phase error in the acquisition phase-locked-loop is detected by a signal quality circuit which disables acquisition if poor signal quality is detected. The data slicer extracts the digital teletext data from the incoming analog waveform. This is performed by sampling the CVBS waveform and processing the samples to extract the teletext data and clock. VDD handbook, full pagewidth Vref 1/3Vi (mA) CVBS VCS FILTER Vref (= slicing level) FILTER gated negative peak detector 1/39V i(mA) BLACK Vref MLC105 Fig.4 Sync separator block diagram. February 1995 23 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 If the ‘DO CARE’ bit for part of the page number is set to logic 0 then that part of the page number is ignored when the acquisition section is deciding whether a page being received off air should be stored or not. For example if the ‘DO CARE’ bits for the 4 subcode digits are all set to logic 0 then every subcode version of the page will be captured. Teletext acquisition The SAA5290 is able to acquire 625-line World System Teletext. Teletext is acquired under control of the on-board 80C51 microcontroller. Pages are requested by writing a series of bytes into the TXT3 SFR which corresponds to the number of the page required. The bytes written into TXT3 are put into a small RAM with an auto-incrementing address. The start address for the RAM is set using the SFR TXT2 register. Table 13 shows the contents of the page request RAM. When the ‘HOLD' bit is set to logic 0 the acquisition section will not recognize any page as having the correct page number and no pages will be captured. Table 13 Register map for page requests (TXT3); note 1 START COLUMN 0 PRD4 MAG1 MAG0 PT3 PT2 PT1 PT0 PU3 PU2 PU1 PU0 X X HT1 HT0 HU3 HU2 HU1 HU0 X MT2 MT1 MT0 MU3 MU2 MU1 MU0 DO CARE Minutes tens 6 MAG2 DO CARE Hours units 5 HOLD DO CARE Hours tens 4 DO CARE Minutes units Note 1. X = don't care. Page memory organization The acquired teletext packets each contain 40 bytes of data and one packet is stored in each row of the text memory. The page memory organization is given in Fig.5. Rows 0 to 23 form the teletext page; Row 24 is available for status messages and FLOF/FASTEXT prompt information. February 1995 PRD0 DO CARE Page units 3 PRD1 DO CARE Page tens 2 PRD2 DO CARE Magazine 1 PRD3 24 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller handbook, full pagewidth 7 characters for status 1 SAA5290 fixed character written by hardware, alphanumerics white normally, alphanumerics green when looking for display page 6 7 8 8 characters usually rolling (time) 31 32 39 24 characters from page header rolling when display page looked for MAIN PAGE DISPLAY AREA 0 1 2 3 4 5 to 20 21 22 23 24 25 PACKET X / 22 PACKET X / 23 PACKET X24 STORED HERE IF TXT0.7 = 1 10 14 10 bytes for received page information ROW 14 bytes free for use by microcontroller MLC106 Fig.5 Basic page memory organization. ROW 0 (see Fig.5) Packet 26 processing Row 0 is for the page header. The first seven characters (0 to 6) are free for status messages. Character 8 is an alphanumeric white or green control character, written automatically by SAA5290 to give a green rolling header when a page is being looked for. The last eight characters are for rolling time. The SAA5290 contains on-board hardware processing of Packet 26 data. If a character corresponding to that being transmitted is available in the character set then the correct character code is written into the display memory. ROW 25 (see Fig.5) The first 10 bytes of row 25 contain control data relating to the received page as shown in Table 14. The remaining 14 bytes are free for use by the microcontroller. PACKET X24 if TXT0.X24 POS = 0 0 PACKET X27 / 0 1 PACKETS 8 / 30 / 0 to 15 2 MLC107 Extension packet memory organization If TXT0.X24 POS bit is set to logic 0, then Packet 24 is written into Row 0 of the extension memory. Fig.6 Organization of the extension memory. Packet X27/0 is written to Row 1 of the extension memory, with bytes 0 to 37 being Hamming checked automatically. Packet 8/30 is written to Row 2 of the extension memory, with bytes 0 to 6 being 8/4 Hamming checked, bytes 7 to 19 unchecked and bytes 20 to 39 odd parity checked. February 1995 ROW handbook, halfpage 25 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 Table 14 Row 25 received control data format ROW 25 D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0 D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0 D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0 D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0 D4 HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND 0 D5 0 0 0 0 0 0 0 0 0 PBLF D6 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 Column 0 1 2 3 4 5 6 7 8 9 Table 15 Page number and sub-code for Table 14 BIT NAME DESCRIPTION Page number MAG magazine PU page units PT page tens PBLF page being looked for HAM.ER Hamming error in corresponding byte Page sub-code MU minutes units MT minutes tens HU hours units HT hours tens C4 to C14 transmitted control bits February 1995 26 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 Display The capabilities of the display are based on the requirements of level 1 teletext, with some enhancements for use with locally generated On-Screen Displays (OSD). The display character set is given in Fig.9. The character set provided contains all the characters required to display Eastern and Western European languages. Register bit TXT4.EAST/ WEST sets whether Eastern or Western languages are set with the C12 to C14 bits. In order to make on-screen displays easy to use, the SAA5290 contains additional display attributes in Column 11. The display consists of 25 rows each of 40 characters, with the characters displayed being those from Rows 0 to 24 of the basic page memory. The page memory stores 8-bit character codes which correspond to 260 displayable characters and 44 control codes, normally displayed as spaces. Each character is defined by a matrix 12 pixels high and 10 pixels deep. When displayed each pixel is 0.5 µs wide and 1 TV line, in each field, high. Control codes are categorized as ‘set at’ or ‘set after’. ‘Set at’ means the code has effect at the current character position and ‘set after’ means they have effect from the following character. Codes 11/0 to 11/7 are always ‘set at’. Codes 11/11 to 11/15 are ‘set after’ when defining the start of an OSD box and ‘set at’ when ending an OSD box. Codes 11/12 to 11/15 force a box condition allowing on-screen display messages to be displayed without having to erase the whole contents of the teletext page. The SAA5290 signals the TV display circuits to display the RGB outputs of the SAA5290 rather than video picture by setting VDS HIGH. The way in which this signal is switched is controlled by the TXT5 and TXT6 SFRs. There are three control functions: background on, text on and picture on. There are separate bits for each function for inside and outside teletext boxes and if the newsflash or subtitle bits are set. This allows the software to configure the type of display required. The effect of the combination of these bits is given in Table 16. The COR bits in Register 5 and Register 6 control when the output is pulled LOW. This output is intended to act on the TV display circuits to reduce the contrast of the video display. On-screen displays are only available in TV mode and not in text mode. In mixed text and TV mode the displayed screen is not defined if an OSD box is encountered in the page memory. Table 16 Display mode PICTURE ON TEXT ON BACKGROUND ON RESULT 0 0 X text mode, black screen 0 1 0 text mode, background always black 0 1 1 text mode 1 0 X TV mode 1 1 0 mixed mode and TV mode 1 1 1 text mode, TV picture outside text area Display timing The display circuitry is driven from the H/VSYNC inputs, and is independent of the input video signal. Consequently HSYNC and VSYNC are always required to slave synchronize the display. if the active edge of VSYNC is in the second half of a line then the field is odd. The active edge is controlled with TXT1.V POLARITY. With TXT0.AUTO FRAME LOW FRAME is HIGH for an odd field and LOW for an even field. With TXT0.AUTO FRAME HIGH FRAME is only active when text is being displayed, when video is displayed it is forced LOW. When TXT0.DISABLE FRAME is HIGH FRAME is always LOW. If TXT1.FIELD POLARITY is logic 1 then VSYNC is delayed by 32 µs before being applied to the display timing circuits. The FRAME output of the SAA5290 is provided to facilitate de-interlacing the teletext display. The behaviour of FRAME is controlled via the register bits TXT0.DISABLE FRAME, TXT0.AUTO FRAME and TXT1.FIELD POLARITY. If the active edge of VSYNC occurs in the first half of a TV line then the field is even, and February 1995 27 Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 Clock generator circuitry. It is operated in parallel resonance. OSCIN is the high gain amplifier input and OSCOUT is the output. To drive the SAA5290 externally OSCIN is driven from an external source and OSCOUT is left open-circuit. The oscillator circuit of the SAA5290 is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between OSCIN and OSCOUT is basically an inverter biased to the transfer point. A crystal must be used as the feedback element to complete the oscillator handbook, halfpage handbook, halfpage OSCGND C1 not connected OSCGND (1) OSCIN external clock C2 (1) not connected OSCOUT MLC110 OSCIN OSCOUT MLC111 (1) The values of C1 and C2 depend on the crystal specification: C1 = C2 = 2CL. Fig.7 Oscillator circuit. February 1995 Fig.8 Oscillator circuit driven from external source. 28 February 1995 b 7 b 6 b5 b 4 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 29 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 3 2 1 0 graphics magenta graphics cyan alpha numerics magenta alpha numerics cyan F E D C B A 9 black back ground new back ground hold graphics release graphics double height double width double size separated graphics contiguous graphics conceal display normal height start box end box steady flash graphics blue alpha numerics blue 8 graphics yellow alpha numerics yellow graphics white graphics green alpha numerics green alpha numerics white graphics red alpha numerics red 1 graphics black 0 1 0 0 0 0 0 alpha numerics black 0 7 6 5 4 r o w column 0 2 0 0 1 2a 0 3 0 0 1 3a 1 0 0 0 0 5 1 0 1 6 0 1 1 6a 0 handbook, full pagewidth 7 0 1 1 7a 1 1 0 8 0 0 1 0 9 0 1 1 1 A 0 0 Fig.9 SAA5290 European character set. 4 1 1 B 0 1 double size OSD double width OSD double height OSD normal size OSD background white background cyan background magenta background blue background yellow background green back ground red background black 1 1 0 C 1 0 1 0 D 1 1 1 1 E 1 0 1 1 F 1 1 1 0 D 1 1 1 1 E 1 0 1 F 1 1 MLC108 1 One page Economy Teletext/TV microcontroller 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 b 3 b 2 b1 b 0 B I T S Philips Semiconductors Preliminary specification SAA5290 CHARACTER SETS Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 handbook, full pagewidth CHARACTER POSITION (COLUMN / ROW) PHCB LANGUAGE E/W C12 C13 C14 2 / 3 ENGLISH 0 0 0 0 GERMAN 0 0 0 1 SWEDISH 0 0 1 0 ITALIAN 0 0 1 1 FRENCH 0 1 0 0 SPANISH 0 1 0 1 TURKISH 0 1 1 0 ENGLISH 0 1 1 1 POLISH 1 0 0 0 GERMAN 1 0 0 1 ESTONIAN 1 0 1 0 GERMAN 1 0 1 1 GERMAN 1 1 0 0 SERBO-CROAT 1 1 0 1 CZECHOSLOVAKIA 1 1 1 0 RUMANIAN 1 1 1 1 2/4 4/0 5/B 5/C 5/D 5/E 5/F 6/0 7/B 7/C 7/D 7/E MLC109 Fig.10 SAA5290 European national option characters. February 1995 30 February 1995 31 VDD VDD CVBS (IF) P1.4 P1.5 1 kΩ Vafc HSYNC VDS R P0.2 P0.3 P0.4 P0.5 FRAME IREF Fig.11 Typical application diagram. MLC112 V SSD2 BLACK 27 kΩ COR P3.4 CVBS1 CVBS0 RGBREF B P0.7 V SSA G P0.6 SAA5290 V DDA VSYNC P0.1 V DDT OSCGND P0.0 VSSD VDD 100 nF VDD 2.2 µF 4.7 kΩ VDD 1 kΩ 10 kΩ 3.3 kΩ VDD 100 nF TV control signals VDD to TV's display circuits line flyback field flyback 47 µF IR RECEIVER VDD One page Economy Teletext/TV microcontroller CVBS (SCART) 100 nF 100 nF OSCOUT P3.2/ADC2 OSCIN RESET P3.1/ADC1 P3.3 V DDM P3.0/ADC0 P1.0/INT1 P1.1/T0 P2.6/PWM5 P2.7 P2.5/PWM4 P1.2/INT0 volume (L) P1.3/T1 P1.6/SCL VDD 12 MHz VSS SDA volume (R) P2.4/PWM3 100 nF RC SCL A1 A2 VDD A0 EEPROM PCF8582E P2.2/PWM1 P1.7/SDA P2.1/PWM0 P2.0/TPWM 100 nF VDD hue 47 µF VDD P2.3/PWM2 PH2369 VDD saturation contrast brightness VDD Vtune 40 V handbook, full pagewidth Philips Semiconductors Preliminary specification SAA5290 APPLICATION INFORMATION February 1995 seating plane Dimensions in mm. 3.2 2.8 32 14.1 13.7 0.18 M 0.51 min 4.57 5.08 max max 0.32 max 17.15 15.90 15.24 15.80 15.24 MSA267 One page Economy Teletext/TV microcontroller Fig.12 Plastic shrink dual in-line package; 52 leads (600 mil) SDIP52, SOT247-1. 26 1 1.3 max 0.53 max 27 1.778 (25x) 47.92 47.02 52 1.73 max handbook, full pagewidth Philips Semiconductors Preliminary specification SAA5290 PACKAGE OUTLINE Philips Semiconductors Preliminary specification One page Economy Teletext/TV microcontroller SAA5290 specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. REPAIRING SOLDERED JOINTS Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. February 1995 33