SC2677 Dual Synchronous Voltage Mode Controller with Current Sharing Circuitry POWER MANAGEMENT Description Features The SC2677 is a versatile 2 phase, synchronous, voltage mode PWM controller that may be used in two distinct ways. First, the SC2677 is ideal for applications where point of use output power exceeds any single input power budget. Alternatively, the SC2677 can be used as a dual switcher. The SC2677 features a temperature compensated voltage reference, an under voltage lockout over current protection and internal level-shifted, highside drive circuitry. 300kHz to 1MHz externally programmable frequency operation Soft Start and Enable function Power Good output provided Under voltage short circuit protection Phase-shifted switchers minimize ripple High efficiency operation, >90% Programmable output(s) as low as 0.5V Industrial temperature range TSSOP-20 package Bias voltage as low as 4.5V Adjustable phase shift between channels In current sharing configuration, the SC2677 can produce a single output voltage from two separate voltage sources (which can be different voltage levels) while maintaining current sharing between the channels. Current sharing is programmable to allow loading each input supply as required by the application. Tw o Phase, Current Sharing Controller Flexible, same or separate VIN Programmable current sharing Thermal distribution via multi-phase output In dual switcher configuration, two feedback paths are provided for independent control of the separate outputs. The device will provide a regulated output from flexibly configured inputs (3.3V, 5V, 12V), provided 5V is present for VCC. The phasing between the two switchers is adjustable to minimize the input and output ripple. Applications Graphics cards Peripheral add-in card Dual-Phase power supply Power supplies requiring two outputs Simplified Application Schematic +5V L1 M1 1 Vout1 2 C1 M2 C2 +12V C3 1uF PWRGD R2 ENABLE R1 11 BSTC 12 DL1 14 13 DH1 COMP1 BST1 15 16 -IN1 17 PHASING SS/ENA PWRGD GND R5 R6 DL2 DH2 PGND 10 9 8 COMP2 0R0 BST2 7 +IN2 -IN2 6 5 4 3 2 1 VCC SC2677 FREQ U1 VREF R7 18 C4 19 R4 20 C5 R3 C6 R8 C7 R9 R11 R10 C8 +12V +3.3V L2 1 Vout2 2 M3 C9 M4 C10 Revision: NOV. 15, 2004 1 www.semtech.com SC2677 POWER MANAGEMENT Absolute Maximum Rating Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Limits Units VIN -0.3 to 15 V ±1 V BST1, BST2 to GND -0.3 to 20 V BSTC to GND -0.3 to 20 V -IN1, +/-IN2 to GND 7 V COMP1, COMP2 to GND 7 V DH1, DH2 to GND -0.3 to 20 V DL1, DL2 to GND -0.3 to BSTC + 0.3 V VCC to GND PGND to GND -3 peak (50nS) PWRGD to GND PHASING SS/ENA to GND (1) V VCC + 0.3 V 7 V -0.3 to 7 V Thermal Resistance Junction to Case θJC 17 °C/W Thermal Resistance Junction to Ambient θJA 90 °C/W Operating Ambient Temperature Range TA 0 to 70 °C Operating Junction Temperature Range TJ 0 to 125 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 sec TLEAD 300 °C Electrical Characteristics Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, TJ = 25°C, VBSTC = VBST = 12V Parameter C onditions Min Typ Max U nits Output Voltage VOUT = VFB 0.495 0.500 0.505 V Supply Voltage V CC 4.5 15 V Supply C urrent UVLO VCC = 5.0 10 mA VCC Ramp up Threshold 2.84 V V CC 100 mV 0.5 V UVLO Hysteresi s Reference Reference Load Regulati on VREF source 10uA ~ 100uA 0.2 % Reference Li ne Regulati on 5V < V C C < 15V 0.7 % Output Li ne Regulati on 5V < VIN < 15V 0.7 % Gai n (Gm) (Error Ampli fi er) C OMP pi n source 100uA Bi as C urrent Offset (Slave Error Ampli fi er) Max C urrent (Error Ampli fi er) Input Bi as C urrent 5 6 mA/V -2 -1 0 mV Source 200 250 uA Si nk 400 460 uA -IN1, +IN2, -IN2 Short C i rcui t Protecti on Threshold 45 Osci llator Frequency Range © 2004 Semtech Corp. 4 300 2 55 2 µA 65 % 1000 kHz www.semtech.com SC2677 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, TJ = 25°C, VBSTC = VBST = 12V Parameter Conditions Min Typ Max Units Oscillator Frequency RSET = 2.5kohm 450 500 550 kHz Oscillator Max Duty Cycle FOSC = 500kHz 86 90 % 180 °C Phasing of DH2 and DL1 VPHASING = 0.585V DH Sink Current DH - PGND = 3.5V 1.7 A DH Sink Current DH - PGND = 2.5V 0.85 A DH Source Current BSTH - DH = 3.75V 1.7 A DH Source Current BSTH - DH = 3V 0.85 A DL Sink Current DL - PGNG = 3.5V 1.7 A DL Sink Current DL - PGND = 2.5V 0.85 A DL Source Current BSTL - DL = 3.75V 1.7 A DL Source Current BSTL - DL = 3V 0.85 A Note 5 50 Dead Time Soft Start Charge Current (2) Soft Start Transition Threshold(2) 120 ns 50 µA 0% duty cycle 400 mV 100% duty cycle 825 mV Synchronous mode 1.22 V Soft Start Enable Soft Start End 85 Power Good Threshold VOUT ramping up Power Good Pull Down Sink Current = 2mA 83% 88% 93% VOUT 0.4 V NOTES: (1) Measured from 50% to 50% pulse amplitude. (2) The soft start pin sources 50µA to an external capacitor. The converter operates in synchronous mode above the soft start transition threshold and in asynchronous mode below it. (3) Power good is an open collector output which is pulled low when the output voltage is under 75%. (4) This device is ESD sensitive. Use of standard ESD handling precautions is required. (5) 120ns maximum at 70°C. Marking Information (TSSOP-20) TOP yyww = Datecode (Example: 9908) xxxx = Semtech Lot # (Example: 90101) © 2004 Semtech Corp. 3 www.semtech.com SC2677 POWER MANAGEMENT Pin Configuration Ordering Information Top View D evice(1) P ackag e SC 2677TSTR TSSOP-20 SC 2677TSTRT(2) TSSOP-20 SC 2677EVB-1 C urrent Share Evaluati on Board SC 2677EVB-2 D ual C hannel Evaluati on Board Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free package. (TSSOP-20 Pin) Pin Descriptions EXPANDED PIN DESCRIPTION Pin 1: (VREF) Internal 0.5V reference. Connected to the + input of the master channel error amplifier. Pin 2: (FREQ) External frequency adjustment. Connect a resistor to AGND to set the switching frequency. Please see more information in Application section. Pin 3: (VCC) Bias pin for the controller. Connect a ceramic decoupling capacitor from this pin to AGND with minimum trace length. Pin 4: (+IN2) “+” input of the slave error amplifier. Pin 5, 16: (-IN2, -IN1) “-” inputs of the error amplifiers. Pin 6, 15: (COMP2, COMP1) Compensation pins of the error amplifiers. Pin 7, 14: (BST2, BST1) Supply pins for the high side drivers. Usually connected to bootstrap circuit. Pin 8, 13: (DH2, DH1) Gate drive pins for the top MOSFETs. Requires a small series resistor. Pin 9, 12: (DL2, DL1) Gate drive pins for the bottom MOSFETs. Requires a small series resistor. © 2004 Semtech Corp. Pin 10: (PGND) Power GND. Return of the high side and low side gate drivers. Pin 11: (BSTC) Supply pin for bottom MOSFET gate drivers. Pin 17: (PHASING) This pin controls the phase shift between master and slave for optimum noise immunity. Use a resistive divider from the FREQ pin (pin 2) to AGND, and connect the tap of the resistive divider to pin 17. Please see more information in Application section. Pin 18: (SS/ENA) Soft start pin. Connect a ceramic capacitor from this pin to AGND, and there is an internal current source charging up this capacitor during soft start. The PWM operation can be disabled if this pin is pulled low. Pin 19: (PWRGD) Power good signal. This is an open collector output. It is pulled low internally if output voltage is outside the power good window. Pin 20: (GND) Analog GND. Return of the analog signals and bias of the chip. 4 www.semtech.com SC2677 POWER MANAGEMENT Block Diagram 1.25V 50uA NOTES (1) Channel 1 is the Master and Channel 2 is the Slave in current sharing configuration. (2) For dual output operation, tie +IN2 to VREF and the two PWM channels are independent. © 2004 Semtech Corp. 5 www.semtech.com +5V ENABLE PWRGD +12V 4.6k 1.0uF 2.2 10uF C36 U1 C41 10uF 0.1uF R31 C40 5.9K R19 R13 19 1uF C39 1000uF 1000uF C28 7.5K R5 10uF 10uF C4 C3 0.1uF C24 1000uF C5 1000uF C42 1uF C25 0R0 R2 SC2677 0R0 R32 IPD06N03LA M5 1uF C38 M3 R24 7.50K IPD06N03LA 301 M7 R21 220nF C33 C35 1nF C60 1.0 77120-A7,2XAwg18,8 Turns,4mohm L2 2 1 2uH R35 220nF 10uF C12 10uF C13 10uF C14 10uF C15 0R0 R36 10uF C16 10uF C45 10uF C46 10uF 10uF 10uF 12.1K C56 1800uF C55 1800uF C20 1800uF C19 1800uF C49 C48 C47 R14 1.78K R8 220nF 1.00K R10 220nF 1uF 3.74K R26 C37 R22 2.49K 1nF C21 1.0 R1 77120-A7,2XAwg18,8 Turns,4mohm L1 2 1 2uH C23 C26 IPD06N03LA IPD06N03LA 13 C2 M1 14 C1 20 GND VR EF 1 PWRGD FR EQ 2 17 PHASING 18 SS/ENA VC C 3 -IN 2 5 +IN2 4 16 -IN 1 15 COMP1 COMP2 6 12 DL1 11 BSTC PGND BST1 BST2 7 DH 1 DH2 8 6 9 DL2 © 2004 Semtech Corp. 10 +3.3V 1.4V/16A +Vout SC2677 POWER MANAGEMENT Evaluation Schematic 2 Channels with Current Sharing www.semtech.com SC2677 POWER MANAGEMENT Applications Information - Theory of Operation Main Loop(s) Soft Start/Enable The Soft Start/Enable (SS/ENA) pin serves several functions. If held below the Enable threshold, both channels are inhibited. DH1 and DH2 will be low, turning off the top FETs. Between the Soft Start Enable threshold and the Soft Start End threshold, the duty cycle is allowed to increase. At the Soft Start End threshold, maximum duty cycle is reached. In practical applications the error amplifier will be controlling the duty cycle before the Soft Start End threshold is reached. To avoid boost problems during start-up in current share mode, both channels start up in asynchronous mode, and the bottom FET body diode is used for circulating current during the top FET off time. When the SS/ENA pin reaches the Soft Start Transition threshold, the channels begin operating in synchronous mode for improved efficiency. The soft start pin sources approximately 50uA and soft start timing can be set by selection of an appropriate soft start capacitor value. a) Two independent channels with either common or different input voltages and different output voltages. The two channels each have their own voltage feedback path from their own output. In this mode, positive input of the error amplifier 2 is connected externally to Vref. If the application uses a common input voltage, the sawtooth phase shift between the channels provides some measure of input ripple current cancellation. It is possible to sequence the start up of the channel with an RC delay between the reference and +IN2. The capacitor will be internally reset during UVLO and soft start. © 2004 Semtech Corp. Frequency Set and Phasing The switching frequency can be programmed by connecting a resistor from the FREQ pin to AGND. The PHASING pin controls the phase shift between the master sawtooth and slave sawtooth which allows the adjustment of the phase shift for maximum noise immunity by controlling the timing between master and slave transition. A resistive divider is used from the FREQ pin to AGND and the divided voltage is fed to the PHASING pin as depicted. 7 11 BSTC 12 DL1 13 DH1 14 BST1 15 COMP1 16 -IN1 17 PHASING 18 SS/ENA PGND 10 DH2 BST2 DL2 9 8 7 -IN2 +IN2 COMP2 6 5 4 VCC SC2677 FREQ U1 3 3.92K 2 R19 PWRGD GND 20 3.57K 19 R13 1 b) Two channels operating in current sharing mode with common output voltage and either common input voltage or different input voltages. In this mode, channel 1 operates as a voltage mode Buck controller, as before, but error amp 2 monitors and amplifies the difference in voltage across the output current sense resistors of channel 1 and channel 2 (Master and Slave) and adjusts the Slave duty cycle to match output currents. To controller also works well for using the output choke winding resistance as current sensing element (please refer the application schematic for details). The amount of the current of the slave channel vs.. the master channel can be programmed according to the application. This feature is especially useful when two input sources are used and each source has its power budget. The offset of the current sharing error amplifier is trimmed whthin the range of -2mV to 0. The polarity being such that the slave is OFF if the master has no current. Power Good VREF The SC2677 is a dual, voltage mode synchronous Buck controller. The two separate channels are identical and share only IC supply pins (Vcc and GND), output driver ground (PGND) and pre-driver supply voltage (BSTC). They also share a common oscillator generating a sawtooth waveform for channel 1 and an dephased sawtooth for channel 2. Channel 2 has both inputs of the error amplifier uncommitted and available externally. This allows the SC2677 to operate in two distinct modes. The controller provides a power good signal. This is an open collector output, which is pulled low if the output voltage is outside of the power good window. www.semtech.com SC2677 POWER MANAGEMENT Applications Information (R 13+ R 19) v s.O scillato r F re q u e n cy It is important to keep the gate traces short, the IC must be close to the power switches. It is recommended to use at least 25 mil width or wider trace when ever possible. A good placement can help if the controller is placed in the middle of the two PWM channels. Oscillator Frequency (kHz) 1000 900 800 700 600 500 Grounding requirements are always important in a buck converter layout, especially at high power. Power ground (PGND) should be returned to the bottom MOSFET source to provide the best gate current return path. Analog ground (GND) shape should be used for the anaglog returns such as chip decoupling, frequency setiing, reference voltage (or soft starting cap), and the compensation. This groung shap should be single point connected to the PGND shape near the ground side of the output capacitors. This will provide noise free analog ground for operation stablity, and also provide best possible remote sensing for the feedback voltage. In case two output rails need to be regulated, the AGND shape should single point connected to the geometrica center of the PGND for the two point of loads. The single ponit tie is a must to prevent the power current from flowing on the AGND shape, so that the analog circuitry in the controller has an electrically quiet reference and to provide the greatest noise free operation. Keep in mind that the AGND pin is never allowed to have bigger than 1V voltage difference vs the PGND pin. This usually achievable by using a ground plan for PGND in PCB layout. Using ground plane for PGND can reduce the physical separation between the two grounds, such that even the fast current transitions in the PGND plane can not generate voltage spikes exceeding the 1V level, therefore preventing unstable and erratic behavior from happening. 400 300 4 6 8 10 12 14 16 18 20 (R 13+ R 19) (ko h m) Vp h a sin g v s P h as e S h ift 180 160 Phase (deg) 140 120 100 80 60 40 20 0 0 .5 5 0 .6 0 0 .6 5 0 .7 0 0 .7 5 0 .8 0 0 .8 5 0 .9 0 V p h a s in g (V ) Shutdown The output short circuit protection is done by output undervoltage detection. Upon output short circuit and when the output voltage drops bellow a certain percentage of the regulation target (see elctrical characteristics table for details, the PWM will be disabled and the output will be dsiabbled and latched off. The latch can be reset by power cycling. Layout Guidelines Power and signal traces must be kept separated for noise considerations. Feedback, current sense traces and analog ground should not cross any traces or planes carrying high switching currents, such as in the input loop or the phase node. The feedback divider must be close to the IC and be returned to analog ground. Current sense traces must be run parallel and close to each other and to analog ground. The input loop, consisting of the input capacitors and both MOSFETs must be kept as small as possible. Since all of the high switching currents occur in the input loop, the enclosed loop area must be kept small to minimize inductance and radiated and conducted noise emissions. Designing for minimum trace length is not the only factor The IC must have a ceramic decoupling capacitor across its supply pins, mounted as close to the device as possible. The small ceramic, noise-filtering capacitors on the current sense lines should also be placed as close to the IC as possible. for best design, often a more optimum layout can be achieved by keeping the wide trace and using proper layer stacking to minimize the stray inductance. © 2004 Semtech Corp. 8 www.semtech.com SC2677 POWER MANAGEMENT Outline Drawing - TSSOP-20 A D IM D e E /2 E1 E P IN 1 IN D IC A T O R ccc C 2 X N /2 T IP S 1 2 3 e /2 B 0 .0 5 0 .8 0 0 .1 9 0 .0 9 6 .4 0 4 .3 0 1 .2 0 0 .1 5 1 .0 5 0 .3 0 0 .2 0 6 .6 0 6 .5 0 4 .5 0 4 .4 0 6 .4 0 B S C 0 .6 5 B S C 0 .4 5 0 .6 0 0 .7 5 ( 1 .0 ) 20 0 8 0 .1 0 0 .1 0 0 .2 0 D aaa C S E A T IN G PLANE .0 4 7 .0 0 6 .0 4 2 .0 1 2 .0 0 7 .2 5 9 .2 5 5 .1 7 7 .1 7 3 .2 5 2 B S C .0 2 6 B S C .0 1 8 .0 2 4 .0 3 0 (.0 3 9 ) 20 0 8 .0 0 4 .0 0 4 .0 0 8 .0 0 2 .0 3 1 .0 0 7 .0 0 3 .2 5 1 .1 6 9 A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc N 2X D IM E N S IO N S IN C H E S M IL L IM E T E R S M IN N O M M A X M IN N O M M A X A2 C A H A1 bxN bbb C A -B D c GAGE PLANE 0 .2 5 L (L 1 ) S ID E V IE W S E E D E T A IL D E T A IL A 01 A NO TES: 1. C O N T R O L L I N G D I M E N S I O N S A R E IN M IL L I M E T E R S ( A N G L E S I N D E G R E E S ) . 2. DATUM S 3. D IM E N S IO N S " E 1 " A N D " D " D O N O T I N C L U D E M O L D F L A S H , P R O T R U S IO N S OR G ATE BURRS. 4. R E F E R E N C E J E D E C S T D M O - 1 5 3 , V A R IA T I O N A C . -A - AND -B - T O B E D E T E R M IN E D A T D A T U M P L A N E -H - Land Pattern - TSSOP-20 X D IM (C ) G C G P X Y Z Z Y D IM E N S IO N S IN C H E S M IL L I M E T E R S ( .2 2 2 ) .1 6 1 .0 2 6 .0 1 6 .0 6 1 .2 8 3 ( 5 .6 5 ) 4 .1 0 0 .6 5 0 .4 0 1 .5 5 7 .2 0 P NOTES: 1. T H IS L A N D P A T T E R N IS F O R R E F E R E N C E P U R P O S E S O N L Y . C O N S U L T Y O U R M A N U F A C T U R IN G G R O U P T O E N S U R E Y O U R C O M P A N Y 'S M A N U F A C T U R I N G G U I D E L I N E S A R E M E T . Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 © 2004 Semtech Corp. 9 www.semtech.com