SCAN12100
1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and
Precision Delay Calibration Measurement
■ DCM also measures chip and other delays to ≤ ± 1200 ps
General Description
The SCAN12100 is a 1228.8 and 614.4 Mbps serializer/deseralizer (SerDes) for high-speed bidirectional serial data
transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. The SCAN12100 integrates
precision delay calibration measurement (DCM) circuitry that
measures link delay components to better than ± 800 ps accuracy.
The SCAN12100 features independent transmit and receive
PLLs, on-chip oscillator, and intelligent clock management
circuitry to automatically perform remote radio head synchronization and reduce the cost and complexity of external clock
networks.
The SCAN12100 is programmable though an MDIO interface
as well as through pins, featuring configurable transmitter deemphasis, receiver equalization, speed rate selection, internal pattern generation/verification, and loop back modes. In
addition to at-speed BIST, the SCAN12100 includes IEEE
1149.1 and 1149.6 testability.
Note: For a full SCAN12100 datasheet please contact
your local National Semiconductor representitive
Features
■
■
■
■
Exceeds LV and HV CPRI voltage and jitter requirements
1228.8, and 614.4 Mbps operation
Pin and package compatibility with the SCAN25100
Integrated delay calibration measurement (DCM) directly
measures T14 and Toffset delays to ≤ ± 800 ps
■
■
■
■
■
■
■
■
■
■
■
■
■
■
accuracy
Deterministic chip latency
Automatic receiver lock and RE synchronization without
reference clock or external crystal
Independent transmit and receive PLLs for seamless RE
synchronization
Low noise recovered clock output
Requires no jitter cleaning in single-hop applications
>8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV
CDM
Hot plug protection
LOS, LOF, 8b/10b line code violation, comma, and
receiver PLL lock reporting
Programmable hyperframe length and start of hyperframe
character
Programmable transmit de-emphasis and receive
equalization with on-chip termination
Advanced testability features
— IEEE 1149.1 and 1149.6
— At-speed BIST pattern generator/verifier
— Multiple loopback modes
1.8V or 3.3V compatible parallel bus interface
100-pin TQFP package with exposed dap
Industrial –40 to +85° C temperature range
Block Diagram
20209542
© 2006 National Semiconductor Corporation
202095
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SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes
November 2006
SCAN12100
Pin Diagram
SCAN12100
20209502
(Top View)
100–Pin TQFP with Exposed Ground Pad
Order Number SCAN12100TYA
See NS Number VXF100B
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2
SCAN12100
Pin Descriptions
Pin #
Pin Name
I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
12
11
DOUTP
DOUTN
O, CML
Inverting and non-inverting high speed CML differential outputs of the serializer. Onchip termination resistors connect from DO+ and DO− to an internal reference
18
17
RINP
RINN
I, CML
Inverting and non-inverting high speed differential inputs of the deseralizer. On-chip
termination resistors connect from RI+ and RI− to an internal reference. On-chip
termination resistors are configured for AC-coupled applications.
PARALLEL DATA BUS
65
66
67
68
69
70
71
72
73
74
DIN [0]
DIN [1]
DIN [2]
DIN [3]
DIN [4]
DIN [5]
DIN [6]
DIN [7]
DIN [8]
DIN [9]
I, LVTTL or 1.8V Transmit data word.
LVCMOS Internal pull down
In 10-bit mode, the 10-bit code-group at DIN [0–9] is serialized with the internal 8b/
10b encoder disabled. Bit 9 is the msb.
The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2
53
54
55
56
57
58
59
60
61
62
ROUT [0]
ROUT [1]
ROUT [2]
ROUT [3]
ROUT [4]
ROUT [5]
ROUT [6]
ROUT [7]
ROUT [8]
ROUT [9]
O, LVTTL or 1.8V Deserialized receive data word.
LVCMOS Internal pull down
In 10-bit mode, ROUT [0-9] is the deserialized received data word in 10-bit code group.
Bit 9 is the msb.
The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2
CLOCK SIGNALS
6
7
REFCLKP
REFCLKN
I, LVDS or
LVPECL
64
TXCLK
I, LVTTL or 1.8V Transmit clock. TXCLK must be synchronous to REFCLK to avoid FIFO under/
LVCMOS Internal overflow though it may differ in phase.
pull down
52
RXCLK
I/O, LVTTL or 1.8V Write mode: RXCLK is recovered clock output pin.
LVCMOS
Read mode: RXCLK is an input pin. ROUT [9:0] are latched out on RXCLK rising and
falling edges. RXCLK must be synchronous to the incoming serial data to avoid FIFO
over/underflow, though it may differ in phase. See RXCLKMODE pin description for
more details.
22
23
SYSCLKP
SYSCLKN
O, LVDS
Inverting and non-inverting differential serializer reference clock. A low jitter clock
source should be connected to REFCLKP & REFCLKN.
30.72 MHz output clock. (OPMODE must be low.)
LINE STATUS
78
LOS
O, LVTTL or 1.8V Receiver CPRI loss of signal (LOS) status (8-bit mode only).
LVCMOS
0 = signal detected (per CPRI standard)
1 = signal lost (per CPRI standard)
77
LOCKB
O, LVTTL or 1.8V Receiver PLL lock status
LVCMOS
0 = Receiver PLL locked
1 = Receiver PLL not locked
3
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SCAN12100
Pin #
79
Pin Name
CDET
I/O, Type
Description
O, LVTTL or 1.8V Comma Detect.
LVCMOS
0 = no comma yet detected in the incoming serial stream or receiver PLL not locked.
1 = the receiver PLL is locked and a positive or negative comma bit sequence detected
in the incoming bit stream. The serial to parallel converter is aligned to the proper 10bit word boundary when comma alignment is enabled (CALIGN_EN = 1).
CONTROL PINS
82
81
88
89
PE [0]
PE [1]
EQ [0]
EQ [1]
I, LVTTL or 1.8V Transmitter de-emphasis configuration.
LVCMOS Internal Pulling both pins low enables MDIO control, default is no de-emphasis.
pull down
PE1
PE0
0
0
No de-emphasis
0
1
Low de-emphasis
1
0
Medium de-emphasis
1
1
Maximum de-emphasis
I, LVTTL or 1.8V Receive input equalization configuration.
LVCMOS Internal Pulling both pins low enables MDIO control, default is no receive equalization.
pull down
EQ1
EQ0
0
0
No receive equalization
0
1
Low receive equalization
1
0
Medium receive equalization
1
1
Maximum receive equalization
90
91
TXPWDNB
RXPWDNB
I, LVTTL or 1.8V Power down control signals.
LVCMOS Internal TXPWDNB
pull down
0 = Transmitter is powered down and DOUT± pins are high impedance.
1 = Transmitter is powered up.
RXPWDNB
0 = Receiver is powered down and ROUT [9:0] as well as LOS, LOCKB, CDET,
RXCLK, and SYSCLK are high impedance.
1 = Receiver is powered up.
92
CALIGN_EN
I, LVTTL or 1.8V Comma alignment enable.
LVCMOS Internal 0 = comma alignment circuitry disabled. Receiver will not realign 10-bit data based on
pull down
incoming comma characters. CDET pin still flags comma detection.
1 = comma detect and alignment circuitry enabled. Receiver aligns 10-bit data to
incoming comma character and flags comma detect through CDET pin.
93
RXCLKMODE
I, LVTTL or 1.8V Receiver recovered clock mode
LVCMOS Internal 0 = Write mode. RXCLK pin is a recovered clock output.
pull down
(RXCLK = output pin)
1 = Read mode. RXCLK pin is ROUT [9:0] bus read input strobe.
(RXCLK = input pin)
80
VSEL
I, LVTTL or 1.8V Selects whether single-ended data and control pins are 3.3V LVTTL or 1.8V LVCMOS.
LVCMOS Internal 0 = 1.8V LVCMOS. Tie VSEL to ground and power IOVDD at 1.8 V.
pull down
1 = 3.3V LVTTL. Tie VSEL to IOVDD supply and power IOVDD at 3.3 V.
94
OPMODE
I, LVTTL or 1.8V Selects SerDes mode.
LVCMOS Internal pull down
0 = Base station mode
1 = Reserved for future use
95
RESETB
I, LVTTL or 1.8V Hardware SerDes reset. Resets PLLs and MDIO registers.
LVCMOS Internal pull down
0 = Hardware SerDes reset
1 = Normal operation
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96
97
Pin Name
SPMODE [0]
SPMODE [1]
I/O, Type
SCAN12100
Pin #
Description
I, LVTTL or 1.8V Speed mode configuration. (OPMODE must be low)
LVCMOS Internal Pulling both pins low enables MDIO control.
pull down
SPMODE [1]
SPMODE [0]
0
0
Rate selected via MDIO
0
1
614.4 Mbps rate mode
1
0
1228.8 Mbps rate mode
1
1
Reserved
98
TENBMODE
I, LVTTL or 1.8V Enable 10-bit mode
LVCMOS, Internal
The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2
pull down
0 = Selects 8-bit mode. Enables the internal 8b/10b encoder and decoder.
1 = Selects 10-bit mode. Bypasses internal 8b/10b encoder and decoder.
99
100
LOOP [0]
LOOP [1]
I, LVTTL or 1.8V Loop back configuration.
LVCMOS, Internal Pulling both pins low enables MDIO control.
pull down
Note: During Special line (remote) loop back mode, the output de-emphasis control
is disabled.
LOOP [1]
LOOP [0]
0
0
Normal mode—no loop back
0
1
Line (remote) loop back mode
1
0
Local loop back mode
1
1
Special line (remote) loop back mode
MDC/MDIO
30
31
37
36
35
34
33
MDC
MDIO
ADD0
ADD1
ADD2
ADD3
ADD4
3.3V LVTTL
MDC/MDIO configuration bus.
Internal pull up on Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL
ADDR pins
compatible, not 1.2V signal compatible.
IEEE 1149.1 (JTAG)
45
41
44
43
46
TDI
TDO
TMS
TCK
TRSTB
3.3V LVTTL
JTAG test bus for IEEE 1149.1 and 1149.6 support.
Internal pull up on
TDI, TMS, and
TRSTB
RESERVED PINS
83
84
RES1
RES2
I
Reserved.
Tie with 5 KΩ resistor to ground.
POWER
9, 15, 20, AVDD18
32, 38, 47,
85
I, Power
1.8V analog supply.
8, 14, 21, AVDD33
42
I, Power
3.3V analog supply.
1, 2, 28, 29 PVDD33
I, Power
3.3V PLL supply (minimize supply noise to < 100 mV peak-to-peak).
50, 51, 76, IOVDD
87
I, Power
1.8V or 3.3V parallel I/O bus and control pin supply.
See VSEL pin description for additional information.
I, Ground
Device ground.
GROUND
3, 4, 5, 10, GND
13, 16, 19,
24, 25, 26,
27, 39, 40,
48, 49, 63,
75, 86
5
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SCAN12100
Pin #
Pin Name
I/O, Type
Description
I, Ground
Device ground. Pad must be soldered and contected to GND plane with a minimum
of 8 thermal vias to achieve specified thermal performance.
GROUND DAP
101
GND
Note: I= input
resistor
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O = output
Internal pull down = input pin is pulled low by an internal resistor
6
Internal pull up = input pin is pulled high by an internal
Derating above 25°C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (AVDD18)
Supply Voltage (PVDD, IOVDD)
Supply Voltage (AVDD33)
LVCMOS Input Voltage
−0.3V to +2.0V
−0.3V to +3.6V
−0.3V to +3.6V
−0.3V to (IOVDD +
0.5V)
LVCMOS Output Voltage
−0.3V to (IOVDD +
0.5V)
MDC/MDIO/ADD[0:4],VSEL Input Voltage
−0.3V to (AVDD33 + 0.5V)
MDIO Output Voltage
−0.3V to (AVDD33 +
0.5V)
CML Receiver Input Voltage
−0.3V to (AVDD +
0.3V)
CML Receiver Output Voltage
−0.3V to (AVDD +
0.3V)
Junction Temperature
+125°C
Storage Temperature
−65°C to +150°C
Lead Temperature
Soldering, 10–20 sec
235 °C
Lead-free +260°C flow is available
Maximum Package Power Dissipation at 25°C
100-pin TQFP with Exposed Pad
4.16 W
Note: This is the maximum TQFP-100 package power
dissipation capability. For SCAN12100 power dissipation,
see the information in the Electrical Characteristics section.
Electrical Characteristics
Symbol
41.6 mW/°C
24.0°C/W
Thermal Resistance , θJA (0 airflow)
ESD Rating
CML RIN/DOUT Pins
HBM, 1.5 kΩ, 100 pF
>8 kV
EIAJ, 0Ω, 200 pF
CDM
All Other Pins
>250V
>2 kV
HBM, 1.5 kΩ, 100 pF
>7 kV
EIAJ, 0Ω, 200 pF
CDM
>250V
>2 kV
Recommended Operating
Conditions
Supply Voltage
AVDD18
AVDD33, PVDD33
IOVDD (1.8V Mode)
IOVDD (3.3V Mode)
Temperature
Junction temperature
Supply Noise
(Peak-to-Peak)
Min
Typ
Max
Unit
1.7
3.135
1.7
3.135
-40
1.8
3.3
1.8
3.3
25
1.9
3.465
1.9
3.465
85
125
V
V
V
V
°C
°C
<100
mV
Over recommended operating supply and temperature ranges unless other specified.
Parameter
Condition
Min
Typ
(Note 2)
Max
Units
LVCMOS DC SPECIFICATIONS (1.8V I/O)
VIH
High level input voltage
VIL
Low level input voltage
0.65VDD
IIN
Input Current
VIN = 0V or 1.9V
−10
VOH
High level output voltage
IOH = −2 mA
1.2
VOL
Low level output voltage
IOL = 2 mA
IOZ
Power Down Output Current
Power down
CIO
Input/Output Capacitance
Typical
V
0.35VDD
V
+50
µA
V
−20
0.45
V
+20
µA
2.8
pF
LVCMOS DC SPECIFICATIONS (3.3V I/O)
VIH
High level input voltage
2
VIL
Low level input voltage
IIN
Input Current
VIN = 0V or 3.465V
−10
VOH
High level output voltage
IOH = −2 mA
2.4
VOL
Low level output voltage
IOL = 2 mA
IOZ
Power Down Output Current
Power down
CIO
Input/Output Capacitance
Typical
V
0.8
V
+50
µA
V
−20
0.4
V
+20
µA
2.8
pF
JTAG DC SPECIFICATIONS (3.3V I/O)
VIH
High level input voltage
VIL
Low level input voltage
2
IIN
Input Current
VIN = 0V or 3.465V
−35
VOH
High level output voltage
IOH = −2 mA
2.4
7
V
0.8
V
+50
µA
V
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SCAN12100
Absolute Maximum Ratings (Note 1)
SCAN12100
Symbol
Parameter
Condition
VOL
Low level output voltage
IOL = 2 mA
CIO
Input/Output Capacitance
Typical
Min
Typ
(Note 2)
Max
0.4
2.8
Units
V
pF
MDIO/MDC/ADD0-4 DC SPECIFICATIONS
VIH
High level input voltage
2.0
3.465
V
VIL
Low level input voltage
GND
0.8
V
IIN
Input Current
VIN = 0 or 3.465V
-150
150
µA
VOH
High level output voltage
IOH = −2 mA
VOL
Low level output voltage
IOL = 2 mA
IOZ
Power Down Output Current
Power down
CIO
Input/Output Capacitance
Typical
2.8
Rx and Tx Powerdown
25
2.4
V
−100
0.4
V
+100
µA
pF
POWER CONSUMPTION (Powerdown)
PPDN
Powerdown Mode
40
mW
RECOMMENDED REFCLK INPUT SPECIFICATIONS
VIDSREFCLK
Differential input voltage
± 100
VICM
Common mode voltage
fREF
REFCLK frequency
OPMODE = 0 (BTS SerDes Mode)
dfREF
REFCLK frequency variation
Variation from nominal frequency
tREF-DC
REFCLK duty cycle
Between 50% of the differential
voltage across REFCLKP and
REFCLKN
tREF-X
REFCLK transition time
Transition time between 20% and
80% of the differential voltage
across REFCLKP and REFCLKN
mVP-P
0.05V
2.4V
V
31.5
MHz
−100
100
ppm
45
55
%
30
30.72
300
pS
SYSCLK DC OUTPUT SPECIFICATIONS
RL = 100Ω
VOD
Differential Output Voltage
VOS
Offset Voltage
IOS
Output Short Circuit Current
Output pair shorted together and
tied to GND
IOZ
Power Down Output Current
Power down
± 250
± 330
± 450
mV
1.125
1.20
1.375
V
35
mA
+30
µA
−30
TRANSMITTER SERIAL TIMING SPECIFICATIONS
VOD
Output differential voltage swing
PE[1]=0, PE[0]=0
± 550
± 700
± 800
mVp-p
PE[1]=0, PE[0]=1
± 630
mVp-p
PE[1]=1, PE[0]=0
± 500
mVp-p
PE[1]=1, PE[0]=1
RDO
Output differential resistance
RO
Output Return Loss
Frequency = 1.229 GHz
tR, tF
Serial data output transition time
(Notes 10, 14)
Measured between 20% and 80%
JITT-DJ
± 200
± 360
± 450
80
100
120
-13.4
ps
Serial data output deterministic jitter Output CJPAT with BER of 10−12
(Notes 3, 10)
(Note 4)
0.14
UIp-p
JITT-TJ
Serial data output total jitter (Notes Output CJPAT pattern with BER of
3, 10)
10−12 (Note 4)
0.279
UIp-p
tLAT-T
Transmit latency (Note 7)
Maximum lock time
100
Ω
dB
130
tDO-LOCK
80
mVp-p
614.4 Mbps
310
1.228 Gbps
155
K28.5 pattern at 1228.8 Mbps
110
ns
130
us
± 1100
mVp-p
120
Ω
RECEIVER SERIAL TIMING SPECIFICATIONS
VID
Input voltage
VCMR
Receiver common mode voltage
RR
Differential Input Terminations
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RINP - RINN
± 100
0.9
80
8
100
V
Parameter
Condition
Min
Typ
(Note 2)
Max
Units
-15
dB
RLRI
Input Return Loss (Note 10)
Frequency = 1.229 GHz
-20
tLAT-R
Receive latency (Note 8)
614.4 Mbps
280
ns
1.228 Gbps
140
ns
10−12
JITR-TOL
Total input jitter tolerance (Note 10) Input CJPAT with BER of
(Note 4)
FR-LOCK
Receiver lock range
Input data rate reference to local
transmit data rate.
tR-LOCK
Maximum lock time
K28.5 pattern at 1228.8 Mbps
−200
0.66
UIp-p
+200
ppm
1
ms
TRANSMITTER INPUT TIMING SPECIFICATIONS
tS-T
Setup Time
DIN [9:0] valid to TXCLK rising or
falling edge
0.5
ns
tH-T
Hold Time
TXCLK rising or falling edge to DIN
[9:0] valid
0.5
ns
tDC
Duty cycle
TXCLK duty cycle
45
55
%
fTXCLK
TXCLK frequency
30
62.5
MHz
6
ns
RECEIVER OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1)
tPDRX
RXCLK Propagation Delay
RXCLK rising or falling edge to
ROUT [9:0] valid
2
4
tDC
Duty cycle
RXCLK input duty cycle
45
55
%
fRXCLKR
RXCLK input frequency
RXCLK input frequency
30
62.5
MHz
tR, tF
Output data transition time
For ROUT [0-9], LOCK, etc. pins.
Measured between 20% and 80%
levels
0.35
ns
RECEIVER OUTPUT TIMING SPECIFICATIONS (Write Mode RXCLKMODE=0)
tS-R
Setup Time
ROUT [9:0] valid to RXCLK rising or
falling edge (Note 9)
2.2
ns
tH-R
Hold Time
RXCLK rising or falling edge to
ROUT [9:0] valid (Note 9)
2.4
ns
tDC
Duty cycle
RXCLK duty cycle
45
fRXCLK
RXCLK frequency
tR, tF
Output data transition time
30
For ROUT [0-9], LOCK, etc. pins.
Measured between 20% and 80%
levels
55
%
62.5
MHz
0.35
ns
CDET OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1)
tPDCD
CDET Propagation Delay
RXCLK rising or falling edge to
CDET
2
4
6
ns
CDET OUTPUT TIMING SPECIFICATIONS (Write Mode RXCLKMODE=0) (Note 5)
tS-C
Setup Time
CDET valid to RXCLK rising or
falling edge
2.6
ns
tH-C
Hold Time
RXCLK rising or falling edge to
CDET valid
2.6
ns
SYSCLK LVDS OUTPUT TIMING SPECIFICATIONS
tSYSCLKNDC
Duty cycle
JITSYSCLK
Cycle to cycle jitter
(Note 10)
40
tR, tF
Output transition time
Between 20% and 80% levels (Note
10)
60
%
65
ps p-p
0.1
0.3
ns
0
2.5
MHz
40
MDC/MDIO TIMING SPECIFICATIONS (Clause 45)
fMDC
MDC Frequency
tS-MDIO
Setup Time
MDIO (input) valid to MDC rising
clock
9
10
ns
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SCAN12100
Symbol
SCAN12100
Symbol
Parameter
Condition
Min
tH-MDIO
Hold Time
MDC rising edge to MDIO (input)
invalid
10
tD-MDIO
Delay Time
MDIO (output) delay from MDC
rising edge
0
tX-MDIO
Transition Time
Measured at MDIO when used as
output, CL = 470 pF
Typ
(Note 2)
Max
Units
ns
300
ns
1
ns
MINIMUM PULSE WIDTH, Hardware Reset (Note 11)
tTX-RST
Transmiter Reset
TXPWDNB = 0
1
us
tRX-RST
Receiver Reset
RXPWDNB = 0
1
us
tRST
SerDes Reset
RESETB = 0
1
us
JTAG TIMING SPECIFICATIONS
RL= 1000Ω, CL = 15 pF
fJTAG
JTAG TCK Frequency
25
MHz
tR-J
tF-J
TDO data transition time (20% to
80%)
tS-TDI
Setup Time TDI to TCK High or Low
2
ns
tH-TDI
Hold Time TDI to TCK High or Low
2
ns
tS-TMS
Setup Time TMS to TCK High or
Low
2
ns
tH-TMS
Hold Time TMS to TCK High or Low
2
ns
tW-TCK
TCK Pulse Width
10
ns
tW-TRST
TRSTB Pulse Width
2.5
ns
tREC
Recovery Time TRSTB to TCK
14
ns
2
ns
DELAY CALIBRATION MEASUREMENT (DCM) (Notes 10, 12, 13)
T14
T14 Delay Accuracy
Toffset
Toffset Delay Accuracy
Tser
Tdes
Receive and Transmit PLLs locked
to valid hyperframe data.
± 800
ps
± 800
ps
Serializer Delay Accuracy
± 1200
ps
Deserializer Delay Accuracy
± 1200
ps
Tin-out
Tin-out Delay Accuracy
± 1200
ps
Tout-in
Tout-in Delay Accuracy
± 1200
ps
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Typical parameters are measured at nominal supply levels and TA = 25°C. They are for reference purposes and are not production-tested.
Note 3: Transmit Jitter testing methodology is defined in Appendix 48B of IEEE 802.2ae-2002. The SCAN12100 transmit output jitter is constant for all valid CPRI
datarates. The transmit jitter is significantly less than the specified limits in terms of UI.
Note 4: CJPAT is a stress pattern defined in IEEE 802.2ae-2002 Appendix 48A
Note 5: CDET nominal valid duration is determined by the CPRI data rate. CDET timing is similar to the ROUT[0:9] timing.
Note 6: Transmit or Receive K28.5 pattern. Assumes TXCLK is stable and toggles only after all SerDes clocks become synchronous.
Note 7: Transmit latency is fixed once the link is established and is guaranteed by the Tser specification.
Note 8: Receive latency is fixed once the link is established and is guaranteed by the Tdes specification.
Note 9: Receiver output timing specifications for TS-R and TH-R are tested at the CPRI rate of 1.2288 Gbps.
Note 10: Limits are guaranteed by design and characterization over process, supply voltage, and temperature variations.
Note 11: Limits are guaranteed by design.
Note 12: Serial side DCM readings are referenced to the first bit of the K28.5 pattern {110000 0101 001111 1010}. Parallel side DCM readings are referenced
to the TXCLK or RXCLK edge (not the data edge) that registers the K character as an input or output.
Note 13: DCM readings are valid when the RXCLK pin on the SCAN12100 is used as an output in "WRITE" mode (RXCLKMODE = 0) and IOVDD = 3.3V.
Note 14: Edge rate characterization includes the loading effects of 1.0 uF AC-coupling capacitors and 4 inches of 100 ohm differential microstrip.
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10
SCAN12100
AC Timing Diagrams
READ MODE
20209509
WRITE MODE
20209510
11
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SCAN12100
The type of registers used in SCAN12100 are RW, RC, RO,
and WC. RW is a read and write register. RC is a read and
clear register. Upon reading the value of the RC register
through MDIO, the register will reset its value. WC is a write
and clear register. Write and clear registers are used for reset
operations. A re-read of the WC register is necessary to verify
the register has been cleared.
Register Description
The SCAN12100 implements the device ID of 61 (0x3D.)
Other registers defined by 802.3ae-2002 are not implemented in SCAN12100. The SCAN12100 has a rich MDIO register
set to allow the chip to be controlled and monitored through
software. Certain functions such as BIST and delay calibration are only accessible through MDIO.
Address
Name
Access
Description
(hex)
0
RESERVED
RW
Reserved.
1
POWERDOWN
RW
Transmiter and Receiver POWERDOWN control.
2
OUI
RO
OUI.
3
OUI Revision
RO
OUI, Device Product and Revision information.
4
RESET
RC
Transmiter and Receiver RESET control.
5
Rx Equalization
RW
CPRI LOF (Loss of Frame) bypass and Receiver EQ control.
6
Tx De-Emphasis
RW
Hyperframe size and Transmitter De-Emphasis control.
7
LOOPBACK
RW
Selects Normal, Line and Local Loopback.
8
MDIO
RO
Required by MDIO.
9
BIST
RW
Pattern and Enable control for Trasmit and Receive BIST.
A
Speed Mode
RW/Pin OW Selects CPRI speed mode.
B
BIST Status
RC
BIST status information.
C
RESERVED
RO
Reserved.
D
DCM Start
RC
Initiates or restarts Delay Calibration Measurement.
E
OUI Duplicate
RO
Duplicate of Register Address 2.
F
OUI Rev. Duplicate
RO
Duplicate of Register Address 3.
10
LOF
RC
CPRI Loss of Frame (LOF) counter.
11
LOS
RC
CPRI Loss of Sync (LOS) counter.
12
Rx Lock
RC
Receiver Loss of Lock (LOCKB) counter.
13
Loss of Clock
RO
Loss of Transmit and/or Receive clock.
14
PLL Status
RO
Tx and Rx PLL status.
15
Hyperframe Length
RW
Programmable Hyperframe Length control.
DCM Trigger
RW
Delay Calibration Trigger pattern.
18
Reserved
RW
Reserved.
19
16-17
Hyperframe Tuning
RW
Programmable Hyperframe size and DCM enable
1A-1D
Reserved
RO
Reserved.
1E
T14 Lower
RO
T14 Measurement.
1F
T14 Upper
RO
T14 Measurement.
20
Toffset Lower
RO
Toffset Measurement.
21
Toffset Upper
RO
Toffset Measurement.
22
Tser Lower
RO
Tser Measurement.
23
Tser Upper
RO
Tser Measurement.
24
Tdes Lower
RO
Tdes Measurement.
25
Tdes Upper
RO
Tdes Measurement.
26
Tin-out Lower
RO
Tin-out Measurement.
27
Tin-out Upper
RO
Tin-out Measurement.
28
Tout-in Lower
RO
Tout-in Measurement.
29
Tout-in Upper
RO
Tout-in Measurement.
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12
SCAN12100
Physical Dimensions inches (millimeters) unless otherwise noted
100-Pin TQFP with Exposed Ground Pad (Top View)
Order Number SCAN12100TYA
NS Package Number VXF100B
See www.national.com/quality/marking_conventions.html for additional part marking information
13
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SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes
Notes
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