SEMTECH Today's Results ...Tomorrow's Vision Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver SK100EP111 Preliminary Information October 4, 1999 This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver Features 32 Lead LQFP Package Logic Symbol 10 CLK0 Description 0 CLK0* Q0:9 CLK1 CLK1* The SK100EP111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the EP111 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the EP111’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. Q4* Q5 23 22 21 20 19 18 Q6* Q4 24 Q6 Q3* Q5* Q3 Pinout 17 VCC0 25 16 VCC0 Q2* 26 15 Q7 Q2 27 14 Q7* Q1* 28 13 Q8 Q1 29 12 Q8* Q0* 30 11 Q9 Q0 31 10 Q9* VCC0 32 SK100EP111 4 CLK0* 5 6 7 8 VEE 3 CLK1* 2 CLK0 9 1 VCC The SK100EP111 is specifically designed, modeled, and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and characterization is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. In most applications, all ten differential pairs will be used and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10–20 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. VBB CLK_SEL CLK_SEL The SK100EP111 is a low skew 1-to-10 diffferential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended if the VBB output is used. HSTL inputs can be used when the EP111 is operating under PECL conditions. The selected signal is fanned out to 10 identical differential outputs. Q0*:9* 1 CLK1 100 ps Part-to-Part Skew 35 ps Output-to-Output Skew Differential Design VBB Output Low Voltage VEE Range of –2.375 to –3.8V for ECL Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL 75 KΩ Input Pulldown Resistors ECL/PECL Outputs VBB • • • • • • • • VCC0 Pin Names Pin Function CLK0, CLK0* CLK1, CKL1* Q0:9, Q0*:9* CLK_SEL VBB Differential ECL/PECL Input Pair Differential HSTL Input Pair Differential PECL Outputs Active Clock Select Input VBB Output Function CLK_SEL Active Input 0 1 CLK0, CLK0* CLK1, CLK1* Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver SEMTECH Today's Results ...Tomorrow's Vision SK100EP111 ECL DC Characteristics -40oC Symbol Characteristic VOH 0oC 25oC Min Typ Max Min Typ Max Min Output HIGH Voltage -1.140 -1.005 -0.880 -1.080 -0.955 -0.880 VOL Output LOW Voltage -1.830 -1.695 -1.555 -1.810 -1.705 VIH Input HIGH Voltage -1.165 VIL Input LOW Voltage -1.810 VBB Output Reference Voltage VEE Power Supply Voltage IIH Input High Current Max Min Typ Max Unit -1.080 -0.880 -1.080 -0.955 -0.880 V -1.620 -1.810 -1.620 -1.810 -1.705 -1.620 V -1.165 -0.880 -1.165 -0.880 -1.165 -0.880 V -1.475 -1.810 -1.475 -1.810 -1.475 -1.810 -1.475 V -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 V -2.375 -3.8 -2.375 -3.8 -2.375 -3.8 -2.375 -3.8 V 150 µA IEE Power Supply Current VEE = -2.375 to -3.8V 117 mA VCMR Common Mode Range VCC 0.3 V VPP Minimum Input Swing 150 80 VEE + 1.7 150 10 8 VCC 0.3 500 Typ 85oC 80 VEE + 1.7 150 108 VCC 0.3 500 80 VEE + 1.7 108 VCC 0.3 500 80 VEE + 1.7 500 mV HSTL DC Characteristics -40oC Symbol Characteristic Min VCMR Common Mode Range VEE + 0.9 VPP Minimum Input Swing 500 Typ 0oC Max Min VCC 1.1 VEE + 0.9 500 Typ 25oC Max Min VCC 1.1 VEE + 0.9 500 Typ 85oC Max Min VCC 1.1 VEE + 0.9 500 Typ Max Unit VCC 1.1 V mV Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver SEMTECH Today's Results ...Tomorrow's Vision SK100EP111 PECL DC Characteristics -40oC Symbol Characteristic VOH 0oC Min Typ Max Min Output HIGH Voltage (Note 1) 2.160 2.295 2.420 VOL Output LOW Voltage (Note 1) 1.470 VIH Input HIGH Voltage (Note 1) VIL Input LOW Voltage (Note 1) VBB Output Reference Voltage (Note 1) VEE Power Supply Voltage IIH Input HIGH Current I EE Power Supply Current VCC = +2.375 to +3.8V VCMR Common Mode Range VPP Minimum Input Swing 25oC Typ Max Min 2.220 2.420 1.750 1.490 2.135 2.420 1.490 Max Min Typ Max Unit 2.220 2.420 2.220 2.345 2.420 V 1.680 1.490 1.680 1.490 1.595 1.680 V 2.135 2.420 2.135 2.420 2.135 2.420 V 1.825 1.490 1.825 1.490 1.825 1.490 1.825 V 1.92 2.04 1.92 2.04 1.92 2.04 1.92 2.04 V 2.375 3.8 2.375 3.8 2.375 3.8 2.375 3.8 V 150 µA 117 mA VCC 0.3 V 150 60 VEE + 1.7 150 70 VCC 0.3 500 Typ 85oC 70 150 80 VEE + 1.7 70 VCC 0.3 VEE + 1.7 500 80 VCC 0.3 500 80 VEE + 1.7 500 mV Note 1: These values are for VCC = 3.3V. Level Specifications will vary 1:1 withVCC. AC Characteristics (VEE = –2.375V to –3.8V; VCC = VCC0 = GND) -40oC 0oC 25oC 85oC Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit tPLH ECL/PECL Prop Delay to Output 310 390 380 440 450 480 350 410 415 460 475 500 375 430 445 480 510 520 480 460 575 550 680 550 ps ps tPHL HSTL Prop Delay to Output 340 580 415 610 485 630 380 620 450 650 510 670 410 640 480 670 545 700 520 670 615 700 720 730 ps ps Within-Device Skew 15 30 15 30 15 30 15 30 ps Part-to-Part Skew 100 145 100 130 100 135 100 150 ps fmax Max Input Frequency 1500 tr , tf Output Rise/Fall Time tskew 200 1500 600 200 1500 600 200 1500 600 200 MHz 600 ps Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver SEMTECH Today's Results ...Tomorrow's Vision SK100EP111 Package Information NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 2. Controlling Dimension: Millimeter 3. Datum Plane –AB– is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. Datums –T–, –U–, and –Z– to be determined at Datum Plane –AB–. 5. Dimensions S and V to be determined at Seating Plane –AC–. 6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 (0.010) per side. Dimensions A and B do not include mold mismatch and are determined at Datum Plane –AB–. 7. Dimension D does not include Dambar protrusion. Dambar protrusion shall not cause the D dimension to exceed 0.520 (0.020). 8. Minimum solder plate thickness shall be 0.0075 (0.0003). 9. Exact shape of each corner may vary from depiction. 4X A, B 0.20 (0.008) A1, B1 32 AB T–U Z 25 1 24 –T, U, Z – S, V 8 17 9 S1,V1 16 SEE DETAIL "Y" SEE DETAIL "AD" G –AB– –AC– 0.10 (0.004) AC MILLIMETERS 8x M C ˚ DIM MIN MAX INCHES MIN MAX R E A 7.000 BSC 0.276 BSC A1 3.500 BSC 0.138 BSC B 7.000 BSC 0.276 BSC B1 W H K Q ˚ 0.250 (0.010) GAUGE PLANE X DETAIL AD ,,,,,, ,,,,,, Base Metal N –T–, –Ü–, –Z– D F AE P 3.500 BSC 0.138 BSC C 1.400 1.600 0.055 D 0.300 0.450 0.012 0.018 E 1.350 1.450 0.053 0.057 F 0.300 0.400 0.012 0.016 G 0.800 BSC 0.063 0.031 BSC H 0.050 0.150 0.002 0.006 J 0.090 0.200 0.004 0.008 K 0.500 0.700 0.020 0.028 M N 12o REF 0.090 0.160 12o REF 0.004 0.006 P 0.400 BSC 0.016 BSC Q 1o 5o 1o 5o R 0.150 0.250 0.006 0.010 S 9.000 BSC 0.354 BSC S1 4.500 BSC 0.177 BSC V 9.000 BSC 0.354 BSC V1 4.500 BSC 0.177 BSC W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF N AE DETAIL Y 0.20 (0.008) M AC T–U Z SECTION AE