SEMICONDUCTOR TECHNICAL DATA ÷÷ The MC100LVE222 is a low voltage, low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE222 can be used as a simple fanout buffer or outputs can be configured to provide half frequency outputs. The combination of 1x and 1/2x frequencies is flexible providing for a myriad of combinations. All timing differences between the 1x and 1/2x signals are compensated for internal to the chip so that the output–to–output skew is identical regardless of what output frequencies are selected. • • • • • • • LOW VOLTAGE 1:15 DIFFERENTIAL ÷1/÷2 ECL/PECL CLOCK DRIVER Fifteen Differential Outputs 200ps Part–to–Part Skew 50ps Output–to–Output Skew Selectable 1x or 1/2x Frequency Outputs Extended Power Supply Range of –3.0V to –5.25V (+3.0V to +5.25V) 52–Lead TQFP Packaging ESD > 2000V FA SUFFIX The fsel and CLK_Sel input pins are asynchronous control signals. As TQFP PACKAGE a result, changing these inputs could cause indeterminent excursions on CASE 848D–03 the outputs immediately following the changes on the inputs. For applications which require a single–ended input, the VBB reference voltage is supplied. For single–ended input applications the VBB reference should be connected to the CLK input and bypassed to ground via a 0.01µf capacitor. The input signal is then driven into the CLK input. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. In most applications all fifteen differential pairs will be used and therefore terminated. In the case where fewer than fifteen pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10–20ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The MC100LVE222, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE222 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE222’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC–2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note AN1406/D. The MC100LVE222 is packaged in the 52–lead TQFP package. For a 3.3V supply this package provides the optimum performance and minimizes board space requirements. The LVE222 will operate from a standard 100E –4.5V supply or a 5.0V PECL supply. The 52–lead TQFP utilizes a 10x10mm body with a lead pitch of 0.65mm. 10/96 Motorola, Inc. 1996 4–1 REV 1 MC100LVE222 VCCO Qc0 Qc0 Qc1 Qc1 Qc2 Qc2 Qc3 Qc3 VCCO NC NC VCCO Pinout: 52–Lead TQFP (Top View) 39 38 37 36 35 34 33 32 31 30 29 28 27 VCCO 40 26 Qd0 Qb2 41 25 Qd0 Qb2 42 24 Qd1 Qb1 43 23 Qd1 Qb1 44 22 Qd2 Qb0 45 21 Qd2 Qb0 46 20 Qd3 VCCO 47 19 Qd3 Qa1 48 18 Qd4 Qa1 49 17 Qd4 Qa0 50 16 Qd5 Qa0 51 15 Qd5 VCCO 52 14 VCCO 7 8 fselb CLK0 CLK0 CLK_Sel CLK1 9 10 11 12 13 VEE 6 fseld 5 fselc 4 VBB 3 CLK1 2 fsela VCC 1 MR MC100LVE222 LOGIC SYMBOL MR CLK0 CLK0 CLK1 CLK1 ÷1 2 Qa0:1 Qa0:1 ÷2 CLK_Sel VBB fsela FUNCTION TABLE 3 Qb0:2 Qb0:2 fselb 4 Qc0:3 Qc0:3 6 Qd0:5 Qd0:5 Function Input 0 1 MR CLK_Sel fseln Active CLK0 ÷1 Reset CLK1 ÷2 fselc fseld MOTOROLA 4–2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVE222 ECL DC CHARACTERISTICS –40°C Symbol Characteristic 0°C 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage –1.085 –1.005 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 V VOL Output LOW Voltage –1.830 –1.695 –1.555 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 V VIH Input HIGH Voltage –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 V VIL Input LOW Voltage –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 V VBB Output Reference Voltage –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V VEE Power Supply Voltage –3.0 –5.25 –3.0 –5.25 –3.0 –5.25 –3.0 –5.25 V IIH Input HIGH Current 150 µA IIL Input CLK0, CLK1 LOW Current Others IEE Power Supply Current 150 –300 0.5 150 –300 0.5 122 136 150 –300 0.5 122 136 µA –300 0.5 122 136 125 139 mA PECL DC CHARACTERISTICS –40°C Symbol Characteristic 0°C 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage1. 2.215 2.295 2.420 2.275 2.345 2.420 2.275 2.345 2.420 2.275 2.345 2.420 V VOL Output LOW Voltage1. 1.470 1.605 1.745 1.490 1.595 1.680 1.490 1.595 1.680 1.490 1.595 1.680 V Input HIGH Voltage1. 2.135 2.420 2.135 2.420 2.135 2.420 2.135 2.420 V VIL Input LOW Voltage1. 1.490 1.825 1.490 1.825 1.490 1.825 1.490 1.825 V VBB Output Reference Voltage1. 1.92 2.04 1.92 2.04 1.92 2.04 1.92 2.04 V VCC Power Supply Voltage 3.0 5.25 3.0 5.25 3.0 5.25 3.0 5.25 V IIH Input HIGH Current 150 µA IIL Input CLK0, CLK1 LOW Current Others IEE Power Supply Current VIH 150 –300 0.5 150 –300 0.5 122 136 150 –300 0.5 122 136 µA –300 0.5 122 136 125 139 mA 1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC. ECLinPS and ECLinPS Lite DL140 — Rev 3 4–3 MOTOROLA MC100LVE222 ECL AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND) –40°C Symbol 0°C 25°C 70°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max tPLH tPHL Propagation Delay to Output IN (differential) IN (single–ended) MR 1040 990 1100 1140 1140 1250 1240 1290 1400 1060 1010 1130 1160 1160 1280 1260 1310 1430 1080 1030 1170 1180 1180 1320 1280 1330 1470 1120 1070 1220 1220 1220 1370 1320 1370 1520 tskew Within–Device Skew Part–to–Part Skew (Diff) VPP Minimum Input Swing VCMR Common Mode Range VPP < 500mV VPP ≥ 500mV tr/tf Output Rise/Fall Time Unit Condition ps 50 200 400 50 200 400 50 200 400 50 200 400 VEE +1.3 –0.4 VEE +1.2 –0.4 VEE +1.2 –0.4 VEE +1.2 –0.4 VEE +1.6 –0.4 VEE +1.5 –0.4 VEE +1.5 –0.4 VEE +1.5 –0.4 200 600 200 600 200 600 200 600 Note 1. Note 2. ps Note 3. mV Note 4. V Note 5. ps 20%–80% 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). PECL AC CHARACTERISTICS (VEE = GND; VCC = VCCO = VCC (min) to VCC (max)) –40°C Symbol 0°C 25°C 70°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max tPLH tPHL Propagation Delay to Output IN (differential) IN (single–ended) MR 1040 990 1100 1140 1140 1250 1240 1290 1400 1060 1010 1130 1160 1160 1280 1260 1310 1430 1080 1030 1170 1180 1180 1320 1280 1330 1470 1120 1070 1220 1220 1220 1370 1320 1370 1520 tskew Within–Device Skew Part–to–Part Skew (Diff) VPP Minimum Input Swing VCMR Common Mode Range VPP < 500mV 1.3 VCC –0.4 1.2 VCC –0.4 1.2 VCC –0.4 1.2 VCC –0.4 VPP ≥ 500mV 1.6 VCC –0.4 1.5 VCC –0.4 1.5 VCC –0.4 1.5 VCC –0.4 200 600 200 600 200 600 200 600 tr/tf Output Rise/Fall Time Unit Condition ps 50 200 400 50 200 400 50 200 400 50 200 400 Note 1. Note 2. ps Note 3. mV Note 4. V Note 5. ps 20%–80% 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D). 3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). MOTOROLA 4–4 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVE222 OUTLINE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 848D–03 ISSUE C –X– X=L, M, N 4X 4X TIPS 0.20 (0.008) H L–M N 0.20 (0.008) T L–M N CL AB 52 G 40 1 AB 39 3X VIEW VIEW Y Y –L– –M– B B1 13 V A S θ2 0.10 (0.004) T –H– –T– SEATING PLANE 4X θ3 VIEW AA 0.05 (0.002) S W θ1 2XR R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA ECLinPS and ECLinPS Lite DL140 — Rev 3 D T L–M S N S SECTION AB–AB S1 4X M U ROTATED 90_ CLOCKWISE –N– C ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ 0.13 (0.005) 26 A1 BASE METAL F J V1 27 14 PLATING 4–5 NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC ––– 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC ––– 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ MOTOROLA MC100LVE222 Motorola reserves the right to make changes without further notice to any products herein. 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