SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
2
D −55°C to 125°C Operating Temperature
D
D
D
D
D
D
D
D
D
D
D
Range, QML Processing
Processed to MIL-PRF-38535 (QML)
Performance
− SMJ320C30-40 (50-ns Cycle)
40 MFLOPS
20 MIPS
− SMJ320C30-50 (40-ns Cycle)
50 MFLOPS
25 MIPS
Two 1K-Word × 32-Bit Single-Cycle
Dual-Access On-Chip RAM Blocks
Validated Ada Compiler
64-Word × 32-Bit Instruction Cache
32-Bit Instruction and Data Words,
24-Bit Addresses
40 / 32-Bit Floating-Point / Integer Multiplier
and Arithmetic Logic Unit (ALU)
Parallel ALU and Multiplier Execution in a
Single Cycle
On-Chip Direct Memory Access (DMA)
Controller for Concurrent I/O and CPU
Operation
Integer, Floating-Point, and Logical
Operations
One 4K-Word × 32-Bit Single-Cycle
Dual-Access On-Chip ROM Block
description
D Two 32-Bit External Ports
D
D
D
D
D
D
D
D
D
D
D
D
D
(24- and 13-Bit Address)
Two Serial Ports With Support for
8- / 16- / 24- / 32-Bit Transfers
Packaging
− 181-Pin Grid Array Ceramic Package
(GB Suffix)
− 196-Pin Ceramic Quad Flatpack With
Nonconductive Tie-Bar (HFG Suffix)
SMD Approval for 40- and 50-MHz Versions
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Zero-Overhead Loops With Single-Cycle
Branches
Interlocked Instructions for
Multiprocessing Support
32-Bit Barrel Shifter
Eight Extended-Precision Registers
(Accumulators)
Two- and Three-Operand Instructions
Conditional Calls and Returns
Block Repeat Capability
Fabricated Using Enhanced Performance
Implanted CMOS (EPICt) by Texas
Instruments
Two 32-Bit Timers
The SMJ320C30 internal busing and special digital signal processor (DSP) instruction set has the speed and
flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions
in hardware that other processors implement through software or microcode. This hardware-intensive approach
provides performance previously unavailable on a single chip. The emphasis on total system cost has resulted
in a less expensive processor that can be designed into systems currently using costly bit-slice processors.
D SMJ320C30-40: 50-ns single-cycle execution time, 5% supply
D SMJ320C30-50: 40-ns single-cycle execution time, 5% supply
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 2004, Texas Instruments Incorporated
!"# $%
$ ! ! & ' $$ ()% $ !* $ #) #$
* ## !%
POST OFFICE BOX 1443
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# &( $% ## & !$/ !$
!* $ #) #$ * ## !%
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1
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
description (continued)
196-Pin HFG Quad Flatpack
( TOP VIEW )
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
1
147
DVDD DVSS
ÉÉ
ÉÉ
VDD
DVSS
DVDD
99
ÉÉ
ÉÉ
98
49
50
ÉÉÉ
ÉÉÉ
VDD
VSS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ÉÉ
ÉÉ
ÉÉ
148
A B C D E F G H J K L M N P R
196
181-Pin GB Grid Array Package
( BOTTOM VIEW )
ÉÉ
ÉÉ
ÉÉ
ÉÉ
The SMJ320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I/ O, and a short machine-cycle time.
High performance and ease of use are results of these features.
General-purpose applications are enhanced by the large address space, multiprocessor interface, internally
and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple
interrupt structure. The SMJ320C30 supports a wide variety of system applications from host processor to
dedicated coprocessor.
High-level language support is implemented easily through a register-based architecture, large address space,
powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.
For additional information when designing for cold temperature operation, please see Texas Instruments
application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature
number SGUA001.
2
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
functional block diagram
RAM
Block 0
(1K × 32)
Cache
(64 × 32)
32
24
24
ÉÉÉ
ÉÉÉ
ÉÉÉ
RAM
Block 1
(1K × 32)
32
24
ROM
Block
(4K × 32)
32
24
32
PDATA Bus
PADDR Bus
XRDY
MSTRB
IOSTRB
XR / W
XD31−XD0
XA12 −XA0
ÉÉÉ
MUX
DDATA Bus
MUX
RDY
HOLD
HOLDA
STRB
R/W
D31− D0
A23 − A0
DADDR1 Bus
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
32
24
32
24
24
32
24
DMA Controller
Serial Port 0
Serial-Port-Control
Register
Global-Control
Register
MUX
DestinationAddress
Register
REG1
TransferCounter
Register
REG2
REG1
CPU1
REG2
32
32
40
40
32-Bit
Barrel
Shifter
Multiplier
ALU
40
40
40
32
40
ExtendedPrecision
Registers
(R7−R0)
Peripheral Address Bus
CPU1
CPU2
Controller
RESET
INT(3 − 0)
IACK
MC / MP
XF(1,0)
VDD
IODVDD
ADVDD
PDVDD
DDVDD
MDVDD
VSS
DVSS
CVSS
IVSS
VBBP
VSUBS
X1
X2 / CLKIN
H1
H3
EMU(6 − 0)
RSV(10 − 0)
Receive/Transmit
(R/X) Timer Register
Source-Address
Register
Peripheral Data Bus
IR
PC
Data-Transmit
Register
Data-Receive
Register
Serial Port 1
Serial-Port-Control
Register
Receive/Transmit
(R/X) Timer Register
ÉÉÉÉ
Data-Transmit
Register
40
40
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
FSX1
DX1
CLKX1
FSR1
DR1
CLKR1
Data-Receive
Register
Timer 0
Global-Control
Register
DISP0, IR0, IR1
ARAU0
BK
ARAU1
24
24
24
32
32
Auxiliary
Registers
(AR0 − AR7)
Timer 1
32
Global-Control
Register
32
32
TCLK0
Timer-Counter
Register
24
32
Other
Registers
(12)
Timer-Period
Register
Timer-Period
Register
TCLK1
Timer-Counter
Register
Port Control
Primary-Control
Register
Expansion-Control
Register
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3
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory map
Figure 1 shows the memory map for the SMJ320C30. See the TMS320C3x User’s Guide (literature number
SPRU031) for a detailed description of this memory mapping. Figure 2 shows the reset, interrupt, and trap
vector/branches memory-map locations. Figure 3 shows the peripheral bus memory-mapped registers.
0h
03Fh
040h
0h
Reset, Interrupt, Trap
Vectors, and Reserved
Locations (64) (External
STRB Active)
0BFh
0C0h
ROM
(Internal)
0FFFh
1000h
External
STRB Active
(8M Words − 64 Words)
7FFFFFh
800000h
801FFFh
802000h
Reset, Interrupt,
Trap Vectors, and Reserved
Locations (192)
External
STRB Active
(8M Words − 4K Words)
7FFFFFh
800000h
Expansion-Bus
MSTRB Active
(8K Words)
Expansion-Bus
MSTRB Active
(8K Words)
801FFFh
802000h
Reserved
(8K Words)
Reserved
(8K Words)
803FFFh
804000h
805FFFh
806000h
803FFFh
804000h
Expansion-Bus
IOSTRB Active
(8K Words)
Expansion-Bus
IOSTRB Active
(8K Words)
805FFFh
806000h
Reserved
(8K Words)
807FFFh
808000h
8097FFh
809800h
809BFFh
809C00h
809FFFh
80A000h
Reserved
(8K Words)
807FFFh
808000h
Peripheral-Bus
Memory-Mapped
Registers
(6K Words Internal)
Peripheral-Bus
Memory-Mapped
Registers
(6K Words Internal)
8097FFh
809800h
RAM Block 0
(1K Word Internal)
RAM Block 0
(1K Word Internal)
809BFFh
809C00h
RAM Block 1
(1K Word Internal)
RAM Block 1
(1K Word Internal)
809FFFh
80A000h
External
STRB Active
(8M Words − 40K Words)
External
STRB Active
(8M Words − 40K Words)
0FFFFFFh
0FFFFFFh
(a) Microprocessor Mode
(b) Microcomputer Mode
Figure 1. Memory Map
4
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory map (continued)
00h
Reset
00h
Reset
01h
INT0
01h
INT0
02h
INT1
02h
INT1
03h
INT2
03h
INT2
04h
INT3
04h
INT3
05h
XINT0
05h
XINT0
06h
RINT0
06h
RINT0
07h
XINT1
07h
XINT1
08h
RINT1
08h
RINT1
09h
TINT0
09h
TINT0
0Ah
TINT1
0Ah
TINT1
0Bh
DINT
0Bh
DINT
0Ch
0Ch
Reserved
1Fh
20h
Reserved
1Fh
20h
TRAP 0
TRAP 0
.
.
.
3Bh
3Ch
3Fh
.
.
.
3Bh
TRAP 27
TRAP 27
3Ch
Reserved
Reserved
BFh
(a) Microprocessor Mode
(a) Microcomputer Mode
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
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5
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory map (continued)
808000h
DMA Global Control
808004h
DMA Source Address
808006h
DMA Destination Address
808008h
DMA Transfer Counter
808020h
Timer 0 Global Control
808024h
Timer 0 Counter
808028h
Timer 0 Period
808030h
Timer 1 Global Control
808034h
Timer 1 Counter
808038h
Timer 1 Period Register
808040h
Serial Port 0 Global Control
808042h
FSX/DX/CLKX Serial Port 0 Control
808043h
FSR/DR/CLKR Serial Port 0 Control
808044h
Serial Port 0 R/X Timer Control
808045h
Serial Port 0 R/X Timer Counter
808046h
Serial Port 0 R/X Timer Period
808048h
Serial Port 0 Data Transmit
80804Ch
Serial Port 0 Data Receive
808050h
Serial Port 1 Global Control
808052h
FSX/DX/CLKX Serial Port 1 Control
808053h
FSR/DR/CLKR Serial Port 1 Control
808054h
Serial Port 1 R/X Timer Control
808055h
Serial Port 1 R/X Timer Counter
808056h
Serial Port 1 R/X Timer Period
808058h
Serial Port 1 Data Transmit
80805Ch
Serial Port 1 Data Receive
808060h
Expansion-Bus Control
808064h
Primary-Bus Control
†Shading denotes reserved address locations
Figure 3. Peripheral Bus Memory-Mapped Registers†
6
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
pin functions
This section gives signal descriptions for the SMJ320C30 devices in the microprocessor mode. The following
tables list each signal, the number of pins, type of operating mode(s) (that is, input, output, or high-impedance
state as indicated by I, O, or Z, respectively), and a brief function description. All pins labeled NC have special
functions and should not be connected by the user. A line over a signal name (for example, RESET) indicates
that the signal is active low (true at logic-0 level). The signals are grouped according to functions.
Pin Functions
PIN
NAME
QTY‡
TYPE†
DESCRIPTION
CONDITIONS
WHEN
SIGNAL IS Z TYPE§
PRIMARY BUS INTERFACE
D31 −D0
32
I/O/Z
32-bit data port of the primary bus interface
S
H
A23 −A0
24
O/Z
24-bit address port of the primary bus interface
S
H
R
R/W
1
O/Z
Read / write for primary bus interface. R / W is high when a read is performed and low
when a write is performed over the parallel interface.
S
H
R
STRB
1
O/Z
External access strobe for the primary bus interface
S
H
RDY
HOLD
HOLDA
1
1
1
I
Ready. RDY indicates that the external device is prepared for a primary bus interface
transaction to complete.
I
Hold for primary bus interface. When HOLD is a logic low, any ongoing transaction
is completed. A23 −A0, D31 −D0, STRB, and R / W are in the high-impedance state
and all transactions over the primary bus interface are held until HOLD becomes a
logic high or the NOHOLD bit of the primary bus control register is set.
O/Z
Hold acknowledge for primary bus interface. HOLDA is generated in response to a
logic low on HOLD. HOLDA indicates that A23 −A0, D31 −D0, STRB, and R / W are
in the high-impedance state and that all transactions over the bus are held. HOLDA
is high in response to a logic high of HOLD or when the NOHOLD bit of the primary
bus control register is set.
S
EXPANSION BUS INTERFACE
XD31 −XD0
32
I/O/Z
32-bit data port of the expansion bus interface
S
R
XA12 −XA0
13
O/Z
13-bit address port of the expansion bus interface
S
R
S
R
XR / W
1
O/Z
Read / write signal for expansion bus interface. When a read is performed, XR / W is
held high; when a write is performed, XR / W is low.
MSTRB
1
O/Z
External memory access strobe for the expansion bus interface
S
IOSTRB
1
O/Z
External I / O access strobe for the expansion bus interface
S
XRDY
1
I
Ready signal. XRDY indicates that the external device is prepared for an expansion
bus interface transaction to complete.
CONTROL SIGNALS
RESET
1
I
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vector.
INT3 −INT0
4
I
External interrupts
IACK
1
O/Z
MC / MP
1
I
XF1, XF0
2
I/O/Z
Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. IACK can
be used to indicate the beginning or end of an interrupt-service routine.
S
Microcomputer / microprocessor mode
External flags. XF1 and XF0 are used as general-purpose I / Os or to support
interlocked processor instructions.
S
R
† I = input, O = output, Z = high-impedance state, NC = no connect
‡ For GB package
§ S = SHZ active, H = HOLD active, R = RESET active
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
Pin Functions (Continued)
PIN
NAME
QTY‡
TYPE†
DESCRIPTION
CONDITIONS
WHEN
SIGNAL IS Z TYPE§
SERIAL PORT 0 SIGNALS
CLKX0
1
I/O/Z
Serial port 0 transmit clock. CLKX0 is the serial-shift clock for the serial port 0
transmitter.
S
R
DX0
1
I/O/Z
Data transmit output. Serial port 0 transmits serial data on DX0.
S
R
S
R
FSX0
1
I/O/Z
Frame synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data
process over DX0.
CLKR0
1
I/O/Z
Serial port 0 receive clock. CLKR0 is the serial-shift clock for the serial port 0 receiver.
S
R
DR0
1
I/O/Z
Data receive. Serial port 0 receives serial data on DR0.
S
R
I/O/Z
Frame synchronization pulse for receive. The FSR0 pulse initiates the receive-data
process over DR0.
S
R
S
R
FSR0
1
SERIAL PORT 1 SIGNALS
CLKX1
1
I/O/Z
Serial port 1 transmit clock. CLKX1 is the serial-shift clock for the serial port 1
transmitter.
DX1
1
I/O/Z
Data transmit output. Serial port 1 transmits serial data on DX1.
S
R
FSX1
1
I/O/Z
Frame synchronization pulse for transmit. The FSX1 pulse initiates the transmit-data
process over DX1.
S
R
CLKR1
1
I/O/Z
Serial port 1 receive clock. CLKR1 is the serial-shift clock for the serial port 1 receiver.
S
R
DR1
1
I/O/Z
Data receive. Serial port 1 receives serial data on DR1.
S
R
FSR1
1
I/O/Z
Frame synchronization pulse for receive. The FSR1 pulse initiates the receive-data
process over DR1.
S
R
I/O/Z
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an
output, TCLK0 outputs pulses generated by timer 0.
S
R
I/O/Z
Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an
output, TCLK1 outputs pulses generated by timer 1.
S
R
TIMER 0 SIGNALS
TCLK0
1
TIMER 1 SIGNALS
TCLK1
1
SUPPLY AND OSCILLATOR SIGNALS (see Note 1)
5-V supply¶
VDD
IODVDD
4
I
2
I
ADVDD
PDVDD
2
I
1
I
DDVDD
2
I
5-V supply¶
5-V supply¶
MDVDD
VSS
1
I
5-V supply¶
4
I
Ground
DVSS
4
I
Ground
5-V supply¶
5-V supply¶
CVSS
2
I
Ground
† I = input, O = output, Z = high-impedance state, NC = no connect
‡ For GB package
§ S = SHZ active, H = HOLD active, R = RESET active
¶ Recommended decoupling capacitor is 0.1 µF.
NOTE 1: CVSS, VSS, and IVSS are on the same plane.
8
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
Pin Functions (Continued)
PIN
NAME
QTY‡
TYPE†
DESCRIPTION
CONDITIONS
WHEN
SIGNAL IS Z TYPE§
SUPPLY AND OSCILLATOR SIGNALS (see Note 1) (CONTINUED)
IVSS
VBBP
1
I
1
NC
Ground
VSUBS
1
I
X1
1
O
Output from the internal oscillator for the crystal. If a crystal is not used, X1 must
be left unconnected.
X2 / CLKIN
1
I
Input to the internal oscillator from the crystal or a clock
H1
1
O/Z
External H1 clock. H1 has a period equal to twice CLKIN.
S
H3
1
O/Z
External H3 clock. H3 has a period equal to twice CLKIN.
S
VBB pump oscillator output
Substrate pin. Tie to ground
RESERVED (see Note 2)
EMU0 −EMU2
3
I
EMU3
1
O/Z
EMU4 / SHZ
1
I
EMU5, EMU6
2
NC
RSV0 −RSV4
5
I
RSV5 −RSV10
6
I/O
Reserved. Use pullup resistors to 5 V
Reserved
S
Shutdown high impedance. When active, EMU4 / SHZ shuts down the SMJ320C30
and places all pins in the high-impedance state. EMU4 / SHZ is used for board-level
testing to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ
corrupts SMJ320C30 memory and register contents. Reset the device with SHZ
high to restore it to a known operating condition.
Reserved
Reserved. Tie pins directly to 5 V
Reserved. Use pullups on each pin to 5 V
Locator
1
NC
Reserved
† I = input, O = output, Z = high-impedance state, NC = No Connect
‡ For GB package
§ S = SHZ active, H = HOLD active, R = RESET active
NOTES: 1. CVSS, VSS, IVSS are on the same plane.
2. The connections specified for the reserved pins must be followed. For best results, 18-kΩ −22-kΩ pullup resistors are
recommended. All 5-V supply pins must be connected to a common supply plane, and all ground pins must be connected to a
common ground plane.
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9
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
Pin Assignments
PIN
NUMBER
HFG
GB
PKG PKG
NAME
PIN
NUMBER
GB
HFG
PKG PKG
NAME
PIN
NUMBER
GB
HFG
PKG PKG
NAME
PIN
NUMBER
GB
HFG
PKG PKG
NAME
PIN
NUMBER
GB
HFG
PKG PKG
NAME
F15
82
A0
C5
139
D5
P2
195
DX1
L2
185
RSV6
R8
29
XD11
G12
81
A1
D6
138
D6
F14
83
EMU0
K4
186
RSV7
R9
30
XD12
G13
80
A2
A4
137
D7
E15
84
EMU1
M1
187
RSV8
P9
31
XD13
G14
79
A3
B5
136
D8
F13
85
EMU2
L3
188
RSV9
N9
32
XD14
G15
78
A4
C6
135
D9
E14
86
EMU3
M2
189
RSV10
R10
33
XD15
H15
77
A5
A5
134
D10
F12
87
EMU4 / SHZ
D12
100
ADVDD{
M9
34
XD16
P10
35
XD17
R11
36
XD18
N10
37
XD19
P11
38
XD20
R12
39
XD21
M10
40
XD22
N11
41
XD23
P12
42
XD24
R13
43
XD25
R14
44
XD26
M11
45
XD27
N12
46
XD28
P13
47
XD29
R15
48
XD30
P15
53
XD31
2
DVDD
101
DVDD
C3
50
DVSSW
C13
98
DVSSW
N3
148
DVSSW
N13
196
DVSSW
B14
96
IVSSw
97
IVSSw
G1
170
IACK
C11
109
D30
D11
105
XA2
126
H2
171
INT0
B12
108
D31
C12
104
XA3
149
H1
176
INT1
F3
161
HOLD
B13
103
XA4
150
J1
177
INT2
E2
160
HOLDA
A15
102
XA5
174
J2
178
INT3
D2
156
XRDY
B15
95
XA6
175
ADVDD{
DDVDD{
DDVDD{
IODVDD{
IODVDD{
IODVDD{
MDVDD{
MDVDD{
PDVDD{
CVSSw
CVSSw
VDD}
VDD}
VDD}
VDD}
VSSw
VSSw
VSSw
VSSw
VSSw
VSSw
VSSw
VSSw
VSSw
D15
88
MC / MP
D1
159
XR / W
C14
94
XA7
99
VSUBS
E3
157
MSTRB
P3
4
FSR0
E12
93
XA8
R4
12
XD0
E1
164
RDY
R2
7
FSX0
D13
92
XA9
P5
13
XD1
F1
167
RESET
N4
5
CLKR0
C15
91
XA10
N6
14
XD2
G4
166
R/ W
M5
6
CLKX0
D14
90
XA11
R5
17
XD3
F2
165
STRB
R1
3
DR0
E13
89
XA12
P6
18
XD4
F4
158
IOSTRB
R3
8
DX0
J3
179
RSV0
M7
19
XD5
C4
144
D0
M3
191
FSR1
J4
180
RSV1
R6
20
XD6
D5
143
D1
P1
194
FSX1
K1
181
RSV2
N7
21
XD7
A2
142
D2
L4
192
CLKR1
K2
182
RSV3
P7
22
XD8
A3
141
D3
N2
193
CLKX1
L1
183
RSV4
R7
23
XD9
B4
140
D4
N1
190
DR1
K3
184
RSV5
P8
24
XD10
H14
72
A6
B6
133
D11
C1
155
EMU5
H11
64
J15
71
A7
D7
132
D12
M6
11
EMU6
D4
114
J14
70
A8
A6
131
D13
B3
145
H1
E8
147
J13
69
A9
C7
130
D14
A1
146
H3
L8
15
K15
68
A10
B7
129
D15
C2
152
X1
M12
16
J12
67
A11
A7
128
D16
B1
151
X2 / CLKIN
K14
66
A12
A8
127
D17
P4
9
TCLK0
L15
65
A13
B8
122
D18
N5
10
TCLK1
K13
63
A14
A9
121
D19
G2
169
XF0
M4
1
L14
62
A15
B9
120
D20
G3
168
XF1
B2
51
M15
61
A16
C9
119
D21
D3
154
VBBP
P14
52
K12
60
A17
A10
118
D22
E4
153
VSUBS
25
L13
59
A18
D9
117
D23
H4
123
VDD}
26
M14
58
A19
B10
116
D24
D8
73
VDD}
172
N15
57
A20
A11
115
D25
M8
74
VDD}
173
C8
28
H3
75
H13
76
49
H5
162
163
M13
56
A21
C10
113
D26
H12
124
L12
55
A22
B11
112
D27
N8
27
VDD}
VSSw
N14
54
A23
A12
111
D28
A13
107
XA0
LOCATOR/NC
D10
110
D29
A14
106
XA1
125
E5
† ADVDD, DDVDD, IODVDD, MDVDD, and PDVDD are on a common plane internal to the device.
‡ VDD is on a common plane internal to the device.
§ VSS, CVSS, and IVSS are on a common plane internal to the device.
¶ DVSS is on a common plane internal to the device.
10
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Continuous power dissipation (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 W
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 3. All voltage values are with respect to VSS.
4. Actual operating power is less. This value was obtained under specially produced worst-case test conditions, which are not
sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both
primary and extension buses at the maximum rate possible. See normal (ICC) current specification in the electrical characteristics
table and also read Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020).
recommended operating conditions (see Note 5)
VDD
VSS
Supply voltage (AVDD, etc.)
VIH
VTH
High-level input voltage
VIL
IOH
Low-level input voltage
MIN
NOM‡
MAX
UNIT
4.75
5
5.25
V
Supply voltage (CVSS, etc.)
0
2.1
High-level input voltage for CLKIN
3
− 0.3*
V
VDD + 0.3*
VDD + 0.3*
V
0.8
V
V
− 300
µA
IOL
Low-level output current
2
TC
Operating case temperature (see Note 6)
− 55
125
‡ All nominal values are at VDD = 5 V, TA (ambient-air temperature)= 25°C.
* This parameter is not production tested.
NOTE 5: All input and output voltage levels are TTL compatible.
NOTE 6: TC MAX at maximum rated operating conditions at any point on the case, TC MIN at initial (time zero) power up
mA
High-level output current
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°C
11
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(see Note 5)
TEST CONDITIONS†
PARAMETER
TYP‡
2.4
3
MAX
UNIT
VOH
High-level output voltage
VOL
Low-level output voltage
IZ
II
High-impedance current
Input current
VDD = MAX
VI = VSS to VDD
IIP
IIC
Input current
Inputs with internal pullups (see Note 7)
Input current ( X2 / CLKIN)
VI = VSS to VDD
ICC
Supply current
VDD = MAX, TA = 25
25°C,
C,
tc(CI) = MIN, See Note 8
IDD
Ci
Supply current, standby; IDLE2, clock shut off
VDD = 5 V, TA = 25°C
Input capacitance
15*
pF
Co
Output capacitance
20*
pF
For XA12 −XA0
All others
VDD = MIN, IOH = MAX
VDD = MIN, IOL = MAX
VDD = MIN, IOL = MAX
MIN
V
0.6*
0.3
− 600
200
V
0.6
V
± 20
µA
± 10
µA
20
µA
± 50
µA
600
mA
50
mA
Cx
X2 / CLKIN capacitance
25*
pF
† For conditions shown as MIN / MAX, use the appropriate value specified in recommended operating conditions.
‡ All typical values are at VDD = 5 V, TA = 25°C.
* This parameter is not production tested.
NOTES: 5. All input and output voltage levels are TTL compatible.
7. Pins with internal pullup devices: INT0 −INT3, MC / MP, RSV0 −RSV10. Although RSV0 −RSV10 have internal pullup devices,
external pullups should be used on each pin as identified in the pin function tables.
8. Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test
conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a
checkerboard pattern to both primary and expansion buses at the maximum rate possible. See Calculation of TMS320C30 Power
Dissipation Application Report (literature number SPRA020).
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
Output
Under
Test
VLOAD
CT
IOH
Where:
IOL
IOH
VLOAD
CT
= 2 mA (all outputs)
= 300 µA (all outputs)
= Selected to emulate 50 Ω termination (typical value = 1.54 V).
= 80-pF typical load-circuit capacitance
Figure 4. Test Load Circuit
12
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PARAMETER MEASUREMENT INFORMATION (CONTINUED)
signal transition levels
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows:
D For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be
no longer high is 2 V and the level at which the output is said to be low is 1 V.
D For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
2.4 V
2V
1V
0.6 V
Figure 5. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
2.1 V and the level at which the input is said to be low is 0.8 V.
D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V and the level at which the input is said to be high is 2.1 V.
2.1 V
0.8 V
Figure 6. TTL-Level Inputs
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. To shorten
the symbols, some of the terminal names and other related terminology have been abbreviated as follows,
unless otherwise noted:
A
A23 −A0
IACK
IACK
ASYNCH
Asynchronous reset signals include XF0, XF1,
CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1,
DX1, FSX1, CLKR1, DR1, FSR1, TCLK0, and TCLK1
INT
INT3−INT0
CLKX includes CLKX0 and CLKX1
IOS
IOSTRB
CH
CI
CLKIN
(M)S
(M)STRB includes MSTRB and STRB
CONTROL
Control signals include STRB, MSTRB, and IOSTRB
RDY
RDY
D
D31 −D0
RESET
RESET
DR
Includes DR0, DR1
RW
R/W
DX
Includes DX0, DX1
S
STRB
SCK
CLKX/R includes CLKX0, CLKX1,
CLKR0, and CLKR1
FS
14
FSX/R includes FSX0, FSX1, FSR0, and FSR1
FSR
Includes FSR0, FSR1
TCLK
TCLK0, TCLK1
FSX
Includes FSX0, FSX1
(X)A
Includes A23 −A0 and XA12 −XA0
GPIO
General-purpose input/output; peripheral pins include
CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1,
and TCLK0/1
(X)D
Includes D31 −D0 and XD31 −XD0
H
Includes H1, H3
XF
XFx includes XF0 and XF1
H1
H1
XF0
XF0
H3
H3
XF1
XF1
HOLD
HOLD
(X)RDY
Includes RDY and XRDY
HOLDA
HOLDA
(X)RW
(X)R/W includes R/W and XR/W
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X2/CLKIN, H1, and H3 timing
The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals. See the
RESET timing in Figure 20 for CLKIN to H1 and H3 delay specification.
timing parameters for X2/CLKIN, H1, H3 (see Note 5, Figure 7, Figure 8, and Figure 9)
320C30-40
NO.†
1
2
3
4
5
6
7
8
9
MIN
320C30-50
MAX
MIN
tf(CI)
tw(CIL)
Fall time, CLKIN
Pulse duration, CLKIN low, tc(CI) = MIN (see Note 9)
9
7
tw(CIH)
tr(CI)
Pulse duration, CLKIN high, tc(CI) = MIN (see Note 9)
9
7
tc(CI)
tf(H)
Cycle time, CLKIN
tw(HL)
tw(HH)
Pulse duration, H1 / H3 low (see Note 10)
P−5
Pulse duration, H1 / H3 high (see Note 10)
P−6
tr(H)
td(HL-HH)
Rise time, H1 / H3
MAX
5*
Rise time, CLKIN
5*
5*
25
Fall time, H1 / H3
303
20
3
ns
ns
ns
5*
ns
303
ns
3
ns
P−5
ns
P−6
ns
3
ns
0
4
ns
tc(H)
Cycle time, H1 / H3
50
606
40
† Numbers in this column match those used in Figure 7, Figure 8, and Figure 9.
* This parameter is not production tested.
NOTES: 5. All input and output voltage levels are TTL compatible.
9. Rise and fall times, assuming a 35 − 65% duty cycle, are incorporated within this specification (see Figure 6).
10. P = tc(CI)
606
ns
9.1
3
UNIT
Delay time, from H1 low to H3 high or from H3 low to H1 high
0
4
10
5
4
1
3
X2 / CLKIN
(1.5 V )
2
Figure 7. X2 / CLKIN Timing
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15
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
timing parameters for X2/CLKIN, H1, H3 (see Note 5, Figure 7, Figure 8, and Figure 9) (continued)
10
6
9
H1
8
7
9.1
9.1
H3
8
9
6
7
10
Figure 8. H1 / H3 Timings
8
7
4.5 V Band
CLKIN to H1/H3 − ns
6
5
4
3
5.5 V Band
2
1
0
−60
−40
−20
0
20
40
60
80
Temperature − Degrees C
Figure 9. CLKIN to H1/H3 as a Function of Temperature
(Typical)
16
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100
120
140
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory read/write timing
The following table defines memory read/write timing parameters for (M)STRB.
timing parameters for a memory [(M)STRB = 0] read/write (see Figure 10 and Figure 11)
NO.†
11
12
13.1
13.2
14.1
14.2
15.1
15.2
16
17.1
17.2
18
19
20
21
22.1
22.2
320C30-40
320C30-50
MIN
MAX
MIN
MAX
UNIT
td[H1L-(M)SL]
td[H1L-(M)SH]
Delay time, H1 low to (M)STRB low
0*
10
0*
4
ns
Delay time, H1 low to (M)STRB high
0*
6
0*
4
ns
td(H1H-RWL)
td[H1H-(X)RWL]
Delay time, H1 high to R / W low
0*
9
0*
7
ns
Delay time, H1 high to (X)R / W low
0*
13
0*
11
ns
td(H1L-A)
td[H1L-(X)A]
Delay time, H1 low to A valid
0*
11
0*
9
ns
Delay time, H1 low to (X)A valid
0*
9
0*
8
ns
tsu(D-H1L)R
tsu[(X)DR-H1L]R
Setup time, D valid before H1 low (read)
14
10
ns
Setup time, (X)D before H1 low (read)
16
14
ns
th[H1L-(X)D]R
tsu(RDY-H1H)
Hold time, (X)D after H1 low (read)
0*
0*
ns
Setup time, RDY before H1 high
8
6
ns
tsu[(X)RDY-H1H]
th[H1H-(X)RDY]
Setup time, (X)RDY before H1 high
9
8
ns
Hold time, (X)RDY after H1 high
0
0
ns
td[H1H-(X)RWH]W
tv[H1L(X)D]W
Delay time, H1 high to (X)R / W high (write)
th[H1H-(X)D]W
td(H1H-A)
Hold time, (X)D after H1 high (write)
Delay time, H1 high to A valid on back-to-back write cycles (write)
15
12
ns
td[H1H-(X)A]
td[A-(X)RDY]
Delay time, H1 high to (X)A valid on back-to-back write cycles (write)
21
18
ns
7*
6*
ns
Valid time, (X)D after H1 low (write)
7
ns
14
ns
0*
26
Delay time, (X)RDY from A valid
† Numbers in this column match those used in Figure 10 and Figure 11.
* This parameter is not production tested.
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9
17
• HOUSTON, TEXAS 77251−1443
0*
ns
17
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory read/write timing (continued)
H3
H1
11
12
(M)STRB
(see Note A)
(X)R/W
14.1/14.2
13.1/13.2
(X)A
15.1/15.2
16
26
(X)D
17.1/17.2
18
(X)RDY
NOTE A: (M)STRB remains low during back-to-back read operations.
Figure 10. Timing for Memory [(M)STRB = 0] Read
18
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory read/write timing (continued)
H3
H1
12
11
(M)STRB
19
13.1 / 13.2
(X)R / W
14.1 / 14.2
22.1 / 22.2
(X)A
20
21
(X)D
18
26
17.1 / 17.2
(X)RDY
Figure 11. Timing for Memory [(M)STRB = 0] Write
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19
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory read/write timing (continued)
The following table defines memory read timing parameters for IOSTRB.
timing parameters for a memory (IOSTRB = 0) read (see Figure 12)
NO.†
27
28
29
30
31
32
33
320C30-40
320C30-50
MIN
MAX
MIN
MAX
td(H1H-IOSL)
td(H1H-IOSH)
Delay time, H1 high to IOSTRB low
0*
9
0*
8
ns
Delay time, H1 high to IOSTRB high
0*
9
0*
8
ns
td[H1L-(X)RWH]
td[H1L-(X)A]
Delay time, H1 low to (X)R / W high
0*
9
0*
8
ns
Delay time, H1 low to (X)A valid
0*
9
0*
8
ns
tsu[(X)D-H1H]R
th[H1H-(X)D]R
Setup time, (X)D before H1 high
13
11
ns
Hold time, (X)D after H1 high
0*
0*
ns
tsu[(X)RDY-H1H]
th[H1H-(X)RDY]
Setup time, (X)RDY before H1 high
9
8
ns
0
0
ns
34
Hold time, (X)RDY after H1 high
† Numbers in this column match those used in Figure 12.
* This parameter is not production tested.
H3
H1
28
27
IOSTRB
29
(X)R / W
30
(X)A
31
32
(X)D
33
34
(X)RDY
Figure 12. Timing for Memory (IOSTRB = 0) Read
20
UNIT
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory read/write timing (continued)
The following table defines memory write timing parameters for IOSTRB.
timing parameters for a memory (IOSTRB = 0) write (see Figure 13)
NO.†
27
28
29
30
33
34
35
36
320C30-40
320C30-50
MIN
MAX
MIN
MAX
UNIT
td(H1H-IOSL)
td(H1H-IOSH)
Delay time, H1 high to IOSTRB low
0*
9
0*
8
ns
Delay time, H1 high to IOSTRB high
0*
9
0*
8
ns
td[H1L-(X)RWH]
td[H1L-(X)A]
Delay time, H1 low to (X)R / W high
0*
9
0*
8
ns
Delay time, H1 low to (X)A valid
0*
9
0*
8
ns
tsu[(X)RDY-H1H]
th[H1H-(X)RDY]
Setup time, (X)RDY before H1 high
9
8
ns
Hold time, (X)RDY after H1 high
0
0
ns
td(H1L-XRWL)
tv[H1H(X)D]W
Delay time, H1 low to XR / W low
0*
13
Valid time, (X)D after H1 high
0*
25
37
th[H1L-(X)D]W
Hold time, (X)D after H1 low
† Numbers in this column match those used in Figure 13.
* This parameter is not production tested.
0
0
11
ns
20
ns
ns
H3
H1
27
28
IOSTRB
29
35
(X)R / W
30
(X)A
37
36
(X)D
33
34
(X)RDY
Figure 13. Timing for Memory (IOSTRB = 0) Write
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
XF0 and XF1 timing when executing LDFI or LDII
The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing parameters for XF0 and XF1 when executing LDFI or LDII (see Figure 14)
NO.†
38
39
td(H3H-XF0L)
tsu(XF1-H1L)
320C30-40
320C30-50
MIN
MIN
Delay time, H3 high to XF0 low
13
Setup time, XF1 valid before H1 low
40
th(H1L-XF1)
Hold time, XF1 after H1 low
† Numbers in this column match those used in Figure 14.
Fetch
LDFI or LDII
MAX
Decode
Read
9
ns
0
ns
Execute
(M)STRB
(X)R / W
(X)A
(X)D
(X)RDY
38
39
40
XF1
Figure 14. Timing for XF0 and XF1 When Executing LDFI or LDII
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ns
0
H1
22
12
UNIT
9
H3
XF0
MAX
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
XF0 timing when executing STFI and STII
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
timing parameters for XF0 when executing STFI or STII (see Figure 15)
NO.†
320C30 - 40
320C30 - 50
MIN
MIN
MAX
41
td(H3H-XF0H) Delay time, H3 high to XF0 high
† The number in this column matches that used in Figure 15.
Fetch
STFI or STII
Decode
13
Read
MAX
12
UNIT
ns
Execute
H3
H1
(M)STRB
(X)R/W
(X)A
(X)D
41
(X)RDY
XF0
Figure 15. Timing for XF0 When Executing an STFI or STII
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
XF0 and XF1 timing when executing SIGI
The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI.
timing parameters for XF0 and XF1 when executing SIGI (see Figure 16)
NO.†
41.1
42
43
44
320C30 - 40
320C30 - 50
MIN
MIN
MAX
13
UNIT
td(H3H-XF0L)
td(H3H-XF0H)
Delay time, H3 high to XF0 low
tsu(XF1-H1L)
th(H1L-XF1)
Setup time, XF1 valid before H1 low
9
9
ns
Hold time, XF1 after H1 low
0
0
ns
Delay time, H3 high to XF0 high
13
† Numbers in this column match those used in Figure 16.
Fetch
SIGI
Decode
Read
Execute
H3
H1
41.1
43
42
XF0
44
XF1
Figure 16. Timing for XF0 and XF1 When Executing SIGI
24
MAX
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12
ns
12
ns
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
loading when XFx is configured as an output
The following table defines the timing parameter for loading the XF register when the XFx pin is configured as
an output.
timing parameters for loading the XFx register when configured as an output pin (see Figure 17)
NO.†
320C30 - 40
320C30 - 50
MIN
MIN
45
tv(H3H-XF)
Valid time, H3 high to XF valid
† The number in this column matches that used in Figure 17.
Fetch Load
Instruction
Decode
MAX
13
Read
MAX
12
UNIT
ns
Execute
H3
H1
1 or 0
OUTXF Bit
45
XFx
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 17. Timing for Loading XFx Register When Configured as an Output Pin
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
changing XFx from an output to an input
The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.
timing parameters of XFx changing from output to input mode (see Figure 18)
NO.†
46
47
td(H3H-XFx)
tsu(XFx-H1L)
320C30 - 40
320C30 - 50
MIN
MIN
Delay time, XFx after H3 high
MAX
13*
MAX
12*
UNIT
ns
Setup time, XFx before H1 low
9
9
ns
th(H1L-XFx)
Hold time, XFx after H1 low
† Numbers in this column match those used in Figure 18.
* This parameter is not production tested.
0
0
ns
48
Execute
Load of IOF
Buffers Go
From Output
to Input
Synchronizer
Delay
Value on
Terminal
Seen in IOF
H3
H1
47
I/OXFx Bit
(see Note A)
XFx
48
46
Output
INXFx Bit
(see Note A)
Data
Sampled
Data
Seen
NOTE A: I / OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register depending on
whether XF0 or XF1, respectively, is being affected.
Figure 18. Timing for Change of XFx From Output to Input Mode
26
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changing XFx from an input to an output
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.
timing parameters of XFx changing from input to output mode (see Figure 19)
NO.†
49
td(H3H-XFIO) Delay time, H3 high to XF switching from input to output
† The number in this column matches that used in Figure 19.
320C30 - 40
320C30 - 50
MIN
MIN
MAX
17
MAX
17
UNIT
ns
Execution of
Load of IOF
H3
H1
I/OXFx Bit
(see Note A)
49
XFx
(see Note A)
NOTE A: I / OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register depending on
whether XF0 or XF1, respectively, is being affected.
Figure 19. Timing for Change of XFx From Input to Output Mode
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27
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 20 occurs; otherwise, an additional delay of one clock cycle can
occur. R/ W and XR/ W are in the high-impedance state during reset and can be provided with a resistive pullup,
nominally 18 kΩ to 22 kΩ, to prevent spurious writes from occurring. The asynchronous reset signals include
XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, and TCLK0/1. HOLD is an asynchronous input and
can be asserted during reset.
Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states
and, therefore, results in slow external accesses until these registers are initialized.
timing parameters for RESET [P = tc(CI)] (see Figure 9 and Figure 20)
NO.
50
320C30 - 50
MIN
MAX
MIN
MAX
10
P*
10
P*
ns
UNIT
51
tsu(RESET)
td(CLKINH-H1H)
Setup time, RESET before CLKIN low
Delay time, CLKIN high to H1 high†
2
14
2
10
ns
52
td(CLKINH-H1L)
Delay time, CLKIN high to H1 low†
2
14
2
10
ns
53
tsu(RESETH-H1L)
Setup time, RESET high before H1 low after ten H1 clock
cycles
9
54
td(CLKINH-H3L)
td(CLKINH-H3H)
Delay time, CLKIN high to H3 low†
Delay time, CLKIN high to H3 high†
tdis(H1H-XD)
tdis(H3H-XA)
Disable time, H1 high to (X)D high-impedance state
59
td(H3H-CONTROLH)
td(H1H-IACKH)
60
tdis(RESETL-ASYNCH)
55
56
57
58
7
ns
2
14
2
10
ns
2
14
2
10
ns
15*
12*
ns
Disable time, H3 high to (X)A high-impedance state
9*
8*
ns
Delay time, H3 high to control signals high
9*
8*
ns
Delay time, H1 high to IACK high
9*
8*
ns
21*
17*
ns
Disable time, RESET low to asynchronous reset signals in
the high-impedance state
† See Figure 9 for temperature dependence for the 40-MHz SMJ320C30.
* This parameter is not production tested.
28
320C30 - 40
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reset timing (continued)
CLKIN
50
RESET
53
51
52
H1
54
H3
Ten H1 Clock Cycles
56
(X)D
(see Note A)
55
(X)A
(see Note B)
57
58
Control Signals
(see Note C)
59
IACK
Asynchronous
Reset Signals
(see Note D)
60
NOTES: A.
B.
C.
D.
In this diagram X(D) includes D31 −D0 and XD31 −XD0.
In this diagram, (X)A includes A23 −A0 and XA12 −XA0.
Control signals include STRB, MSTRB, and IOSTRB.
Asynchronous reset signals include XF1, XF0, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1,
TCLK0, and TCLK1.
E. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In micromputer mode, the reset
vector is fetched twice, with no software wait states.
Figure 20. Timing for Reset [P = tc(Cl)]
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
interrupt-response timing
The following table defines the timing parameters for the INT signals.
timing parameters for INT3−INT0 [Q = tc(H)] (see Figure 21)
NO.
61
62
tsu(INT)
tw(INT)
Setup time, INT3 −INT0 before H1 low
320C30 - 40
320C30 - 50
MIN
MIN
MAX
13
Pulse duration, INT3 −INT0, to assure only one interrupt seen
MAX
10
Q
< 2Q*
Q
UNIT
ns
< 2Q*
ns
* This parameter is not production tested.
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
SMJ320C30 interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
D A minimum of one H1 falling edge
D No more than two H1 falling edges
The SMJ320C30 can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 21 occurs; otherwise, an additional delay
of one clock cycle is possible.
Reset or
Interrupt
Vector
Read
Fetch First
Instruction of
Service Routine
H3
H1
61
INT3 −INT0
Pins
62
First
Instruction
Address
INT3 −INT0
Flag
Vector Address
Addr
Data
Figure 21. Timing for INT3 −INT0 Response [Q = tc(H)]
30
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interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal.
timing parameters for IACK (see Figure 22)
NO.†
63
64
td(H1H-IACKL)
td(H1H-IACKH)
320C30 - 40
320C30 - 50
MIN
MIN
MAX
MAX
UNIT
Delay time, H1 high to IACK low
9
7
ns
Delay time, H1 high to IACK high
9
7
ns
† Numbers in this column match those used in Figure 22.
Fetch IACK
Instruction
IACK
Data Read
H3
H1
63
64
IACK
Address
Data
Figure 22. Timing for Interrupt-Acknowledge (IACK)
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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
serial-port timing parameters (see Figure 23 and Figure 24)
CLOCK
SOURCE
NO.
320C30 - 40
MIN
MAX
65
td(H1-SCK)
Delay time, H1 high to
internal CLKX / R
tc(SCK)
Cycle time,
CLKX / R
CLKX / R ext
66
CLKX / R int
tc(H)× 2.5*
tc(H)× 2
CLKX / R ext
tc(H)+12*
tw(SCK)
Pulse
duration,
CLKX / R
high / low
67
68
69
tr(SCK)
tf(SCK)
70
71
72
73
74
75
76
77
320C30 - 50
13
tc(H)× 232*
MAX
10
tc(H)× 2.6*
tc(H)× 2
tc(H)× 232*
UNIT
ns
ns
tc(H)+10*
ns
CLKX / R int
[tc(SCK) / 2] −15
[tc(SCK) / 2]+5
[tc(SCK) / 2] −5
[tc(SCK) / 2]+5
Rise time, CLKX / R
7*
6*
ns
Fall time, CLKX / R
7*
6*
ns
Delay time,
CLKX to DX
valid
CLKX ext
30
24
td(DX)
CLKX int
17
16
Setup time,
DR before
CLKR low
CLKR ext
9
9
tsu(DR)
CLKR int
21
17
Hold time,
DR from
CLKR low
CLKR ext
9
7
th(DR)
CLKR int
0
0
Delay time,
CLKX to
internal FSX
high / low
CLKX ext
27
22
td(FSX)
CLKX int
15
15
Setup time,
FSR before
CLKR low
CLKR ext
9
7
tsu(FSR)
CLKR int
9
7
CLKX / R ext
9
7
th(FS)
Hold time,
FSX / R input
from
CLKX / R low
CLKX / R int
0
0
Setup time,
external FSX
before CLKX
high
CLKX ext
−[tc(H) − 8]
CLKX int
−[tc(H) −21]
tsu(FSX)
td(CH-DX)V
Delay time,
CLKX to first
DX bit, FSX
precedes
CLKX high
ns
ns
ns
ns
ns
ns
[tc(SCK) / 2] −10*
−[tc(H) − 8]
[tc(SCK) / 2] −10*
ns
CLKX ext
tc(SCK) / 2*
30
−[tc(H) −21]
tc(SCK) / 2*
24
ns
CLKX int
78
td(FSX-DX)V
Delay time, FSX to first DX
bit, CLKX precedes FSX
79
tdDXZ
Delay time, CLKX high to DX
high impedance following last
data bit
18
14
30
24
ns
17*
14*
ns
* This parameter is not production tested.
32
MIN
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serial-port timing parameters (continued)
Unless otherwise indicated, the data-rate timings shown in Figure 23 and Figure 24 are valid for all serial-port
modes, including handshake. See serial-port timing parameter tables.
Timing diagrams shown in Figure 23 and Figure 24 show operations with the serial port global-control register
bits CLKXP = CLKRP = FSXP = FSRP = 0.
Timing diagrams shown in Figure 23 and Figure 24 depend upon the length of the serial-port word, n, where
n = 8, 16, 24, or 32 bits, respectively.
66
65
H1
65
67
67
CLKX/ R
69
68
70
79
72
Bit n − 1
DX
Bit n − 2
Bit 0
71
DR
Bit n − 2
Bit n − 1
FSR
74
73
73
FSX (int)
75
FSX (ext)
75
76
Figure 23. Serial-Port Timing for Fixed-Data-Rate Mode
CLKX / R
73
FSX (int)
78
76
FSX (ext)
70
79
77
Bit n − 1
DX
Bit n − 2
Bit n − 3
Bit 0
75
FSR
68
Bit n − 1
DR
71
Bit n − 2
Bit n − 3
72
NOTE A: Timings not expressly specified for variable-data-rate mode are the same as those for fixed-data-rate mode.
Figure 24. Serial-Port Timing for Variable-Data-Rate Mode
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HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 25 occurs; otherwise, an additional delay of one clock cycle is
possible.
The “timing parameters for HOLD / HOLDA” table defines the timing parameters for the HOLD and HOLDA
signals.
The NOHOLD bit of the primary bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, allowing
the processor to continue until a second write is encountered.
HOLD/HOLDA timing (see Figure 25)
NO.†
80
81
82
83
84
85
86
87
88
89
90
91
320C30 - 50
MIN
MIN
tsu(HOLD)
tv(HOLDA)
Setup time, HOLD before H1 low
13
Valid time, HOLDA after H1 low
0*
tw(HOLD)
tw(HOLDA)
Pulse duration, HOLD low
Pulse duration, HOLDA low
2tc(H)
tc(H) −5*
0*
MAX
2tc(H)
tc(H) −5*
0*
Disable time, H1 low to STRB high impedance
0*
9*
0*
ten(H1L-S)
tdis(H1L-RW)
Enable time, H1 low to STRB active
0*
9*
0*
Disable time, H1 low to R / W high impedance
0*
9*
0*
ten(H1L-RW)
tdis(H1L-A)
Enable time, H1 low to R / W active
0*
9*
0*
Disable time, H1 low to address high impedance
0*
9*
0*
ten(H1L-A)
tdis(H1H-D)
Enable time, H1 low to address valid
0*
13*
0*
Disable time, H1 high to data high impedance
0*
12*
0*
• HOUSTON, TEXAS 77251−1443
9*
0*
Delay time, H1 low to STRB high for a HOLD
POST OFFICE BOX 1443
MAX
10
9
td(H1L-SH)H
tdis(H1L-S)
† Numbers in this column are used in Figure 25.
* This parameter is not production tested.
34
320C30 - 40
UNIT
ns
7
ns
ns
ns
7*
8*
ns
7*
8*
ns
7*
8*
ns
12*
8*
ns
ns
ns
ns
ns
SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
HOLD/HOLDA timing (continued)
H3
H1
80
80
82
HOLD
81
81
83
HOLDA
(see Note A)
84
(M)STRB
and
STRB
85
86
87
88
89
90
R/W
A
91
D
Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low through one H1 cycle after HOLD returns to high.
Figure 25. Timing for HOLD/HOLDA
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general-purpose I/O timing
Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The contents of the
internal-control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The following table defines peripheral pin general-purpose I/O timing parameters.
timing parameters for peripheral pin general-purpose I/O (see Note 11 and Figure 26)
NO.†
92
93
tsu(GPIOH1L)
th(GPIOH1L)
320C30 - 40
320C30 - 50
MIN
MIN
Setup time, general-purpose input before H1 low
Hold time, general-purpose input after H1 low
MAX
MAX
UNIT
10*
9*
ns
0*
0*
ns
94
td(GPIOH1H) Delay time, general-purpose output after H1 high
13*
10*
ns
† Numbers in this column are used in Figure 26.
* This parameter is not production tested.
NOTE 11: Peripheral pins include CLKX0 / 1, CLKR0 / 1, DX0 / 1, DR0 / 1, FSX0 / 1, FSR0 / 1, and TCLK0 / 1. The modes of these pins are defined
by the contents of internal control registers associated with each peripheral.
H3
H1
94
93
94
92
Peripheral
Pin
Figure 26. Timing for Peripheral Pin General-Purpose I/O
36
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changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and the reverse.
timing parameters for peripheral pin changing from general-purpose output to input mode
(see Note 12 and Figure 27)
NO.†
95
96
th(H1H)
tsu(GPIOH1L)
320C30 - 40
320C30 - 50
MIN
MIN
MAX
Hold time after H1 high
13
Setup time, peripheral pin before H1 low
9
MAX
10
9
UNIT
ns
ns
97
th(GPIOH1L)
Hold time, peripheral pin after H1 low
0
0
ns
† Numbers in this column are used in Figure 27.
NOTE 12: Peripheral pins include CLKX0 / 1, CLKR0 / 1, DX0 / 1, DR0 / 1, FSX0 / 1, FSR0 / 1, and TCLK0 / 1. The modes of these pins are defined
by the contents of internal control registers associated with each peripheral.
Execute Store
of Peripheral
Control
Register
Buffers Go
From Output to
Input
Synchronizer Delay
Value on
Terminal Seen in
Peripheral
Control Register
H3
H1
96
I/O
Control Bit
97
95
Peripheral
Pin
Output
Data Bit
Data Sampled
Data
Seen
Figure 27. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
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timing parameters for peripheral pin changing from general-purpose input to output mode
(see Figure 28)
NO.
98
td(GPIOH1H)
Delay time, H1 high to peripheral pin switching from input to output
320C30 - 40
320C30 - 50
MIN
MIN
MAX
13
MAX
10
Execution of Store of
Peripheral Control
Register
H3
H1
I/O
Control
Bit
98
Peripheral
Pin
Figure 28. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode
38
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UNIT
ns
SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
timer pin (TCLK0 and TCLK1) timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following table defines the timing parameters for the timer pin.
timing parameters for timer pin (TCLK0 and TCLK1) (see Figure 29)
320C30 - 40‡
NO.
MIN
320C30 - 50‡
MAX
MIN
MAX
UNIT
99
tsu(TCLK-H1L)
Setup time,
TCLK ext
before H1 low
TCLK ext
10
8
ns
100
th(TCLK-H1L)
Hold time,
TCLK ext after
H1 low
TCLK ext
0
0
ns
101
td(TCLK-H1H)
Delay time, H1
high to TCLK
int valid
TCLK int
tc(TCLK)
Cycle time,
TCLK
TCLK ext
102
103
tw(TCLK)
Pulse duration,
TCLK high / low
TCLK ext
TCLK int
TCLK int
9
tc(H) × 2.6*
tc(H) × 2
tc(H) + 12*
[tc(TCLK) / 2] −5
tc(H) × 232*
[tc(TCLK) / 2]+5
9
tc(H) × 2.6*
tc(H) × 2
tc(H) + 10*
[tc(TCLK) / 2] −5
ns
ns
tc(H) × 232*
ns
ns
[tc(TCLK) / 2]+5
ns
† Numbers in this column are used in Figure 29.
‡ Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous
input clock.
* This parameter is not production tested.
H3
H1
100
103
101
101
99
Timer
Pin
102
NOTE A: Period and polarity of valid logic level are specified by contents of internal control registers.
Figure 29. Timing for Timer Pin
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SHZ pin timing
The following table defines the timing parameter for the SHZ pin.
timing parameters for SHZ pin (see Figure 30)
320C30 -40
320C30 -50
NO.†
104
105
tdis(SHZ)
ten(SHZ)
UNIT
MIN
MAX
Disable time, SHZ low to all O, I / O high impedance
0*
3P + 15*
ns
Enable time, SHZ high to all O, I / O active
0*
2P*
ns
† Numbers in this column are used in Figure 30.
* This parameter is not production tested.
H3
H1
1.5
SHZ
(see
Note A)
104
105
All I / Os
NOTE A: Enabling SHZ destroys SMJ320C30 register and memory contents. Assert SHZ and reset the SMJ320C30 to restore it to a known
condition.
Figure 30. Timing for SHZ
40
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SMJ320C30 part order information
TECHNOLOGY
POWER
SUPPLY
OPERATING
FREQUENCY
SMJ320C30GBM40
0.7-µm CMOS
5 V ± 5%
40 MHz
Ceramic 181-pin PGA
QML
SM320C30GBM40
0.7-µm CMOS
5 V ± 5%
40 MHz
Ceramic 181-pin PGA
Standard
QML
Standard
DEVICE
PACKAGE TYPE
PROCESSING
LEVEL
SMJ320C30HFGM40
0.7-µm CMOS
5 V ± 5%
40 MHz
Ceramic 196-pin quad flatpack with
nonconductive tie bar
SM320C30HFGM40
0.7-µm CMOS
5 V ± 5%
40 MHz
Ceramic 196-pin quad flatpack with
nonconductive tie bar
5962−9052604MXA
0.7-µm CMOS
5 V ± 5%
40 MHz
Ceramic 181-pin PGA
DESC SMD
DESC SMD
5962−9052604MUA
0.7-µm CMOS
5 V ± 5%
40 MHz
Ceramic 196-pin quad flatpack with
nonconductive tie bar
SMJ320C30GBM50
0.7-µm CMOS
5 V ± 5%
50 MHz
Ceramic 181-pin PGA
QML
SM320C30GBM50
0.7-µm CMOS
5 V ± 5%
50 MHz
Ceramic 181-pin PGA
Standard
QML
Standard
SMJ320C30HFGM50
0.7-µm CMOS
5 V ± 5%
50 MHz
Ceramic 196-pin quad flatpack with
nonconductive tie bar
SM320C30HFGM50
0.7-µm CMOS
5 V ± 5%
50 MHz
Ceramic 196-pin quad flatpack with
nonconductive tie bar
5962−9052605MXA
0.7-µm CMOS
5 V ± 5%
50 MHz
Ceramic 181-pin PGA
DESC SMD
5962−9052605MUA
0.7-µm CMOS
5 V ± 5%
50 MHz
Ceramic 196-pin quad flatpack with
nonconductive tie bar
DESC SMD
C
GB
SMJ
PREFIX
SMJ =
SM =
320
30
M
40
SPEED RANGE
40 = 40 MHz
50 = 50 MHz
MIL-STD-38535 (QML)
Standard Processing
TEMPERATURE RANGE
M = − 55°C to 125°C
L =
0°C to 70°C
DEVICE FAMILY
320 = SMJ320 Family
PACKAGE TYPE
GB
= 181-Pin Grid Array (PGA) Ceramic
Package
HFG = 196-Pin Ceramic Quad Flatpack with a
nonconductive tie bar
KGD = Known Good Die
TECHNOLOGY
C = CMOS
DEVICE
30 = 320C30
Figure 31. SMJ320C30 Device Nomenclature
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
41
SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
MECHANICAL DATA
HFG (S-CQFP-F196)
CERAMIC QUAD FLATPACK WITH TIE BAR
1.365 (34,67)
1.325 (33,66)
Thermal Resistance Characteristics
0.600 (15,20) TYP
“A”
49
0.225 (5,72)
Tie Bar Width
0.175 (4,45)
1
50
196
°C/W
PARAMETER
1.200 (30,48) TYP
RθJA
28.9
RθJC
1.3
2.505 (63,63)
2.485 (63,12)
1.710 (43,43)
1.690 (42,93)
148
98
99
147
“C”
1.150 (29,21)
8 Places
0.061 (1,55)
DIA 4 Places
0.059 (1,50)
“B”
0.105 (2,67) MAX
0.018 (0,46) MAX
0.010 (0,25)
196 0.006 (0,15)
Braze
0.040 (1,02)
0.030 (0,76)
0.025 (0,64)
DETAIL “A”
0.014 (0,36)
0.002 (0,05)
0.008 (0,20)
0.004 (0,10)
0.020 (0,51) MAX
DETAIL “B”
0.130 (3,30) MAX
DETAIL “C”
4040231-6 / F 04/96
NOTES: A.
B.
C.
D.
E.
F.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Ceramic quad flatpack with flat leads brazed to nonconductive tie-bar carrier
This package can be hermetically sealed with a metal lid.
The terminals will be gold plated.
Falls within JEDEC MO -113 AB
The above data applies to the SMJ320C30 196-pin QFP.
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
MECHANICAL DATA (CONTINUED)
GA-GB (S-CPGA-P15 X 15)
CERAMIC PIN GRID ARRAY PACKAGE
A or A1 SQ
1.400 (35,56) TYP
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIM
MIN
MAX
A
1.540 (39,12)
1.590 (40,38)
Large
Outline
A1
1.480 (37,59)
1.535 (38,99)
Small
Outline
B
0.110 (2,79)
0.205 (5,21)
Cavity
Up
B1
0.095 (2,41)
0.205 (5,21)
Cavity
Down
C
0.040 (1,02)
0.060 (1,52)
Cavity
Up
C1
0.025 (0,63)
0.060 (1,52)
Cavity
Down
B or B1
C or C1
0.050 (1,27) DIA
4 Places
0.022 (0,55)
0.016 (0,41)
0.140 (3,56)
0.120 (3,05)
0.100 (2,54)
DIA TYP
Notes
MAXIMUM PINS WITHIN MATRIX − 225
4040114-8 / C 04/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Index mark may appear on top or bottom depending on package vendor.
Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within
0.030 (0,76) diameter relative to the edges of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold plated or solder dipped.
G. Falls within MIL-STD-1835 CMGA7-PN and CMGA19-PN and JEDEC MO-067AG and MO-066AG, respectively
Thermal Resistance Characteristics
PARAMETER
°C/W
RθJA
26.6
RθJC
1.1
The above data applies to the SMJ320C30 181-pin PGA.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
43
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
5962-9052604MUA
5962-9052604MXA
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
Package
Type
Package
Drawing
ACTIVE
CFP
HFG
196
1
TBD
Call TI
Level-NC-NC-NC
ACTIVE
CPGA
GB
181
1
TBD
Call TI
Level-NC-NC-NC
5962-9052604Q9A
OBSOLETE
XCEPT
KGD
0
TBD
Call TI
Call TI
5962-9052605MUA
ACTIVE
CFP
HFG
196
4
TBD
Call TI
Level-NC-NC-NC
5962-9052605MXA
ACTIVE
CPGA
GB
181
1
TBD
Call TI
Level-NC-NC-NC
5962-9052605QXC
ACTIVE
CPGA
GB
181
1
TBD
Call TI
Level-NC-NC-NC
SM320C30GBM40
ACTIVE
CPGA
GB
181
1
TBD
Call TI
Level-NC-NC-NC
SM320C30GBM50
ACTIVE
CPGA
GB
181
1
TBD
Call TI
Level-NC-NC-NC
SM320C30HFGM40
ACTIVE
CFP
HFG
196
1
TBD
Call TI
Level-NC-NC-NC
SM320C30HFGM50
ACTIVE
CFP
HFG
196
1
TBD
Call TI
Level-NC-NC-NC
SMJ320C30GBM40
ACTIVE
CPGA
GB
181
1
TBD
Call TI
Level-NC-NC-NC
SMJ320C30GBM50
ACTIVE
CPGA
GB
181
1
TBD
Call TI
Level-NC-NC-NC
SMJ320C30HFGM40
ACTIVE
CFP
HFG
196
1
TBD
Call TI
Level-NC-NC-NC
SMJ320C30HFGM50
ACTIVE
CFP
HFG
196
4
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP023C – JANUARY 1995 – REVISED JUNE 1999
HFG (S-CQFP-F196)
CERAMIC QUAD FLATPACK WITH NCTB
1.365 (34,67)
SQ
1.335 (33,91)
”A”
49
1.200 (30,48)
BSC
0.225 (5,72)
0.175 (4,45)
Tie Bar Width
1
50
196
Á
Á
Á
Á
1.710 (43,43)
1.690 (42,93)
2.505 (63,63)
2.485 (63,12)
148
98
99
1.150 (29,21)
BSC 8 Places
0.061 (1,55)
DIA 4 Places
0.059 (1,50)
147
Á
Á
Á
Á
”C”
”B”
0.105 (2,67) MAX
0.018 (0,46) MAX
0.013 (0,33)
196 X
0.007 (0,18)
Braze
0.040 (1,02)
0.030 (0,76)
0.025 (0,64)
DETAIL ”A”
0.009 (0,23)
0.004 (0,10)
0.020 (0,51) MAX
DETAIL ”B”
0.014 (0,36)
0.002 (0,05)
0.130 (3,30) MAX
DETAIL ”C”
4040231-6/J 01/99
NOTES: A.
B.
C.
D.
E.
F.
G.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier
This package is hermetically sealed with a metal lid.
The leads are gold-plated and can be solder-dipped.
Leads not shown for clarity purposes
Falls within JEDEC MO-113AB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MCPG014A – FEBRUARY 1996 – REVISED JANUARY 2002
GB (S-CPGA-P181)
CERAMIC PIN GRID ARRAY
1.590 (40,40)
SQ
1.560 (39,62)
1.400 (35,56) TYP
0.100 (2,54) TYP
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bottom View
0.185 (4,70)
0.140 (3,55)
0.055 (1,40)
0.045 (1,14)
0.050 (1,27) DIA
4 Places
0.022 (0,55)
0.016 (0,41)
0.140 (3,56)
0.120 (3,05)
DIA TYP
4073426/C 11/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Index mark can appear on top or bottom, depending on package vendor.
Pins are located within 0.010 (0,25) diameter of true position relative to
each other at maximum material condition and within 0.030 (0,76) diameter
relative to the edge of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold-plated or solder-dipped.
G. Falls within MIL-STD-1835 CMGA7-PN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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