5962-9052604Q9B SMD

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R060-92
91-11-25
M. L. Poelking
B
Changes in accordance with NOR 5962-R006-93
92-11-05
M. L. Poelking
C
Add device type 03. Update boilerplate. Editorial changes
throughout.
92-12-10
M. L. Poelking
D
Add device type 04. Update boilerplate. Editorial changes
throughout.
96-07-09
M. L. Poelking
E
Add case outlines T and M. Changes to boilerplate. Editorial
changes throughout.
96-10-03
M. L. Poelking
F
Changes in accordance with NOR 5962-R296-97.
97-06-06
M. L. Poelking
G
Add device type 05. Editorial changes throughout. - LTG
97-12-01
M. L. Poelking
H
Changes in accordance with NOR 5962-R103-98
98-05-06
M. L. Poelking
J
Changes in accordance with NOR 5962-R171-98
98-10-22
M. L. Poelking
K
Changes in accordance with NOR 5962-R002-00
99-11-15
M. L. Poelking
L
Incorporate revisions H, J, and K. Add paragraph 6.7, application
note, to document. Update boilerplate to MIL-PRF-38535
requirements. – LTG
02-06-17
Thomas M. Hess
M
Update die dimensions and bond pad coordinates due to die shrink.
Update boilerplate to current MIL-PRF-38535 requirements. – CFS
04-08-27
Thomas M. Hess
N
Update boilerplate to current MIL-PRF-38535 requirements. – CFS
08-11-17
Thomas M. Hess
REV
N
N
N
N
SHEET
55
56
57
58
REV
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
SHEET
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
REV
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
SHEET
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
REV STATUS
REV
N
N
N
N
N
N
N
N
N
N
N
N
N
N
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Christopher A. Rauch
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Tim H. Noh
APPROVED BY
Don M. Cool
MICROCIRCUIT, DIGITAL, CMOS, DIGITAL
SIGNAL PROCESSOR, MONOLITHIC SILICON
DRAWING APPROVAL DATE
91-09-13
REVISION LEVEL
N
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-90526
58
5962-E039-09
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and appendix F of MIL-PRF-38535, “General provisions for TAB microcircuits” and space application (device class V). A choice
of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a
choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
90526
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
M
X
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
320C30
320C30
320C30
320C30
320C30
Digital signal processor, 28 MHz
Digital signal processor, 25 MHz
Digital signal processor, 33 MHz
Digital signal processor, 40 MHz
Digital signal processor, 50 MHz
01
02
03
04
05
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN
class level B microcircuits in accordance with MIL-PRF-38535, appendix A and
appendix F of MIL-PRF-38535
Q or V
Certification and qualification to MIL-PRF-38535 and appendix F of
MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
U
X
Y 1/
Z 1/
T
M
Descriptive designator
See figure 1
CMGA7-P181
See figure 1
See figure 1
See figure 1
See figure 1
Terminals
Package style
196
181
196
196
203
196
Quad flat pack with non-conductive tiebar
Pin grid array
Leadless chip carrier
Quad flat package
Environmentally protected tape automated bond
Tape automated bond
__________
1/ Not available from an approved source of supply.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
2
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 and appendix F of MIL-PRF-38535 for device classes Q
and V or MIL-PRF-38535, appendix A and appendix F of MIL-PRF-38535 for device class M.
1.3 Absolute maximum ratings. 2/
Supply voltage range (VDD) 3/ .....................................
Input voltage range .......................................................
Output voltage range .....................................................
Continuous power dissipation 4/ ..................................
Storage temperature range ...........................................
Junction temperature (TJ) Case outlines X and U:
Device types 03, 04, and 05 ........................................
Junction temperature (TJ) Case outlines T and M:
Device type 03 ............................................................
Thermal resistance, junction to case (θJC):
Case X ........................................................................
Case U ........................................................................
Maximum die temperature rise for the die at 100%:
Cases T and M ............................................................
Thermal resistance, junction to ambient (θJA):
Case U ........................................................................
-0.3 V dc to 7.0 V dc
-0.3 V dc to 7.0 V dc
-0.3 V dc to 7.0 V dc
3.15 W
-55°C to +150°C
+150°C
+125°C
See MIL-STD-1835
1.5°C/W
0.09°C/W
29°C/W
1.4 Recommended operating conditions.
Supply voltages (VDD):
Device type 01, 04 and 05 ...........................................
Device type 02 and 03 .................................................
Supply voltages (CVSS, etc.) (VSS) .................................
High level input voltage (VIH): 5/
Except CLKX0 and CLKX1 ..........................................
High level input voltage (VIH): 5/
Pins CLKX0 and CLKX1 ..............................................
Low level input voltage (VIL) 5/ .....................................
High level output current (IOH) .......................................
Low level output current (IOL) .........................................
CLKIN high level input voltage (VTH) 5/ ........................
Operating case temperature (TC) ..................................
4.75 V dc min to 5.25 V dc max
4.5 V dc min to 5.5 V dc max
0 V dc nominal
2.1 V dc min to VDD +0.3 V dc max
2.2 V dc min to VDD +0.3 V dc max
-0.3 V dc min to 0.8 V dc max
-300 μA max
2 mA max
3.0 V dc min to VDD +0.3 V dc max
-55°C min to +125°C max
__________
2/
3/
4/
5/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
All voltage values are with respect to VSS.
Actual operating power will be less. This value was obtained under specially produced worst-case test conditions, which are
not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard
pattern to both primary and expansion buses at the maximum rate possible.
VIH max, VIL min, and VTH max are guaranteed from characterization but not tested.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535
-
Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
MIL-STD-1835
-
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103
MIL-HDBK-780
-
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535, and appendix F of MIL-PRF-38535 “General provisions for TAB microcircuits”, and as specified herein or as
modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form,
fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF38535, appendix A for non-JAN class level B devices and as specified herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535, appendix F of MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix
A, appendix F of MIL-PRF-38535 and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and on figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3.
3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
4
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535 and appendix F of MIL-PRF-38535
(see 3.1 herein). Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A and appendix F of
MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535,
appendix F of MIL-PRF-38535 (see 3.1 herein) and herein or for device class M, the requirements of MIL-PRF-38535,
appendix A, appendix F of MIL-PRF-38535, and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A).
3.11 ROM coding processing option. If ROM coding is to be utilized by the user, an altered item drawing (AID) must be
supplied to the vendor. It is recommended that users insure the vendor perform subgroups 7 and 9 after programming to verify
the specific program configuration.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
N
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
1, 2, 3
All
1, 2, 3
All
Limits
Min
High level output voltage
VOH
Low level output voltage 2/
VOL
VDD = min
IOH = -300.0 μA
VDD = min
IOL = 2.0 mA
Unit
Max
2.4
For pins A23-A0
V
0.6
V
0.8
V
Three-state current
IZ
VDD = max
1, 2, 3
All
-20.0
20.0
μA
Input current
Input current with internal
pull-ups 3/
IIN
VIN = 0.0 V to VDD max
1, 2, 3
All
-10.0
10.0
μA
IIP
1, 2, 3
All
-600.0
20.0
μA
Input current, (X2/CLKIN)
IIC
VIN = 0.0 V to 5.5 V
1, 2, 3
All
-50.0
50.0
μA
Supply current 4/
ICC
VDD = max
1
mA
fx = 28 MHz
01
600.0
fx = 25 MHz
02
600.0
fx = 33 MHz
03
600.0
fx = 40 MHz
04
600.0
05
600.0
All
15.0
fx = 50 MHz
See 4.4.1b
4
Input capacitance 5/
CIN
Output capacitance 5/
COUT
20.0
X2/CLKIN capacitance 5/
CX
25.0
Functional testing
Fall time, CLKIN 5/
tF1
Pulse duration, CLKIN low
tW1
See 4.4.1d
See figure 4
X2/CLKIN timing
tC1 = 35 ns
7, 8
All
9, 10, 11
All
9, 10, 11
tW2
5.0
01
12.5
tC1 = 40 ns
02
14.0
tC1 = 30 ns
03
10.5
tC1 = 25 ns
04
9.0
tC1 = 20 ns
Pulse duration, CLKIN
high
05
7.0
01
12.5
tC1 = 40 ns
02
14.0
tC1 = 30 ns
03
10.5
9, 10, 11
tC1 = 35 ns
tC1 = 25 ns
04
9.0
tC1 = 20 ns
05
7.0
Rise time, CLKIN 5/
tR1
9, 10, 11
All
Cycle time, CLKIN
tC1
9, 10, 11
01
02
03
04
05
pF
35.0
40.0
30.0
25.0
20.0
ns
ns
ns
5.0
ns
303.0
303.0
303.0
303.0
303.0
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
N
SHEET
6
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
9, 10, 11
01, 03
04, 05
3.0
02
4.0
Min
Fall time, H1/H3
tF2
Pulse duration, H1/H3 low
tW3
Pulse duration, H1/H3
high
See figure 4
H1/H3 timing
P = tC1
01- 03
04, 05
P-6
P-5
tW4
01- 03
04, 05
P-7
P-6
Rise time, H1/H3
tR2
01- 03
04, 05
Delay time, from H1(H3)
low to H3(H1) high 6/
tD1
01- 03
04, 05
Cycle time, H1/H3
tC2
Delay time, from H1 low to
(M)STRB low 6/
Delay time, from H1 low to
(M)STRB high 6/
tD2
01
02
03
04
05
01-04
05
01-03
04
05
01-03
04
05
01
02
03
04
05
01
02
03, 04
05
01
02
03
04
05
01, 02
03
04
05
01, 02
03
04
05
See figure 4
Memory ((M)STRB = 0)
9, 10, 11
tD3
Delay time, from H1 high
to R/W low 6/
tD4
Delay time, from H1 high
to (X)R/W low 6/
tD5
Delay time, from H1 low to
A valid 6/
tD6
Delay time, from H1 low to
XA valid 6/
tD7
Setup time, D valid before
H1 low (read)
tSU1
Setup time, XD before
H1 low (read)
tSU2
Unit
Max
ns
ns
4.0
3.0
ns
0
0
5.0
4.0
ns
70.0
80.0
60.0
50.0
40.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
19.0
16.0
14.0
10.0
20.0
18.0
16.0
14.0
606.0
606.0
606.0
606.0
606.0
10.0
4.0
10.0
6.0
4.0
10.0
9.0
7.0
17.0
18.0
15.0
13.0
11.0
16.0
18.0
14.0
9.0
13.0
15.0
10.0
9.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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SIZE
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A
REVISION LEVEL
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SHEET
7
TABLE I. Electrical performance characteristics – Continued.
Test
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
9, 10, 11
All
0.0
ns
10.0
8.0
6.0
10.0
12.0
9.0
8.0
ns
tSU4
01, 02
03, 04
05
01
02
03, 04
05
tH2
All
0.0
ns
tD8
01, 02
03
04
05
01-03
04
05
Symbol
Limits
Min
Hold time, (X)D after H1
low (read) 6/
Setup time, RDY before H1
high
Setup time, XRDY before
H1 high
Hold time, XRDY after H1
high
Delay time, from H1 high to
(X)R/W high (write)
tH1
See figure 4
Memory ((M)STRB = 0)
tSU3
(X)D valid after H1 low
(write)
tV1
Hold time, X(D) after H1
high (write) 6/
Delay time, from H1 high
to A valid on back-to-back
write cycles
tH3
All
tD9
Delay time, from H1 high
to XA valid on back-toback write cycles
tD10
01, 02
03
04
05
01, 02
03
04
05
01-03
04
05
01, 02
03
04
05
01-03
04
05
01
02
03
04
05
01
02
03
04
05
Delay time, from (X)RDY
to A valid 5/
Delay time, from H1 high
to IOSTRB low 6/
tD11
tD12
Delay time, from H1 high
to IOSTRB high 6/
tD13
Delay time, from H1 low
to XR/W high 6/
tD14
Delay time, from H1 low to
XA valid 6/
tD15
See figure 4
Memory (I(O)STRB = 0)
9, 10, 11
Unit
Max
ns
12.0
10.0
9.0
7.0
20.0
17.0
14.0
ns
ns
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
22.0
18.0
15.0
12.0
32.0
25.0
21.0
18.0
8.0
7.0
6.0
11.0
10.0
9.0
8.0
10.0
9.0
8.0
11.0
13.0
10.0
9.0
8.0
12.0
14.0
10.0
9.0
8.0
ns
ns
ns
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
N
SHEET
8
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
9, 10, 11
01-03
04
05
Min
15.0
13.0
11.0
Unit
Max
Setup time, XD before H1
high
tSU5
Hold time, XD after H1
high 6/
tH4
All
0.0
ns
tSU6
01
02
03, 04
05
10.0
12.0
9.0
8.0
ns
tH5
All
0.0
ns
tD16
01-03
04
05
01-03
04
05
0.0
0.0
0.0
All
01-03
04
05
01, 02
03
04, 05
0.0
Setup time, XRDY before
H1 high
Hold time, XRDY after H1
high
Delay time, from H1 low to
(X)R/W low 6/
XD valid after H1 high
tV2
Hold time, XD after H1 low
Delay time, from H3 high to
XF0 low
tD17
Setup time, XF1 valid before
H1 low
tSU7
Hold time, XF1 after H1 low
Delay time, from H3 high
to XF0 high
tH7
See figure 4
Memory ((IO)STRB = 0)
tH6
See figure 4
Timing for XF0 and XF1
when executing LDFI
or LDII
9, 10, 11
tD18
See figure 4
Timing for XF0 when
executing a STFI or STII
9, 10, 11
Delay time, from H3 high
to XF0 low
tD19
See figure 4
Timing for XF0 and XF1
when executing a SIGI
9, 10, 11
Delay time, from H3 high
to XF0 high
tD20
Setup time, XF1 valid
before H1 low
tSU8
Hold time, XF1 after H1 low
tH8
XF valid after H3 high
tV3
Hold time, XF after H3 high
5/
tH9
Setup time, XF before H1
low
tSU9
Hold time, XF after H1 low
tH10
See figure 4
Timing for loading XF
register when conformed
as an output pin
See figure 4
Change of XF from output
to input mode
9, 10, 11
9, 10, 11
All
01, 02
03
04
05
01-03
04
05
01, 02
03
04
05
01-03
04, 05
ns
15.0
13.0
11.0
30.0
25.0
20.0
ns
ns
ns
15.0
13.0
12.0
ns
15.0
12.0
9.0
ns
0.0
ns
20.0
18.0
13.0
12.0
15.0
13.0
12.0
20.0
18.0
13.0
12.0
ns
ns
ns
12.0
9.0
ns
All
01, 02
03
04
05
01, 02
03
04
05
01-03
04, 05
0.0
ns
12.0
9.0
ns
All
0.0
ns
20.0
15.0
13.0
12.0
20.0
15.0
13.0
12.0
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
9
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
9, 10, 11
01-03
04, 05
9, 10, 11
All
Limits
Min
Delay time, from H3 high
to XF switching from
input to output
Setup time, for RESET
before CLKIN low 5/
Delay time, from CLKIN high
to H1 high
Delay time, from CLKIN high
to H1 low
Setup time, RESET high
before H1 low and after 10
H1 clock cycles 6/
Delay time, from CLKIN high
to H3 low
tD21
tSU10
tD22
tD23
tSU11
tD24
Delay time, from CLKIN high
to H3 high
tD25
Disable time, from H1 high
to (X)D three-state 5/
tDIS1
Disable time, from H3 high
to (X)A three-state 5/
tDIS2
Delay time, from H3 high to
control signals high 5/
tD26
Delay time, from H1 high to
IACK high 5/
tD27
Disable time, from RESET
low to asynchronously
reset signals 5/
Setup time, INT(3-0) before
H1 low
Pulse duration, to guarantee
one interrupt seen 5/ 6/ 7/
See figure 4
Change of XF from input
to output mode
See figure 4
RESET TIMING
tDIS3
tSU12
See figure 4
INT(3-0) response timing
9, 10, 11
tW5
Unit
Max
20.0
17.0
ns
10.0
tC(C1)
ns
01, 02
03, 04
05
01, 02
03, 04
5
01, 02
03
04
05
01, 02
03, 04
05
01, 02
03, 04
05
01, 02
03
04
05
01, 02
03
04
05
01-03
04
05
01, 02
03
04
05
01-03
04
05
3.0
2.0
2.0
3.0
2.0
2.0
15.0
10.0
9.0
7.0
3.0
2.0
2.0
3.0
2.0
2.0
18.0
14.0
10.0
18.0
14.0
10.0
ns
01-03
04
05
15.0
13.0
10.0
All
P
ns
ns
18.0
14.0
10.0
18.0
14.0
10.0
20.0
18.0
15.0
12.0
12.0
10.0
9.0
8.0
10.0
9.0
8.0
12.0
10.0
9.0
8.0
25.0
21.0
17.0
ns
ns
ns
ns
ns
ns
ns
ns
< 2P
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
10
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
9, 10, 11
01, 02
03
04
05
01, 02
03
04
05
01, 02
03
04
05
Limits
Min
Delay time, from H1 high to
IACK low
tD28
Delay time, from H1 high to
IACK high during first cycle
of IACK instruction data
read
Delay time, from H1 high
to internal CLKX/R
tD29
Cycle time, CLKX/R
tC3
tD30
See figure 4
IACK TIMING
See figure 4
Data Rate Mode
9, 10, 11
CLKX/R ext
All
Pulse width CLKX/R
tW6
tR3
Fall time, CLKX/R 5/
tF3
Delay time, from CLKX to
DX valid
tD31
ns
ns
tC2 x
232
ns
01, 02
tC2+15
ns
03, 04
tC2+12
ns
05
tC2+10
(tC3/2)
-15
All
See figure 4
Fixed data rate mode
tSU13
ns
CLKX/R ext 6/
9, 10, 11
CLKX ext
CLKX int
Setup time, DR before
CLKR low
ns
CLKX/R ext 6/
CLKX/R int
Rise time, CLKX/R 5/
Max
12.0
10.0
9.0
7.0
12.0
10.0
9.0
7.0
17.0
15.0
13.0
10.0
tC2
x 2.6
tC2 x 2
CLKX/R int 5/
Unit
CLKR ext
CLKR int
Hold time, DR from CLKR
low
tH11
CLKR ext
Delay time, from CLKX to
internal FSX high/low
tD32
CLKX ext
CLKR int 6/
01-03
04
05
01-03
04
05
01-03
04
05
01-03
04
05
01-03
04, 05
01-03
04
05
01-03
04
05
All
01-03
04
05
01-03
04, 05
CLKX int
ns
(tC3/2)
+5
8.0
7.0
6.0
8.0
7.0
6.0
35.0
30.0
24.0
20.0
17.0
16.0
ns
ns
ns
ns
ns
10.0
9.0
25.0
21.0
17.0
10.0
9.0
7.0
ns
ns
ns
0.0
ns
32.0
27.0
22.0
17.0
15.0
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
11
TABLE I. Electrical performance characteristics – Continued.
Test
Setup time, FSR before
CLKR low
Symbol
tSU14
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
See figure 4
Fixed data
rate mode
Group A
subgroups
Device
type
9, 10, 11
01-03
04
05
Min
10.0
9.0
7.0
01-03
04
05
01-03
04
05
10.0
9.0
7.0
10.0
9.0
7.0
ns
CLKX/R int
6/
All
0.0
ns
CLKX ext 5/
All
CLKX int 5/
All
-(tC2
-8)
-(tC2
-21)
CLKR ext
CLKR int
Hold time, FSX/R from
CLKX/R low
Setup time, external FSX
before CLKX
Delay time, from CLKX to
first DX bit, FSX precedes
CLKX high
tH12
CLKX/R ext
tSU15
Setup time, HOLD valid
before H1 low
HOLDA valid after H1 low 6/
Pulse width, HOLD low
Pulse width, HOLDA low 6/
Delay time, from H1 low to
STRB high for a HOLD
5/ 6/
Disable time, from H1 low to
STRB high impedance
state 5/ 6/
Enable time from H1 low to
STRB active 5/ 6/
Disable time, from H1 low to
R/W high impedance
state 5/ 6/
Max
ns
ns
(tC3/2)
-10
tC3/2
ns
36.0
30.0
24.0
21.0
18.0
14.0
36.0
30.0
24.0
20.0
17.0
14.0
ns
ns
15.0
13.0
10.0
0.0
0.0
0.0
tW7
All
2.0
H1
cycles
tW8
All
ns
tD36
01-03
04
05
01-03
04
05
01-03
04
05
01-03
04
05
tC(H)
-5
0.0
0.0
9, 10, 11
CLKX ext
CLKX int
Delay time, from FSX to
first DX bit, CLKX
precedes FSX
Delay time, from CLKX high
to DX high-Z following
last data bit 5/
Unit
01-03
04
05
01-03
04
05
01-03
04
05
01-03
04
05
01-03
04
05
01-03
04
05
tD33
See figure 4
Variable rate
data mode
Limits
tD34
tD35
tSU16
See figure 4
HOLD/HOLDA Timing
9, 10, 11
tV4
tDIS4
tEN1
tDIS5
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
ns
ns
10.0
9.0
7.0
ns
10.0
9.0
7.0
10.0
9.0
8.0
10.0
9.0
7.0
10.0
9.0
8.0
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
12
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Enable time, from H1 low to
R/W active 5/ 6/
tEN2
Disable time, from H1 low to
address high impedance
state 5/ 6/
tDIS6
Enable time, from H1 low to
address valid 5/ 6/
tEN3
Disable time, from H1 high
to data high impedance
state 5/ 6/
Setup time, general purpose
input before H1 low
tDIS7
tSU17
Conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
See figure 4
HOLD/HOLDA Timing
See figure 4
Peripheral pin general
General purpose I/O timing
Group A
subgroups
Device
type
9, 10, 11
01-03
04
05
01, 02
03
04
05
01-03
04
05
01-03
04
05
01, 02
03
04
05
Min
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
15.0
12.0
10.0
9.0
0.0
9, 10, 11
Limits
Unit
Max
10.0
9.0
7.0
15.0
10.0
9.0
8.0
15.0
13.0
12.0
15.0
12.0
8.0
ns
ns
ns
ns
ns
Hold time, general purpose
input after H1 low
Delay time, general purpose
output after H1 high
tH13
All
tD37
Setup time, TCLK ext before
H1 low 8/
tSU18
01-03
04
05
01, 02
03
04
05
15.0
12.0
10.0
8.0
ns
Hold time, TCLK ext after
H1 low 8/
Delay time, TCLK int valid
after H1 high
tH14
All
0.0
ns
tD38
Hold time, after H1 high 5/
tH15
Setup time, peripheral pin
before H1 low
tSU19
01, 02
03
04, 05
01-03
04
05
01, 02
03
04, 05
15.0
12.0
9.0
ns
Hold time, peripheral pin
after H1 low
Delay time, from H1 high to
peripheral pin switching
from input to output
tH16
All
0.0
ns
tD39
See figure 4
Timer pin timing
9, 10, 11
See figure 4
Change of peripheral pin
from general purpose
output to input mode
9, 10, 11
See figure 4
Change of peripheral pin
from general purpose
input to output mode
9, 10, 11
01-03
04
05
ns
15.0
13.0
10.0
15.0
12.0
9.0
15.0
13.0
10.0
15.0
13.0
10.0
ns
ns
ns
ns
See footnotes on next page.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
13
TABLE I. Electrical performance characteristics – Continued.
1/ For devices 01, 04 and 05: 4.75 V ≤ VDD ≤ 5.25 V. For devices 02 and 03: 4.5 V ≤ VDD ≤ 5.5 V, unless
otherwise specified. All other test conditions shall be worst case conditions unless otherwise specified.
2/ VOL for XA(12-0) is guaranteed from characterization data but not tested.
3/ Pins with internal pull-up devices: INT(0-3), MC/MP, RSV(0-10).
4/ Actual operating current will be less than this maximum value. This value was obtained under
specially produced worst-case test conditions, which are not sustained during normal device
operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both
primary and expansion buses at the maximum rate possible.
5/ Maximum limit is derived by design to the limits specified in table I.
6/ Minimum limit is derived from characterization to the limits specified in table I.
7/ Interrupt pulse width must be at least 1 P wide to guarantee it will be seen. It must be less than
2 P wide to guarantee it will be responded to only once. The recommended pulse width is 1.5 P.
P = one H1 cycle.
8/ Applicable for a synchronous input clock.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
N
SHEET
14
Case U
NOTES:
1. Actual pin count not represented for clarity purposes.
2. Metric equivalents for information purposes only.
3. A terminal 1 identification mark shall be located at the index corner in the area shown.
Terminal 1 is located immediately adjacent to and counterclockwise from the index
corner. Terminal numbers increase in a counterclockwise direction when viewed as
shown. The index corner shall be clearly unique.
FIGURE 1. Case outlines.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
15
Case U
Millimeters
Letter
Inches
Notes
Min
Max
Min
Max
A
---
3.30
---
0.130
A1
---
2.67
---
0.105
A2
0.15
0.30
0.006
0.012
A3
---
0.046
---
0.018
B
0.18
0.33
0.007
0.013
B1
.064 BSC
At braze pads
.025
C
0.10
0.23
0.004
0.009
D
63.50
64.52
2.500
2.540
D1,E1
33.70
34.70
1.325
1.365
D2,E2
30.50 BSC
1.200 BSC
D3,E3
15.25 BSC
0.600 BSC
D4
---
0.51
---
0.020
E
63.50
64.52
2.500
2.540
F
63.12
63.63
2.485
2.505
Tie bar dimension
G
42.93
43.43
1.690
1.710
Tie bar dimension
H
4.45
5.72
0.175
0.225
Tie bar dimension
H1
0.76
1.02
0.030
0.040
Tie bar dimension
0.061
4 places
J
K
29.21 BSC
1.50
1.150 BSC
1.55
0.059
FIGURE 1. Case outlines - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
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SHEET
16
Case Y
FIGURE 1. Case outlines - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
N
SHEET
17
Case Z
NOTES: Actual terminal count not represented for clarity purposes.
FIGURE 1. Case outlines - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
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SHEET
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Case Z
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
3.302
0.130
A1
2.667
0.105
B
0.152
0.254
0.006
0.010
C
0.102
0.203
0.004
0.008
D, E
47.752
48.641
1.880
1.915
D1, E1
33.909
34.671
1.335
1.365
D2, E2
30.48 BSC
1.200 BSC
D3, E3
15.24 BSC
0.600 BSC
L
6.35
0.250
N
196
196
ND
49
49
NOTES:
N = Total number of leads.
ND = Total number of leads per side.
FIGURE 1. Case outlines - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
19
Case T, M
FIGURE 1. Case outlines – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
20
Device types: 01, 02, 03, 04, and 05
1/ 2/ 3/ 4/
Case outline: X
Terminal
Terminal
Terminal
Terminal
symbol
number
symbol
number
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
F15
A0
C4
D0
P3
A13
XA0
R4
XD0
G12
A1
D5
D1
R2
G13
A2
A2
D2
N4
FSX0
A14
XA1
P5
XD1
CLKR0
D11
XA2
N6
XD2
G14
A3
A3
D3
M5
G15
A4
B4
D4
R1
CLKX0
C12
XA3
R5
XD3
DR0
B13
XA4
P6
H15
A5
C5
D5
XD4
R3
DX0
A15
XA5
M7
XD5
H14
A6
D6
J15
A7
A4
D6
M3
FSR1
B15
XA6
R6
XD6
D7
P1
FSX1
C14
XA7
N7
XD7
J14
A8
B5
J13
A9
C6
D8
L4
CLKR1
E12
XA8
P7
XD8
D9
N2
CLKX1
D13
XA9
R7
XD9
K15
A10
J12
A11
A5
D10
N1
DR1
C15
XA10
P8
XD10
B6
D11
P2
DX1
D14
XA11
R8
K14
A12
XD11
D7
D12
E13
XA12
R9
XD12
FSR0
L15
A13
A6
D13
F14
EMU0
J3
RSV0
P9
XD13
K13
A14
C7
D14
E15
EMU1
J4
RSV1
N9
XD14
L14
A15
B7
D15
F13
EMU2
K1
RSV2
R10
XD15
M15
A16
A7
D16
E14
EMU3
K2
RSV3
M9
XD16
K12
A17
A8
D17
F12
EMU4
L1
RSV4
P10
XD17
L13
A18
B8
D18
C1
EMU5
K3
RSV5
R11
XD18
M14
A19
A9
D19
M6
EMU6
L2
RSV6
N10
XD19
N15
A20
B9
D20
B3
H1
K4
RSV7
P11
XD20
M13
A21
C9
D21
A1
H3
M1
RSV8
R12
XD21
L12
A22
A10
D22
L3
RSV9
M10
XD22
N14
A23
D9
D23
C2
X1
M2
RSV10
N11
XD23
E5
LOC
B10
D24
B1
X2/CLKIN
D12
ADVDD
P12
XD24
G1
IACK
A11
D25
P4
TCLK0
H11
ADVDD
R13
XD25
H2
INT0
C10
D26
N5
TCLK1
D4
DDVDD
R14
XD26
H1
INT1
B11
D27
E8
DDVDD
M11
XD27
J1
INT2
A12
D28
G2
XF0
L8
IODVDD
N12
XD28
J2
INT3
D10
D29
G3
XF1
M12
IODVDD
P13
XD29
D15
MC/MP
C11
D30
D3
VBBP
H5
MDVDD
R15
XD30
E3
MSTRB
B12
D31
E1
RDY
E4
VSUBS
M4
PDVDD
P15
XD31
H4
VDD
B2
CVSS
C3
DVSS
F1
RESET
F3
HOLD
D8
VDD
P14
CVSS
C13
DVSS
G4
R/W
E2
HOLDA
M8
VDD
C8
VSS
N3
DVSS
F2
STRB
D2
XRDY
H12
VDD
H3
VSS
N13
DVSS
F4
IOSTRB
D1
XR/W
N8
VSS
H13
VSS
B14
IVSS
See footnotes on next sheet.
FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
21
Device types: 01, 02, 03, 04, and 05
1/ 2/ 3/ 4/
Case outlines: U, Y, and Z
Terminal
Terminal
Terminal
Terminal
symbol
number
symbol
number
XD22
A3
118
79
Terminal
number
1
Terminal
symbol
PDVDD
Terminal
number
40
Terminal
symbol
D22
Terminal
number
157
Terminal
symbol
MSTRB
2
PDVDD
41
XD23
80
A2
119
D21
158
IOSTRB
3
DR0
42
XD24
81
4
FSR0
43
XD25
82
A1
120
D20
159
XR/W
A0
121
D19
160
HOLDA
5
CLKR0
44
XD26
6
CLKX0
45
XD27
83
EMU0
122
D18
161
HOLD
84
EMU1
123
VDD
162
MDVDD
7
FSX0
46
8
DX0
47
XD28
85
EMU2
124
VDD
163
MDVDD
XD29
86
EMU3
125
VSS
164
RDY
STRB
9
TCLK0
48
XD30
87
EMU4
126
VSS
165
10
TCLK1
49
IODVDD
88
MC/MP
127
D17
166
R/W
11
EMU6
50
DVSS
89
XA12
128
D16
167
RESET
12
XD0
51
CVSS
90
XA11
129
D15
168
XF1
13
XD1
52
CVSS
91
XA10
130
D14
169
XF0
14
XD2
53
XD31
92
XA9
131
D13
170
IACK
15
IODVDD
54
A23
93
XA8
132
D12
171
INT0
16
IODVDD
55
A22
94
XA7
133
D11
172
VDD
17
XD3
56
A21
95
XA6
134
D10
173
VDD
18
XD4
57
A20
96
IVSS
135
D9
174
VSS
19
XD5
58
A19
97
IVSS
136
D8
175
VSS
20
XD6
59
A18
98
DVSS
137
D7
176
INT1
21
XD7
60
A17
99
VSUBS
138
D6
177
INT2
22
XD8
61
A16
199
ADVDD
139
D5
178
INT3
23
XD9
62
A15
101
ADVDD
140
D4
179
RSV0
24
XD10
63
A14
102
XA5
141
D3
180
RSV1
25
VDD
64
ADVDD
103
XA4
142
D2
181
RSV2
26
VDD
65
A13
104
XA3
143
D1
182
RSV3
27
VSS
66
A12
105
XA2
144
D0
183
RSV4
28
VSS
67
A11
106
XA1
145
H1
184
RSV5
29
XD11
68
A10
107
XA0
146
H3
185
RSV6
30
XD12
69
A9
108
D31
147
DDVDD
186
RSV7
31
XD13
70
A8
109
D30
148
DVSS
187
RSV8
32
XD14
71
A7
110
D29
149
CVSS
188
RSV9
33
XD15
72
A6
111
D28
150
CVSS
189
RSV10
34
XD16
73
VDD
112
D27
151
X2/CLKIN
190
DR1
35
XD17
74
VDD
113
D26
152
X1
191
FSR1
36
XD18
75
VSS
114
DDVDD
153
VSUBS
192
CLKR1
37
XD19
76
VSS
115
D25
154
VBBP
193
CLKX1
38
XD20
77
A5
116
D24
155
EMU5
194
FSX1
39
XD21
78
A4
117
D23
156
XRDY
195
DX1
196
DVSS
1/
2/
3/
4/
ADVDD, DDVDD, IODVDD, MDVDD, and PDVDD pins are on a common plane internal to the device.
VDD pins are on a common plane internal to the device.
VSS, CVSS, and IVSS pins are on a common plane internal to the device.
DVSS pins are on a common plane internal to the device.
FIGURE 2. Terminal connections – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
22
Cases: T and M
DIE BOND PAD LOCATIONS
Die Side #1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DIE/TAB
BOND PAD
IDENTITY
TAB TEST
PAD
LOCATIONS
X COORDINATE
OF THE DIE
BOND PAD
Y COORDINATE
OF THE DIE
BOND PAD
PITCH OF LEAD (#,#)
REFERENCE WHICH DIE
BOND PADS
PDVDD
PDVDD
DR0
FSR0
CLKR0
CLKX0
FSX0
DX0
TCLK0
TCLK1
EMU6
XD0
XD1
XD2
IODVDD
IODVDD
XD3
XD4
XD5
XD6
XD7
XD8
XD9
XD10
VDD
VDD
VSS
VSS
XD11
XD12
XD13
XD14
XD15
XD16
XD17
XD18
XD19
XD20
XD21
XD22
XD23
XD24
XD25
XD26
XD27
XD28
XD29
XD30
IODVDD
IODVDD
1,2
3,4
5
6
7
8
9
10
11
12
13
14
15
16
17,18
19,20
21
22
23
24
25
26
27
28
29,30
31,32
33,34,35
36,37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58,59
60,61
-423.80
9563.00
9367.80
9199.20
9007.20
8823.20
8631.20
8447.20
8255.20
8071.20
7879.20
7695.20
7503.20
7319.20
7127.20
6947.00
6751.80
6853.20
6399.20
6207.20
6023.20
5831.20
5647.20
5455.20
5271.20
5083.00
4887.80
4731.00
4535.80
4367.20
4183.20
3991.20
3807.20
3615.20
3431.20
3239.20
3055.20
2863.20
2679.20
2487.20
2303.20
2111.20
1927.20
1735.20
1551.20
1359.20
1175.20
983.20
799.20
619.00
423.80
195.20 (1,2)
168.60 (2,3)
192.00 (3,4)
184.00 (4,5)
192.00 (5,6)
184.00 (6,7)
192.00 (7,8)
184.00 (8,9)
192.00 (9,10)
184.00 (10,11)
192.00 (11,12)
184.00 (12,13)
192.00 (13,14)
180.20 (14,15)
195.20 (15,16)
168.60 (16,17)
184.00 (17,18)
192.00 (18,19)
184.00 (19,20)
192.00 (20,21)
184.00 (21,22)
192.00 (22,23)
184.00 (23,24)
188.20 (24,25)
195.20 (25,26)
156.80 (26,27)
195.20 (27,28)
168.60 (28,29)
184.00 (29,30)
192.00 (30,31)
184.00 (31,32)
192.00 (32,33)
184.00 (33,34)
192.00 (34,35)
184.00 (35,36)
192.00 (36,37)
184.00 (37,38)
192.00 (38,39)
184.00 (39,40)
192.00 (40,41)
184.00 (41,42)
192.00 (42,43)
184.00 (43,44)
192.00 (44,45)
184.00 (45,46)
192.00 (46,47)
184.00 (47,48)
180.20 (48,49)
195.20 (49,50)
FIGURE 2. Terminal connections – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
23
Cases: T and M
DIE BOND PAD
LOCATIONS
DIE/TAB
BOND
PAD
IDENTITY
TAB TEST
PAD
LOCATIONS
X COORDINATE
OF THE DIE
BOND PAD
Y COORDINATE
0.00
195.20
374.80
570.00
746.60
938.60
1138.60
1338.60
1530.60
1730.60
1922.60
2122.60
2322.60
2514.36
2902.80
2714.60
2902.80
3098.00
3274.60
3474.60
3666.60
3866.60
4258.60
4458.60
4650.60
4846.80
5042.00
5214.80
2410.00
5578.60
5778.60
5970.60
6170.60
6370.60
6562.60
6774.80
6990.80
7198.80
7402.60
7606.80
7822.80
8026.60
8218.60
8418.60
8610.60
8810.60
9010.60
9202.60
9398.80
9594.00
9758.80
9954.00
0.00
PITCH OF LEAD (#,#)
REFERENCE WHICH DIE
BOND PADS
OF THE DIE
BOND PAD
Die Side #2
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
DVSS
DVSS
CVSS
CVSS
XD31
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
ADVDD
ADVDD
A13
A12
A11
A10
A9
A8
A7
A6
VDD
VDD
VSS
VSS
A5
A4
A3
A2
A1
A0
EMU0
EMU1
EMU2
EMU3
EMU4
MC/MP
XA12
XA11
XA10
XA9
XA8
XA7
XA6
IVSS
IVSS
DVSS
DVSS
62,63
64
65,66
67
68
69
70
71
72
73
74
75
76
77
78
79,80
81
82
83
84
85
86
87
88
89
90,91
92,93
94,95
96,97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117,118
119
120,121
122
195.20 (51,52)
179.60 (52,53)
195.20 (53,54)
176.60 (54,55)
192.00 (55,56)
200.00 (56,57)
200.00 (57,58)
192.00 (58,59)
200.00 (59,60)
192.00 (60,61)
200.00 (61,62)
200.00 (62,63)
192.00 (63,64)
200.00 (64,65)
188.20 (65,66)
195.20 (66,67)
176.60 (67,68)
200.00 (68,69)
192.00 (69,70)
200.00 (70,71)
200.00 (71,72)
192.00 (72,73)
200.00 (73,74)
192.00 (74,75)
196.20 (75,76)
195.20 (76,77)
172.80 (77,78)
195.20 (78,79)
168.60 (79,80)
200.00 (80,81)
192.00 (81,82)
200.00 (82,83)
200.00 (83,84)
192.00 (84,85)
212.20 (85,86)
216.00 (86,87)
208.00 (87,88)
203.80 (88,89)
204.20 (89,90)
216.00 (90,91)
203.80 (91,92)
192.00 (92,93)
200.00 (93,94)
192.00 (94,95)
200.00 (95,96)
200.00 (96,97)
192.00 (97,98)
196.20 (98,99)
195.20 (99,100)
164.80 (100,101)
195.20 (101,102)
FIGURE 2. Terminal connections – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
24
Cases: T and M
DIE BOND PAD
LOCATIONS
DIE/TAB
BOND
PAD
IDENTITY
TAB TEST
PAD
LOCATIONS
X COORDINATE
OF THE DIE
BOND PAD
Y COORDINATE
10377.80
430.60
625.80
764.40
986.40
1170.40
1362.40
1546.40
1738.40
1922.40
2114.40
2298.40
2490.40
2674.40
2866.40
3046.60
3241.80
3410.40
3594.40
3786.40
3970.40
4162.40
4346.40
4538.40
4722.40
4910.60
5105.80
5262.60
5457.80
5626.40
5810.40
6002.40
6186.40
6378.40
6562.40
6754.40
6938.40
7130.40
7314.40
7506.40
7690.40
7882.40
8066.40
8258.40
8442.40
8634.40
8818.40
9010.40
9194.40
9374.60
9569.80
PITCH OF LEAD (#,#)
REFERENCE WHICH DIE
BOND PADS
OF THE DIE
BOND PAD
Die Side #3
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
ADVDD
ADVDD
XA5
XA4
XA3
XA2
XA1
XA0
D31
D30
D29
D28
D27
D26
DDVDD
DDVDD
D25
D24
D23
D22
D21
D20
D19
D18
VDD
VDD
VSS
VSS
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
H1
H3
DDVDD
DDVDD
123,124
125,126
127
128
129
130
131
132
133
134
135
136
137
138
139,140
141,142
143
144
145
146
147
148
149
150
151,152
153,154,155
156,157
158,159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180,181
182,183
195.20 (103,104)
168.60 (104,105)
192.00 (105,106)
184.00 (106,107)
192.00 (107,108)
184.00 (108,109)
192.00 (109,110)
184.00 (110,111)
192.00 (111,112)
184.00 (112,113)
192.00 (113,114)
184.00 (114,115)
192.00 (115,116)
180.20 (116,117)
195.20 (117,118)
168.60 (118,119)
184.00 (119,120)
192.00 (120,121)
184.00 (121,122)
192.00 (122,123)
184.00 (123,124)
192.00 (124,125)
184.00 (125,126)
188.20 (126,127)
195.20 (127,128)
156.80 (128,129)
195.20 (129,130)
168.60 (130,131)
184.00 (131,132)
192.00 (132,133)
184.00 (133,134)
192.00 (134,135)
184.00 (135,136)
192.00 (136,137)
184.00 (137,138)
192.00 (138,139)
184.00 (139,140)
192.00 (140,141)
184.00 (141,142)
192.00 (142,143)
184.00 (143,144)
192.00 (144,145)
184.00 (145,146)
192.00 (146,147)
184.00 (147,148)
192.00 (148,149)
184.00 (149,150)
180.20 (150,151)
195.20 (151,152)
FIGURE 2. Terminal connections – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
25
Cases: T and M
DIE BOND PAD
LOCATIONS
DIE/TAB
BOND
PAD
IDENTITY
TAB TEST
PAD
LOCATIONS
X COORDINATE
OF THE DIE
BOND PAD
Y COORDINATE
9947.20
9752.00
9587.20
9392.00
9217.00
9043.80
8696.00
8535.40
7935.40
7739.40
7551.40
7359.40
7175.40
6991.40
6795.20
6611.20
6416.00
6243.20
6055.40
5863.40
5667.20
5479.40
5295.40
5111.40
4915.20
4731.20
4536.00
4371.20
4176.00
4003.20
3803.20
3603.20
3403.20
3203.20
3003.20
2795.20
2595.20
2407.40
2223.40
2039.40
1855.40
1671.40
1479.40
1295.40
1111.40
927.40
743.40
559.40
375.40
195.20
0.00
9993.60
9993.60
9993.60
9993.60
9986.80
9986.80
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
9993.60
PITCH OF LEAD (#,#)
REFERENCE WHICH DIE
BOND PADS
OF THE DIE
BOND PAD
Die Side #4
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
DVSS
DVSS
CVSS
CVSS
X2/CLKIN
X1
VSUBS
VBBP
EMU5
XRDY
MSTRB
IOSTRB
XRW
HOLDA
HOLD
MDVDD
MDVDD
RDY
STRB
R/W
RESET
XF1
XF0
IACK
INT0
VDD
VDD
VSS
VSS
INT1
INT2
INT3
RSV0
RSV1
RSV2
RSV3
RSV4
RSV5
RSV6
RSV7
RSV8
RSV9
RSV10
DR1
FSR1
CLKR1
CLKX1
FSX1
DX1
DVSS
DVSS
184
185,186
187
188,189
190
191
192,193
194
195
196
197
198
199
200
201
202
203,204
205
206
207
208
209
210
211
212
213,214
215,216
217,218
219,220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241,242
243,244
195.20 (153,154)
164.80 (154,155)
195.20 (155,156)
175.00 (156,157)
173.20 (157,158)
347.80 (158,159)
160.60 (159,160)
600.00 (160,161)
196.00 (161,162)
188.00 (162,163)
192.00 (163,164)
184.00 (164,165)
184.00 (165,166)
196.20 (166,167)
184.00 (167,168)
195.20 (168,169)
172.80 (169,170)
187.80 (170,171)
192.00 (171,172)
196.20 (172,173)
187.80 (173,174)
184.00 (174,175)
184.00 (175,176)
196.20 (176,177)
184.00 (177,178)
195.20 (178,179)
164.80 (179,180)
195.20 (180,181)
172.80 (181,182)
200.00 (182,183)
200.00 (183,184)
200.00 (184,185)
200.00 (185,186)
200.00 (186,187)
208.00 (187,188)
200.00 (188,189)
187.80 (189,190)
184.00 (190,191)
184.00 (191,192)
184.00 (192,193)
184.00 (193,194)
192.00 (194,195)
184.00 (195,196)
184.00 (196,197)
184.00 (197,198)
184.00 (198,199)
184.00 (199,200)
184.00 (200,201)
180.20 (201,202)
195.20 (202,203)
FIGURE 2. Terminal connections – Continued.
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FIGURE 3. Functional block diagram.
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Where: IOL = 2.0 mA (all outputs)
IOH = 300 μA (all outputs)
VLoad = 1.54 V to emulate 50Ω
CT = 80 pF typical load circuit capacitance.
FIGURE 4. Switching waveforms and test circuit.
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X2/CLKIN timing
H1/H3 timing
FIGURE 4. Switching waveforms and test circuit – Continued.
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Memory ((M)STRB = 0) Read
FIGURE 4. Switching waveforms and test circuit – Continued.
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Memory ((M)STRB = 0) Write
Memory ((IO)STRB = 0) Read
FIGURE 4. Switching waveforms and test circuit – Continued.
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Memory ((IO)STRB = 0) Write
FIGURE 4. Switching waveforms and test circuit – Continued.
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Timing XF0 and XF1 when executing LDF1 or LDII
Timing for XF0 when executing a STF1 or STII
FIGURE 4. Switching waveforms and test circuit – Continued.
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Timing for XF0 and XF1 when executing SIGI
Timing for loading XF register when configured as an output pin
FIGURE 4. Switching waveforms and test circuit – Continued.
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Change of XF from output to input mode
Change of XF from input to output mode
FIGURE 4. Switching waveforms and test circuit – Continued.
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RESET Timing
NOTES:
1. RESET is asynchronous input and can be asserted at any point during a clock cycle. If the specified timings
are met, the exact sequence shown will occur; otherwise, an additional delay of one clock cycle may occur.
2. Note that the R/W outputs are placed in a high impedance state during reset and can be provided with a resistive
pull-up, nominally 20 KΩ if desirable spurious writes could be caused when these outputs go low.
3. (X)D includes D(31-0) and XD(31-0).
4. (X)A includes A(23-0), XA(12-0).
5. Control signals include STRB, MSTRB, and IOSTRB
6. Asynchronously reset signals include XF1, XF0, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1,
DR1, FSR1, TCLK0, and TCLK1.
FIGURE 4. Switching waveforms and test circuit – Continued.
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INT(3-0) response timing
NOTES:
7. Interrupt pulse width must be at least 1 P wide to guarantee it will be seen. It must be less
than 2 P wide to guarantee it will be responded to only once. The recommended pulse width is 1.5 P.
8. INT is an asynchronous input and can be asserted at any point during a clock cycle. If the
specified timings are met, the exact sequence shown will occur; otherwise, an additional delay
of one clock cycle may occur.
IACK timing
NOTE 9:
The IACK output is active for the entire duration of the bus cycle and is therefore extended if
the bus cycle utilizes wait states.
FIGURE 4. Switching waveforms and test circuit – Continued.
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Fixed data rate mode
NOTES:
10. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
11. These timings are valid for all serial port modes, including handshake, except where otherwise indicated.
Variable data rate mode
NOTES:
12. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
13. Timings not expressly specified for variable data rate mode are the same as those for fixed data rate mode.
14. Timings are valid for all serial port modes, including handshake mode, except where otherwise indicated.
FIGURE 4. Switching waveforms and test circuit – Continued.
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HOLD/HOLDA timing
NOTE 15: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings
are met, the exact sequence shown will occur; otherwise, an additional delay of one clock cycle may occur.
Peripheral pin general-purpose I/O timing
NOTE 16: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of
these pins are defined by the contents of internal control registers associated with each peripheral.
Timer pin timings
NOTE 17: Period and polarity of valid logic level are specified by contents of internal control registers.
FIGURE 4. Switching waveforms and test circuit – Continued.
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Change of peripheral pin from general purpose output to input mode
Change of peripheral pin from general-purpose input to output mode
FIGURE 4. Switching waveforms and test circuit – Continued.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 and appendix F of MIL-PRF-38535, or as modified in the device manufacturer's Quality Management (QM) plan.
The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and
inspection procedures shall be in accordance with MIL-PRF-38535, appendix A, and appendix F of MIL-PRF-38535.
4.2
Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and appendix F of
MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For
device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and appendix F of MIL-PRF-38535, and
shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 and appendix F of MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein.
Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and, appendix F of
MIL-PRF-38535, and as specified herein. Inspections to be performed for device class M shall be those specified in method
5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
STANDARD
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4.4.1 Group A inspection.
a.
Tests shall be as specified in table II herein.
b.
Subgroup 4 (CIN, COUT and CX measurements) shall be measured only for the initial test and after process or
design changes which may affect capacitance. A minimum sample size of five devices with zero rejects shall be
required.
c.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
d.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
TABLE II. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
---
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class Q
---
Device
class V
---
1/ 1, 2, 3, 7, 8, 9, 10,
11
1/ 1, 2, 3, 7,
8, 9, 10, 11
2/ 1, 2, 3, 7,
8, 9, 10, 11
1, 2, 3, 4, 7, 8, 9, 10,
11
1, 2, 3, 4, 7, 8,
9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
2, 8a, 10
2, 8a, 10
2, 8a, 10
2, 8a, 10
2, 8a, 10
2, 8a, 10
2, 8a, 10
2, 8a, 10
2, 8a, 10
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
4.4.2 Group B inspection.
a. Attachability is not a requirement of Case outlines T and M.
b. For Case outlines T and M bond strength (method 2011) shall not be less than 30 g.
c. For Case outlines T and M constant acceleration in accordance with Method 2001 test condition E, Y1 direction,
is required. 4 devices are to be tested with zero failures.
4.4.3 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
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4.4.3.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005 of MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.3.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.4 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.5 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table II herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table II herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
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6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331 and as follows:
PIN
Name
Numbers
I/O/Z
1/
Description
Primary bus interface
D31-D0
A23-A0
32
24
I/O/Z
O/Z
R/W
1
O/Z
STRB
1
O/Z
RDY
1
I
HOLD
1
I
HOLDA
1
O
32-bit data port of the primary bus interface.
24-bit address port of the primary bus interface.
Read/write signal for primary bus interface. This pin is high when a read is
performed and low when a write is performed over the parallel interface.
External access strobe for the primary bus interface.
Ready signal. This pin indicates that the external device is prepared for a
primary bus interface transaction to complete. As long as RDY is a logic
high, the data and address buses of the primary bus interface remain valid.
Hold signal for primary bus interface. When HOLD is a logic low, any
ongoing transaction is completed. The A23-A0, D31-D0, STRB and R/W
signals are placed in a high-impedance state, and all transactions over the
primary bus interface are held until HOLD becomes a logic high.
Hold acknowledge signal for primary bus interface. This signal is generated
in response to a logic low on HOLD. It signals that A23-A0, D31-D0, STRB
and R/W are placed in a high-impedance state and that all transactions over
the bus will be held. HOLDA will be high in response to logic high of HOLD.
Expansion bus interface
XD31-XD0
XA12-XA0
32
13
I/O/Z
O/Z
32-bit data port of the expansion bus interface.
13-bit address port of the expansion bus interface.
Read/write signal for expansion bus interface. When a read is performed,
this pin is held high; when a write is performed, this pin is low.
XR/W
1
O/Z
MSTRB
1
O
External memory access strobe for the expansion bus interface.
IOSTRB
1
O
XRDY
1
I
External I/O access strobe for the expansion bus interface.
Ready signal. This pin indicates that the external device is prepared for an
expansion bus interface transaction to complete. As long as XRDY is high,
the data and address buses of the expansion bus interface remain valid.
Control signals
RESET
1
I
Reset. When RESET is a logic low, the device is placed in the reset
condition. When RESET becomes a logic high, execution begins from the
location specified by the reset vector.
INT3-INT0
4
I
External interrupts.
IACK
1
O
Interrupt acknowledge signal. IACK is set to a logic high by the IACK
instruction. IACK can be used to indicate the beginning or end of an
interrupt service routine.
MC/MP
XF1, XF0
1
2
I
I/O
Microcomputer/microprocessor mode pin.
External flag pins. They are used as general-purpose I/O pins or to support
interlocked processor instructions.
See footnotes at end of table.
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6.5 Abbreviations, symbols, and definitions – Continued.
Name
PIN
Numbers
I/O/Z
1/
Description
Serial port 0 signals
CLKX0
1
I/O
DX0
FSX0
1
1
O/Z
I/O
CLKR0
1
I/O
DR0
FSR0
1
1
I
I
Serial port 0 transmit clock. This pin serves as the serial shift clock
for the serial port 0 transmitter.
Data transmit output. Serial port 0 transmits serial data on this pin.
Frame synchronization pulse for transmit. The FSX0 pulse initiates the
transmit data process over pin DX0.
Serial port 0 receive clock. This pin serves as the serial shift clock for
the serial port 0 transmitter.
Data receive. Serial port 0 receives serial data via the DR0 pin.
Frame synchronization pulse for receive. The FSR0 pulse initiates the
receive data process over DR0.
Serial port 1 signals
CLKX1
1
I/O
DX1
FSX1
1
1
O/Z
I/O
CLKR1
1
I/O
DR1
FSR1
1
1
I
I
Serial port 1 transmit clock. This pin serves as the serial shift clock
for the serial port 1 transmitter
Data transmit output. Serial port 1 transmits serial data on this pin.
Frame synchronization pulse for transmit. The FSX1 pulse initiates the
transmit data process over pin DX1.
Serial port 1 receive clock. This pin serves as the serial shift clock for
the serial port 1 transmitter.
Data receive. Serial port 1 receives serial data via the DR1 pin.
Frame synchronization pulse for receive. The FSR1 pulse initiates the
receive data process over DR1.
Timer 0 signals
TCLK0
1
I/O
Timer clock. As an input, TCLK0 is used by timer 0 to count external
pulses. As an output pin, TCLK0 outputs pulses generated by timer 0.
Timer 1 signals
TCLK1
1
I/O
Timer clock. As an input, TCLK1 is used by timer 1 to count external
pulses. As an output pin, TCLK1 outputs pulses generated by timer 1.
Supply and oscillator signals 2/
VDD
IODVDD
ADVDD
PDVDD
DDVDD
MDVDD
VSS
DVSS
CVSS
IVSS
4/8
2/3
2/3
1/2
2/2
1/2
4/8
4/4
2/4
1/2
I
I
I
I
I
I
I
I
I
I
+5 V supply pin.
+5 V supply pin.
+5 V supply pin.
+5 V supply pin.
+5 V supply pin.
+5 V supply pin.
Ground pin.
Ground pin.
Ground pin.
Ground pin.
See footnotes at end of table.
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6.5 Abbreviations, symbols, and definitions – Continued.
PIN
Name
Numbers
I/O/Z
1/
Description
Supply and oscillator signals 2/ - Continued.
VBBP
VSUBS
X1
1/1
1/2
1
NC
I
O
X2/CLKIN
H1
H3
1
1
1
I
O
O
VBB pump oscillator output.
Substrate pin. Tie to ground.
Output pin from the internal oscillator for the crystal. If a crystal is not
used, this pin should be left unconnected.
Input pin to the internal oscillator from the crystal or a clock.
External H1 clock. This clock has a period equal to twice CLKIN.
External H3 clock. This clock has a period equal to twice CLKIN.
Reserved
EMU0-EMU2
EMU3
EMU4
EMU5,EMU6
RSV0-RSV10
1/
2/
3
1
1
2
11
I
O
I
NC
I
Reserved. Use pullups to +5 V.
Reserved.
Reserved. Use pullups to +5 V.
Reserved.
Reserved. Use pullups to +5 V.
I = input,
O = output,
Z = high impedance state,
NC = no connection.
Case X and Y power pins.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Application note. Devices supplied to this drawing have been known to exhibit cold start sensitivity. Contact the device
manufacturer for further information or see the manufacturer’s literature, SGUA001, for more detail information.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
46
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number
(PIN). When available a choice of Radiation Hardness Assurance (RHA) level is reflected in the PIN.
A.1.2 PIN. The PIN shall be as shown in the following example:
5962
-
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
90526
04
Q
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
details
(see A.1.2.4)
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels. A
dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
Generic number
04
05
320C30
320C30
Circuit function
Digital signal processor, 40 MHz
Digital signal processor, 50 MHz
A.1.2.3 Device class designator.
Device class
Q or V
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
47
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
A.1.2.4 Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.4.1 Die Physical dimensions.
Die Types
Figure number
04
05
A-1
A-1
A.1.2.4.2 Die Bonding pad locations and Electrical functions.
Die Types
Figure number
04
05
A-1
A-1
A.1.2.4.3 Interface Materials.
Die Types
Figure number
04
05
A-1
A-1
A.1.2.4.4 Assembly related information.
Die Types
Figure number
04
05
A-1
A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 within the body of this drawing for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 within the body of this drawing for details.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
48
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
A.2 APPLICABLE DOCUMENTS
A.2.1 Government specification, standard, and handbooks. The following specification, standard, and handbook s form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOK
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations
unless a specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item Requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535 and herein and the manufacturer’s QM plan, for device classes Q and V.
A.3.2.1 Die Physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and figure A-1.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
49
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table I.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN
listed in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a) Wafer Lot acceptance for Class V product using the criteria defined within MIL-STD-883 TM 5007.
b) 100% wafer probe (see paragraph A.3.4).
c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 TM2010 or the
alternate procedures allowed within MIL-STD-883 TM5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table II herein. Group E tests and conditions are as specified in paragraph 4.4.5 herein.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
50
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be in accordance with the manufacturer’s QM plan
or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43218-3990 or telephone
(614)-692-0547.
A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined with
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA and have
agreed to this drawing.
A.6.5 Application note. Devices supplied to this drawing have been known to exhibit cold start sensitivity. Contact the
device manufacturer for further information or see the manufacturer’s literature, SGUA001, for more detail information.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
51
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
Die bonding pad locations and electrical functions.
Die physical dimensions.
Die Size:
Die Thickness:
7006 x 8456 microns.
15 ± 1 mils.
Interface materials.
Top Metallization:
SiAl
Backside Metallization:
None
9.0kA ±1kA
Glassivation.
Type:
Thickness:
SiO2
8.0kA ±1kA
Substrate:
Silicon on Sapphire (SOS)
Assembly related information.
Substrate Potential:
Insulator
Special assembly
instructions:
Bond a VDD pad first.
FIGURE A-1. Die bonding pad locations and electrical functions.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
52
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
The following metallization diagram supplies the locations and electrical functions of the bonding pads. The internal metallization
layout and alphanumeric information contained within this diagram may or may not represent the actual circuit defined by this
SMD.
Die-Numbering Format
FIGURE A-1. Die bonding pad locations and electrical functions - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
53
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
PAD
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PAD
FUNCTION
PDVDD
PDVDD
DR0
FSR0
CLXRO
CLKX0
FSX0
DX0
TCLK0
TCLK1
PADTOG
IOD0
IOD1
IOD2
IODVDD
IODVDD
IOD3
IOD4
IOD5
IOD6
IOD7
IOD8
IOD9
IOD10
VDDL
VDDL
DVSS
VSSL
CVSS
IOD11
IOD12
IOD13
IOD14
IOD15
IOD16
IOD17
IOD18
IOD19
IOD20
IOD21
IOD22
IOD23
IOD24
IOD25
IOD26
PITCH
TAB COORDINATES
X COORD
Y COORD
6778.434
617.994
6778.434
745.134
6778.434
869.154
6778.434
986.154
6778.434
1125.306
6778.434
1272.258
6778.434
1476.774
6778.434
2146.17
6778.434
2283.294
6778.434
2420.418
6778.434
2537.418
6778.434
2654.418
6778.434
2771.418
6778.434
2908.542
6778.434
3045.666
6778.434
3162.666
6778.434
3299.79
6778.434
3436.914
6778.434
3553.914
6778.434
3691.038
6778.434
3828.162
6778.434
3945.162
6778.434
4062.162
6778.434
4199.286
6778.434
4336.41
6778.434
4453.41
6778.434
4574.466
6778.434
4699.422
6778.434
4838.574
6778.434
4988.49
6778.434
5145.738
6778.434
5295.342
6778.434
5444.946
6778.434
5594.55
6778.434
5744.154
6778.434
5893.758
6778.434
6037.122
6778.434
6154.122
6778.434
6271.122
6778.434
6388.122
6778.434
6505.122
6778.434
6622.122
6778.434
6739.122
6778.434
6856.122
6778.434
7129.122
127.14
124.02
117
139.152
146.952
204.516
669.396
137.124
137.124
117
117
117
137.124
137.124
117
137.124
137.124
117
137.124
137.124
117
117
137.124
137.124
117
121.056
124.956
139.152
149.916
157.248
149.604
149.604
149.604
149.604
149.604
143.364
117
117
117
117
117
117
117
273
135.72
DIE PAD
FIGURE A-1. Die bonding pad locations and electrical functions - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
54
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
PAD
NO.
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
PAD
FUNCTION
IOD27
IOD28
IOD29
IOD30
IODVDD
IODVDD
DVSS
VSSL
IVSS
CVSS
IOD31
A(23)
A(22)
A(21)
A(20)
A(19)
A(18)
A(17)
A(16
A(15)
A(14)
ADVDD
ADVDD
A(13)
A(12)
A(11)
A(10)
A(9)
A(8)
A(7)
A(6)
VDDL
VDDL
DVSS
CVSS
A(5)
A(4)
A(3)
A(2)
A(1)
A(0)
C0
C1
SCANIN
SCANOUT
PITCH
TAB COORDINATES
X COORD
Y COORD
6778.434
7264.842
6778.434
7400.562
6778.434
7536.282
6778.434
7672.002
6778.434
7807.878
6437.262
8228.766
6320.262
8228.766
6203.262
8228.766
6086.262
8228.766
5969.262
8228.766
5852.262
8228.766
5735.262
8228.766
5618.262
8228.766
5501.262
8228.766
5384.262
8228.766
5267.262
8228.766
5144.022
8228.766
5027.022
8228.766
4910.022
8228.766
4793.022
8228.766
4676.022
8228.766
4559.022
8228.766
4442.022
8228.766
4325.022
8228.766
4208.022
8228.766
4091.022
8228.766
3974.022
8228.766
3857.022
8228.766
3740.022
8228.766
3623.022
8228.766
3506.022
8228.766
3385.434
8228.766
3264.066
8228.766
3147.066
8228.766
3030.066
8228.766
2913.066
8228.766
2796.066
8228.766
2679.066
8228.766
2562.066
8228.766
2445.066
8228.766
2328.066
8228.766
2211.066
8228.766
2094.066
8228.766
1977.066
8228.766
1860.066
8228.766
135.72
135.72
135.72
135.876
117
117
117
117
117
117
117
117
117
117
123.24
117
117
117
117
117
117
117
117
117
117
117
117
117
117
120.588
121.368
117
117
117
117
117
117
117
117
117
117
117
117
117
DIE PAD
FIGURE A-1. Die bonding pad locations and electrical functions - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
55
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
PAD
NO.
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
PAD
FUNCTION
MCS
MCMPIOA12
IOA11
IOA10
IOA9
IOA8
IOA7
IOA6
CVSS
IVSS
VSSL
DVSS
ADVDD
ADVDD
IOA5
IOA4
IOA3
IOA2
IOA1
IOA0
D31
D30
D29
D28
D27
D26
DDVDD
DDVDD
D25
D24
D23
D22
D21
D20
D19
D18
VDDL
VDDL
DVSS
CVSS
VSSL
D17
D16
D15
PITCH
TAB COORDINATES
X COORD
Y COORD
1743.066
8228.766
1626.066
8228.766
1509.066
8228.766
1392.066
8228.766
1275.066
8228.766
1158.066
8228.766
1041.066
8228.766
924.066
8228.766
807.066
8228.766
686.166
8228.766
569.166
8228.766
227.214
7696.65
227.214
7575.75
227.214
7458.594
227.214
7341.594
227.214
7168.434
227.214
7026.474
227.214
6878.274
227.214
6748.794
227.058
6531.954
227.058
6414.954
227.058
6297.954
227.058
6149.754
227.058
6032.754
227.058
5915.754
227.058
5767.554
227.058
5650.554
227.058
5533.554
227.058
5366.634
227.214
5237.154
227.214
5107.674
227.214
4978.194
227.214
4848.714
227.214
4719.234
227.214
4577.274
227.214
4460.274
227.214
4318.314
227.214
4201.314
227.214
4076.046
227.214
3950.778
227.214
3813.03
227.214
3677.154
227.214
3541.434
227.214
3405.714
227.214
3269.994
117
117
117
117
117
117
117
117
120.9
117
120.9
117.156
117
173.16
141.96
148.2
129.48
216.84
117
117
148.2
117
117
148.2
117
117
166.92
129.48
129.48
129.48
129.48
129.48
141.96
117
141.96
117
125.268
125.268
137.748
135.876
135.72
135.72
135.72
135.72
DIE PAD
FIGURE A-1. Die bonding pad locations and electrical functions - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
56
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
PAD
NO.
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
PAD
FUNCTION
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
H1
H3
DDVDD
DDVDD
DVSS
VSSL
IVSS
CVSS
X2
X1
VSUBS
BNKSELIORDYMSTRBIOSTRB
IORWHOLDAHOLDMDVDD
MDVDD
RDYSTRBRWRESETXF1
XF0
IACKINT0-|
VDDL
PITCH
TAB COORDINATES
X COORD
Y COORD
227.214
3134.274
227.214
2978.43
227.214
2802.462
227.214
2626.494
227.214
2470.65
227.214
2314.806
227.214
2138.838
227.214
2001.714
227.214
1872.234
227.214
1742.754
227.214
1613.274
227.214
1483.794
227.214
1354.314
227.214
1224.834
227.214
1014.234
227.214
884.754
227.214
755.274
227.214
625.482
569.166
227.214
686.166
227.214
803.166
227.214
920.166
227.214
1037.166
227.214
1154.166
227.214
1271.166
227.214
1388.166
227.214
1511.406
227.214
1628.406
227.214
1745.406
227.214
1862.406
227.214
1979.406
227.214
2096.406
227.214
2213.406
227.214
2330.406
227.214
2447.406
227.214
2564.406
227.214
2681.406
227.214
2798.406
227.214
2915.406
227.214
3032.406
227.214
3149.406
227.214
3266.406
227.214
3383.406
227.214
3500.406
227.214
155.844
175.968
175.968
155.844
155.844
175.968
137.124
129.48
129.48
129.48
129.48
129.48
129.48
210.6
129.48
129.48
129.792
117
117
117
117
117
117
117
123.24
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
118.092
DIE PAD
FIGURE A-1. Die bonding pad locations and electrical functions - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
57
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90526
PAD
NO.
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
PAD
FUNCTION
VDDL
VSSL|
IVSS
INT1INT2INT3INT4INT5INT6INT7INT8INTS0TINTS0R-IN
INTS1T-OUT
INTS1RINTT0INTT1DR1
FSR1
CLKR1
CLKX1
FSX1
DX1
CVSS
DVSS
PITCH
TAB COORDINATES
X COORD
Y COORD
3618.498
227.214
3742.206
227.214
3859.206
227.214
3976.206
227.214
4093.206
227.214
4210.206
227.214
4327.206
227.214
4444.206
227.214
4561.206
227.214
4678.206
227.214
4795.206
227.214
4912.206
227.214
5029.206
227.214
5146.206
227.214
5263.206
227.214
5380.206
227.214
5497.206
227.214
5614.206
227.214
5731.206
227.214
5848.206
227.214
5965.206
227.214
6082.206
227.214
6199.206
227.214
6316.206
227.214
6433.206
227.214
123.708
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
117
DIE PAD
FIGURE A-1. Die bonding pad locations and electrical functions - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90526
A
REVISION LEVEL
N
SHEET
58
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 08-11-17
Approved sources of supply for SMD 5962-90526 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/ .
1/
2/
3/
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
Number
Vendor
Similar
PIN 2/
5962-9052601MUX
5962-9052601MXX
5962-9052601MYX
5962-9052601MZX
3/
3/
3/
3/
SMJ320C30HFGM28
SMJ320C30GBM28
SMJ320C30HUM28
SMJ320C30HTM28
5962-9052602MUX
5962-9052602MXX
5962-9052602MYX
5962-9052602MZX
3/
3/
3/
3/
SMJ320C30HFGM25
SMJ320C30GBM25
SMJ320C30HUM25
SMJ320C30HTM25
5962-9052603MUA
5962-9052603MXA
5962-9052603QTC
5962-9052603QMC
3/
3/
3/
3/
SMJ320C30HFGM33
SMJ320C30GBM33
SMJ320C30TAM33
SMJ320C30TBM33
5962-9052604MUA
5962-9052604MXA
5962-9052604Q9A
5962-9052604Q9B
01295
01295
3/
01295
SMJ320C30HFGM40
SMJ320C30GBM40
SMJ320C30KGDM40B
SMJ320C30KGDM40C
5962-9052605MUA
5962-9052605MXA
5962-9052605QXC
5962-9052605Q9A
5962-9052605Q9B
01295
01295
01295
3/
01295
SMJ320C30HFGM50
SMJ320C30GBM50
SMJ320C30GBM50
SMJ320C30KGDM50B
SMJ320C30KGDM50C
The lead finish shown for each PIN representing a hermetic package is the
most readily available from the manufacturer listed for that part. If the desired
lead finish is not listed contact the Vendor to determine its availability.
Caution. Do not use this number for item acquisition. Items acquired to this
number may not satisfy the performance requirements of this drawing.
Not available from an approved source of supply.
Vendor CAGE
number
01295
Vendor name
and address
Texas Instruments Inc.
Semiconductor Group
8505 Forest Ln.
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.