SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 2x2 LVPECL CROSSPOINT SWITCH FEATURES • • • • • • • • • • High Speed 2x2 LVPECL Crosspoint Switch LVDS Crosspoint Switch Available in SN65LVCP22 50 ps (Typ), of Peak-to-Peak Jitter With PRBS = 223– 1 Pattern Output (Channel-to-Channel) Skew Is 10 ps (Typ), 50 ps (Max) Configurable as 2:1 Mux, 1:2 Demux, Repeater or 1:2 Signal Splitter Inputs Accept LVDS, LVPECL, and CML Signals Fast Switch Time of 1.7 ns (Typ) Fast Propagation Delay of 0.75 ns (Typ) 16 Lead SOIC and TSSOP Packages Operating Temperature: –40°C to 85°C APPLICATIONS • • • • • • • • • Gigabit Ethernet Redundant Transmission Paths Gigabit Interface Converters (GBICs) Fibre Channel Redundant Transmission Paths HDTV Video Routing Base Stations Protection Switching for Serial Backplanes Network Switches/Routers Optical Networking Line Cards/Switches Clock Distribution DESCRIPTION The SN65LVCP23 is a 2x2 LVPECL crosspoint switch. The dual channels incorporate wide common-mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals. The dual outputs are LVPECL drivers to provide high-speed operation. The SN65LVCP23 provides a single device supporting 2:2 buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2 switching, and LVDS/CML to LVPECL level translation on each channel. The flexible operation of the SN65LVCP23 provides a single device to support the redundant serial bus transmission needs (working and protection switching cards) of fault-tolerant switch systems found in optical networking, wireless infrastructure, and data communications systems. TI offers an additional gigabit repeater/translator in the SN65LVDS101. The SN65LVCP23 uses a fully differential data path to ensure low-noise generation, fast switching times, low pulse width distortion, and low jitter. Output channel-to-channel skew is less than 10 ps (typ) and 50 ps (max) to ensure accurate alignment of outputs in all applications. Both SOIC and TSSOP package options are available. OUTPUTS OPERATING SIMULTANEOUSLY 1.3 Gbps 223 -1 PRBS OUTPUT 1 VCC = 3.3 V |VID| = 200 mV, VIC = 1.2 V Vertical Scale = 400 mV/div OUTPUT 2 650 MHz Horizontal Scale = 200 ps Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2006, Texas Instruments Incorporated SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER (1) SYMBOLIZATION SOIC SN65LVCP23D LVCP23 TSSOP SN65LVCP23PW LVCP23 PACKAGE DESIGNATOR (1) Add the suffix R for taped and reeled carrier PACKAGE DISSIPATION RATINGS (1) (2) PACKAGE CIRCUIT BOARD MODEL TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING SOIC (D) High-K (2) 1361 mW 13.9 mW/°C 544 mW TSSOP (PW) High-K (2) 1074 mW 10.7 mW/°C 430 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the High-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICS PARAMETER θJB TEST CONDITIONS Junction-to-board thermal resistance θJC Junction-to-case thermal resistance PD Device power dissipation VALUE UNITS D 15.7 °C/W PW 22.1 °C/W D 26.1 °C/W PW 17.3 °C/W Typical VCC = 3.3 V, TA = 25°C, 2 Gbps 165 mW Maximum VCC = 3.6 V, TA = 85°C, 2 Gbps 234 mW FUNCTIONAL BLOCK DIAGRAM OUT 0 OUT 1 EN 0 EN 1 SEL 1 SEL 0 0 1 0 IN 0 IN 1 2 Submit Documentation Feedback 1 SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 CIRCUIT FUNCTION TABLE INPUTS (1) OUTPUTS (1) IN 0 IN 1 SEL 0 SEL1 EN 0 EN 1 OUT 0 OUT 1 X X X X L L L L >100 mV X L L H L H L <-100 mV X L L H L L L <-100 mV X L L H H L L >100 mV X L L H H H H >100 mV X L L L H L H <-100 mV X L L L H L L >100 mV X L H H L H L <-100 mV X L H H L L L <-100 mV <-100 mV L H H H L L <-100 mV >100 mV L H H H L H >100 mV <-100 mV L H H H H L >100 mV >100 mV L H H H H H X >100 mV L H L H L H X <-100 mV L H L H L L X >100 mV H H H L H L X <-100 mV H H H L L L X <-100 mV H H H H L L X >100 mV H H H H H H X >100 mV H H L H L H X <-100 mV H H L H L L X >100 mV H L H L H L X <-100 mV H L H L L L <-100 mV <-100 mV H L H H L L <-100 mV >100 mV H L H H H L >100 mV <-100 mV H L H H L H >100 mV >100 mV H L H H H H >100 mV X H L L H L H <-100 mV X H L L H L L (1) LOGIC DIAGRAM EN 0 IN 0 OUT 0 IN 1 OUT 1 EN 1 EN 0 IN 0 OUT 0 IN 1 OUT 1 EN 1 EN 0 IN 0 OUT 0 IN 1 OUT 1 EN 1 EN 0 IN 0 OUT 0 IN 1 OUT 1 EN 1 H = High level, L = Low level, Z = High impedance, X = Don't care Submit Documentation Feedback 3 SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS INPUTS IN + VCC IN - 400 Ω SEL, EN 7V 7V 7V OUTPUTS VCC VCC R R VCC R OUT + VCC 7V OUT - 7V 4 300 kΩ Submit Documentation Feedback SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNITS Supply voltage range, (2) VCC –0.5 V to 4 V CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1) –0.5 V to 4 V Receiver input voltage (IN+, IN–) –0.7 V to 4.3 V LVPECL driver output voltage (OUT+, OUT–) Output current –0.5 V to 4 V Continuous 50 mA Surge 100 mA Storage temperature range –65°C to 125°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds Continuous power dissipation Electrostatic discharge (1) (2) (3) (4) 235°C See Dissipation Rating Table Human body model (3) All pins ±5 kV Charged-device mode (4) All pins ±500 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminals. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage 3 Receiver input voltage 0 Junction temperature NOM MAX 3.3 3.6 UNIT V 4 V 125 °C TA Operating free-air temperature (1) –40 85 °C |VID| Magnitude of differential input voltage 0.1 3 V (1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. Submit Documentation Feedback 5 SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS TYP (1) MIN MAX UNIT CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1) VIH High-level input voltage 2 VCC VIL Low-level input voltage 0.8 V IIH High-level input current VIN = 3.6 V or 2.0 V, VCC = 3.6 V ±3 ±20 µA IIL Low-level input current VIN = 0.0 V or 0.8 V, VCC = 3.6 V ±1 ±10 µA VCL Input clamp voltage ICL = –18 mA –0.8 –1.5 V GND V LVPECL OUTPUT SPECIFICATIONS (OUT0, OUT1) VOH Output high voltage VOL Output low voltage |VOD| Differential output voltage CO Differential output capacitance RL = 50 Ω to VTT , VTT = VCC – 2.0 V, See Figure 2 VCC – 1.3 VCC – 0.85 VCC – 2.2 VCC – 1.65 600 VI = 0.4 sin(4E6πt) + 0.5 V 800 1000 3 V mV pF RECEIVER DC SPECIFICATIONS (IN0, IN1) VTH Positive-going differential input voltage threshold See Figure 1 and Table 1 VTL Negative-going differential input voltage threshold See Figure 1 and Table 1 100 –100 VID(HYS) Differential input voltage hysteresis VCMR Common-mode voltage range IIN Input current CIN Differential input capacitance mV 25 VID = 100 mV, VCC = 3.0 V to 3.6 V 0.05 mV 3.95 VIN = 4 V, VCC = 3.6 V or 0.0 V ±1 ±10 VIN = 0 V, VCC = 3.6 V or 0.0 V ±1 ±10 VI = 0.4 sin (4E6πt) + 0.5 V mV 1 V µA pF SUPPLY CURRENT ICCD (1) 6 DC supply current No load All typical values are at 25°C and with a 3.3-V supply. Submit Documentation Feedback 50 65 mA SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSET Input to SEL setup time Figure 5 1 0.5 ns tHOLD Input to SEL hold time Figure 5 1.1 0.5 ns tSWITCH SEL to switched output Figure 5 1.7 2.5 ns tPHKL Disable time, high-level-to-known LOW Figure 4 2 2.5 ns tPKLH Enable time, known LOW-to-high-level output Figure 4 2 2.5 ns 80%) (1) tLHT Differential output signal rise time (20% – tHLT Differential output signal fall time (20% – 80%) (1) tJIT Added peak-to-peak jitter tJrms Added random jitter (rms) output (1) Figure 3 80 110 220 ps Figure 3 80 110 220 ps VID = 200 mV, 50% duty cycle, VCM = 1.2 V, 650 MHz 15 30 ps VID = 200 mV, PRBS = 223–1 data pattern and K28.5 (0011111010), VCM = 1.2 V at 1.3 Gbps 50 100 ps VID = 200 mV, 50% duty cycle, VCM = 1.2 V, 650 MHz 0.3 0.5 psRMS tPLHD Propagation delay time, low-to-high-level VCC = 3.3 V, TA = 25°C, See Figure 3 400 750 1100 ps tPHLD Propagation delay time, high-to-low-level output (1) VCC = 3.3 V, TA = 25°C, See Figure 3 400 750 1100 ps |) (2) tskew Pulse skew (|tPLHD– tPHLD Figure 3 20 100 tCCS Output channel-to-channel skew, splitter mode Figure 3 10 50 fMAX Maximum operating frequency (3) (1) (2) (3) 1 ps ps GHz Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device. Signal generator conditions: 50% duty cycle, tr or tf ≤ 100 ps (10% to 90%), transmitter output criteria: duty cycle = 45% to 55% VOD ≥ 300 mV. PIN ASSIGNMENTS D or PW PACKAGE (TOP VIEW) SEL1 SEL0 IN0+ IN0VCC IN1+ IN1VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Submit Documentation Feedback EN0 EN1 OUT0+ OUT0GND OUT1+ OUT1GND 7 SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION IIN+ OUT + IN+ VID IN+ +IN- VOD VIN+ VIC VIN- 2 VOY IN- OUT - VOUT++VOUT- VOZ IIN- 2 Figure 1. Voltage and Current Definitions Y Driver Device Receiver Device VOD Z 50 Ω 50 Ω VTT = VCC -2 V Figure 2. Typical Termination for LVPECL Output Driver OUT+ IN+ 1 pF VID VIN+ IN- VOD VOUT+ VTT 50 Ω OUT- VIN- 50 Ω VOUT- VTT VIN+ 1.4 V VIN- 1V 0.4 V 0V -0.4 V VID tPHLD +VOD tPLHD 80% 0V Vdiff = (OUT+) - (OUT-) 20% -VOD tHLT tLHT NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 3. Timing Test Circuit and Waveforms 8 Submit Documentation Feedback SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION (continued) OUT+ 1 V or 1.4 V 1 pF 1.2 V 50 Ω VOUT+ OUT- EN 50 Ω VOUT- VTT VTT 3V 1.5 V 0V EN +VOD 0V -VOD Vdiff = (OUT+) - (OUT-) tPHKL tPKLH NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Enable and Disable Time Circuit and Definitions Table 1. Receiver Input Voltage Threshold Test APPLIED VOLTAGES (1) RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE OUTPUT (1) VIA VIB VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V L 4.0 V 3.9 V 100 mV 3.95 V H 3.9 V 4. 0 V –100 mV 3.95 V L 0.1 V 0.0 V 100 mV 0.05 V H 0.0 V 0.1 V –100 mV 0.05 V L 1.7 V 0.7 V 1000 mV 1.2 V H 0.7 V 1.7 V –1000 mV 1.2 V L 4.0 V 3.0 V 1000 mV 3.5 V H 3.0 V 4.0 V –1000 mV 3.5 V L 1.0 V 0.0 V 1000 mV 0.5 V H 0.0 V 1.0 V –1000 mV 0.5 V L H H = high level, L = low level Submit Documentation Feedback 9 SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 IN0 IN1 SEL tSET tHOLD OUT IN0 IN1 tSWITCH EN IN0 IN1 SEL tSET OUT tHOLD IN1 IN0 tSWITCH EN NOTE: tSET and tHOLD times specify that data must be in a stable state before and after mux control switches. Figure 5. Input to Select for Both Rising and Falling Edge Setup and Hold Times 10 Submit Documentation Feedback SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 900 80 60 40 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, |V ID| = 200 mV Output = Loaded 20 0 500 1000 1500 2000 30 VCC = 3 − 3.6 V, VIC = 1.2 V, |V ID| = 300 mV Input = 1 MHz 825 750 tPLH tPHL 675 15 800 mV 500 mV 10 300 mV 600 −60 −40 −20 2500 0 0 20 40 60 80 0 100 100 200 300 400 500 600 TA − Free-Air Temperature − °C f − Frequency − MHz Figure 6. Figure 7. Figure 8. PEAK-TO-PEAK JITTER vs DATA RATE PEAK-TO-PEAK JITTER vs FREQUENCY PEAK-TO-PEAK JITTER vs DATA RATE 30 VCC = 3.3 V, TA = 25°C, VIC = 400 mV, Input = PRBS 223−1 60 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, Input = Clock Peak-to-Peak Jitter − ps 25 800 mV 40 300 mV 30 20 500 mV 20 15 500 mV 10 800 mV 700 800 mV 40 500 mV 30 20 300 mV 10 5 10 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V Input = PRBS 223-1 50 Peak-to-Peak Jitter − ps 60 300 mV 0 0 200 400 600 800 1000 1200 1400 0 Data Rate − Mbps Figure 9. 100 200 300 400 500 f − Frequency − MHz 600 0 700 0 200 400 600 800 1000 1200 1400 Data Rate − Mbps Figure 10. Figure 11. PEAK-TO-PEAK JITTER vs FREQUENCY PEAK-TO-PEAK JITTER vs DATA RATE 70 30 VCC = 3.3 V, TA = 25°C, VIC = 3.3 V, Input = Clock 25 60 Peak-to-Peak Jitter − ps 0 Peak-to-Peak Jitter − ps Peak-to-Peak Jitter − ps 20 5 f − Frequency − MHz 50 VCC = 3.3 V, TA = 25°C, VIC = 400 mV, Input = Clock 25 Peak-to-Peak Jitter − ps t pd − Propagation Delay Time − ps I CC − Supply Current − mA 100 0 PEAK-TO-PEAK JITTER vs FREQUENCY 20 15 500 mV 10 5 300 mV 50 500 mV 40 30 800 mV 20 VCC = 3.3 V, TA = 25°C, VIC = 3.3 V, Input = PRBS 223−1 10 800 mV 500 mV 0 0 0 100 200 300 400 500 600 700 0 200 400 600 800 1000 1200 1400 Data Rate − Mbps f − Frequency − MHz Figure 12. Figure 13. Submit Documentation Feedback 11 SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY 50 820 40 30 660 20 Added Random Jitter 10 170 140 110 80 50 500 0 0 250 500 750 1000 1250 1500 1750 2000 f − Frequency − MHz 20 0 500 1000 1500 2000 2500 3000 3500 Data Rate − Mbps Figure 14. 12 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, |V ID| = 200 mV Input = PRBS 223−1 200 740 580 230 Peak-to-Peak Jitter − ps VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, |V ID| = 200 mV Period Jitter − ps V OD − Differential Output Voltage − mV 900 PEAK-TO-PEAK JITTER vs DATA RATE Figure 15. Submit Documentation Feedback SN65LVCP23 www.ti.com SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 APPLICATION INFORMATION TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.) 50 Ω 3.3 V or 5 V 3.3 V SN65LVCP23 A ECL B 50 Ω 50 Ω 50 Ω VTT = VCC -2 V VTT Figure 16. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 3.3 V 50 Ω 3.3 V 50 Ω SN65LVCP23 3.3 V A CML B 50 Ω 50 Ω 3.3 V Figure 17. Current-Mode Logic (CML) 3.3 V 3.3 V 50 Ω SN65LVCP23 A ECL B 50 Ω 1.1 kΩ VTT 1.5 kΩ VTT = VCC -2 V 3.3 V Figure 18. Single-Ended (LVPECL) 3.3 V or 5 V 50 Ω 3.3 V SN65LVCP23 A 100 Ω LVDS B 50 Ω Figure 19. Low-Voltage Differential Signaling (LVDS) Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 12-Sep-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVCP23D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVCP23DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVCP23DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVCP23DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVCP23PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVCP23PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVCP23PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVCP23PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2008 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVCP23DR D 16 SITE 60 330 16 6.5 10.3 2.1 8 16 Q1 SN65LVCP23PWR PW 16 SITE 60 330 12 6.67 5.4 1.6 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 12-Feb-2008 Package Pins Site Length (mm) Width (mm) Height (mm) SN65LVCP23DR D 16 SITE 60 346.0 346.0 33.0 SN65LVCP23PWR PW 16 SITE 60 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 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